Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3770835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3902488

1

T1

877

T2

2911

T3

25148

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4439480	1			T1	3		T2	2546		T3	30532
values[0x0]	1616204	1			T1	443		T2	1372		T3	12924
values[0x1]	1617639	1			T1	434		T2	1419		T3	12889

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2667955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5005368

1

T1

878

T2

3560

T3

34912

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26750	1			T3	188		T4	39		T6	7
valid_sources[0x01]	29173	1			T2	1		T3	198		T4	159
valid_sources[0x02]	29985	1			T2	25		T3	161		T4	141
valid_sources[0x03]	33065	1			T2	24		T3	94		T4	283
valid_sources[0x04]	29189	1			T2	108		T3	397		T4	75
valid_sources[0x05]	28679	1			T2	41		T3	84		T4	247
valid_sources[0x06]	30479	1			T2	40		T3	142		T4	179
valid_sources[0x07]	30412	1			T2	37		T3	131		T4	769
valid_sources[0x08]	28073	1			T3	153		T4	382		T6	7
valid_sources[0x09]	29773	1			T3	114		T4	160		T6	4
valid_sources[0x0a]	27612	1			T2	25		T3	93		T4	71
valid_sources[0x0b]	32990	1			T3	387		T4	119		T6	3
valid_sources[0x0c]	31487	1			T3	339		T4	207		T5	1
valid_sources[0x0d]	30691	1			T2	5		T3	121		T4	323
valid_sources[0x0e]	28781	1			T2	32		T3	88		T4	182
valid_sources[0x0f]	28082	1			T2	120		T3	392		T4	167
valid_sources[0x10]	27827	1			T2	14		T3	106		T4	176
valid_sources[0x11]	29042	1			T3	112		T4	116		T6	3
valid_sources[0x12]	29239	1			T2	6		T3	196		T4	203
valid_sources[0x13]	29970	1			T2	46		T3	326		T4	135
valid_sources[0x14]	28693	1			T2	29		T3	213		T4	110
valid_sources[0x15]	27666	1			T3	174		T4	110		T6	2
valid_sources[0x16]	31490	1			T2	8		T3	161		T4	223
valid_sources[0x17]	31971	1			T2	46		T3	266		T4	34
valid_sources[0x18]	29006	1			T2	33		T3	202		T4	349
valid_sources[0x19]	30727	1			T2	53		T3	235		T4	1206
valid_sources[0x1a]	38210	1			T2	25		T3	273		T4	462
valid_sources[0x1b]	31076	1			T2	6		T3	86		T4	344
valid_sources[0x1c]	27964	1			T3	160		T4	290		T6	4
valid_sources[0x1d]	39583	1			T3	129		T4	159		T6	7
valid_sources[0x1e]	28316	1			T2	38		T3	214		T4	360
valid_sources[0x1f]	30244	1			T3	203		T4	93		T6	4
valid_sources[0x20]	32917	1			T3	237		T4	178		T6	8
valid_sources[0x21]	40277	1			T2	12		T3	280		T4	180
valid_sources[0x22]	29344	1			T2	35		T3	248		T4	453
valid_sources[0x23]	31525	1			T2	26		T3	120		T4	67
valid_sources[0x24]	29254	1			T2	2		T3	290		T4	190
valid_sources[0x25]	30316	1			T2	23		T3	127		T4	423
valid_sources[0x26]	31405	1			T1	449		T2	5		T3	241
valid_sources[0x27]	27680	1			T2	40		T3	91		T4	180
valid_sources[0x28]	31921	1			T2	12		T3	83		T4	100
valid_sources[0x29]	32955	1			T2	20		T3	176		T4	261
valid_sources[0x2a]	26608	1			T2	27		T3	268		T4	120
valid_sources[0x2b]	29740	1			T2	36		T3	237		T4	482
valid_sources[0x2c]	27946	1			T2	15		T3	332		T4	265
valid_sources[0x2d]	30665	1			T2	14		T3	107		T4	199
valid_sources[0x2e]	29122	1			T2	19		T3	141		T4	285
valid_sources[0x2f]	27089	1			T2	20		T3	109		T4	39
valid_sources[0x30]	37177	1			T3	183		T4	421		T6	2
valid_sources[0x31]	29138	1			T2	29		T3	155		T4	379
valid_sources[0x32]	30893	1			T3	284		T4	275		T6	5
valid_sources[0x33]	30351	1			T2	16		T3	275		T4	519
valid_sources[0x34]	29405	1			T2	30		T3	244		T4	479
valid_sources[0x35]	29676	1			T2	47		T3	181		T4	121
valid_sources[0x36]	29253	1			T2	15		T3	300		T4	651
valid_sources[0x37]	27047	1			T2	28		T3	155		T4	86
valid_sources[0x38]	31568	1			T3	230		T4	348		T6	3
valid_sources[0x39]	30871	1			T2	5		T3	167		T4	278
valid_sources[0x3a]	31223	1			T3	166		T4	58		T6	1
valid_sources[0x3b]	30902	1			T2	96		T3	217		T4	572
valid_sources[0x3c]	32363	1			T2	37		T3	186		T4	57
valid_sources[0x3d]	33345	1			T2	11		T3	96		T4	205
valid_sources[0x3e]	27026	1			T3	202		T4	146		T6	7
valid_sources[0x3f]	26576	1			T2	13		T3	200		T4	136
valid_sources[0x40]	29997	1			T2	12		T3	322		T4	185
valid_sources[0x41]	27127	1			T2	8		T3	103		T4	126
valid_sources[0x42]	29353	1			T2	10		T3	440		T4	204
valid_sources[0x43]	29485	1			T3	228		T4	165		T6	8
valid_sources[0x44]	28331	1			T2	16		T3	173		T4	195
valid_sources[0x45]	30342	1			T2	5		T3	292		T4	196
valid_sources[0x46]	27303	1			T2	26		T3	150		T4	179
valid_sources[0x47]	28783	1			T2	15		T3	332		T4	481
valid_sources[0x48]	28276	1			T2	65		T3	229		T4	230
valid_sources[0x49]	28879	1			T2	34		T3	192		T4	195
valid_sources[0x4a]	28186	1			T3	148		T4	43		T6	4
valid_sources[0x4b]	28960	1			T2	150		T3	169		T4	423
valid_sources[0x4c]	27338	1			T2	32		T3	302		T4	105
valid_sources[0x4d]	30216	1			T2	23		T3	155		T4	636
valid_sources[0x4e]	29619	1			T2	11		T3	83		T4	181
valid_sources[0x4f]	28627	1			T2	44		T3	248		T4	559
valid_sources[0x50]	30841	1			T2	13		T3	401		T4	198
valid_sources[0x51]	29406	1			T2	47		T3	268		T4	523
valid_sources[0x52]	27436	1			T2	36		T3	147		T4	109
valid_sources[0x53]	29359	1			T2	4		T3	161		T4	240
valid_sources[0x54]	33021	1			T2	10		T3	214		T4	193
valid_sources[0x55]	35318	1			T2	12		T3	210		T4	20
valid_sources[0x56]	28659	1			T2	51		T3	218		T4	137
valid_sources[0x57]	29053	1			T2	34		T3	185		T4	346
valid_sources[0x58]	28711	1			T3	297		T4	72		T5	3
valid_sources[0x59]	32363	1			T2	9		T3	225		T4	625
valid_sources[0x5a]	27821	1			T2	17		T3	244		T4	90
valid_sources[0x5b]	28625	1			T2	3		T3	220		T4	106
valid_sources[0x5c]	33031	1			T2	61		T3	289		T4	148
valid_sources[0x5d]	31340	1			T2	54		T3	219		T4	95
valid_sources[0x5e]	28600	1			T2	20		T3	199		T4	398
valid_sources[0x5f]	32053	1			T2	29		T3	204		T4	104
valid_sources[0x60]	28589	1			T2	4		T3	188		T4	45
valid_sources[0x61]	28468	1			T3	194		T4	489		T6	3
valid_sources[0x62]	30201	1			T2	37		T3	227		T4	88
valid_sources[0x63]	28603	1			T2	29		T3	65		T4	144
valid_sources[0x64]	29339	1			T2	2		T3	197		T4	230
valid_sources[0x65]	29114	1			T2	2		T3	117		T4	3
valid_sources[0x66]	32788	1			T3	297		T4	381		T6	3
valid_sources[0x67]	27595	1			T2	49		T3	163		T4	104
valid_sources[0x68]	27698	1			T2	27		T3	188		T4	378
valid_sources[0x69]	27960	1			T2	47		T3	106		T4	95
valid_sources[0x6a]	29215	1			T2	38		T3	250		T4	11
valid_sources[0x6b]	28887	1			T2	2		T3	229		T4	159
valid_sources[0x6c]	28449	1			T3	339		T4	230		T6	1
valid_sources[0x6d]	27513	1			T2	13		T3	179		T4	88
valid_sources[0x6e]	36403	1			T2	7		T3	283		T4	111
valid_sources[0x6f]	33532	1			T2	18		T3	133		T4	154
valid_sources[0x70]	33398	1			T2	8		T3	360		T4	170
valid_sources[0x71]	27938	1			T2	129		T3	259		T4	123
valid_sources[0x72]	27404	1			T2	57		T3	246		T4	173
valid_sources[0x73]	31130	1			T2	1		T3	82		T4	364
valid_sources[0x74]	30094	1			T2	49		T3	168		T4	72
valid_sources[0x75]	27501	1			T2	91		T3	248		T4	163
valid_sources[0x76]	29287	1			T3	214		T4	218		T6	2
valid_sources[0x77]	28785	1			T2	32		T3	184		T4	1003
valid_sources[0x78]	31497	1			T2	2		T3	296		T4	153
valid_sources[0x79]	28446	1			T2	24		T3	158		T4	52
valid_sources[0x7a]	29372	1			T2	22		T3	243		T4	34
valid_sources[0x7b]	29431	1			T2	2		T3	256		T4	320
valid_sources[0x7c]	32111	1			T2	98		T3	205		T4	273
valid_sources[0x7d]	27503	1			T2	20		T3	183		T4	64
valid_sources[0x7e]	27850	1			T2	36		T3	304		T4	259
valid_sources[0x7f]	25843	1			T2	23		T3	107		T4	83
valid_sources[0x80]	27619	1			T2	6		T3	283		T4	73

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1015969

1

T1

2

T2

849

T3

2728

values[0x0]

all_enables

biggest_size

1454438

1

T1

442

T2

1047

T3

11330

values[0x1]

all_enables

biggest_size

1432081

1

T1

433

T2

1015

T3

11090