Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3793140

1

T1

3

T2

2426

T3

31197

full_word

3903835

1

T1

877

T2

2911

T3

25148

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7696615	1			T1	880		T2	5337		T3	56345
auto[TlIntgErrCmd]	122	1			T58	3		T96	14		T97	7
auto[TlIntgErrData]	111	1			T58	2		T96	11		T97	8
auto[TlIntgErrBoth]	127	1			T58	5		T96	5		T97	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4443158

1

T1

3

T2

2546

T3

30532

auto[1]

3253817

1

T1

877

T2

2791

T3

25813

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3426735	1			T1	1		T2	1697		T3	27804
auto[TlIntgErrNone]	partial	auto[1]	366077	1			T1	2		T2	729		T3	3393
auto[TlIntgErrNone]	full_word	auto[0]	1016274	1			T1	2		T2	849		T3	2728
auto[TlIntgErrNone]	full_word	auto[1]	2887529	1			T1	875		T2	2062		T3	22420
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T58	1		T96	6		T97	2
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T96	6		T97	5		T260	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T58	1		T262	1		T265	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T58	1		T96	2		T261	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T58	1		T96	4		T97	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T58	1		T96	5		T97	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T96	1		T262	2		T265	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T96	1		T266	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T96	2		T97	3		T261	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T58	4		T96	3		T97	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T261	1		T265	1		T267	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T58	1		T97	1		T260	1