Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	513464390	2510404	0	0
gen_wmask[1].MaskCheckPortA_A	513464390	2510404	0	0
gen_wmask[2].MaskCheckPortA_A	513464390	2510404	0	0
gen_wmask[3].MaskCheckPortA_A	513464390	2510404	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513464390	2510404	0	0
T1	6943	832	0	0
T2	388089	4049	0	0
T3	1039743	13668	0	0
T4	743999	21374	0	0
T5	1684	0	0	0
T6	358241	832	0	0
T7	161168	832	0	0
T8	81741	832	0	0
T9	1383523	13088	0	0
T10	7480	196	0	0
T11	240815	5329	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513464390	2510404	0	0
T1	6943	832	0	0
T2	388089	4049	0	0
T3	1039743	13668	0	0
T4	743999	21374	0	0
T5	1684	0	0	0
T6	358241	832	0	0
T7	161168	832	0	0
T8	81741	832	0	0
T9	1383523	13088	0	0
T10	7480	196	0	0
T11	240815	5329	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513464390	2510404	0	0
T1	6943	832	0	0
T2	388089	4049	0	0
T3	1039743	13668	0	0
T4	743999	21374	0	0
T5	1684	0	0	0
T6	358241	832	0	0
T7	161168	832	0	0
T8	81741	832	0	0
T9	1383523	13088	0	0
T10	7480	196	0	0
T11	240815	5329	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513464390	2510404	0	0
T1	6943	832	0	0
T2	388089	4049	0	0
T3	1039743	13668	0	0
T4	743999	21374	0	0
T5	1684	0	0	0
T6	358241	832	0	0
T7	161168	832	0	0
T8	81741	832	0	0
T9	1383523	13088	0	0
T10	7480	196	0	0
T11	240815	5329	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	394732484	1703239	0	0
gen_wmask[1].MaskCheckPortA_A	394732484	1703239	0	0
gen_wmask[2].MaskCheckPortA_A	394732484	1703239	0	0
gen_wmask[3].MaskCheckPortA_A	394732484	1703239	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1703239	0	0
T1	6943	832	0	0
T2	137015	1358	0	0
T3	240133	10474	0	0
T4	281391	10809	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	5205	0	0
T10	3609	37	0	0
T11	0	4160	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1703239	0	0
T1	6943	832	0	0
T2	137015	1358	0	0
T3	240133	10474	0	0
T4	281391	10809	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	5205	0	0
T10	3609	37	0	0
T11	0	4160	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1703239	0	0
T1	6943	832	0	0
T2	137015	1358	0	0
T3	240133	10474	0	0
T4	281391	10809	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	5205	0	0
T10	3609	37	0	0
T11	0	4160	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1703239	0	0
T1	6943	832	0	0
T2	137015	1358	0	0
T3	240133	10474	0	0
T4	281391	10809	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	5205	0	0
T10	3609	37	0	0
T11	0	4160	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	118731906	807165	0	0
gen_wmask[1].MaskCheckPortA_A	118731906	807165	0	0
gen_wmask[2].MaskCheckPortA_A	118731906	807165	0	0
gen_wmask[3].MaskCheckPortA_A	118731906	807165	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	807165	0	0
T2	251074	2691	0	0
T3	799610	3194	0	0
T4	462608	10565	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	7883	0	0
T10	3871	159	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	807165	0	0
T2	251074	2691	0	0
T3	799610	3194	0	0
T4	462608	10565	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	7883	0	0
T10	3871	159	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	807165	0	0
T2	251074	2691	0	0
T3	799610	3194	0	0
T4	462608	10565	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	7883	0	0
T10	3871	159	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	807165	0	0
T2	251074	2691	0	0
T3	799610	3194	0	0
T4	462608	10565	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	7883	0	0
T10	3871	159	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	5736	0	0
T16	0	4974	0	0
T20	0	2561	0	0
T21	0	1036	0	0