Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T9
1	0	Covered	T3,T4,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	632196296	512128397	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	632196296	2867118	0	0
GntImpliesValid_A	632196296	2867118	0	0
GrantKnown_A	632196296	512128397	0	0
IdxKnown_A	632196296	512128397	0	0
IndexIsCorrect_A	632196296	2867118	0	0
LockArbDecision_A	632196296	0	0	0
NoReadyValidNoGrant_A	632196296	0	0	0
ReadyAndValidImplyGrant_A	632196296	2867118	0	0
ReqAndReadyImplyGrant_A	632196296	2867118	0	0
ReqImpliesValid_A	632196296	2867118	0	0
ReqStaysHighUntilGranted0_M	632196296	0	0	0
RoundRobin_A	632196296	10	0	906
ValidKnown_A	632196296	512128397	0	0
gen_data_port_assertion.DataFlow_A	632196296	2867118	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	512128397	0	0
T1	18167	18076	0	0
T2	639163	382930	0	0
T3	1839353	1032290	0	0
T4	1206607	735987	0	0
T5	1684	1586	0	0
T6	416083	358151	0	0
T7	180916	161091	0	0
T8	106456	81677	0	0
T9	1830184	1372318	0	0
T10	11351	7290	0	0
T11	481630	240411	0	0
T12	96065	95888	0	0
T13	0	1113121	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	512128397	0	0
T1	18167	18076	0	0
T2	639163	382930	0	0
T3	1839353	1032290	0	0
T4	1206607	735987	0	0
T5	1684	1586	0	0
T6	416083	358151	0	0
T7	180916	161091	0	0
T8	106456	81677	0	0
T9	1830184	1372318	0	0
T10	11351	7290	0	0
T11	481630	240411	0	0
T12	96065	95888	0	0
T13	0	1113121	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	512128397	0	0
T1	18167	18076	0	0
T2	639163	382930	0	0
T3	1839353	1032290	0	0
T4	1206607	735987	0	0
T5	1684	1586	0	0
T6	416083	358151	0	0
T7	180916	161091	0	0
T8	106456	81677	0	0
T9	1830184	1372318	0	0
T10	11351	7290	0	0
T11	481630	240411	0	0
T12	96065	95888	0	0
T13	0	1113121	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	10	0	906
T26	104123	0	0	1
T27	161285	0	0	1
T37	318931	1	0	1
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	12798	0	0	1
T47	1210	0	0	1
T48	875	0	0	1
T49	275084	0	0	1
T50	213565	0	0	1
T51	490653	0	0	1
T52	619106	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	512128397	0	0
T1	18167	18076	0	0
T2	639163	382930	0	0
T3	1839353	1032290	0	0
T4	1206607	735987	0	0
T5	1684	1586	0	0
T6	416083	358151	0	0
T7	180916	161091	0	0
T8	106456	81677	0	0
T9	1830184	1372318	0	0
T10	11351	7290	0	0
T11	481630	240411	0	0
T12	96065	95888	0	0
T13	0	1113121	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632196296	2867118	0	0
T1	6943	832	0	0
T2	388089	6216	0	0
T3	1839353	15945	0	0
T4	1206607	24175	0	0
T5	1684	0	0	0
T6	416083	832	0	0
T7	180916	832	0	0
T8	106456	832	0	0
T9	1830184	18922	0	0
T10	11351	279	0	0
T11	481630	5506	0	0
T12	192130	0	0	0
T13	0	7455	0	0
T16	0	6158	0	0
T17	72	0	0	0
T20	0	4209	0	0
T21	0	1036	0	0
T22	0	8366	0	0
T34	0	134	0	0
T35	0	268	0	0
T36	0	409	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	118731906	28223916	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	118731906	632775	0	0
GntImpliesValid_A	118731906	632775	0	0
GrantKnown_A	118731906	28223916	0	0
IdxKnown_A	118731906	28223916	0	0
IndexIsCorrect_A	118731906	632775	0	0
LockArbDecision_A	118731906	0	0	0
NoReadyValidNoGrant_A	118731906	0	0	0
ReadyAndValidImplyGrant_A	118731906	632775	0	0
ReqAndReadyImplyGrant_A	118731906	632775	0	0
ReqImpliesValid_A	118731906	632775	0	0
ReqStaysHighUntilGranted0_M	118731906	0	0	0
RoundRobin_A	118731906	0	0	0
ValidKnown_A	118731906	28223916	0	0
gen_data_port_assertion.DataFlow_A	118731906	632775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	28223916	0	0
T2	251074	246008	0	0
T3	799610	103408	0	0
T4	462608	102896	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	378376	0	0
T10	3871	3768	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	141456	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	28223916	0	0
T2	251074	246008	0	0
T3	799610	103408	0	0
T4	462608	102896	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	378376	0	0
T10	3871	3768	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	141456	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	28223916	0	0
T2	251074	246008	0	0
T3	799610	103408	0	0
T4	462608	102896	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	378376	0	0
T10	3871	3768	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	141456	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	28223916	0	0
T2	251074	246008	0	0
T3	799610	103408	0	0
T4	462608	102896	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	378376	0	0
T10	3871	3768	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	141456	0	0
T16	0	80720	0	0
T17	0	72	0	0
T20	0	135840	0	0
T22	0	83208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	632775	0	0
T2	251074	4157	0	0
T3	799610	4105	0	0
T4	462608	4307	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	10970	0	0
T10	3871	201	0	0
T11	240815	0	0	0
T12	96065	0	0	0
T13	0	5589	0	0
T16	0	3226	0	0
T20	0	4209	0	0
T22	0	3457	0	0
T34	0	134	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T9
1	0	Covered	T3,T4,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	118731906	89255959	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	118731906	384584	0	0
GntImpliesValid_A	118731906	384584	0	0
GrantKnown_A	118731906	89255959	0	0
IdxKnown_A	118731906	89255959	0	0
IndexIsCorrect_A	118731906	384584	0	0
LockArbDecision_A	118731906	0	0	0
NoReadyValidNoGrant_A	118731906	0	0	0
ReadyAndValidImplyGrant_A	118731906	384584	0	0
ReqAndReadyImplyGrant_A	118731906	384584	0	0
ReqImpliesValid_A	118731906	384584	0	0
ReqStaysHighUntilGranted0_M	118731906	0	0	0
RoundRobin_A	118731906	0	0	0
ValidKnown_A	118731906	89255959	0	0
gen_data_port_assertion.DataFlow_A	118731906	384584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	89255959	0	0
T1	11224	11224	0	0
T2	251074	0	0	0
T3	799610	688754	0	0
T4	462608	351705	0	0
T6	57842	57840	0	0
T7	19748	19748	0	0
T8	24715	24715	0	0
T9	446661	57376	0	0
T10	3871	0	0	0
T11	240815	240411	0	0
T12	0	95888	0	0
T13	0	971665	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	89255959	0	0
T1	11224	11224	0	0
T2	251074	0	0	0
T3	799610	688754	0	0
T4	462608	351705	0	0
T6	57842	57840	0	0
T7	19748	19748	0	0
T8	24715	24715	0	0
T9	446661	57376	0	0
T10	3871	0	0	0
T11	240815	240411	0	0
T12	0	95888	0	0
T13	0	971665	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	89255959	0	0
T1	11224	11224	0	0
T2	251074	0	0	0
T3	799610	688754	0	0
T4	462608	351705	0	0
T6	57842	57840	0	0
T7	19748	19748	0	0
T8	24715	24715	0	0
T9	446661	57376	0	0
T10	3871	0	0	0
T11	240815	240411	0	0
T12	0	95888	0	0
T13	0	971665	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	89255959	0	0
T1	11224	11224	0	0
T2	251074	0	0	0
T3	799610	688754	0	0
T4	462608	351705	0	0
T6	57842	57840	0	0
T7	19748	19748	0	0
T8	24715	24715	0	0
T9	446661	57376	0	0
T10	3871	0	0	0
T11	240815	240411	0	0
T12	0	95888	0	0
T13	0	971665	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118731906	384584	0	0
T3	799610	531	0	0
T4	462608	8043	0	0
T6	57842	0	0	0
T7	19748	0	0	0
T8	24715	0	0	0
T9	446661	772	0	0
T10	3871	0	0	0
T11	240815	1169	0	0
T12	96065	0	0	0
T13	0	1866	0	0
T16	0	2932	0	0
T17	72	0	0	0
T21	0	1036	0	0
T22	0	4909	0	0
T35	0	268	0	0
T36	0	409	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394732484	394648522	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	394732484	1849759	0	0
GntImpliesValid_A	394732484	1849759	0	0
GrantKnown_A	394732484	394648522	0	0
IdxKnown_A	394732484	394648522	0	0
IndexIsCorrect_A	394732484	1849759	0	0
LockArbDecision_A	394732484	0	0	0
NoReadyValidNoGrant_A	394732484	0	0	0
ReadyAndValidImplyGrant_A	394732484	1849759	0	0
ReqAndReadyImplyGrant_A	394732484	1849759	0	0
ReqImpliesValid_A	394732484	1849759	0	0
ReqStaysHighUntilGranted0_M	394732484	0	0	0
RoundRobin_A	394732484	10	0	906
ValidKnown_A	394732484	394648522	0	0
gen_data_port_assertion.DataFlow_A	394732484	1849759	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	394648522	0	0
T1	6943	6852	0	0
T2	137015	136922	0	0
T3	240133	240128	0	0
T4	281391	281386	0	0
T5	1684	1586	0	0
T6	300399	300311	0	0
T7	141420	141343	0	0
T8	57026	56962	0	0
T9	936862	936566	0	0
T10	3609	3522	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	394648522	0	0
T1	6943	6852	0	0
T2	137015	136922	0	0
T3	240133	240128	0	0
T4	281391	281386	0	0
T5	1684	1586	0	0
T6	300399	300311	0	0
T7	141420	141343	0	0
T8	57026	56962	0	0
T9	936862	936566	0	0
T10	3609	3522	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	394648522	0	0
T1	6943	6852	0	0
T2	137015	136922	0	0
T3	240133	240128	0	0
T4	281391	281386	0	0
T5	1684	1586	0	0
T6	300399	300311	0	0
T7	141420	141343	0	0
T8	57026	56962	0	0
T9	936862	936566	0	0
T10	3609	3522	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	10	0	906
T26	104123	0	0	1
T27	161285	0	0	1
T37	318931	1	0	1
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	12798	0	0	1
T47	1210	0	0	1
T48	875	0	0	1
T49	275084	0	0	1
T50	213565	0	0	1
T51	490653	0	0	1
T52	619106	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	394648522	0	0
T1	6943	6852	0	0
T2	137015	136922	0	0
T3	240133	240128	0	0
T4	281391	281386	0	0
T5	1684	1586	0	0
T6	300399	300311	0	0
T7	141420	141343	0	0
T8	57026	56962	0	0
T9	936862	936566	0	0
T10	3609	3522	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394732484	1849759	0	0
T1	6943	832	0	0
T2	137015	2059	0	0
T3	240133	11309	0	0
T4	281391	11825	0	0
T5	1684	0	0	0
T6	300399	832	0	0
T7	141420	832	0	0
T8	57026	832	0	0
T9	936862	7180	0	0
T10	3609	78	0	0
T11	0	4337	0	0