Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396608780	3972	0	0
addr_swap_data_rd_A	396608780	1296	0	0
addr_swap_mask_rd_A	396608780	1196	0	0
cfg_rd_A	396608780	1228	0	0
cmd_filter_0_rd_A	396608780	2488	0	0
cmd_filter_1_rd_A	396608780	2282	0	0
cmd_filter_2_rd_A	396608780	2789	0	0
cmd_filter_3_rd_A	396608780	2427	0	0
cmd_filter_4_rd_A	396608780	2765	0	0
cmd_filter_5_rd_A	396608780	2403	0	0
cmd_filter_6_rd_A	396608780	2968	0	0
cmd_filter_7_rd_A	396608780	2424	0	0
cmd_info_0_rd_A	396608780	1761	0	0
cmd_info_10_rd_A	396608780	1698	0	0
cmd_info_11_rd_A	396608780	1638	0	0
cmd_info_12_rd_A	396608780	1845	0	0
cmd_info_13_rd_A	396608780	1767	0	0
cmd_info_14_rd_A	396608780	1882	0	0
cmd_info_15_rd_A	396608780	1615	0	0
cmd_info_16_rd_A	396608780	1797	0	0
cmd_info_17_rd_A	396608780	1983	0	0
cmd_info_18_rd_A	396608780	1498	0	0
cmd_info_19_rd_A	396608780	1818	0	0
cmd_info_1_rd_A	396608780	1671	0	0
cmd_info_20_rd_A	396608780	1881	0	0
cmd_info_21_rd_A	396608780	1618	0	0
cmd_info_22_rd_A	396608780	1726	0	0
cmd_info_23_rd_A	396608780	1713	0	0
cmd_info_2_rd_A	396608780	1619	0	0
cmd_info_3_rd_A	396608780	1655	0	0
cmd_info_4_rd_A	396608780	1662	0	0
cmd_info_5_rd_A	396608780	1558	0	0
cmd_info_6_rd_A	396608780	1774	0	0
cmd_info_7_rd_A	396608780	1806	0	0
cmd_info_8_rd_A	396608780	1690	0	0
cmd_info_9_rd_A	396608780	1796	0	0
cmd_info_en4b_rd_A	396608780	1246	0	0
cmd_info_ex4b_rd_A	396608780	1283	0	0
cmd_info_wrdi_rd_A	396608780	1191	0	0
cmd_info_wren_rd_A	396608780	1159	0	0
intercept_en_rd_A	396608780	1462	0	0
intr_enable_rd_A	396608780	2386	0	0
jedec_cc_rd_A	396608780	1137	0	0
jedec_id_rd_A	396608780	1154	0	0
mailbox_addr_rd_A	396608780	1103	0	0
payload_swap_data_rd_A	396608780	1194	0	0
payload_swap_mask_rd_A	396608780	1187	0	0
read_threshold_rd_A	396608780	1256	0	0
tpm_access_0_rd_A	396608780	1346	0	0
tpm_access_1_rd_A	396608780	1152	0	0
tpm_cfg_rd_A	396608780	1443	0	0
tpm_did_vid_rd_A	396608780	1138	0	0
tpm_int_enable_rd_A	396608780	1044	0	0
tpm_int_status_rd_A	396608780	1244	0	0
tpm_int_vector_rd_A	396608780	1257	0	0
tpm_intf_capability_rd_A	396608780	1228	0	0
tpm_rid_rd_A	396608780	1159	0	0
tpm_sts_rd_A	396608780	1199	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	3972	0	0
T57	6192	4	0	0
T58	27253	1	0	0
T59	3160	118	0	0
T94	4071	76	0	0
T95	13235	201	0	0
T96	29012	8	0	0
T97	55303	1	0	0
T98	12497	9	0	0
T99	8137	7	0	0
T108	5759	19	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1296	0	0
T57	6192	9	0	0
T113	10847	13	0	0
T145	90781	227	0	0
T146	5137	1	0	0
T147	11836	24	0	0
T148	5680	11	0	0
T149	21768	89	0	0
T150	7321	11	0	0
T151	20251	90	0	0
T152	8011	26	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1196	0	0
T57	6192	3	0	0
T113	10847	9	0	0
T145	90781	242	0	0
T146	5137	5	0	0
T147	11836	9	0	0
T148	5680	15	0	0
T149	21768	88	0	0
T150	7321	14	0	0
T151	20251	53	0	0
T152	8011	29	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1228	0	0
T113	10847	15	0	0
T123	4134	14	0	0
T124	10093	19	0	0
T145	90781	229	0	0
T146	5137	6	0	0
T147	11836	4	0	0
T149	21768	87	0	0
T150	7321	14	0	0
T151	20251	54	0	0
T152	8011	21	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2488	0	0
T57	6192	51	0	0
T113	10847	230	0	0
T145	90781	215	0	0
T146	5137	68	0	0
T147	11836	30	0	0
T148	5680	4	0	0
T149	21768	105	0	0
T150	7321	133	0	0
T151	20251	31	0	0
T152	8011	23	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2282	0	0
T57	6192	13	0	0
T113	10847	10	0	0
T145	90781	241	0	0
T146	5137	8	0	0
T147	11836	10	0	0
T148	5680	29	0	0
T149	21768	79	0	0
T150	7321	138	0	0
T151	20251	61	0	0
T152	8011	30	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2789	0	0
T57	6192	48	0	0
T113	10847	261	0	0
T123	4134	96	0	0
T145	90781	211	0	0
T146	5137	91	0	0
T147	11836	31	0	0
T149	21768	68	0	0
T150	7321	8	0	0
T151	20251	103	0	0
T152	8011	19	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2427	0	0
T57	6192	55	0	0
T113	10847	226	0	0
T123	4134	8	0	0
T124	10093	220	0	0
T145	90781	201	0	0
T147	11836	14	0	0
T149	21768	58	0	0
T150	7321	120	0	0
T151	20251	55	0	0
T152	8011	39	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2765	0	0
T57	6192	5	0	0
T113	10847	240	0	0
T145	90781	249	0	0
T146	5137	4	0	0
T147	11836	20	0	0
T148	5680	2	0	0
T149	21768	110	0	0
T150	7321	146	0	0
T151	20251	46	0	0
T152	8011	10	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2403	0	0
T57	6192	61	0	0
T102	9369	10	0	0
T113	10847	127	0	0
T145	90781	199	0	0
T146	5137	38	0	0
T147	11836	36	0	0
T148	5680	7	0	0
T149	21768	73	0	0
T150	7321	8	0	0
T151	20251	36	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2968	0	0
T57	6192	67	0	0
T101	20387	8	0	0
T113	10847	268	0	0
T145	90781	225	0	0
T146	5137	1	0	0
T147	11836	39	0	0
T148	5680	10	0	0
T149	21768	37	0	0
T150	7321	141	0	0
T151	20251	77	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2424	0	0
T57	6192	61	0	0
T113	10847	142	0	0
T145	90781	226	0	0
T146	5137	74	0	0
T147	11836	40	0	0
T148	5680	14	0	0
T149	21768	26	0	0
T150	7321	231	0	0
T151	20251	45	0	0
T152	8011	25	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1761	0	0
T113	10847	53	0	0
T123	4134	69	0	0
T145	90781	267	0	0
T146	5137	6	0	0
T147	11836	21	0	0
T148	5680	2	0	0
T149	21768	101	0	0
T150	7321	31	0	0
T151	20251	38	0	0
T152	8011	34	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1698	0	0
T57	6192	12	0	0
T113	10847	5	0	0
T145	90781	226	0	0
T146	5137	42	0	0
T147	11836	49	0	0
T148	5680	7	0	0
T149	21768	38	0	0
T150	7321	64	0	0
T151	20251	107	0	0
T152	8011	30	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1638	0	0
T57	6192	9	0	0
T113	10847	152	0	0
T145	90781	225	0	0
T146	5137	8	0	0
T147	11836	30	0	0
T148	5680	8	0	0
T149	21768	21	0	0
T150	7321	8	0	0
T151	20251	86	0	0
T152	8011	7	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1845	0	0
T57	6192	9	0	0
T113	10847	51	0	0
T123	4134	55	0	0
T145	90781	243	0	0
T146	5137	2	0	0
T147	11836	19	0	0
T149	21768	127	0	0
T150	7321	64	0	0
T151	20251	47	0	0
T152	8011	46	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1767	0	0
T57	6192	8	0	0
T113	10847	124	0	0
T145	90781	225	0	0
T146	5137	37	0	0
T147	11836	10	0	0
T148	5680	4	0	0
T149	21768	48	0	0
T150	7321	6	0	0
T151	20251	65	0	0
T152	8011	50	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1882	0	0
T57	6192	4	0	0
T113	10847	160	0	0
T145	90781	203	0	0
T146	5137	28	0	0
T147	11836	1	0	0
T148	5680	24	0	0
T149	21768	21	0	0
T150	7321	44	0	0
T151	20251	78	0	0
T152	8011	1	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1615	0	0
T57	6192	27	0	0
T113	10847	40	0	0
T123	4134	4	0	0
T145	90781	180	0	0
T147	11836	16	0	0
T148	5680	3	0	0
T149	21768	66	0	0
T150	7321	62	0	0
T151	20251	75	0	0
T152	8011	3	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1797	0	0
T57	6192	13	0	0
T113	10847	124	0	0
T145	90781	196	0	0
T146	5137	8	0	0
T147	11836	40	0	0
T148	5680	1	0	0
T149	21768	50	0	0
T150	7321	53	0	0
T151	20251	31	0	0
T152	8011	17	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1983	0	0
T57	6192	33	0	0
T113	10847	119	0	0
T123	4134	44	0	0
T124	10093	114	0	0
T145	90781	231	0	0
T147	11836	57	0	0
T149	21768	72	0	0
T150	7321	74	0	0
T151	20251	98	0	0
T152	8011	27	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1498	0	0
T57	6192	4	0	0
T113	10847	97	0	0
T145	90781	196	0	0
T146	5137	1	0	0
T147	11836	34	0	0
T148	5680	29	0	0
T149	21768	14	0	0
T150	7321	63	0	0
T151	20251	81	0	0
T152	8011	28	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1818	0	0
T57	6192	32	0	0
T113	10847	78	0	0
T145	90781	185	0	0
T146	5137	12	0	0
T147	11836	40	0	0
T148	5680	9	0	0
T149	21768	40	0	0
T150	7321	107	0	0
T151	20251	71	0	0
T152	8011	36	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1671	0	0
T57	6192	14	0	0
T109	13898	8	0	0
T113	10847	53	0	0
T145	90781	231	0	0
T146	5137	43	0	0
T147	11836	49	0	0
T148	5680	2	0	0
T149	21768	80	0	0
T150	7321	65	0	0
T151	20251	69	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1881	0	0
T57	6192	33	0	0
T105	11343	2	0	0
T113	10847	54	0	0
T145	90781	232	0	0
T146	5137	35	0	0
T147	11836	18	0	0
T148	5680	23	0	0
T149	21768	75	0	0
T150	7321	10	0	0
T151	20251	82	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1618	0	0
T57	6192	29	0	0
T109	13898	5	0	0
T113	10847	14	0	0
T145	90781	223	0	0
T146	5137	30	0	0
T147	11836	26	0	0
T148	5680	27	0	0
T149	21768	56	0	0
T150	7321	50	0	0
T151	20251	55	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1726	0	0
T57	6192	36	0	0
T113	10847	114	0	0
T145	90781	229	0	0
T146	5137	27	0	0
T147	11836	19	0	0
T148	5680	8	0	0
T149	21768	61	0	0
T150	7321	3	0	0
T151	20251	60	0	0
T152	8011	25	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1713	0	0
T57	6192	39	0	0
T109	13898	2	0	0
T113	10847	60	0	0
T145	90781	208	0	0
T146	5137	8	0	0
T147	11836	17	0	0
T148	5680	5	0	0
T149	21768	73	0	0
T150	7321	2	0	0
T151	20251	86	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1619	0	0
T57	6192	40	0	0
T113	10847	60	0	0
T123	4134	40	0	0
T145	90781	201	0	0
T146	5137	34	0	0
T147	11836	40	0	0
T148	5680	11	0	0
T149	21768	122	0	0
T150	7321	12	0	0
T151	20251	60	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1655	0	0
T57	6192	8	0	0
T101	20387	3	0	0
T105	11343	3	0	0
T113	10847	104	0	0
T145	90781	181	0	0
T147	11836	10	0	0
T148	5680	30	0	0
T149	21768	45	0	0
T150	7321	58	0	0
T151	20251	40	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1662	0	0
T57	6192	9	0	0
T113	10847	55	0	0
T145	90781	220	0	0
T146	5137	5	0	0
T147	11836	29	0	0
T148	5680	33	0	0
T149	21768	69	0	0
T150	7321	60	0	0
T151	20251	86	0	0
T152	8011	25	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1558	0	0
T57	6192	1	0	0
T113	10847	57	0	0
T145	90781	260	0	0
T146	5137	21	0	0
T147	11836	6	0	0
T148	5680	4	0	0
T149	21768	62	0	0
T150	7321	66	0	0
T151	20251	90	0	0
T152	8011	5	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1774	0	0
T57	6192	32	0	0
T113	10847	130	0	0
T123	4134	36	0	0
T145	90781	212	0	0
T146	5137	42	0	0
T147	11836	69	0	0
T149	21768	39	0	0
T150	7321	1	0	0
T151	20251	87	0	0
T152	8011	34	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1806	0	0
T57	6192	6	0	0
T105	11343	8	0	0
T113	10847	48	0	0
T145	90781	218	0	0
T146	5137	23	0	0
T147	11836	37	0	0
T148	5680	15	0	0
T149	21768	84	0	0
T150	7321	106	0	0
T151	20251	62	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1690	0	0
T113	10847	170	0	0
T123	4134	3	0	0
T145	90781	267	0	0
T146	5137	1	0	0
T147	11836	24	0	0
T148	5680	6	0	0
T149	21768	22	0	0
T150	7321	7	0	0
T151	20251	33	0	0
T152	8011	33	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1796	0	0
T57	6192	36	0	0
T109	13898	6	0	0
T113	10847	49	0	0
T145	90781	217	0	0
T146	5137	6	0	0
T147	11836	26	0	0
T148	5680	17	0	0
T149	21768	129	0	0
T150	7321	14	0	0
T151	20251	63	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1246	0	0
T109	13898	8	0	0
T113	10847	28	0	0
T145	90781	241	0	0
T146	5137	13	0	0
T147	11836	24	0	0
T148	5680	12	0	0
T149	21768	59	0	0
T150	7321	8	0	0
T151	20251	70	0	0
T152	8011	20	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1283	0	0
T57	6192	13	0	0
T109	13898	6	0	0
T113	10847	20	0	0
T145	90781	213	0	0
T146	5137	11	0	0
T147	11836	26	0	0
T148	5680	4	0	0
T149	21768	75	0	0
T150	7321	12	0	0
T151	20251	93	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1191	0	0
T57	6192	13	0	0
T113	10847	11	0	0
T123	4134	1	0	0
T145	90781	219	0	0
T147	11836	17	0	0
T148	5680	2	0	0
T149	21768	74	0	0
T150	7321	18	0	0
T151	20251	35	0	0
T152	8011	18	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1159	0	0
T57	6192	7	0	0
T113	10847	15	0	0
T123	4134	1	0	0
T145	90781	197	0	0
T147	11836	5	0	0
T148	5680	10	0	0
T149	21768	45	0	0
T150	7321	7	0	0
T151	20251	69	0	0
T152	8011	32	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1462	0	0
T57	6192	3	0	0
T113	10847	48	0	0
T123	4134	24	0	0
T145	90781	254	0	0
T146	5137	10	0	0
T147	11836	26	0	0
T148	5680	3	0	0
T149	21768	89	0	0
T150	7321	38	0	0
T151	20251	111	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	2386	0	0
T9	936862	21	0	0
T10	3609	0	0	0
T11	530267	0	0	0
T12	194970	0	0	0
T13	343561	25	0	0
T14	1102	0	0	0
T15	1810	0	0	0
T16	338172	0	0	0
T17	914	0	0	0
T40	0	74	0	0
T60	0	34	0	0
T74	0	25	0	0
T77	0	7	0	0
T86	646819	0	0	0
T153	0	100	0	0
T154	0	35	0	0
T155	0	16	0	0
T156	0	83	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1137	0	0
T57	6192	1	0	0
T109	13898	3	0	0
T113	10847	20	0	0
T145	90781	235	0	0
T146	5137	1	0	0
T147	11836	30	0	0
T148	5680	3	0	0
T149	21768	66	0	0
T150	7321	8	0	0
T151	20251	19	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1154	0	0
T57	6192	5	0	0
T123	4134	2	0	0
T145	90781	183	0	0
T146	5137	12	0	0
T147	11836	63	0	0
T148	5680	13	0	0
T149	21768	64	0	0
T150	7321	13	0	0
T151	20251	52	0	0
T152	8011	17	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1103	0	0
T57	6192	8	0	0
T113	10847	15	0	0
T123	4134	6	0	0
T124	10093	9	0	0
T145	90781	205	0	0
T147	11836	21	0	0
T148	5680	1	0	0
T149	21768	84	0	0
T150	7321	6	0	0
T151	20251	29	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1194	0	0
T57	6192	1	0	0
T113	10847	9	0	0
T123	4134	2	0	0
T145	90781	215	0	0
T147	11836	45	0	0
T148	5680	14	0	0
T149	21768	68	0	0
T150	7321	2	0	0
T151	20251	80	0	0
T152	8011	34	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1187	0	0
T57	6192	1	0	0
T113	10847	8	0	0
T145	90781	235	0	0
T146	5137	2	0	0
T147	11836	30	0	0
T148	5680	9	0	0
T149	21768	110	0	0
T150	7321	4	0	0
T151	20251	77	0	0
T152	8011	17	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1256	0	0
T57	6192	1	0	0
T101	20387	10	0	0
T105	11343	5	0	0
T109	13898	3	0	0
T113	10847	3	0	0
T145	90781	234	0	0
T146	5137	8	0	0
T147	11836	33	0	0
T148	5680	3	0	0
T149	21768	69	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1346	0	0
T113	10847	19	0	0
T124	10093	61	0	0
T145	90781	235	0	0
T146	5137	20	0	0
T147	11836	14	0	0
T148	5680	4	0	0
T149	21768	97	0	0
T150	7321	41	0	0
T151	20251	81	0	0
T152	8011	33	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1152	0	0
T57	6192	8	0	0
T101	20387	4	0	0
T109	13898	7	0	0
T113	10847	15	0	0
T145	90781	212	0	0
T146	5137	1	0	0
T147	11836	22	0	0
T148	5680	17	0	0
T149	21768	104	0	0
T150	7321	9	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1443	0	0
T57	6192	21	0	0
T113	10847	7	0	0
T145	90781	224	0	0
T146	5137	10	0	0
T147	11836	50	0	0
T148	5680	4	0	0
T149	21768	75	0	0
T150	7321	35	0	0
T151	20251	81	0	0
T152	8011	15	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1138	0	0
T113	10847	26	0	0
T123	4134	6	0	0
T145	90781	209	0	0
T146	5137	5	0	0
T147	11836	63	0	0
T148	5680	6	0	0
T149	21768	41	0	0
T150	7321	8	0	0
T151	20251	45	0	0
T152	8011	24	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1044	0	0
T57	6192	3	0	0
T113	10847	12	0	0
T145	90781	181	0	0
T146	5137	11	0	0
T147	11836	26	0	0
T148	5680	4	0	0
T149	21768	59	0	0
T150	7321	14	0	0
T151	20251	40	0	0
T152	8011	22	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1244	0	0
T79	4213	6	0	0
T113	10847	9	0	0
T123	4134	3	0	0
T124	10093	12	0	0
T145	90781	235	0	0
T147	11836	82	0	0
T149	21768	83	0	0
T150	7321	3	0	0
T151	20251	84	0	0
T152	8011	30	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1257	0	0
T109	13898	3	0	0
T113	10847	20	0	0
T145	90781	219	0	0
T146	5137	3	0	0
T147	11836	22	0	0
T148	5680	35	0	0
T149	21768	34	0	0
T150	7321	8	0	0
T151	20251	97	0	0
T152	8011	4	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1228	0	0
T57	6192	11	0	0
T113	10847	15	0	0
T145	90781	220	0	0
T146	5137	6	0	0
T147	11836	17	0	0
T148	5680	11	0	0
T149	21768	95	0	0
T150	7321	9	0	0
T151	20251	61	0	0
T152	8011	46	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1159	0	0
T57	6192	10	0	0
T113	10847	17	0	0
T145	90781	207	0	0
T146	5137	3	0	0
T147	11836	18	0	0
T148	5680	4	0	0
T149	21768	88	0	0
T150	7321	14	0	0
T151	20251	52	0	0
T152	8011	56	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396608780	1199	0	0
T113	10847	17	0	0
T123	4134	6	0	0
T124	10093	2	0	0
T145	90781	248	0	0
T147	11836	31	0	0
T148	5680	7	0	0
T149	21768	35	0	0
T150	7321	9	0	0
T151	20251	117	0	0
T152	8011	1	0	0