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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.90 98.30 94.11 98.61 89.36 97.06 95.83 98.07


Total test records in report: 1081
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T821 /workspace/coverage/default/16.spi_device_tpm_rw.1727364854 May 09 01:31:11 PM PDT 24 May 09 01:31:15 PM PDT 24 163719832 ps
T822 /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1939082899 May 09 01:32:31 PM PDT 24 May 09 01:32:41 PM PDT 24 1535049507 ps
T823 /workspace/coverage/default/7.spi_device_mailbox.3524477083 May 09 01:30:07 PM PDT 24 May 09 01:31:42 PM PDT 24 117118000095 ps
T137 /workspace/coverage/default/35.spi_device_stress_all.4184404493 May 09 01:32:54 PM PDT 24 May 09 01:36:39 PM PDT 24 102460437886 ps
T824 /workspace/coverage/default/29.spi_device_upload.1267732830 May 09 01:32:27 PM PDT 24 May 09 01:32:33 PM PDT 24 159688124 ps
T253 /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3898870432 May 09 01:32:10 PM PDT 24 May 09 01:32:26 PM PDT 24 4707429923 ps
T825 /workspace/coverage/default/16.spi_device_tpm_sts_read.133445803 May 09 01:31:07 PM PDT 24 May 09 01:31:10 PM PDT 24 213356703 ps
T826 /workspace/coverage/default/12.spi_device_alert_test.269256714 May 09 01:30:49 PM PDT 24 May 09 01:30:51 PM PDT 24 36567476 ps
T827 /workspace/coverage/default/3.spi_device_upload.3774201712 May 09 01:29:53 PM PDT 24 May 09 01:30:25 PM PDT 24 71736436700 ps
T828 /workspace/coverage/default/30.spi_device_intercept.2192126999 May 09 01:32:25 PM PDT 24 May 09 01:32:49 PM PDT 24 9541659157 ps
T829 /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3031184850 May 09 01:32:16 PM PDT 24 May 09 01:32:20 PM PDT 24 148945745 ps
T830 /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.116531848 May 09 01:29:24 PM PDT 24 May 09 01:33:14 PM PDT 24 95605584754 ps
T831 /workspace/coverage/default/45.spi_device_upload.4224423726 May 09 01:33:34 PM PDT 24 May 09 01:33:38 PM PDT 24 195446179 ps
T832 /workspace/coverage/default/8.spi_device_csb_read.1715647633 May 09 01:30:10 PM PDT 24 May 09 01:30:12 PM PDT 24 24845719 ps
T833 /workspace/coverage/default/5.spi_device_upload.3484615059 May 09 01:29:58 PM PDT 24 May 09 01:30:07 PM PDT 24 1289270361 ps
T834 /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3458208072 May 09 01:30:33 PM PDT 24 May 09 01:30:44 PM PDT 24 4236754444 ps
T835 /workspace/coverage/default/1.spi_device_alert_test.1505702115 May 09 01:29:37 PM PDT 24 May 09 01:29:38 PM PDT 24 17012205 ps
T836 /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3246682345 May 09 01:33:31 PM PDT 24 May 09 01:33:43 PM PDT 24 1191152827 ps
T837 /workspace/coverage/default/39.spi_device_cfg_cmd.3757224799 May 09 01:33:06 PM PDT 24 May 09 01:33:12 PM PDT 24 1946948290 ps
T838 /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1370333719 May 09 01:33:40 PM PDT 24 May 09 01:33:52 PM PDT 24 2172364397 ps
T839 /workspace/coverage/default/27.spi_device_stress_all.924623479 May 09 01:32:26 PM PDT 24 May 09 01:33:50 PM PDT 24 7365769389 ps
T840 /workspace/coverage/default/46.spi_device_stress_all.358653522 May 09 01:33:49 PM PDT 24 May 09 01:34:49 PM PDT 24 19707420487 ps
T243 /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2790858142 May 09 01:33:20 PM PDT 24 May 09 01:35:43 PM PDT 24 175918485532 ps
T841 /workspace/coverage/default/16.spi_device_stress_all.2388020414 May 09 01:31:13 PM PDT 24 May 09 01:31:15 PM PDT 24 53206078 ps
T19 /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3776211950 May 09 01:32:32 PM PDT 24 May 09 01:35:38 PM PDT 24 28998237596 ps
T842 /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2882066118 May 09 01:32:28 PM PDT 24 May 09 01:32:32 PM PDT 24 112897181 ps
T843 /workspace/coverage/default/14.spi_device_upload.2339054843 May 09 01:30:57 PM PDT 24 May 09 01:31:01 PM PDT 24 98184214 ps
T844 /workspace/coverage/default/15.spi_device_flash_mode.3503354132 May 09 01:30:59 PM PDT 24 May 09 01:31:53 PM PDT 24 4047630719 ps
T845 /workspace/coverage/default/3.spi_device_tpm_sts_read.236681702 May 09 01:29:48 PM PDT 24 May 09 01:29:50 PM PDT 24 217157234 ps
T846 /workspace/coverage/default/18.spi_device_tpm_rw.2965952549 May 09 01:31:15 PM PDT 24 May 09 01:31:16 PM PDT 24 11804310 ps
T847 /workspace/coverage/default/33.spi_device_alert_test.1327722776 May 09 01:32:36 PM PDT 24 May 09 01:32:39 PM PDT 24 35759629 ps
T848 /workspace/coverage/default/25.spi_device_flash_mode.4082541576 May 09 01:32:14 PM PDT 24 May 09 01:32:34 PM PDT 24 4612016813 ps
T849 /workspace/coverage/default/7.spi_device_read_buffer_direct.3784507843 May 09 01:30:12 PM PDT 24 May 09 01:30:23 PM PDT 24 1629880919 ps
T850 /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2043962084 May 09 01:31:45 PM PDT 24 May 09 01:31:48 PM PDT 24 286106609 ps
T851 /workspace/coverage/default/45.spi_device_tpm_sts_read.2211472091 May 09 01:33:31 PM PDT 24 May 09 01:33:33 PM PDT 24 45020439 ps
T852 /workspace/coverage/default/42.spi_device_alert_test.2115027112 May 09 01:33:18 PM PDT 24 May 09 01:33:21 PM PDT 24 15424191 ps
T853 /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.376206900 May 09 01:30:33 PM PDT 24 May 09 01:30:38 PM PDT 24 1187989213 ps
T854 /workspace/coverage/default/9.spi_device_alert_test.1527366882 May 09 01:30:35 PM PDT 24 May 09 01:30:38 PM PDT 24 26879294 ps
T855 /workspace/coverage/default/33.spi_device_tpm_all.3213861888 May 09 01:32:39 PM PDT 24 May 09 01:32:51 PM PDT 24 1825318998 ps
T856 /workspace/coverage/default/12.spi_device_tpm_sts_read.641898216 May 09 01:30:41 PM PDT 24 May 09 01:30:42 PM PDT 24 103380566 ps
T223 /workspace/coverage/default/44.spi_device_stress_all.4211125601 May 09 01:33:31 PM PDT 24 May 09 01:36:20 PM PDT 24 7015689594 ps
T232 /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3293508636 May 09 01:29:48 PM PDT 24 May 09 01:30:15 PM PDT 24 9127963708 ps
T857 /workspace/coverage/default/49.spi_device_tpm_all.3692530804 May 09 01:34:30 PM PDT 24 May 09 01:34:55 PM PDT 24 4867510736 ps
T858 /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4277071824 May 09 01:33:10 PM PDT 24 May 09 01:33:13 PM PDT 24 716587391 ps
T859 /workspace/coverage/default/3.spi_device_intercept.3164957711 May 09 01:29:51 PM PDT 24 May 09 01:29:54 PM PDT 24 366431212 ps
T860 /workspace/coverage/default/5.spi_device_tpm_all.3798983686 May 09 01:29:59 PM PDT 24 May 09 01:30:15 PM PDT 24 7612417553 ps
T861 /workspace/coverage/default/24.spi_device_stress_all.2490631471 May 09 01:32:08 PM PDT 24 May 09 01:32:10 PM PDT 24 85072054 ps
T862 /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1903650598 May 09 01:33:40 PM PDT 24 May 09 01:33:49 PM PDT 24 3028569872 ps
T863 /workspace/coverage/default/18.spi_device_read_buffer_direct.1023786263 May 09 01:31:21 PM PDT 24 May 09 01:31:33 PM PDT 24 2927161047 ps
T864 /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3907649782 May 09 01:32:06 PM PDT 24 May 09 01:32:09 PM PDT 24 99688385 ps
T865 /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3107906383 May 09 01:32:26 PM PDT 24 May 09 01:32:32 PM PDT 24 1909216992 ps
T866 /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.681463808 May 09 01:33:06 PM PDT 24 May 09 01:33:17 PM PDT 24 11639123998 ps
T138 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2546070529 May 09 01:30:55 PM PDT 24 May 09 01:31:48 PM PDT 24 6057020583 ps
T867 /workspace/coverage/default/33.spi_device_mailbox.395636243 May 09 01:32:35 PM PDT 24 May 09 01:32:50 PM PDT 24 645670570 ps
T249 /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.798699518 May 09 01:30:54 PM PDT 24 May 09 01:31:49 PM PDT 24 10263134009 ps
T868 /workspace/coverage/default/6.spi_device_tpm_sts_read.2238911744 May 09 01:30:08 PM PDT 24 May 09 01:30:10 PM PDT 24 85641721 ps
T251 /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2330008025 May 09 01:33:23 PM PDT 24 May 09 01:37:52 PM PDT 24 128351594309 ps
T869 /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1154455395 May 09 01:33:38 PM PDT 24 May 09 01:33:43 PM PDT 24 2851153230 ps
T870 /workspace/coverage/default/12.spi_device_tpm_rw.3710977407 May 09 01:30:38 PM PDT 24 May 09 01:30:40 PM PDT 24 281534815 ps
T871 /workspace/coverage/default/7.spi_device_flash_all.620576699 May 09 01:30:06 PM PDT 24 May 09 01:32:00 PM PDT 24 31053723312 ps
T872 /workspace/coverage/default/2.spi_device_intercept.4239806196 May 09 01:29:48 PM PDT 24 May 09 01:29:54 PM PDT 24 156152343 ps
T873 /workspace/coverage/default/47.spi_device_cfg_cmd.2854779567 May 09 01:34:00 PM PDT 24 May 09 01:34:04 PM PDT 24 751596204 ps
T874 /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2987551216 May 09 01:31:13 PM PDT 24 May 09 01:34:51 PM PDT 24 35764318969 ps
T875 /workspace/coverage/default/41.spi_device_read_buffer_direct.3922528612 May 09 01:33:22 PM PDT 24 May 09 01:33:26 PM PDT 24 292678933 ps
T876 /workspace/coverage/default/27.spi_device_flash_all.15190389 May 09 01:32:17 PM PDT 24 May 09 01:33:07 PM PDT 24 3723759434 ps
T877 /workspace/coverage/default/48.spi_device_alert_test.2569154507 May 09 01:34:15 PM PDT 24 May 09 01:34:17 PM PDT 24 14432849 ps
T878 /workspace/coverage/default/17.spi_device_mailbox.1236192691 May 09 01:31:07 PM PDT 24 May 09 01:31:29 PM PDT 24 1597345825 ps
T235 /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2409143671 May 09 01:31:53 PM PDT 24 May 09 01:43:25 PM PDT 24 337816265844 ps
T879 /workspace/coverage/default/40.spi_device_read_buffer_direct.1404693903 May 09 01:33:14 PM PDT 24 May 09 01:33:26 PM PDT 24 1359033299 ps
T880 /workspace/coverage/default/10.spi_device_flash_mode.1578859400 May 09 01:30:34 PM PDT 24 May 09 01:30:40 PM PDT 24 145376603 ps
T881 /workspace/coverage/default/23.spi_device_alert_test.1050777699 May 09 01:32:03 PM PDT 24 May 09 01:32:04 PM PDT 24 13894367 ps
T882 /workspace/coverage/default/18.spi_device_upload.891287922 May 09 01:31:13 PM PDT 24 May 09 01:31:40 PM PDT 24 14592406084 ps
T883 /workspace/coverage/default/7.spi_device_csb_read.1412764636 May 09 01:30:02 PM PDT 24 May 09 01:30:04 PM PDT 24 57989114 ps
T884 /workspace/coverage/default/49.spi_device_tpm_rw.2772678649 May 09 01:34:12 PM PDT 24 May 09 01:34:14 PM PDT 24 23099362 ps
T241 /workspace/coverage/default/32.spi_device_flash_all.3130992247 May 09 01:32:39 PM PDT 24 May 09 01:34:20 PM PDT 24 77922534536 ps
T885 /workspace/coverage/default/15.spi_device_tpm_sts_read.2779578005 May 09 01:31:12 PM PDT 24 May 09 01:31:14 PM PDT 24 282349222 ps
T886 /workspace/coverage/default/36.spi_device_csb_read.590807917 May 09 01:32:53 PM PDT 24 May 09 01:32:55 PM PDT 24 60094056 ps
T887 /workspace/coverage/default/46.spi_device_tpm_rw.2429371331 May 09 01:33:53 PM PDT 24 May 09 01:33:55 PM PDT 24 15373694 ps
T61 /workspace/coverage/default/0.spi_device_ram_cfg.1935725092 May 09 01:29:16 PM PDT 24 May 09 01:29:17 PM PDT 24 17171932 ps
T888 /workspace/coverage/default/38.spi_device_tpm_all.2336717297 May 09 01:33:06 PM PDT 24 May 09 01:33:54 PM PDT 24 18050607344 ps
T889 /workspace/coverage/default/41.spi_device_tpm_sts_read.2910898946 May 09 01:33:26 PM PDT 24 May 09 01:33:28 PM PDT 24 65187145 ps
T890 /workspace/coverage/default/30.spi_device_flash_mode.3054890836 May 09 01:32:25 PM PDT 24 May 09 01:32:32 PM PDT 24 111758819 ps
T891 /workspace/coverage/default/37.spi_device_read_buffer_direct.3281996903 May 09 01:33:15 PM PDT 24 May 09 01:33:24 PM PDT 24 7213644851 ps
T892 /workspace/coverage/default/49.spi_device_cfg_cmd.3419288995 May 09 01:34:13 PM PDT 24 May 09 01:34:20 PM PDT 24 360949334 ps
T893 /workspace/coverage/default/22.spi_device_upload.1241372451 May 09 01:31:49 PM PDT 24 May 09 01:31:56 PM PDT 24 1096579272 ps
T894 /workspace/coverage/default/14.spi_device_tpm_sts_read.1582715490 May 09 01:30:56 PM PDT 24 May 09 01:30:58 PM PDT 24 688887431 ps
T895 /workspace/coverage/default/32.spi_device_flash_and_tpm.2719421181 May 09 01:32:36 PM PDT 24 May 09 01:33:03 PM PDT 24 3316628345 ps
T896 /workspace/coverage/default/37.spi_device_flash_mode.2915772306 May 09 01:33:06 PM PDT 24 May 09 01:33:31 PM PDT 24 1420774613 ps
T897 /workspace/coverage/default/42.spi_device_flash_all.3854957644 May 09 03:01:42 PM PDT 24 May 09 03:02:29 PM PDT 24 5968998615 ps
T898 /workspace/coverage/default/19.spi_device_tpm_sts_read.1437204960 May 09 01:31:34 PM PDT 24 May 09 01:31:36 PM PDT 24 64858763 ps
T899 /workspace/coverage/default/39.spi_device_flash_all.3873515386 May 09 01:33:10 PM PDT 24 May 09 01:33:12 PM PDT 24 23767907 ps
T900 /workspace/coverage/default/16.spi_device_flash_all.3529658528 May 09 01:31:05 PM PDT 24 May 09 01:32:52 PM PDT 24 61695598049 ps
T901 /workspace/coverage/default/29.spi_device_intercept.2902447216 May 09 01:32:15 PM PDT 24 May 09 01:32:18 PM PDT 24 260560388 ps
T902 /workspace/coverage/default/48.spi_device_flash_all.3479499552 May 09 01:34:05 PM PDT 24 May 09 01:36:12 PM PDT 24 65037894019 ps
T903 /workspace/coverage/default/43.spi_device_tpm_sts_read.2475576756 May 09 01:33:16 PM PDT 24 May 09 01:33:18 PM PDT 24 80695366 ps
T904 /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3904002744 May 09 01:30:09 PM PDT 24 May 09 01:30:12 PM PDT 24 98149437 ps
T905 /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3734951479 May 09 01:30:34 PM PDT 24 May 09 01:30:39 PM PDT 24 1222783458 ps
T906 /workspace/coverage/default/45.spi_device_flash_all.1641099976 May 09 01:33:52 PM PDT 24 May 09 01:34:24 PM PDT 24 7357597042 ps
T907 /workspace/coverage/default/42.spi_device_intercept.3467540139 May 09 01:33:21 PM PDT 24 May 09 01:33:29 PM PDT 24 418204914 ps
T908 /workspace/coverage/default/27.spi_device_csb_read.2230951271 May 09 01:32:19 PM PDT 24 May 09 01:32:21 PM PDT 24 46776443 ps
T909 /workspace/coverage/default/35.spi_device_csb_read.431932112 May 09 01:32:42 PM PDT 24 May 09 01:32:43 PM PDT 24 48008462 ps
T910 /workspace/coverage/default/11.spi_device_alert_test.3974639783 May 09 01:30:37 PM PDT 24 May 09 01:30:39 PM PDT 24 61480165 ps
T911 /workspace/coverage/default/25.spi_device_tpm_all.1759157268 May 09 01:32:10 PM PDT 24 May 09 01:32:15 PM PDT 24 1082042806 ps
T912 /workspace/coverage/default/9.spi_device_intercept.2842168639 May 09 01:30:19 PM PDT 24 May 09 01:30:23 PM PDT 24 338544965 ps
T913 /workspace/coverage/default/20.spi_device_flash_all.2293075933 May 09 01:31:49 PM PDT 24 May 09 01:32:45 PM PDT 24 11482908714 ps
T914 /workspace/coverage/default/40.spi_device_csb_read.196804860 May 09 01:33:11 PM PDT 24 May 09 01:33:13 PM PDT 24 90899078 ps
T915 /workspace/coverage/default/12.spi_device_tpm_all.3072978097 May 09 01:30:41 PM PDT 24 May 09 01:31:16 PM PDT 24 2738833404 ps
T916 /workspace/coverage/default/17.spi_device_alert_test.1054647704 May 09 01:31:12 PM PDT 24 May 09 01:31:14 PM PDT 24 12600726 ps
T917 /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.515046535 May 09 01:32:25 PM PDT 24 May 09 01:39:42 PM PDT 24 222038504609 ps
T918 /workspace/coverage/default/13.spi_device_flash_and_tpm.1337016112 May 09 01:30:57 PM PDT 24 May 09 01:32:06 PM PDT 24 11713281230 ps
T919 /workspace/coverage/default/7.spi_device_upload.1183247530 May 09 01:30:03 PM PDT 24 May 09 01:30:08 PM PDT 24 488945524 ps
T920 /workspace/coverage/default/37.spi_device_upload.2258128447 May 09 01:33:10 PM PDT 24 May 09 01:33:20 PM PDT 24 644434262 ps
T227 /workspace/coverage/default/23.spi_device_flash_and_tpm.2355420822 May 09 01:31:56 PM PDT 24 May 09 01:41:18 PM PDT 24 310526904698 ps
T921 /workspace/coverage/default/29.spi_device_mailbox.1346001964 May 09 01:32:26 PM PDT 24 May 09 01:32:56 PM PDT 24 2713525595 ps
T922 /workspace/coverage/default/21.spi_device_tpm_all.28427522 May 09 01:31:48 PM PDT 24 May 09 01:32:05 PM PDT 24 10438771965 ps
T923 /workspace/coverage/default/1.spi_device_tpm_sts_read.1981774466 May 09 01:29:31 PM PDT 24 May 09 01:29:32 PM PDT 24 16618486 ps
T924 /workspace/coverage/default/38.spi_device_pass_cmd_filtering.703722489 May 09 01:33:07 PM PDT 24 May 09 01:33:33 PM PDT 24 8030650448 ps
T925 /workspace/coverage/default/24.spi_device_flash_and_tpm.183235815 May 09 01:32:04 PM PDT 24 May 09 01:34:07 PM PDT 24 38277599281 ps
T926 /workspace/coverage/default/44.spi_device_intercept.3237618505 May 09 01:33:35 PM PDT 24 May 09 01:33:45 PM PDT 24 7811328863 ps
T927 /workspace/coverage/default/39.spi_device_tpm_sts_read.2253921178 May 09 01:33:07 PM PDT 24 May 09 01:33:09 PM PDT 24 16995326 ps
T928 /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2742338510 May 09 01:32:14 PM PDT 24 May 09 01:32:24 PM PDT 24 3371068326 ps
T929 /workspace/coverage/default/28.spi_device_read_buffer_direct.1934931624 May 09 01:32:16 PM PDT 24 May 09 01:32:35 PM PDT 24 1834895318 ps
T930 /workspace/coverage/default/40.spi_device_tpm_all.455256331 May 09 01:33:13 PM PDT 24 May 09 01:33:16 PM PDT 24 227520579 ps
T254 /workspace/coverage/default/33.spi_device_flash_and_tpm.1896222841 May 09 01:32:49 PM PDT 24 May 09 01:35:05 PM PDT 24 58365208914 ps
T931 /workspace/coverage/default/43.spi_device_tpm_all.2360762187 May 09 01:33:24 PM PDT 24 May 09 01:33:39 PM PDT 24 2672928363 ps
T932 /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.509387416 May 09 01:31:52 PM PDT 24 May 09 01:31:53 PM PDT 24 26604829 ps
T933 /workspace/coverage/default/8.spi_device_cfg_cmd.3455445228 May 09 01:30:14 PM PDT 24 May 09 01:30:18 PM PDT 24 109610043 ps
T934 /workspace/coverage/default/9.spi_device_read_buffer_direct.955938048 May 09 01:30:28 PM PDT 24 May 09 01:30:36 PM PDT 24 522853493 ps
T935 /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.392932248 May 09 01:31:04 PM PDT 24 May 09 01:32:40 PM PDT 24 26763279401 ps
T936 /workspace/coverage/default/16.spi_device_mailbox.429587430 May 09 01:31:12 PM PDT 24 May 09 01:31:35 PM PDT 24 12040149662 ps
T937 /workspace/coverage/default/46.spi_device_mailbox.2943875857 May 09 01:33:53 PM PDT 24 May 09 01:34:20 PM PDT 24 7011568482 ps
T938 /workspace/coverage/default/25.spi_device_tpm_sts_read.3005673870 May 09 01:32:07 PM PDT 24 May 09 01:32:08 PM PDT 24 257176410 ps
T939 /workspace/coverage/default/45.spi_device_mailbox.171104391 May 09 01:33:42 PM PDT 24 May 09 01:34:10 PM PDT 24 1939875207 ps
T316 /workspace/coverage/default/11.spi_device_flash_mode.2838454546 May 09 01:30:34 PM PDT 24 May 09 01:30:48 PM PDT 24 804799107 ps
T940 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1249802772 May 09 01:29:43 PM PDT 24 May 09 01:30:40 PM PDT 24 6042228861 ps
T941 /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3147636823 May 09 01:33:18 PM PDT 24 May 09 01:33:23 PM PDT 24 1788863957 ps
T942 /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1333813608 May 09 01:29:24 PM PDT 24 May 09 01:29:36 PM PDT 24 5121351498 ps
T943 /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2426154267 May 09 01:33:15 PM PDT 24 May 09 01:37:49 PM PDT 24 29335471125 ps
T944 /workspace/coverage/default/40.spi_device_mailbox.1691223902 May 09 01:33:07 PM PDT 24 May 09 01:34:26 PM PDT 24 21063852217 ps
T945 /workspace/coverage/default/12.spi_device_stress_all.3957710485 May 09 01:30:54 PM PDT 24 May 09 01:34:19 PM PDT 24 73459375096 ps
T946 /workspace/coverage/default/27.spi_device_tpm_sts_read.3071559280 May 09 01:32:08 PM PDT 24 May 09 01:32:10 PM PDT 24 46217931 ps
T947 /workspace/coverage/default/13.spi_device_flash_all.2508375533 May 09 01:30:50 PM PDT 24 May 09 01:31:32 PM PDT 24 22414259023 ps
T948 /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.529431297 May 09 01:33:20 PM PDT 24 May 09 01:33:40 PM PDT 24 1563230420 ps
T949 /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3501815161 May 09 01:30:37 PM PDT 24 May 09 01:30:54 PM PDT 24 5320745059 ps
T950 /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3508941322 May 09 01:33:04 PM PDT 24 May 09 01:33:19 PM PDT 24 1873484753 ps
T951 /workspace/coverage/default/8.spi_device_tpm_sts_read.2097216633 May 09 01:30:11 PM PDT 24 May 09 01:30:13 PM PDT 24 25772134 ps
T952 /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2428636540 May 09 01:34:08 PM PDT 24 May 09 01:35:57 PM PDT 24 40488349315 ps
T953 /workspace/coverage/default/14.spi_device_read_buffer_direct.563685864 May 09 01:30:56 PM PDT 24 May 09 01:31:12 PM PDT 24 3115236267 ps
T954 /workspace/coverage/default/16.spi_device_tpm_all.1500777205 May 09 01:31:13 PM PDT 24 May 09 01:31:22 PM PDT 24 5361094170 ps
T955 /workspace/coverage/default/17.spi_device_tpm_sts_read.3195555375 May 09 01:31:01 PM PDT 24 May 09 01:31:03 PM PDT 24 35191075 ps
T956 /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3605657866 May 09 01:29:50 PM PDT 24 May 09 01:31:03 PM PDT 24 34594750902 ps
T957 /workspace/coverage/default/47.spi_device_flash_all.1293559200 May 09 01:34:06 PM PDT 24 May 09 01:35:26 PM PDT 24 9810241537 ps
T958 /workspace/coverage/default/40.spi_device_tpm_rw.3657869217 May 09 01:33:07 PM PDT 24 May 09 01:33:09 PM PDT 24 67955237 ps
T959 /workspace/coverage/default/43.spi_device_tpm_rw.3333783538 May 09 01:33:21 PM PDT 24 May 09 01:33:24 PM PDT 24 330213507 ps
T960 /workspace/coverage/default/11.spi_device_mailbox.2073752138 May 09 01:30:31 PM PDT 24 May 09 01:30:44 PM PDT 24 393077854 ps
T961 /workspace/coverage/default/4.spi_device_alert_test.3947247406 May 09 01:30:02 PM PDT 24 May 09 01:30:04 PM PDT 24 40923506 ps
T139 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3220178158 May 09 01:16:21 PM PDT 24 May 09 01:16:26 PM PDT 24 191859726 ps
T962 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1239876534 May 09 01:16:23 PM PDT 24 May 09 01:16:26 PM PDT 24 15930525 ps
T963 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4000264080 May 09 01:16:23 PM PDT 24 May 09 01:16:25 PM PDT 24 156979729 ps
T57 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.371027846 May 09 01:15:53 PM PDT 24 May 09 01:15:58 PM PDT 24 74620746 ps
T58 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.276232773 May 09 01:16:22 PM PDT 24 May 09 01:16:31 PM PDT 24 1090181915 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2090117856 May 09 01:15:49 PM PDT 24 May 09 01:15:51 PM PDT 24 324577456 ps
T59 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3584414182 May 09 01:16:26 PM PDT 24 May 09 01:16:32 PM PDT 24 33283056 ps
T113 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1746749466 May 09 01:16:25 PM PDT 24 May 09 01:16:31 PM PDT 24 108500467 ps
T964 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3070694397 May 09 01:16:27 PM PDT 24 May 09 01:16:31 PM PDT 24 44882284 ps
T94 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2302283436 May 09 01:16:22 PM PDT 24 May 09 01:16:26 PM PDT 24 40737222 ps
T98 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3369871140 May 09 01:16:08 PM PDT 24 May 09 01:16:13 PM PDT 24 499949417 ps
T965 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2231723766 May 09 01:16:23 PM PDT 24 May 09 01:16:26 PM PDT 24 14224613 ps
T99 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3040214404 May 09 01:16:22 PM PDT 24 May 09 01:16:25 PM PDT 24 262545583 ps
T95 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3386006142 May 09 01:15:49 PM PDT 24 May 09 01:15:54 PM PDT 24 529519422 ps
T966 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.452946567 May 09 01:16:22 PM PDT 24 May 09 01:16:24 PM PDT 24 12145630 ps
T96 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1983225244 May 09 01:16:11 PM PDT 24 May 09 01:16:34 PM PDT 24 3626738591 ps
T967 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1708603360 May 09 01:16:24 PM PDT 24 May 09 01:16:28 PM PDT 24 17309208 ps
T968 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1082877065 May 09 01:16:22 PM PDT 24 May 09 01:16:23 PM PDT 24 46665555 ps
T108 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1880568448 May 09 01:16:25 PM PDT 24 May 09 01:16:33 PM PDT 24 60634635 ps
T969 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2494061001 May 09 01:16:25 PM PDT 24 May 09 01:16:29 PM PDT 24 19273604 ps
T114 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.109015122 May 09 01:15:51 PM PDT 24 May 09 01:16:28 PM PDT 24 2269666431 ps
T970 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3888900818 May 09 01:15:48 PM PDT 24 May 09 01:15:50 PM PDT 24 22702334 ps
T97 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3924243532 May 09 01:16:11 PM PDT 24 May 09 01:16:30 PM PDT 24 709072063 ps
T971 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3188844716 May 09 01:16:27 PM PDT 24 May 09 01:16:32 PM PDT 24 14077740 ps
T115 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3323460796 May 09 01:15:50 PM PDT 24 May 09 01:15:55 PM PDT 24 46242878 ps
T972 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.342817014 May 09 01:15:53 PM PDT 24 May 09 01:16:00 PM PDT 24 302239695 ps
T101 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.729440521 May 09 01:15:50 PM PDT 24 May 09 01:15:57 PM PDT 24 815546545 ps
T102 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1654780815 May 09 01:16:10 PM PDT 24 May 09 01:16:16 PM PDT 24 217922556 ps
T106 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2522740075 May 09 01:16:09 PM PDT 24 May 09 01:16:15 PM PDT 24 127950511 ps
T116 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2637998305 May 09 01:15:50 PM PDT 24 May 09 01:16:13 PM PDT 24 1282254065 ps
T973 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1556084021 May 09 01:15:52 PM PDT 24 May 09 01:15:56 PM PDT 24 11160048 ps
T260 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3016359256 May 09 01:16:26 PM PDT 24 May 09 01:16:36 PM PDT 24 106144054 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2610663317 May 09 01:15:52 PM PDT 24 May 09 01:15:57 PM PDT 24 73896735 ps
T974 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.906202217 May 09 01:16:25 PM PDT 24 May 09 01:16:30 PM PDT 24 18145402 ps
T975 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2272063627 May 09 01:16:09 PM PDT 24 May 09 01:16:12 PM PDT 24 57190859 ps
T104 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.516900398 May 09 01:16:23 PM PDT 24 May 09 01:16:29 PM PDT 24 61774195 ps
T976 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.215084066 May 09 01:16:10 PM PDT 24 May 09 01:16:16 PM PDT 24 63067604 ps
T977 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1865619949 May 09 01:16:23 PM PDT 24 May 09 01:16:26 PM PDT 24 29989564 ps
T145 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1475771441 May 09 01:15:41 PM PDT 24 May 09 01:15:56 PM PDT 24 907836807 ps
T103 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1470150967 May 09 01:15:54 PM PDT 24 May 09 01:16:02 PM PDT 24 147050717 ps
T261 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1028757610 May 09 01:16:25 PM PDT 24 May 09 01:16:48 PM PDT 24 615085217 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1785134194 May 09 01:16:10 PM PDT 24 May 09 01:16:17 PM PDT 24 483980085 ps
T978 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.269307896 May 09 01:16:10 PM PDT 24 May 09 01:16:16 PM PDT 24 340611825 ps
T146 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4035974937 May 09 01:15:39 PM PDT 24 May 09 01:15:43 PM PDT 24 205579697 ps
T105 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1969945180 May 09 01:16:23 PM PDT 24 May 09 01:16:28 PM PDT 24 226902055 ps
T979 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1326302959 May 09 01:15:54 PM PDT 24 May 09 01:15:58 PM PDT 24 11150074 ps
T264 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3112845278 May 09 01:16:10 PM PDT 24 May 09 01:16:20 PM PDT 24 437581594 ps
T980 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.451099463 May 09 01:16:25 PM PDT 24 May 09 01:16:29 PM PDT 24 41989894 ps
T981 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.8995413 May 09 01:16:11 PM PDT 24 May 09 01:16:18 PM PDT 24 59361717 ps
T982 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4001640858 May 09 01:16:25 PM PDT 24 May 09 01:16:29 PM PDT 24 44449118 ps
T983 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3808473081 May 09 01:16:10 PM PDT 24 May 09 01:16:14 PM PDT 24 13683123 ps
T984 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2136940660 May 09 01:16:25 PM PDT 24 May 09 01:16:30 PM PDT 24 115957396 ps
T985 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.569692984 May 09 01:15:53 PM PDT 24 May 09 01:16:00 PM PDT 24 634275272 ps
T147 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1387863216 May 09 01:15:52 PM PDT 24 May 09 01:15:58 PM PDT 24 236759155 ps
T148 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2545431801 May 09 01:16:10 PM PDT 24 May 09 01:16:15 PM PDT 24 236748620 ps
T109 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1359671465 May 09 01:16:11 PM PDT 24 May 09 01:16:17 PM PDT 24 144803004 ps
T986 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.244142577 May 09 01:15:53 PM PDT 24 May 09 01:16:00 PM PDT 24 568442820 ps
T107 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2352677268 May 09 01:16:25 PM PDT 24 May 09 01:16:33 PM PDT 24 119299326 ps
T987 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3717273881 May 09 01:15:43 PM PDT 24 May 09 01:15:59 PM PDT 24 1536052077 ps
T118 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1636078281 May 09 01:16:12 PM PDT 24 May 09 01:16:16 PM PDT 24 73773653 ps
T988 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1877910247 May 09 01:15:50 PM PDT 24 May 09 01:15:57 PM PDT 24 222711955 ps
T119 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3509203080 May 09 01:16:10 PM PDT 24 May 09 01:16:15 PM PDT 24 47180978 ps
T989 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.150151793 May 09 01:16:24 PM PDT 24 May 09 01:16:28 PM PDT 24 49282298 ps
T149 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.344531073 May 09 01:16:25 PM PDT 24 May 09 01:16:33 PM PDT 24 1360669811 ps
T120 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.312310289 May 09 01:16:11 PM PDT 24 May 09 01:16:17 PM PDT 24 71327725 ps
T110 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3712342145 May 09 01:16:09 PM PDT 24 May 09 01:16:13 PM PDT 24 86332333 ps
T990 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1358386601 May 09 01:15:49 PM PDT 24 May 09 01:15:59 PM PDT 24 115643138 ps
T991 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.455743273 May 09 01:16:24 PM PDT 24 May 09 01:16:27 PM PDT 24 18253572 ps
T992 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4194636238 May 09 01:16:09 PM PDT 24 May 09 01:16:13 PM PDT 24 167491168 ps
T993 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1880125571 May 09 01:16:10 PM PDT 24 May 09 01:16:16 PM PDT 24 100644515 ps
T994 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3228171214 May 09 01:15:50 PM PDT 24 May 09 01:16:29 PM PDT 24 1925474678 ps
T995 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4027022043 May 09 01:15:50 PM PDT 24 May 09 01:16:01 PM PDT 24 1177325143 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3061047115 May 09 01:15:41 PM PDT 24 May 09 01:15:45 PM PDT 24 29829109 ps
T150 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1063679159 May 09 01:16:11 PM PDT 24 May 09 01:16:16 PM PDT 24 76290058 ps
T996 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1636332182 May 09 01:16:11 PM PDT 24 May 09 01:16:16 PM PDT 24 55720597 ps
T151 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1655644645 May 09 01:16:22 PM PDT 24 May 09 01:16:28 PM PDT 24 1841112824 ps
T997 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1834784565 May 09 01:15:52 PM PDT 24 May 09 01:15:58 PM PDT 24 162616009 ps
T998 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.698763555 May 09 01:15:51 PM PDT 24 May 09 01:15:55 PM PDT 24 72037545 ps
T152 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3529596655 May 09 01:16:25 PM PDT 24 May 09 01:16:31 PM PDT 24 84342834 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3348126744 May 09 01:15:53 PM PDT 24 May 09 01:15:58 PM PDT 24 34545962 ps
T999 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2340724603 May 09 01:16:23 PM PDT 24 May 09 01:16:26 PM PDT 24 42943262 ps
T1000 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.729906573 May 09 01:15:52 PM PDT 24 May 09 01:15:56 PM PDT 24 12287862 ps
T1001 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.190238626 May 09 01:16:10 PM PDT 24 May 09 01:16:13 PM PDT 24 45461266 ps
T1002 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2602259512 May 09 01:15:51 PM PDT 24 May 09 01:15:54 PM PDT 24 24008594 ps
T262 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2172444860 May 09 01:15:52 PM PDT 24 May 09 01:16:10 PM PDT 24 2182793972 ps
T1003 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2153985266 May 09 01:15:51 PM PDT 24 May 09 01:15:57 PM PDT 24 257412967 ps
T1004 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1056551677 May 09 01:16:25 PM PDT 24 May 09 01:16:30 PM PDT 24 21909400 ps
T1005 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1174141691 May 09 01:15:43 PM PDT 24 May 09 01:15:53 PM PDT 24 2912620015 ps
T1006 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.154277283 May 09 01:15:39 PM PDT 24 May 09 01:15:41 PM PDT 24 26248370 ps
T123 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2845435223 May 09 01:15:43 PM PDT 24 May 09 01:15:46 PM PDT 24 86161503 ps
T1007 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3185506130 May 09 01:16:10 PM PDT 24 May 09 01:16:15 PM PDT 24 171749458 ps
T1008 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3195207213 May 09 01:16:27 PM PDT 24 May 09 01:16:31 PM PDT 24 37585622 ps
T1009 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1439782042 May 09 01:15:50 PM PDT 24 May 09 01:15:55 PM PDT 24 117612966 ps
T1010 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.409827276 May 09 01:16:25 PM PDT 24 May 09 01:16:34 PM PDT 24 305323640 ps
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