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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.90 98.30 94.11 98.61 89.36 97.06 95.83 98.07


Total test records in report: 1081
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T1011 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3482400847 May 09 01:16:11 PM PDT 24 May 09 01:16:15 PM PDT 24 16857811 ps
T1012 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2248998901 May 09 01:16:09 PM PDT 24 May 09 01:16:12 PM PDT 24 47225001 ps
T124 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2168411940 May 09 01:16:11 PM PDT 24 May 09 01:16:17 PM PDT 24 531279885 ps
T263 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1130019102 May 09 01:16:24 PM PDT 24 May 09 01:16:33 PM PDT 24 428696911 ps
T1013 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.597835197 May 09 01:16:23 PM PDT 24 May 09 01:16:27 PM PDT 24 372843937 ps
T1014 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3669157296 May 09 01:16:08 PM PDT 24 May 09 01:16:10 PM PDT 24 25914926 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3670513641 May 09 01:15:45 PM PDT 24 May 09 01:15:50 PM PDT 24 132755172 ps
T1015 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.655890710 May 09 01:16:23 PM PDT 24 May 09 01:16:25 PM PDT 24 47354728 ps
T1016 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1392080130 May 09 01:16:11 PM PDT 24 May 09 01:16:16 PM PDT 24 27775100 ps
T79 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4040993704 May 09 01:15:42 PM PDT 24 May 09 01:15:46 PM PDT 24 110920669 ps
T1017 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1404491702 May 09 01:15:43 PM PDT 24 May 09 01:16:00 PM PDT 24 786366219 ps
T1018 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2985324549 May 09 01:16:11 PM PDT 24 May 09 01:16:15 PM PDT 24 31811524 ps
T1019 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1655034708 May 09 01:16:24 PM PDT 24 May 09 01:16:27 PM PDT 24 55252780 ps
T1020 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1551344798 May 09 01:16:11 PM PDT 24 May 09 01:16:16 PM PDT 24 43622549 ps
T1021 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.270979347 May 09 01:15:55 PM PDT 24 May 09 01:16:03 PM PDT 24 65808903 ps
T1022 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.130959907 May 09 01:16:25 PM PDT 24 May 09 01:16:30 PM PDT 24 72659248 ps
T1023 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2651241737 May 09 01:16:09 PM PDT 24 May 09 01:16:16 PM PDT 24 302379884 ps
T1024 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.77015144 May 09 01:15:53 PM PDT 24 May 09 01:15:58 PM PDT 24 38934459 ps
T1025 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3672065883 May 09 01:16:25 PM PDT 24 May 09 01:16:31 PM PDT 24 161365237 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2153924280 May 09 01:15:51 PM PDT 24 May 09 01:15:57 PM PDT 24 43653092 ps
T80 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2485756233 May 09 01:15:51 PM PDT 24 May 09 01:15:55 PM PDT 24 294708286 ps
T1027 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.118974735 May 09 01:16:25 PM PDT 24 May 09 01:16:30 PM PDT 24 15999416 ps
T265 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.418614869 May 09 01:16:11 PM PDT 24 May 09 01:16:32 PM PDT 24 1095438928 ps
T1028 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1398737621 May 09 01:15:52 PM PDT 24 May 09 01:15:59 PM PDT 24 198086951 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.390445952 May 09 01:15:51 PM PDT 24 May 09 01:16:03 PM PDT 24 596505983 ps
T1029 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2646646587 May 09 01:16:24 PM PDT 24 May 09 01:16:28 PM PDT 24 21549560 ps
T267 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1360870768 May 09 01:16:08 PM PDT 24 May 09 01:16:21 PM PDT 24 811626329 ps
T1030 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.511974960 May 09 01:15:41 PM PDT 24 May 09 01:15:44 PM PDT 24 17516182 ps
T1031 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.619775960 May 09 01:15:53 PM PDT 24 May 09 01:15:58 PM PDT 24 204979603 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3100329107 May 09 01:15:46 PM PDT 24 May 09 01:15:50 PM PDT 24 501357428 ps
T1033 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.113310554 May 09 01:16:11 PM PDT 24 May 09 01:16:18 PM PDT 24 47938748 ps
T1034 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3543535778 May 09 01:16:28 PM PDT 24 May 09 01:16:32 PM PDT 24 36211856 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2958594650 May 09 01:15:51 PM PDT 24 May 09 01:15:56 PM PDT 24 53880605 ps
T1036 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.455837383 May 09 01:16:26 PM PDT 24 May 09 01:16:31 PM PDT 24 163454365 ps
T1037 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3523122252 May 09 01:16:27 PM PDT 24 May 09 01:16:31 PM PDT 24 22908314 ps
T1038 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2209440145 May 09 01:15:55 PM PDT 24 May 09 01:15:59 PM PDT 24 440400210 ps
T1039 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3322724108 May 09 01:16:08 PM PDT 24 May 09 01:16:13 PM PDT 24 148859661 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.576772455 May 09 01:16:25 PM PDT 24 May 09 01:16:32 PM PDT 24 254934839 ps
T1041 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3066178997 May 09 01:16:10 PM PDT 24 May 09 01:16:19 PM PDT 24 584059822 ps
T1042 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.107049283 May 09 01:16:10 PM PDT 24 May 09 01:16:14 PM PDT 24 38652870 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1676127037 May 09 01:15:51 PM PDT 24 May 09 01:15:55 PM PDT 24 12904365 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2542401823 May 09 01:15:51 PM PDT 24 May 09 01:16:13 PM PDT 24 314438255 ps
T81 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4051452728 May 09 01:15:52 PM PDT 24 May 09 01:15:57 PM PDT 24 122743898 ps
T266 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2960507802 May 09 01:16:11 PM PDT 24 May 09 01:16:26 PM PDT 24 206870113 ps
T1045 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.616634187 May 09 01:16:25 PM PDT 24 May 09 01:16:30 PM PDT 24 36665656 ps
T1046 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.478496256 May 09 01:16:11 PM PDT 24 May 09 01:16:16 PM PDT 24 51232262 ps
T1047 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2610399591 May 09 01:15:50 PM PDT 24 May 09 01:15:54 PM PDT 24 91622901 ps
T1048 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.130450984 May 09 01:16:20 PM PDT 24 May 09 01:16:23 PM PDT 24 915235384 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1962473943 May 09 01:15:48 PM PDT 24 May 09 01:15:49 PM PDT 24 16123895 ps
T1050 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.954099806 May 09 01:16:11 PM PDT 24 May 09 01:16:16 PM PDT 24 71330522 ps
T1051 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1761590684 May 09 01:16:10 PM PDT 24 May 09 01:16:17 PM PDT 24 620245178 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4219037738 May 09 01:15:51 PM PDT 24 May 09 01:15:55 PM PDT 24 11368624 ps
T1053 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1731680552 May 09 01:16:23 PM PDT 24 May 09 01:16:28 PM PDT 24 108848921 ps
T1054 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.439769756 May 09 01:16:09 PM PDT 24 May 09 01:16:11 PM PDT 24 105143468 ps
T1055 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.494715083 May 09 01:16:27 PM PDT 24 May 09 01:16:32 PM PDT 24 18747848 ps
T1056 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.657128378 May 09 01:16:27 PM PDT 24 May 09 01:16:31 PM PDT 24 16638593 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4086084950 May 09 01:15:53 PM PDT 24 May 09 01:16:31 PM PDT 24 2094559458 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1754754233 May 09 01:15:44 PM PDT 24 May 09 01:15:50 PM PDT 24 247548408 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3862489004 May 09 01:15:49 PM PDT 24 May 09 01:16:06 PM PDT 24 3200807555 ps
T1060 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1903343461 May 09 01:16:25 PM PDT 24 May 09 01:16:29 PM PDT 24 18230778 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2746255537 May 09 01:15:42 PM PDT 24 May 09 01:15:45 PM PDT 24 124628905 ps
T1062 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3576167868 May 09 01:15:53 PM PDT 24 May 09 01:15:58 PM PDT 24 103451389 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4158822488 May 09 01:15:49 PM PDT 24 May 09 01:15:51 PM PDT 24 35861412 ps
T1064 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2877634194 May 09 01:15:49 PM PDT 24 May 09 01:15:54 PM PDT 24 282579560 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1967594417 May 09 01:15:50 PM PDT 24 May 09 01:16:16 PM PDT 24 1592296473 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.88694254 May 09 01:15:48 PM PDT 24 May 09 01:15:51 PM PDT 24 209817629 ps
T1067 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1503141172 May 09 01:16:23 PM PDT 24 May 09 01:16:47 PM PDT 24 3686375865 ps
T1068 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2324357495 May 09 01:16:10 PM PDT 24 May 09 01:16:20 PM PDT 24 191374489 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2103601528 May 09 01:15:51 PM PDT 24 May 09 01:15:55 PM PDT 24 29124990 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1463707348 May 09 01:16:09 PM PDT 24 May 09 01:16:15 PM PDT 24 577639310 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3777545721 May 09 01:16:09 PM PDT 24 May 09 01:16:13 PM PDT 24 112273822 ps
T1072 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2016125031 May 09 01:15:53 PM PDT 24 May 09 01:15:57 PM PDT 24 42443096 ps
T1073 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2478656721 May 09 01:16:11 PM PDT 24 May 09 01:16:17 PM PDT 24 698843895 ps
T1074 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1062961129 May 09 01:16:23 PM PDT 24 May 09 01:16:26 PM PDT 24 15553884 ps
T1075 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2152969911 May 09 01:16:27 PM PDT 24 May 09 01:16:31 PM PDT 24 47793759 ps
T1076 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1473150860 May 09 01:16:26 PM PDT 24 May 09 01:16:31 PM PDT 24 103390659 ps
T1077 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1712309044 May 09 01:16:26 PM PDT 24 May 09 01:16:30 PM PDT 24 31465576 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1521223841 May 09 01:16:24 PM PDT 24 May 09 01:16:28 PM PDT 24 45611078 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1171636684 May 09 01:15:51 PM PDT 24 May 09 01:16:08 PM PDT 24 207050138 ps
T1080 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3736659800 May 09 01:16:22 PM PDT 24 May 09 01:16:27 PM PDT 24 59892357 ps
T1081 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.955158790 May 09 01:15:52 PM PDT 24 May 09 01:16:08 PM PDT 24 831769139 ps

Test location /workspace/coverage/default/17.spi_device_stress_all.1733656709
Short name T9
Test name
Test status
Simulation time 10074109518 ps
CPU time 83.82 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 249056 kb
Host smart-9a2a3748-d750-477a-9ae1-6e002e9090b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733656709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1733656709
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3373623809
Short name T22
Test name
Test status
Simulation time 444405174489 ps
CPU time 868.08 seconds
Started May 09 01:33:28 PM PDT 24
Finished May 09 01:47:57 PM PDT 24
Peak memory 254072 kb
Host smart-030af799-c799-44c9-9467-525b24e540fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373623809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3373623809
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.371027846
Short name T57
Test name
Test status
Simulation time 74620746 ps
CPU time 1.92 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 216316 kb
Host smart-199cc1c6-96ba-4a44-a535-0fb65b6201b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371027846 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.371027846
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4161249644
Short name T13
Test name
Test status
Simulation time 35788840990 ps
CPU time 431.27 seconds
Started May 09 01:31:08 PM PDT 24
Finished May 09 01:38:21 PM PDT 24
Peak memory 252860 kb
Host smart-5f90b0f9-28e6-4403-b026-3bcc6526d6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161249644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4161249644
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1038380174
Short name T32
Test name
Test status
Simulation time 78602065942 ps
CPU time 289.49 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:37:30 PM PDT 24
Peak memory 265596 kb
Host smart-811c344d-bc46-4952-9fcc-bd1dd565cd34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038380174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1038380174
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1935725092
Short name T61
Test name
Test status
Simulation time 17171932 ps
CPU time 0.8 seconds
Started May 09 01:29:16 PM PDT 24
Finished May 09 01:29:17 PM PDT 24
Peak memory 216176 kb
Host smart-57075b22-2659-4fdd-8b25-9ff404bf5c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935725092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1935725092
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2792535427
Short name T30
Test name
Test status
Simulation time 180410293699 ps
CPU time 776.12 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:45:10 PM PDT 24
Peak memory 269804 kb
Host smart-d89b6703-3f76-487e-b8e8-70da706f52ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792535427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2792535427
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1312988218
Short name T31
Test name
Test status
Simulation time 351334966602 ps
CPU time 541.02 seconds
Started May 09 01:34:08 PM PDT 24
Finished May 09 01:43:09 PM PDT 24
Peak memory 263924 kb
Host smart-c58dce76-bedb-486a-9fa7-a30904b86fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312988218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1312988218
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1115058731
Short name T56
Test name
Test status
Simulation time 84657465 ps
CPU time 1.21 seconds
Started May 09 01:29:32 PM PDT 24
Finished May 09 01:29:35 PM PDT 24
Peak memory 236324 kb
Host smart-bd260564-5b59-40f9-90c6-bcf0d4d1bfd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115058731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1115058731
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1746749466
Short name T113
Test name
Test status
Simulation time 108500467 ps
CPU time 2.52 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 215172 kb
Host smart-8f564c55-a92f-4b5d-a1d7-280f3ec07100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746749466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1746749466
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2529206310
Short name T45
Test name
Test status
Simulation time 78495822677 ps
CPU time 841.03 seconds
Started May 09 01:31:47 PM PDT 24
Finished May 09 01:45:49 PM PDT 24
Peak memory 289748 kb
Host smart-33b91a06-0159-4c21-88da-7285ebfeff14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529206310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2529206310
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.350086087
Short name T39
Test name
Test status
Simulation time 66092118301 ps
CPU time 206.66 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:36:19 PM PDT 24
Peak memory 254180 kb
Host smart-16559b69-57db-493c-ae99-ba7d402af529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350086087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.350086087
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2981448706
Short name T141
Test name
Test status
Simulation time 1051085844 ps
CPU time 15.03 seconds
Started May 09 02:59:32 PM PDT 24
Finished May 09 02:59:49 PM PDT 24
Peak memory 240812 kb
Host smart-ca93d8b8-d2d8-4aae-8917-91b92b2f59f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981448706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2981448706
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1983225244
Short name T96
Test name
Test status
Simulation time 3626738591 ps
CPU time 19.77 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:34 PM PDT 24
Peak memory 215612 kb
Host smart-1288d301-7330-4d61-b367-71e2f79400d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983225244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1983225244
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3362277180
Short name T82
Test name
Test status
Simulation time 299722288732 ps
CPU time 647.86 seconds
Started May 09 01:34:03 PM PDT 24
Finished May 09 01:44:52 PM PDT 24
Peak memory 250924 kb
Host smart-4b8f358a-556f-4281-805d-ca316a30ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362277180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3362277180
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1470150967
Short name T103
Test name
Test status
Simulation time 147050717 ps
CPU time 5.03 seconds
Started May 09 01:15:54 PM PDT 24
Finished May 09 01:16:02 PM PDT 24
Peak memory 215648 kb
Host smart-8babb70c-a775-4053-abd5-e8258d29fe36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470150967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
470150967
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.473507668
Short name T164
Test name
Test status
Simulation time 52699058053 ps
CPU time 324.04 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:38:16 PM PDT 24
Peak memory 260756 kb
Host smart-34c68435-607e-4b18-af7d-0ca30cf7f8d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473507668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.473507668
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2835448876
Short name T233
Test name
Test status
Simulation time 68699174097 ps
CPU time 265.26 seconds
Started May 09 01:30:10 PM PDT 24
Finished May 09 01:34:36 PM PDT 24
Peak memory 250064 kb
Host smart-cf74e638-4f2e-4450-8d94-842c735e68a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835448876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2835448876
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.489182638
Short name T16
Test name
Test status
Simulation time 140906374130 ps
CPU time 339.99 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:37:56 PM PDT 24
Peak memory 252680 kb
Host smart-d1820e63-c1e7-46d1-bea6-31beb39f12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489182638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.489182638
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2409143671
Short name T235
Test name
Test status
Simulation time 337816265844 ps
CPU time 690.64 seconds
Started May 09 01:31:53 PM PDT 24
Finished May 09 01:43:25 PM PDT 24
Peak memory 268704 kb
Host smart-b8307d6a-7432-47c4-9f39-c1496ace6e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409143671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2409143671
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.171387529
Short name T3
Test name
Test status
Simulation time 100056634268 ps
CPU time 280.79 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:37:07 PM PDT 24
Peak memory 249304 kb
Host smart-41a8a57e-6abb-42ea-8c30-2cd092c3e6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171387529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.171387529
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3776211950
Short name T19
Test name
Test status
Simulation time 28998237596 ps
CPU time 184.7 seconds
Started May 09 01:32:32 PM PDT 24
Finished May 09 01:35:38 PM PDT 24
Peak memory 253208 kb
Host smart-f4ba7ce2-d582-46a2-aa1f-77cc01db39db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776211950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3776211950
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1652679139
Short name T23
Test name
Test status
Simulation time 50167098179 ps
CPU time 471.95 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:40:07 PM PDT 24
Peak memory 252204 kb
Host smart-4a6e1483-bab4-4351-8f80-d5435d61deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652679139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1652679139
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4015410883
Short name T334
Test name
Test status
Simulation time 18016507 ps
CPU time 0.69 seconds
Started May 09 01:30:27 PM PDT 24
Finished May 09 01:30:29 PM PDT 24
Peak memory 204800 kb
Host smart-07eb2032-ff5f-483f-b728-104b846ff14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015410883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4015410883
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4064067389
Short name T222
Test name
Test status
Simulation time 190415489567 ps
CPU time 346.72 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:37:00 PM PDT 24
Peak memory 253568 kb
Host smart-74147515-19e1-4f07-b32a-8261aac0d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064067389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4064067389
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3172735790
Short name T29
Test name
Test status
Simulation time 47833712490 ps
CPU time 105.16 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:33:42 PM PDT 24
Peak memory 253444 kb
Host smart-433fe4fd-dac6-495e-ab0c-a9aa56c52b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172735790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3172735790
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4197267846
Short name T506
Test name
Test status
Simulation time 8978915792 ps
CPU time 115.24 seconds
Started May 09 01:30:36 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 255568 kb
Host smart-bb5ef6ac-4b58-4c57-a648-526a86af06ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197267846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4197267846
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4040993704
Short name T79
Test name
Test status
Simulation time 110920669 ps
CPU time 1.45 seconds
Started May 09 01:15:42 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 216128 kb
Host smart-9c434712-1d37-4ceb-9e2f-19d44f06f6e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040993704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4040993704
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.418614869
Short name T265
Test name
Test status
Simulation time 1095438928 ps
CPU time 17.84 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:32 PM PDT 24
Peak memory 216440 kb
Host smart-907330ae-307d-4a13-b4e5-8fde467a1d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418614869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.418614869
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1826656096
Short name T237
Test name
Test status
Simulation time 3604909103 ps
CPU time 43.21 seconds
Started May 09 01:30:24 PM PDT 24
Finished May 09 01:31:08 PM PDT 24
Peak memory 249144 kb
Host smart-a5c9c0ef-1ba5-4f12-a008-911b733554da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826656096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1826656096
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.221854454
Short name T230
Test name
Test status
Simulation time 183222525261 ps
CPU time 340.42 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:37:35 PM PDT 24
Peak memory 256688 kb
Host smart-988f2e8c-5ff0-4bf7-a583-8b6c10ff20d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221854454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.221854454
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2547863035
Short name T1
Test name
Test status
Simulation time 73880653 ps
CPU time 2.95 seconds
Started May 09 01:32:27 PM PDT 24
Finished May 09 01:32:33 PM PDT 24
Peak memory 233768 kb
Host smart-7164e0cb-4c2c-4522-80d4-6ea12a27c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547863035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2547863035
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_intercept.211479714
Short name T91
Test name
Test status
Simulation time 425975131 ps
CPU time 5.29 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:32:58 PM PDT 24
Peak memory 218352 kb
Host smart-2e7421af-cef8-48b8-8054-3f7c7927b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211479714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.211479714
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.113310554
Short name T1033
Test name
Test status
Simulation time 47938748 ps
CPU time 3.15 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:18 PM PDT 24
Peak memory 215456 kb
Host smart-7a1f6835-12f9-451c-95db-49ec89a45863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113310554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.113310554
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3559237014
Short name T311
Test name
Test status
Simulation time 15986612964 ps
CPU time 31.34 seconds
Started May 09 01:29:49 PM PDT 24
Finished May 09 01:30:21 PM PDT 24
Peak memory 240832 kb
Host smart-6f0bf165-7a2f-41d3-9e19-93f6f63f84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559237014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3559237014
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.374306348
Short name T163
Test name
Test status
Simulation time 44348891738 ps
CPU time 429.95 seconds
Started May 09 01:31:43 PM PDT 24
Finished May 09 01:38:55 PM PDT 24
Peak memory 254208 kb
Host smart-1a1e55e6-d164-460a-a607-18ae0c830d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374306348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.374306348
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4211125601
Short name T223
Test name
Test status
Simulation time 7015689594 ps
CPU time 168.17 seconds
Started May 09 01:33:31 PM PDT 24
Finished May 09 01:36:20 PM PDT 24
Peak memory 272324 kb
Host smart-c2a4156b-946b-4b65-b88c-ee7ac992b876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211125601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4211125601
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1033351231
Short name T214
Test name
Test status
Simulation time 40267442919 ps
CPU time 75.04 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:31:25 PM PDT 24
Peak memory 250248 kb
Host smart-bb9a507b-0e3e-459b-8471-199bdc824ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033351231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1033351231
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1407105509
Short name T142
Test name
Test status
Simulation time 1031549718 ps
CPU time 12.53 seconds
Started May 09 01:29:21 PM PDT 24
Finished May 09 01:29:35 PM PDT 24
Peak memory 232568 kb
Host smart-7f2e2b22-2a7f-4523-bebe-02d9831da265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407105509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1407105509
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2324357495
Short name T1068
Test name
Test status
Simulation time 191374489 ps
CPU time 6.46 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:20 PM PDT 24
Peak memory 215484 kb
Host smart-80318726-0833-4976-b331-f8692a08021f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324357495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2324357495
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.758250802
Short name T429
Test name
Test status
Simulation time 3137468514 ps
CPU time 9.24 seconds
Started May 09 01:30:26 PM PDT 24
Finished May 09 01:30:36 PM PDT 24
Peak memory 218896 kb
Host smart-315e028d-1e9b-4498-8de2-71139c42063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758250802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.758250802
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.434424261
Short name T327
Test name
Test status
Simulation time 299674571 ps
CPU time 2.23 seconds
Started May 09 01:29:29 PM PDT 24
Finished May 09 01:29:32 PM PDT 24
Peak memory 216140 kb
Host smart-14f60d26-83b0-450d-a8f6-d1fa4d1cb3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434424261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.434424261
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2355420822
Short name T227
Test name
Test status
Simulation time 310526904698 ps
CPU time 560.91 seconds
Started May 09 01:31:56 PM PDT 24
Finished May 09 01:41:18 PM PDT 24
Peak memory 264404 kb
Host smart-2b06bc75-f0c1-4f3c-86e6-5c4877e24000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355420822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2355420822
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2890035657
Short name T168
Test name
Test status
Simulation time 94486829895 ps
CPU time 60.94 seconds
Started May 09 01:32:07 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 238636 kb
Host smart-4952bfab-87e4-4a96-bd46-fe77ccab2727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890035657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2890035657
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1053799546
Short name T185
Test name
Test status
Simulation time 13465177818 ps
CPU time 88.78 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:33:36 PM PDT 24
Peak memory 253040 kb
Host smart-1d549a13-d820-4aed-ad51-ab2a2bfa3b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053799546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1053799546
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1896222841
Short name T254
Test name
Test status
Simulation time 58365208914 ps
CPU time 135.2 seconds
Started May 09 01:32:49 PM PDT 24
Finished May 09 01:35:05 PM PDT 24
Peak memory 264156 kb
Host smart-929f170e-c745-45c1-ba8a-aeb376d17ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896222841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1896222841
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.820871802
Short name T226
Test name
Test status
Simulation time 20906202524 ps
CPU time 282.78 seconds
Started May 09 01:33:23 PM PDT 24
Finished May 09 01:38:07 PM PDT 24
Peak memory 257364 kb
Host smart-1d0986d8-95b5-4cad-aa12-0471e6aca740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820871802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.820871802
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.720356034
Short name T25
Test name
Test status
Simulation time 19300700101 ps
CPU time 13.46 seconds
Started May 09 01:33:53 PM PDT 24
Finished May 09 01:34:08 PM PDT 24
Peak memory 239088 kb
Host smart-79067226-1674-4a5b-a91a-f78906852ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720356034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.720356034
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.327655130
Short name T224
Test name
Test status
Simulation time 33698231211 ps
CPU time 130.44 seconds
Started May 09 01:34:15 PM PDT 24
Finished May 09 01:36:27 PM PDT 24
Peak memory 256884 kb
Host smart-39c17516-ea41-452f-b50c-44cab3bbd090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327655130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.327655130
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2154118495
Short name T190
Test name
Test status
Simulation time 9056516282 ps
CPU time 89.94 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:31:41 PM PDT 24
Peak memory 254428 kb
Host smart-e2bbc852-c0cb-4883-b1f1-dacbf068ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154118495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2154118495
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.148277121
Short name T180
Test name
Test status
Simulation time 34324396 ps
CPU time 2.54 seconds
Started May 09 01:30:25 PM PDT 24
Finished May 09 01:30:29 PM PDT 24
Peak memory 232668 kb
Host smart-6d537aa3-73ed-4d58-b105-e1d892f81b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148277121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.148277121
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2090117856
Short name T78
Test name
Test status
Simulation time 324577456 ps
CPU time 1.41 seconds
Started May 09 01:15:49 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 206968 kb
Host smart-331bd764-46e8-44a7-8f35-faa83f904fba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090117856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2090117856
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1754754233
Short name T1058
Test name
Test status
Simulation time 247548408 ps
CPU time 4.46 seconds
Started May 09 01:15:44 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 215444 kb
Host smart-6b612d0d-1413-4b43-8279-07be3eeccf18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754754233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
754754233
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3596377219
Short name T71
Test name
Test status
Simulation time 789685684 ps
CPU time 8.95 seconds
Started May 09 01:29:36 PM PDT 24
Finished May 09 01:29:46 PM PDT 24
Peak memory 222372 kb
Host smart-f87d4f01-9f49-4a9a-bcd5-fb2aa18ef198
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596377219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3596377219
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1404491702
Short name T1017
Test name
Test status
Simulation time 786366219 ps
CPU time 15.25 seconds
Started May 09 01:15:43 PM PDT 24
Finished May 09 01:16:00 PM PDT 24
Peak memory 215140 kb
Host smart-e7ea92a9-f1aa-447c-8db0-39c9467f726f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404491702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1404491702
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1475771441
Short name T145
Test name
Test status
Simulation time 907836807 ps
CPU time 13.36 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:56 PM PDT 24
Peak memory 215044 kb
Host smart-62ea3427-399d-4c65-9fea-e53ea672cb78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475771441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1475771441
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4035974937
Short name T146
Test name
Test status
Simulation time 205579697 ps
CPU time 1.67 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:43 PM PDT 24
Peak memory 215352 kb
Host smart-41700c91-8846-4615-8a0c-906234c75caf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035974937 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4035974937
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2845435223
Short name T123
Test name
Test status
Simulation time 86161503 ps
CPU time 1.33 seconds
Started May 09 01:15:43 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 206984 kb
Host smart-22f5809e-cf67-46b2-afbc-293c63fbc43f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845435223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
845435223
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.511974960
Short name T1030
Test name
Test status
Simulation time 17516182 ps
CPU time 0.71 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 203616 kb
Host smart-7b640486-42e2-48fa-a88f-d7de66846f0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511974960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.511974960
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3061047115
Short name T121
Test name
Test status
Simulation time 29829109 ps
CPU time 1.35 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 215344 kb
Host smart-2d4698c4-688f-4379-ade7-cbed08175994
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061047115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3061047115
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.154277283
Short name T1006
Test name
Test status
Simulation time 26248370 ps
CPU time 0.64 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 203512 kb
Host smart-506522a0-06fa-40a5-a02a-4aed0e64055c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154277283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.154277283
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3100329107
Short name T1032
Test name
Test status
Simulation time 501357428 ps
CPU time 2.97 seconds
Started May 09 01:15:46 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 214988 kb
Host smart-f8caeac0-317b-4585-87d9-b365026829a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100329107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3100329107
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3670513641
Short name T112
Test name
Test status
Simulation time 132755172 ps
CPU time 3.71 seconds
Started May 09 01:15:45 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 215360 kb
Host smart-8814defd-1f28-4a5c-b8da-d7547c67676d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670513641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
670513641
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1174141691
Short name T1005
Test name
Test status
Simulation time 2912620015 ps
CPU time 7.97 seconds
Started May 09 01:15:43 PM PDT 24
Finished May 09 01:15:53 PM PDT 24
Peak memory 215460 kb
Host smart-22700dcd-12ea-41e6-ae45-ca2c50849f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174141691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1174141691
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2637998305
Short name T116
Test name
Test status
Simulation time 1282254065 ps
CPU time 20.52 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 207060 kb
Host smart-ddc31aec-0e3e-4490-92e8-9ec29aa9f389
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637998305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2637998305
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1967594417
Short name T1065
Test name
Test status
Simulation time 1592296473 ps
CPU time 23.43 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 207028 kb
Host smart-0fa4421f-3354-4d7f-a4d4-c53d650f0559
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967594417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1967594417
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.88694254
Short name T1066
Test name
Test status
Simulation time 209817629 ps
CPU time 2.78 seconds
Started May 09 01:15:48 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 216800 kb
Host smart-42057177-7baf-438c-a025-ef852784904d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88694254 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.88694254
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2610663317
Short name T117
Test name
Test status
Simulation time 73896735 ps
CPU time 1.4 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 206976 kb
Host smart-dd4ce6ca-2271-4ea8-9ec0-7d8c3206944b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610663317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
610663317
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2746255537
Short name T1061
Test name
Test status
Simulation time 124628905 ps
CPU time 0.72 seconds
Started May 09 01:15:42 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 203616 kb
Host smart-c6879099-2130-43f4-9241-d1b2d9412fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746255537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
746255537
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2103601528
Short name T1069
Test name
Test status
Simulation time 29124990 ps
CPU time 2.14 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 215400 kb
Host smart-04ca1362-fd98-4c2c-9263-68f64d40c13f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103601528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2103601528
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1326302959
Short name T979
Test name
Test status
Simulation time 11150074 ps
CPU time 0.68 seconds
Started May 09 01:15:54 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 203716 kb
Host smart-f5ce8436-a270-472f-a824-f38e2471c3dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326302959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1326302959
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.569692984
Short name T985
Test name
Test status
Simulation time 634275272 ps
CPU time 4.27 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:16:00 PM PDT 24
Peak memory 215256 kb
Host smart-fe204207-c64d-42c3-8169-98d0cf26dac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569692984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.569692984
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3717273881
Short name T987
Test name
Test status
Simulation time 1536052077 ps
CPU time 14.27 seconds
Started May 09 01:15:43 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 215136 kb
Host smart-928a6e11-cd47-4322-8ad4-2a26d34297a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717273881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3717273881
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2478656721
Short name T1073
Test name
Test status
Simulation time 698843895 ps
CPU time 2.89 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:17 PM PDT 24
Peak memory 216736 kb
Host smart-97794624-2de0-4036-a600-cbae24d5d96d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478656721 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2478656721
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.312310289
Short name T120
Test name
Test status
Simulation time 71327725 ps
CPU time 2.37 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:17 PM PDT 24
Peak memory 215236 kb
Host smart-931ce9ff-4586-4b5d-9056-f88e41145a37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312310289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.312310289
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3808473081
Short name T983
Test name
Test status
Simulation time 13683123 ps
CPU time 0.7 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:14 PM PDT 24
Peak memory 203604 kb
Host smart-c5833e82-17ef-4786-91d4-6dd746eaeb42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808473081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3808473081
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.215084066
Short name T976
Test name
Test status
Simulation time 63067604 ps
CPU time 3.83 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215232 kb
Host smart-1b364cc2-8ff7-4c51-8ccc-f62affc25e9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215084066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.215084066
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2522740075
Short name T106
Test name
Test status
Simulation time 127950511 ps
CPU time 3.8 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 215360 kb
Host smart-f5bc2b88-d4a6-4f1b-9d45-95908195aad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522740075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2522740075
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3322724108
Short name T1039
Test name
Test status
Simulation time 148859661 ps
CPU time 3.25 seconds
Started May 09 01:16:08 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 217000 kb
Host smart-acb22d2a-f8ae-450d-957b-056af30977ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322724108 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3322724108
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4194636238
Short name T992
Test name
Test status
Simulation time 167491168 ps
CPU time 1.58 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 215232 kb
Host smart-1724c7f7-2d5a-4aa1-87cd-0b7c418142e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194636238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4194636238
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.190238626
Short name T1001
Test name
Test status
Simulation time 45461266 ps
CPU time 0.77 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 203544 kb
Host smart-5a3f4746-412a-4acd-ac03-2311d4080883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190238626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.190238626
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1551344798
Short name T1020
Test name
Test status
Simulation time 43622549 ps
CPU time 2.47 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215268 kb
Host smart-1ee332dc-76fd-47cf-8857-52f3abe8847d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551344798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1551344798
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3712342145
Short name T110
Test name
Test status
Simulation time 86332333 ps
CPU time 1.55 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 215552 kb
Host smart-b06ea708-45c9-44a8-9135-24e265a1902b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712342145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3712342145
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3112845278
Short name T264
Test name
Test status
Simulation time 437581594 ps
CPU time 7.39 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:20 PM PDT 24
Peak memory 215392 kb
Host smart-5e4afaee-659f-467a-a62d-29a779298c93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112845278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3112845278
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1880125571
Short name T993
Test name
Test status
Simulation time 100644515 ps
CPU time 2.87 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 216680 kb
Host smart-72e0d7e1-082f-4908-b1ce-8ca4a874feef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880125571 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1880125571
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1063679159
Short name T150
Test name
Test status
Simulation time 76290058 ps
CPU time 2.02 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215148 kb
Host smart-0485f1a9-ba99-44c1-8382-6781a490035d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063679159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1063679159
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3482400847
Short name T1011
Test name
Test status
Simulation time 16857811 ps
CPU time 0.75 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 203576 kb
Host smart-1a1cd80d-16f4-45a8-8698-e83fde1f3a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482400847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3482400847
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2545431801
Short name T148
Test name
Test status
Simulation time 236748620 ps
CPU time 1.67 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 215212 kb
Host smart-cdf91af0-f227-46b0-ae24-00137084388f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545431801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2545431801
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.478496256
Short name T1046
Test name
Test status
Simulation time 51232262 ps
CPU time 1.76 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215300 kb
Host smart-720171a8-a3ec-48ce-9b75-019c1918a7d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478496256 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.478496256
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3509203080
Short name T119
Test name
Test status
Simulation time 47180978 ps
CPU time 1.85 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 215184 kb
Host smart-75e91af8-f3e9-4155-bd25-017fca8c3dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509203080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3509203080
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2248998901
Short name T1012
Test name
Test status
Simulation time 47225001 ps
CPU time 0.85 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:12 PM PDT 24
Peak memory 203544 kb
Host smart-7ade6995-9a2b-4c05-8823-83f1b2761ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248998901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2248998901
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.439769756
Short name T1054
Test name
Test status
Simulation time 105143468 ps
CPU time 1.7 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:11 PM PDT 24
Peak memory 215236 kb
Host smart-c94cd22e-d525-4ba7-951b-1915c87172d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439769756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.439769756
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1463707348
Short name T1070
Test name
Test status
Simulation time 577639310 ps
CPU time 3.8 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 215452 kb
Host smart-fc12fb4b-ebe2-433b-a290-3b442faccc74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463707348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1463707348
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3066178997
Short name T1041
Test name
Test status
Simulation time 584059822 ps
CPU time 6.32 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:19 PM PDT 24
Peak memory 222488 kb
Host smart-949d289d-9e31-4711-b58d-adc24e6d3f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066178997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3066178997
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.269307896
Short name T978
Test name
Test status
Simulation time 340611825 ps
CPU time 2.75 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 216704 kb
Host smart-b45af06e-927f-4a9e-b3d4-aa8ce84fbae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269307896 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.269307896
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1636078281
Short name T118
Test name
Test status
Simulation time 73773653 ps
CPU time 1.3 seconds
Started May 09 01:16:12 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215180 kb
Host smart-c8439923-e7d9-41b4-9a65-df283cfaf959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636078281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1636078281
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3669157296
Short name T1014
Test name
Test status
Simulation time 25914926 ps
CPU time 0.78 seconds
Started May 09 01:16:08 PM PDT 24
Finished May 09 01:16:10 PM PDT 24
Peak memory 203604 kb
Host smart-a9753e01-ee73-4f15-addd-ae56cc8a9d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669157296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3669157296
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3777545721
Short name T1071
Test name
Test status
Simulation time 112273822 ps
CPU time 3.11 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 215304 kb
Host smart-8948cb08-6304-40fe-96a7-807ac4788657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777545721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3777545721
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1654780815
Short name T102
Test name
Test status
Simulation time 217922556 ps
CPU time 2.55 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215512 kb
Host smart-f2e85c70-560b-4da8-b3f9-a5a55447155f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654780815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1654780815
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3924243532
Short name T97
Test name
Test status
Simulation time 709072063 ps
CPU time 15.64 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 215320 kb
Host smart-ca846b6e-bb71-4ff9-b9ea-c24e7f8e62c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924243532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3924243532
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.130450984
Short name T1048
Test name
Test status
Simulation time 915235384 ps
CPU time 2.53 seconds
Started May 09 01:16:20 PM PDT 24
Finished May 09 01:16:23 PM PDT 24
Peak memory 216620 kb
Host smart-4cc56525-5608-49f8-be8b-cccdafd1051a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130450984 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.130450984
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.597835197
Short name T1013
Test name
Test status
Simulation time 372843937 ps
CPU time 2.79 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:27 PM PDT 24
Peak memory 215164 kb
Host smart-c0ab0b95-4a60-42e6-9292-4982bce49c2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597835197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.597835197
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.655890710
Short name T1015
Test name
Test status
Simulation time 47354728 ps
CPU time 0.72 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:25 PM PDT 24
Peak memory 203612 kb
Host smart-3141912d-be9d-42f1-956b-dc53f23561d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655890710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.655890710
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3529596655
Short name T152
Test name
Test status
Simulation time 84342834 ps
CPU time 2.02 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 215244 kb
Host smart-f4dcce8d-0e6c-4fe1-98f8-fd61791ff3b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529596655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3529596655
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2352677268
Short name T107
Test name
Test status
Simulation time 119299326 ps
CPU time 4.13 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:33 PM PDT 24
Peak memory 215548 kb
Host smart-a002a103-1850-47e8-b5ac-08b44c02d885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352677268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2352677268
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.276232773
Short name T58
Test name
Test status
Simulation time 1090181915 ps
CPU time 7.62 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 215336 kb
Host smart-f62d9c58-3e9b-492c-a3ec-abca33e597b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276232773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.276232773
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3040214404
Short name T99
Test name
Test status
Simulation time 262545583 ps
CPU time 2.64 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:25 PM PDT 24
Peak memory 216348 kb
Host smart-38c660a4-f938-4ac8-96e8-cb4583d6fc9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040214404 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3040214404
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.576772455
Short name T1040
Test name
Test status
Simulation time 254934839 ps
CPU time 2.95 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:32 PM PDT 24
Peak memory 215204 kb
Host smart-d44af504-cc8d-4236-bc2b-5f196ae2451c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576772455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.576772455
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2231723766
Short name T965
Test name
Test status
Simulation time 14224613 ps
CPU time 0.74 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 203632 kb
Host smart-fb9d329a-8014-466b-a930-30878a81969a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231723766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2231723766
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3220178158
Short name T139
Test name
Test status
Simulation time 191859726 ps
CPU time 3.81 seconds
Started May 09 01:16:21 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 215252 kb
Host smart-6ce47580-7745-4d10-a8da-08a81bc90d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220178158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3220178158
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2302283436
Short name T94
Test name
Test status
Simulation time 40737222 ps
CPU time 1.45 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 215356 kb
Host smart-4d6165b1-5838-49c2-a29a-99f7ca962674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302283436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2302283436
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1503141172
Short name T1067
Test name
Test status
Simulation time 3686375865 ps
CPU time 22.39 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:47 PM PDT 24
Peak memory 216404 kb
Host smart-3b5f7620-44cd-44e9-bfe2-2318393276bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503141172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1503141172
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1731680552
Short name T1053
Test name
Test status
Simulation time 108848921 ps
CPU time 2.9 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 216568 kb
Host smart-076ff326-5f38-47ce-b324-3881281779d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731680552 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1731680552
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4001640858
Short name T982
Test name
Test status
Simulation time 44449118 ps
CPU time 0.7 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:29 PM PDT 24
Peak memory 203616 kb
Host smart-594bed78-28e8-4cf8-80fb-ba858c54c8a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001640858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4001640858
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1655644645
Short name T151
Test name
Test status
Simulation time 1841112824 ps
CPU time 4.35 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 215276 kb
Host smart-088b1b4c-f815-4497-a3c5-66ba7c661433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655644645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1655644645
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1969945180
Short name T105
Test name
Test status
Simulation time 226902055 ps
CPU time 2.8 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 215396 kb
Host smart-10ed47a2-6258-4493-ad57-40f76bf58e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969945180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1969945180
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3016359256
Short name T260
Test name
Test status
Simulation time 106144054 ps
CPU time 6.86 seconds
Started May 09 01:16:26 PM PDT 24
Finished May 09 01:16:36 PM PDT 24
Peak memory 215732 kb
Host smart-831179d0-b028-44cd-9275-7325bd2c73d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016359256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3016359256
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1880568448
Short name T108
Test name
Test status
Simulation time 60634635 ps
CPU time 3.86 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:33 PM PDT 24
Peak memory 217828 kb
Host smart-3d43c450-ef88-414a-bb41-eb3f8dc04f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880568448 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1880568448
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3672065883
Short name T1025
Test name
Test status
Simulation time 161365237 ps
CPU time 2.15 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 207020 kb
Host smart-31bfc411-3bb1-4618-87b3-14774594b31b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672065883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3672065883
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.452946567
Short name T966
Test name
Test status
Simulation time 12145630 ps
CPU time 0.76 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:24 PM PDT 24
Peak memory 203608 kb
Host smart-b20b4776-b962-4f47-b0f0-b6074794482c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452946567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.452946567
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.344531073
Short name T149
Test name
Test status
Simulation time 1360669811 ps
CPU time 4.62 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:33 PM PDT 24
Peak memory 215288 kb
Host smart-bd7ee441-e3e4-47f6-bb05-0564ab051b3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344531073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.344531073
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3584414182
Short name T59
Test name
Test status
Simulation time 33283056 ps
CPU time 2.01 seconds
Started May 09 01:16:26 PM PDT 24
Finished May 09 01:16:32 PM PDT 24
Peak memory 216384 kb
Host smart-cf30d9c0-6b35-44e8-a33a-c2731fb94969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584414182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3584414182
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1130019102
Short name T263
Test name
Test status
Simulation time 428696911 ps
CPU time 6.49 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:33 PM PDT 24
Peak memory 215288 kb
Host smart-ab03628e-a84e-4a1a-9328-7f0cb601a53b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130019102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1130019102
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.516900398
Short name T104
Test name
Test status
Simulation time 61774195 ps
CPU time 3.89 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:29 PM PDT 24
Peak memory 218536 kb
Host smart-d5f787a3-c033-4b3f-b862-272be81bcf05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516900398 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.516900398
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1521223841
Short name T1078
Test name
Test status
Simulation time 45611078 ps
CPU time 1.4 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 206960 kb
Host smart-d65ffdab-4e8f-4ee3-99af-f07b6c96dcde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521223841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1521223841
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1239876534
Short name T962
Test name
Test status
Simulation time 15930525 ps
CPU time 0.75 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 203940 kb
Host smart-d056e1db-1271-4f85-9df5-b181ef39be87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239876534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1239876534
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.409827276
Short name T1010
Test name
Test status
Simulation time 305323640 ps
CPU time 4.35 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:34 PM PDT 24
Peak memory 215616 kb
Host smart-b7c187a9-44b7-43ba-a1af-0a434ad69586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409827276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.409827276
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3736659800
Short name T1080
Test name
Test status
Simulation time 59892357 ps
CPU time 3.94 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:27 PM PDT 24
Peak memory 216404 kb
Host smart-746cad4d-fd9d-433d-a990-035bade469b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736659800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3736659800
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1028757610
Short name T261
Test name
Test status
Simulation time 615085217 ps
CPU time 19.55 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:48 PM PDT 24
Peak memory 215332 kb
Host smart-b5535c97-97a6-4ad0-b889-258646c3b76d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028757610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1028757610
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3862489004
Short name T1059
Test name
Test status
Simulation time 3200807555 ps
CPU time 15.9 seconds
Started May 09 01:15:49 PM PDT 24
Finished May 09 01:16:06 PM PDT 24
Peak memory 207092 kb
Host smart-b203877a-5e8a-49b6-896d-2912a8bc2c50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862489004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3862489004
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3228171214
Short name T994
Test name
Test status
Simulation time 1925474678 ps
CPU time 36.96 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:16:29 PM PDT 24
Peak memory 215180 kb
Host smart-69c81bde-c32d-43d0-a473-80071dc2befe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228171214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3228171214
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2610399591
Short name T1047
Test name
Test status
Simulation time 91622901 ps
CPU time 1.37 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 206964 kb
Host smart-316a7dbc-8186-4dc2-82d3-d41b772661f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610399591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2610399591
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1834784565
Short name T997
Test name
Test status
Simulation time 162616009 ps
CPU time 1.72 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 215224 kb
Host smart-bf9bc048-08e2-43aa-afb4-7653e887e60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834784565 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1834784565
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.698763555
Short name T998
Test name
Test status
Simulation time 72037545 ps
CPU time 1.23 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 206988 kb
Host smart-6333725d-4c7c-4898-848f-1e1e0e587646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698763555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.698763555
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2602259512
Short name T1002
Test name
Test status
Simulation time 24008594 ps
CPU time 0.76 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 203600 kb
Host smart-e66fcf9a-9c18-4351-b3ce-760088bbf0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602259512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
602259512
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3323460796
Short name T115
Test name
Test status
Simulation time 46242878 ps
CPU time 1.57 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 215344 kb
Host smart-02e82b07-9cc5-4553-a32e-982289a6c0d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323460796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3323460796
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4219037738
Short name T1052
Test name
Test status
Simulation time 11368624 ps
CPU time 0.66 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 203832 kb
Host smart-ee627dec-0c0e-4df1-b8b8-0adf31c5150a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219037738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4219037738
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.342817014
Short name T972
Test name
Test status
Simulation time 302239695 ps
CPU time 3.56 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:16:00 PM PDT 24
Peak memory 215268 kb
Host smart-de558a94-e708-4f2a-91e8-16b487dfb54f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342817014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.342817014
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1439782042
Short name T1009
Test name
Test status
Simulation time 117612966 ps
CPU time 1.96 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 215464 kb
Host smart-47f9558f-df15-42e6-834d-3abab69bda65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439782042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
439782042
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2542401823
Short name T1044
Test name
Test status
Simulation time 314438255 ps
CPU time 19.32 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 215208 kb
Host smart-c99af65f-25bb-46a5-9c6d-fd1d028d0494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542401823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2542401823
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.616634187
Short name T1045
Test name
Test status
Simulation time 36665656 ps
CPU time 0.77 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203616 kb
Host smart-13ceb90b-8580-422d-a3a9-562551a73a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616634187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.616634187
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1082877065
Short name T968
Test name
Test status
Simulation time 46665555 ps
CPU time 0.7 seconds
Started May 09 01:16:22 PM PDT 24
Finished May 09 01:16:23 PM PDT 24
Peak memory 203592 kb
Host smart-9c4d6b4d-994b-45dd-8ecc-26bbdd1d3b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082877065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1082877065
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2494061001
Short name T969
Test name
Test status
Simulation time 19273604 ps
CPU time 0.77 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:29 PM PDT 24
Peak memory 203928 kb
Host smart-7ba30d1a-0487-4ac4-b2d2-1b073090c9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494061001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2494061001
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1062961129
Short name T1074
Test name
Test status
Simulation time 15553884 ps
CPU time 0.72 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 203636 kb
Host smart-d4e17366-2bbb-4786-870c-817119b760dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062961129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1062961129
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4000264080
Short name T963
Test name
Test status
Simulation time 156979729 ps
CPU time 0.79 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:25 PM PDT 24
Peak memory 203536 kb
Host smart-80cdb421-9049-4b86-be19-2ae77a76750e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000264080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4000264080
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1708603360
Short name T967
Test name
Test status
Simulation time 17309208 ps
CPU time 0.76 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 203900 kb
Host smart-fbd1e1c0-abb0-476a-a1fa-5a5617dd227f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708603360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1708603360
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1056551677
Short name T1004
Test name
Test status
Simulation time 21909400 ps
CPU time 0.74 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203600 kb
Host smart-c502b96d-a020-4aa7-a178-74e25e620933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056551677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1056551677
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2340724603
Short name T999
Test name
Test status
Simulation time 42943262 ps
CPU time 0.74 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 203632 kb
Host smart-2950d765-b594-4429-8a73-d53e7dca1cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340724603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2340724603
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.906202217
Short name T974
Test name
Test status
Simulation time 18145402 ps
CPU time 0.78 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203948 kb
Host smart-8664d561-aef3-4dfd-a034-622843a9297a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906202217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.906202217
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1865619949
Short name T977
Test name
Test status
Simulation time 29989564 ps
CPU time 0.73 seconds
Started May 09 01:16:23 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 203548 kb
Host smart-45237089-3ad3-4e17-a2e8-7ebcf6c6c665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865619949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1865619949
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.390445952
Short name T125
Test name
Test status
Simulation time 596505983 ps
CPU time 8.23 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:16:03 PM PDT 24
Peak memory 206992 kb
Host smart-08b75a23-f866-4d45-8068-9fd3d69d061c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390445952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.390445952
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4086084950
Short name T1057
Test name
Test status
Simulation time 2094559458 ps
CPU time 34.29 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 206784 kb
Host smart-c584f551-e6fe-4b21-8717-47a7380c56b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086084950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4086084950
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4051452728
Short name T81
Test name
Test status
Simulation time 122743898 ps
CPU time 1.41 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 206988 kb
Host smart-05a40b6b-c6e6-42a1-b9b1-444763fc99d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051452728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4051452728
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2153924280
Short name T1026
Test name
Test status
Simulation time 43653092 ps
CPU time 2.68 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 217428 kb
Host smart-0e580e07-cdae-4fec-989f-88a35460692d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153924280 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2153924280
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3348126744
Short name T122
Test name
Test status
Simulation time 34545962 ps
CPU time 2.46 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 215160 kb
Host smart-1c29e28b-4315-4fb0-a8e8-7ff0454ad44e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348126744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
348126744
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1962473943
Short name T1049
Test name
Test status
Simulation time 16123895 ps
CPU time 0.71 seconds
Started May 09 01:15:48 PM PDT 24
Finished May 09 01:15:49 PM PDT 24
Peak memory 203904 kb
Host smart-76048e7b-e585-4313-8947-edfce1526064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962473943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
962473943
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4158822488
Short name T1063
Test name
Test status
Simulation time 35861412 ps
CPU time 1.21 seconds
Started May 09 01:15:49 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 215296 kb
Host smart-78fcb9a9-2d14-40ea-aa9b-fd7e638901a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158822488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4158822488
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1556084021
Short name T973
Test name
Test status
Simulation time 11160048 ps
CPU time 0.67 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:56 PM PDT 24
Peak memory 203788 kb
Host smart-79741f72-0f36-4988-8bda-46ece2fe0bf2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556084021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1556084021
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2153985266
Short name T1003
Test name
Test status
Simulation time 257412967 ps
CPU time 3.93 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 215244 kb
Host smart-11612115-f381-4b26-acc4-34513a7c1574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153985266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2153985266
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.729440521
Short name T101
Test name
Test status
Simulation time 815546545 ps
CPU time 4.64 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 215500 kb
Host smart-9264711e-1797-4364-ba7d-538c4cdf2575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729440521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.729440521
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4027022043
Short name T995
Test name
Test status
Simulation time 1177325143 ps
CPU time 8.01 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:16:01 PM PDT 24
Peak memory 215312 kb
Host smart-e2093fc1-9e84-4e7c-8343-40e605a506fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027022043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4027022043
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2136940660
Short name T984
Test name
Test status
Simulation time 115957396 ps
CPU time 0.71 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203640 kb
Host smart-f02d756b-d181-4750-866a-545c64b9e2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136940660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2136940660
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1903343461
Short name T1060
Test name
Test status
Simulation time 18230778 ps
CPU time 0.76 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:29 PM PDT 24
Peak memory 203660 kb
Host smart-668f04cb-a4cb-416a-9491-f64909caf191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903343461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1903343461
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.451099463
Short name T980
Test name
Test status
Simulation time 41989894 ps
CPU time 0.73 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:29 PM PDT 24
Peak memory 203660 kb
Host smart-5fd22c2b-c9db-4423-9dd8-f7e9754b3023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451099463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.451099463
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.118974735
Short name T1027
Test name
Test status
Simulation time 15999416 ps
CPU time 0.75 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203940 kb
Host smart-db2278ab-d402-4931-a277-92ff1ac9665f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118974735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.118974735
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3188844716
Short name T971
Test name
Test status
Simulation time 14077740 ps
CPU time 0.76 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:32 PM PDT 24
Peak memory 203588 kb
Host smart-3b69dd6c-7ac4-415c-ab28-b1de13807342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188844716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3188844716
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.150151793
Short name T989
Test name
Test status
Simulation time 49282298 ps
CPU time 0.77 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 203564 kb
Host smart-1fe2e428-7a3e-4d80-b0f1-308725498404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150151793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.150151793
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.130959907
Short name T1022
Test name
Test status
Simulation time 72659248 ps
CPU time 0.73 seconds
Started May 09 01:16:25 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203596 kb
Host smart-402ffbfc-d323-4559-b3a7-483b1e4e2dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130959907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.130959907
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1655034708
Short name T1019
Test name
Test status
Simulation time 55252780 ps
CPU time 0.74 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:27 PM PDT 24
Peak memory 203528 kb
Host smart-7bd8ac4e-4ace-4482-97d9-e53437b3831b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655034708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1655034708
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3543535778
Short name T1034
Test name
Test status
Simulation time 36211856 ps
CPU time 0.74 seconds
Started May 09 01:16:28 PM PDT 24
Finished May 09 01:16:32 PM PDT 24
Peak memory 203588 kb
Host smart-fa9b1630-a259-4662-b6ff-756816e8ee37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543535778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3543535778
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.455743273
Short name T991
Test name
Test status
Simulation time 18253572 ps
CPU time 0.76 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:27 PM PDT 24
Peak memory 203416 kb
Host smart-2b38b503-3309-4af3-8e20-c70cc9d58ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455743273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.455743273
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1171636684
Short name T1079
Test name
Test status
Simulation time 207050138 ps
CPU time 13.7 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:16:08 PM PDT 24
Peak memory 206776 kb
Host smart-03fa2e5d-dc5e-4d9d-b4a0-439d93e26a87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171636684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1171636684
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.109015122
Short name T114
Test name
Test status
Simulation time 2269666431 ps
CPU time 33.95 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 207060 kb
Host smart-7cf97f04-8044-4bb6-99ba-b34f541d91db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109015122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.109015122
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2485756233
Short name T80
Test name
Test status
Simulation time 294708286 ps
CPU time 1.46 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 206880 kb
Host smart-a081e728-51fc-4697-8f76-2ce883abc8b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485756233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2485756233
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1398737621
Short name T1028
Test name
Test status
Simulation time 198086951 ps
CPU time 3.62 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 217160 kb
Host smart-01b5fa09-8247-4bca-bb59-db29bf30424f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398737621 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1398737621
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.619775960
Short name T1031
Test name
Test status
Simulation time 204979603 ps
CPU time 1.78 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 215132 kb
Host smart-4494e076-6b0e-416c-aa11-703441f3f55a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619775960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.619775960
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3888900818
Short name T970
Test name
Test status
Simulation time 22702334 ps
CPU time 0.7 seconds
Started May 09 01:15:48 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 203624 kb
Host smart-47730df6-6f74-46f5-b0d0-e216fa90eeee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888900818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
888900818
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2958594650
Short name T1035
Test name
Test status
Simulation time 53880605 ps
CPU time 1.71 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:56 PM PDT 24
Peak memory 215120 kb
Host smart-e0612b76-7c28-4248-9177-96657c9a6e32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958594650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2958594650
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1676127037
Short name T1043
Test name
Test status
Simulation time 12904365 ps
CPU time 0.69 seconds
Started May 09 01:15:51 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 203740 kb
Host smart-acd72dd9-49c0-4da0-8938-b6f673f3ae45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676127037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1676127037
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1387863216
Short name T147
Test name
Test status
Simulation time 236759155 ps
CPU time 2.91 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 215212 kb
Host smart-9cb800c3-3bec-418e-a199-88547a2bb491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387863216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1387863216
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3386006142
Short name T95
Test name
Test status
Simulation time 529519422 ps
CPU time 3.65 seconds
Started May 09 01:15:49 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 215444 kb
Host smart-fa7b0d94-5e48-470f-9489-3fda8d5f81ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386006142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
386006142
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2172444860
Short name T262
Test name
Test status
Simulation time 2182793972 ps
CPU time 14.31 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:16:10 PM PDT 24
Peak memory 215904 kb
Host smart-a75dd224-436c-4ebd-bb94-40c4140538f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172444860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2172444860
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2646646587
Short name T1029
Test name
Test status
Simulation time 21549560 ps
CPU time 0.77 seconds
Started May 09 01:16:24 PM PDT 24
Finished May 09 01:16:28 PM PDT 24
Peak memory 203556 kb
Host smart-71d042c9-841e-4bf9-a1fe-4193314962c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646646587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2646646587
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1712309044
Short name T1077
Test name
Test status
Simulation time 31465576 ps
CPU time 0.75 seconds
Started May 09 01:16:26 PM PDT 24
Finished May 09 01:16:30 PM PDT 24
Peak memory 203636 kb
Host smart-49e98e6e-d114-465e-a744-b4567bf5c75a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712309044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1712309044
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3070694397
Short name T964
Test name
Test status
Simulation time 44882284 ps
CPU time 0.73 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203660 kb
Host smart-896c9524-bd4d-478b-8db1-1301994db3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070694397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3070694397
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3195207213
Short name T1008
Test name
Test status
Simulation time 37585622 ps
CPU time 0.74 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203932 kb
Host smart-f5c353b3-fe17-4718-b2d6-4b7c3067a1d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195207213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3195207213
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.455837383
Short name T1036
Test name
Test status
Simulation time 163454365 ps
CPU time 0.68 seconds
Started May 09 01:16:26 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203584 kb
Host smart-b4bbdf43-1408-4cfd-84f7-cd0d7a7cbe5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455837383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.455837383
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.494715083
Short name T1055
Test name
Test status
Simulation time 18747848 ps
CPU time 0.78 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:32 PM PDT 24
Peak memory 203596 kb
Host smart-efa45b97-a314-416b-be90-2f887bf0abec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494715083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.494715083
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1473150860
Short name T1076
Test name
Test status
Simulation time 103390659 ps
CPU time 0.73 seconds
Started May 09 01:16:26 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203576 kb
Host smart-8a20adbd-d368-4f48-9610-1db62791eb5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473150860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1473150860
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2152969911
Short name T1075
Test name
Test status
Simulation time 47793759 ps
CPU time 0.78 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203864 kb
Host smart-eb0da90f-4249-4055-bda8-7e2671420172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152969911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2152969911
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.657128378
Short name T1056
Test name
Test status
Simulation time 16638593 ps
CPU time 0.75 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203864 kb
Host smart-592ac110-7756-4069-acd8-0ba15c19d296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657128378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.657128378
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3523122252
Short name T1037
Test name
Test status
Simulation time 22908314 ps
CPU time 0.82 seconds
Started May 09 01:16:27 PM PDT 24
Finished May 09 01:16:31 PM PDT 24
Peak memory 203852 kb
Host smart-b0c920ca-5d65-499d-bf46-10ee0da2a59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523122252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3523122252
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1877910247
Short name T988
Test name
Test status
Simulation time 222711955 ps
CPU time 4.07 seconds
Started May 09 01:15:50 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 217588 kb
Host smart-f5ce9363-6c8c-4796-ac66-ecf261177c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877910247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1877910247
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3576167868
Short name T1062
Test name
Test status
Simulation time 103451389 ps
CPU time 2.06 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 215116 kb
Host smart-9435a840-c541-425b-843a-751d5afd94fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576167868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
576167868
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.729906573
Short name T1000
Test name
Test status
Simulation time 12287862 ps
CPU time 0.69 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:15:56 PM PDT 24
Peak memory 203600 kb
Host smart-5a544d96-d7a4-4cde-b42a-1340514217c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729906573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.729906573
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2877634194
Short name T1064
Test name
Test status
Simulation time 282579560 ps
CPU time 3.11 seconds
Started May 09 01:15:49 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 215244 kb
Host smart-ae7f5098-5b32-4784-a645-35cec4e0732c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877634194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2877634194
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.77015144
Short name T1024
Test name
Test status
Simulation time 38934459 ps
CPU time 1.65 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 215424 kb
Host smart-ad1f704c-2f9a-4ac5-95bc-7e2001e79541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77015144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.77015144
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1358386601
Short name T990
Test name
Test status
Simulation time 115643138 ps
CPU time 7.56 seconds
Started May 09 01:15:49 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 215332 kb
Host smart-a253cca9-7430-49aa-b280-bca192f3a611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358386601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1358386601
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2209440145
Short name T1038
Test name
Test status
Simulation time 440400210 ps
CPU time 1.48 seconds
Started May 09 01:15:55 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 207216 kb
Host smart-64ade39a-9808-45be-8d9b-324f780b08f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209440145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
209440145
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2016125031
Short name T1072
Test name
Test status
Simulation time 42443096 ps
CPU time 0.73 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 203920 kb
Host smart-d66ed711-ad77-478b-9bae-7861266d9833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016125031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
016125031
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.244142577
Short name T986
Test name
Test status
Simulation time 568442820 ps
CPU time 3.89 seconds
Started May 09 01:15:53 PM PDT 24
Finished May 09 01:16:00 PM PDT 24
Peak memory 215272 kb
Host smart-7920ab2b-b1bb-4540-9968-0a6fe2081e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244142577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.244142577
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.955158790
Short name T1081
Test name
Test status
Simulation time 831769139 ps
CPU time 12.89 seconds
Started May 09 01:15:52 PM PDT 24
Finished May 09 01:16:08 PM PDT 24
Peak memory 215676 kb
Host smart-86d3d599-d789-48ea-b40e-325ccf063e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955158790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.955158790
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1785134194
Short name T111
Test name
Test status
Simulation time 483980085 ps
CPU time 3.66 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:17 PM PDT 24
Peak memory 217348 kb
Host smart-280cca4b-b287-4a39-8992-2e3484c9156b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785134194 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1785134194
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1636332182
Short name T996
Test name
Test status
Simulation time 55720597 ps
CPU time 1.31 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215236 kb
Host smart-74061844-0e5a-48c4-86d5-e4e2330ccfb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636332182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
636332182
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2985324549
Short name T1018
Test name
Test status
Simulation time 31811524 ps
CPU time 0.74 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 203604 kb
Host smart-d6599787-21bb-4a35-9639-469d017bb70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985324549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
985324549
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1392080130
Short name T1016
Test name
Test status
Simulation time 27775100 ps
CPU time 1.77 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215256 kb
Host smart-0a863f44-1793-423e-a23a-8ca99c13e9dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392080130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1392080130
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.270979347
Short name T1021
Test name
Test status
Simulation time 65808903 ps
CPU time 5.12 seconds
Started May 09 01:15:55 PM PDT 24
Finished May 09 01:16:03 PM PDT 24
Peak memory 216668 kb
Host smart-9d79355c-f2d0-4596-9074-100595c1b6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270979347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.270979347
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3369871140
Short name T98
Test name
Test status
Simulation time 499949417 ps
CPU time 3.72 seconds
Started May 09 01:16:08 PM PDT 24
Finished May 09 01:16:13 PM PDT 24
Peak memory 217804 kb
Host smart-f6efbefb-824a-4ed2-bbbb-5b9bff932c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369871140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3369871140
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.954099806
Short name T1050
Test name
Test status
Simulation time 71330522 ps
CPU time 2.52 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215200 kb
Host smart-23da1e40-c8dd-40d5-9eb3-9b60fa4776b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954099806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.954099806
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.107049283
Short name T1042
Test name
Test status
Simulation time 38652870 ps
CPU time 0.71 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:14 PM PDT 24
Peak memory 203592 kb
Host smart-36d070d1-9552-4f91-92ee-db4d1f0053a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107049283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.107049283
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2651241737
Short name T1023
Test name
Test status
Simulation time 302379884 ps
CPU time 3.81 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 215232 kb
Host smart-42b0ebd2-6710-47cd-a81c-1c26c6f472f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651241737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2651241737
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1359671465
Short name T109
Test name
Test status
Simulation time 144803004 ps
CPU time 3.58 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:17 PM PDT 24
Peak memory 216640 kb
Host smart-14e62778-104a-4635-a86d-e3d22fb6d87b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359671465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
359671465
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1360870768
Short name T267
Test name
Test status
Simulation time 811626329 ps
CPU time 12.86 seconds
Started May 09 01:16:08 PM PDT 24
Finished May 09 01:16:21 PM PDT 24
Peak memory 215296 kb
Host smart-2f60da68-fb87-4979-87dc-d55ea0db40ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360870768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1360870768
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3185506130
Short name T1007
Test name
Test status
Simulation time 171749458 ps
CPU time 2.46 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:15 PM PDT 24
Peak memory 217476 kb
Host smart-1d4f39e3-0bb1-4736-8e72-52cc7dbb9ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185506130 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3185506130
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2168411940
Short name T124
Test name
Test status
Simulation time 531279885 ps
CPU time 2.62 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:17 PM PDT 24
Peak memory 206964 kb
Host smart-776f0269-89c7-485e-8ee4-5d0c13ee62df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168411940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
168411940
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2272063627
Short name T975
Test name
Test status
Simulation time 57190859 ps
CPU time 0.7 seconds
Started May 09 01:16:09 PM PDT 24
Finished May 09 01:16:12 PM PDT 24
Peak memory 203616 kb
Host smart-0482ab16-6b11-4f63-98b9-b48197a3a70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272063627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
272063627
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.8995413
Short name T981
Test name
Test status
Simulation time 59361717 ps
CPU time 3.77 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:18 PM PDT 24
Peak memory 215332 kb
Host smart-5123098c-334a-4a0a-b15f-f45457ba7c98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8995413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_
device_same_csr_outstanding.8995413
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1761590684
Short name T1051
Test name
Test status
Simulation time 620245178 ps
CPU time 4.01 seconds
Started May 09 01:16:10 PM PDT 24
Finished May 09 01:16:17 PM PDT 24
Peak memory 215484 kb
Host smart-bbbb9e6a-3e93-457b-914d-352138aea391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761590684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
761590684
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2960507802
Short name T266
Test name
Test status
Simulation time 206870113 ps
CPU time 12.33 seconds
Started May 09 01:16:11 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 216720 kb
Host smart-41e6c015-252c-41bd-a6c5-0b5ab90d5d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960507802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2960507802
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2315324024
Short name T518
Test name
Test status
Simulation time 39512721 ps
CPU time 0.72 seconds
Started May 09 01:29:21 PM PDT 24
Finished May 09 01:29:23 PM PDT 24
Peak memory 205328 kb
Host smart-514281cd-7b1b-40ad-aeb9-8e429336605d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315324024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
315324024
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1836221484
Short name T440
Test name
Test status
Simulation time 3146657196 ps
CPU time 26.17 seconds
Started May 09 01:29:32 PM PDT 24
Finished May 09 01:30:00 PM PDT 24
Peak memory 224444 kb
Host smart-5e047b8e-6880-4c2a-906e-191d3507c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836221484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1836221484
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1634000315
Short name T390
Test name
Test status
Simulation time 32225761 ps
CPU time 0.8 seconds
Started May 09 01:29:21 PM PDT 24
Finished May 09 01:29:24 PM PDT 24
Peak memory 206564 kb
Host smart-fd69f8d1-9463-471a-99bc-6ad040899b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634000315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1634000315
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1863413637
Short name T11
Test name
Test status
Simulation time 5410867161 ps
CPU time 56.46 seconds
Started May 09 01:29:21 PM PDT 24
Finished May 09 01:30:20 PM PDT 24
Peak memory 240856 kb
Host smart-eb567e5b-d297-424a-be16-2c692c2f496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863413637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1863413637
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2335413606
Short name T697
Test name
Test status
Simulation time 6129223471 ps
CPU time 52.64 seconds
Started May 09 01:29:32 PM PDT 24
Finished May 09 01:30:26 PM PDT 24
Peak memory 235184 kb
Host smart-5208e234-63f0-4f8c-8f48-4937a2d5778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335413606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2335413606
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.116531848
Short name T830
Test name
Test status
Simulation time 95605584754 ps
CPU time 228.88 seconds
Started May 09 01:29:24 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 240936 kb
Host smart-a0b47d6a-ef60-463d-9290-49beeb5ddd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116531848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
116531848
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3734405871
Short name T664
Test name
Test status
Simulation time 319531873 ps
CPU time 7.02 seconds
Started May 09 01:29:31 PM PDT 24
Finished May 09 01:29:39 PM PDT 24
Peak memory 238304 kb
Host smart-b8fb4579-69d3-42c9-96a0-d4ccca4f158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734405871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3734405871
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2408342992
Short name T177
Test name
Test status
Simulation time 17420445624 ps
CPU time 74.84 seconds
Started May 09 01:29:18 PM PDT 24
Finished May 09 01:30:33 PM PDT 24
Peak memory 250976 kb
Host smart-b634d058-d9db-409c-a30f-ba6a02491b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408342992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2408342992
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2003792910
Short name T753
Test name
Test status
Simulation time 2851453935 ps
CPU time 10.44 seconds
Started May 09 01:29:28 PM PDT 24
Finished May 09 01:29:40 PM PDT 24
Peak memory 232724 kb
Host smart-717967ef-bc35-4eb6-8fe1-dbaa3aec64ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003792910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2003792910
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4123623402
Short name T270
Test name
Test status
Simulation time 2178179256 ps
CPU time 6.14 seconds
Started May 09 01:29:27 PM PDT 24
Finished May 09 01:29:34 PM PDT 24
Peak memory 233716 kb
Host smart-9e093cf6-5587-44c0-9a76-fdc0a20ed51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123623402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4123623402
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3881033068
Short name T614
Test name
Test status
Simulation time 810401079 ps
CPU time 9.76 seconds
Started May 09 01:29:20 PM PDT 24
Finished May 09 01:29:32 PM PDT 24
Peak memory 219076 kb
Host smart-9488fff6-dd40-40c8-a7c0-2ce2e73af995
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881033068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3881033068
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1096710899
Short name T153
Test name
Test status
Simulation time 22942364486 ps
CPU time 31.18 seconds
Started May 09 01:29:25 PM PDT 24
Finished May 09 01:29:57 PM PDT 24
Peak memory 224544 kb
Host smart-d4c92fa8-682d-4acf-ba01-6e61d7905818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096710899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1096710899
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3627553045
Short name T808
Test name
Test status
Simulation time 12867221308 ps
CPU time 33.69 seconds
Started May 09 01:29:20 PM PDT 24
Finished May 09 01:29:56 PM PDT 24
Peak memory 216304 kb
Host smart-253cbff0-f611-4f65-a040-bdc93818d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627553045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3627553045
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.563649380
Short name T703
Test name
Test status
Simulation time 9592605196 ps
CPU time 14.36 seconds
Started May 09 01:29:09 PM PDT 24
Finished May 09 01:29:24 PM PDT 24
Peak memory 216264 kb
Host smart-95b37a88-73d9-433e-8299-c62ff3a08cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563649380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.563649380
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1697321400
Short name T633
Test name
Test status
Simulation time 83843639 ps
CPU time 1.04 seconds
Started May 09 01:29:28 PM PDT 24
Finished May 09 01:29:30 PM PDT 24
Peak memory 207260 kb
Host smart-5679c341-5621-4c3d-81fd-d2c33f1ffe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697321400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1697321400
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3065263568
Short name T397
Test name
Test status
Simulation time 50226865 ps
CPU time 0.93 seconds
Started May 09 01:29:21 PM PDT 24
Finished May 09 01:29:24 PM PDT 24
Peak memory 205776 kb
Host smart-65461ddd-dfdd-4968-bdb9-a4c787140e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065263568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3065263568
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3106162954
Short name T383
Test name
Test status
Simulation time 33590530 ps
CPU time 2.39 seconds
Started May 09 01:29:31 PM PDT 24
Finished May 09 01:29:35 PM PDT 24
Peak memory 212944 kb
Host smart-f1826837-64ff-4515-b660-a28e5c00ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106162954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3106162954
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1505702115
Short name T835
Test name
Test status
Simulation time 17012205 ps
CPU time 0.7 seconds
Started May 09 01:29:37 PM PDT 24
Finished May 09 01:29:38 PM PDT 24
Peak memory 204728 kb
Host smart-75bccbfa-e93f-4bb7-85d1-742e0b28ca14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505702115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
505702115
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2278951036
Short name T708
Test name
Test status
Simulation time 1123738350 ps
CPU time 10.7 seconds
Started May 09 01:29:37 PM PDT 24
Finished May 09 01:29:48 PM PDT 24
Peak memory 218452 kb
Host smart-1c923295-8d01-4930-987d-1a1bfa6377bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278951036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2278951036
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4074317407
Short name T666
Test name
Test status
Simulation time 18854640 ps
CPU time 0.79 seconds
Started May 09 01:29:31 PM PDT 24
Finished May 09 01:29:34 PM PDT 24
Peak memory 205460 kb
Host smart-087ba6d1-6155-4f10-8317-99b5d8b6eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074317407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4074317407
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2842773686
Short name T210
Test name
Test status
Simulation time 567582140 ps
CPU time 5.35 seconds
Started May 09 01:29:33 PM PDT 24
Finished May 09 01:29:40 PM PDT 24
Peak memory 224444 kb
Host smart-3cfbae73-2731-4fd8-88f9-8a343b6fd44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842773686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2842773686
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3782565193
Short name T716
Test name
Test status
Simulation time 18390787968 ps
CPU time 164.16 seconds
Started May 09 01:29:33 PM PDT 24
Finished May 09 01:32:18 PM PDT 24
Peak memory 256940 kb
Host smart-596d737d-b077-4ed9-bc0a-bbf1a70fed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782565193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3782565193
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2536727830
Short name T378
Test name
Test status
Simulation time 18619326321 ps
CPU time 169.41 seconds
Started May 09 01:29:33 PM PDT 24
Finished May 09 01:32:24 PM PDT 24
Peak memory 233740 kb
Host smart-45521ad6-4d11-403e-8777-484a37315966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536727830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2536727830
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2827513901
Short name T473
Test name
Test status
Simulation time 5070001481 ps
CPU time 15.06 seconds
Started May 09 01:29:33 PM PDT 24
Finished May 09 01:29:49 PM PDT 24
Peak memory 224440 kb
Host smart-6191a164-936b-4d88-b2a3-ac3f30d8bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827513901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2827513901
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.113045600
Short name T195
Test name
Test status
Simulation time 125944992 ps
CPU time 2.47 seconds
Started May 09 01:29:32 PM PDT 24
Finished May 09 01:29:36 PM PDT 24
Peak memory 232616 kb
Host smart-0db50467-7b3b-4ad3-a57d-a781540e825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113045600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.113045600
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4126772226
Short name T554
Test name
Test status
Simulation time 12786390860 ps
CPU time 47.72 seconds
Started May 09 01:29:36 PM PDT 24
Finished May 09 01:30:24 PM PDT 24
Peak memory 238372 kb
Host smart-f9161c6f-5868-4d0e-be9f-37b25ebdea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126772226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4126772226
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.692865721
Short name T769
Test name
Test status
Simulation time 497005964 ps
CPU time 5.47 seconds
Started May 09 01:29:36 PM PDT 24
Finished May 09 01:29:42 PM PDT 24
Peak memory 234932 kb
Host smart-12954aa4-cf9b-4bda-ba74-7d22322b428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692865721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
692865721
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.114551952
Short name T201
Test name
Test status
Simulation time 28165495622 ps
CPU time 20.43 seconds
Started May 09 01:29:31 PM PDT 24
Finished May 09 01:29:52 PM PDT 24
Peak memory 233380 kb
Host smart-0fec5719-5d4a-4260-ae82-eef92a8473b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114551952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.114551952
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2036506279
Short name T64
Test name
Test status
Simulation time 237361316 ps
CPU time 1.12 seconds
Started May 09 01:29:33 PM PDT 24
Finished May 09 01:29:35 PM PDT 24
Peak memory 234676 kb
Host smart-c1b7bd31-a315-4f68-ae20-d27819968041
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036506279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2036506279
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3375148673
Short name T133
Test name
Test status
Simulation time 63628556 ps
CPU time 1.15 seconds
Started May 09 01:29:32 PM PDT 24
Finished May 09 01:29:35 PM PDT 24
Peak memory 206860 kb
Host smart-61f2a3cc-4651-43ee-aa89-65b48a5d5d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375148673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3375148673
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1761705790
Short name T555
Test name
Test status
Simulation time 7066588768 ps
CPU time 33.52 seconds
Started May 09 01:29:22 PM PDT 24
Finished May 09 01:29:57 PM PDT 24
Peak memory 216340 kb
Host smart-de8b81d9-128d-46d8-b463-f781b2d97db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761705790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1761705790
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1333813608
Short name T942
Test name
Test status
Simulation time 5121351498 ps
CPU time 10.76 seconds
Started May 09 01:29:24 PM PDT 24
Finished May 09 01:29:36 PM PDT 24
Peak memory 216216 kb
Host smart-e908c80c-ba6b-4885-83ef-219601515c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333813608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1333813608
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.449842972
Short name T463
Test name
Test status
Simulation time 88772306 ps
CPU time 4.31 seconds
Started May 09 01:29:19 PM PDT 24
Finished May 09 01:29:24 PM PDT 24
Peak memory 216136 kb
Host smart-9d8c4b87-cc64-40ca-9f38-82e01fec2aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449842972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.449842972
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1981774466
Short name T923
Test name
Test status
Simulation time 16618486 ps
CPU time 0.72 seconds
Started May 09 01:29:31 PM PDT 24
Finished May 09 01:29:32 PM PDT 24
Peak memory 205640 kb
Host smart-d9817777-9cb1-4a75-9595-092e9c2b9675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981774466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1981774466
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1986597034
Short name T291
Test name
Test status
Simulation time 901487691 ps
CPU time 2.64 seconds
Started May 09 01:29:32 PM PDT 24
Finished May 09 01:29:36 PM PDT 24
Peak memory 234340 kb
Host smart-6dd98be3-c830-48a0-a845-dd6448ca26d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986597034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1986597034
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2668261969
Short name T548
Test name
Test status
Simulation time 1835111066 ps
CPU time 16.92 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:53 PM PDT 24
Peak memory 220836 kb
Host smart-73a090ec-2112-4140-acce-9d85ca95172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668261969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2668261969
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1869643975
Short name T699
Test name
Test status
Simulation time 21248502 ps
CPU time 0.82 seconds
Started May 09 01:30:32 PM PDT 24
Finished May 09 01:30:35 PM PDT 24
Peak memory 206868 kb
Host smart-1597728d-b874-4344-bc41-0a2607ad05a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869643975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1869643975
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2762840049
Short name T781
Test name
Test status
Simulation time 31760195666 ps
CPU time 58.91 seconds
Started May 09 01:30:26 PM PDT 24
Finished May 09 01:31:26 PM PDT 24
Peak memory 232624 kb
Host smart-1fbbcf50-33e4-46ae-abe5-14fc89625e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762840049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2762840049
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1578859400
Short name T880
Test name
Test status
Simulation time 145376603 ps
CPU time 4.61 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:40 PM PDT 24
Peak memory 224304 kb
Host smart-e13210d5-95fd-44d0-ab72-a8442b581daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578859400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1578859400
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.484936471
Short name T793
Test name
Test status
Simulation time 1056495780 ps
CPU time 4.82 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:41 PM PDT 24
Peak memory 233728 kb
Host smart-b2a072dd-83b9-4fe6-ae2f-cb3fa75d907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484936471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.484936471
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3212926309
Short name T734
Test name
Test status
Simulation time 725883034 ps
CPU time 14.93 seconds
Started May 09 01:30:33 PM PDT 24
Finished May 09 01:30:49 PM PDT 24
Peak memory 249704 kb
Host smart-060afcf5-5cb4-434a-9f49-3e276ad6df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212926309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3212926309
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3458208072
Short name T834
Test name
Test status
Simulation time 4236754444 ps
CPU time 9.13 seconds
Started May 09 01:30:33 PM PDT 24
Finished May 09 01:30:44 PM PDT 24
Peak memory 233700 kb
Host smart-91bf9c2d-0b6b-4ceb-8c14-4dffc6ef5ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458208072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3458208072
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1125684580
Short name T651
Test name
Test status
Simulation time 205186732 ps
CPU time 4.17 seconds
Started May 09 01:30:28 PM PDT 24
Finished May 09 01:30:33 PM PDT 24
Peak memory 219848 kb
Host smart-9968f644-3d04-4e31-97a1-c9a2ff9c940d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1125684580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1125684580
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3864706753
Short name T156
Test name
Test status
Simulation time 37322274362 ps
CPU time 70.22 seconds
Started May 09 01:30:26 PM PDT 24
Finished May 09 01:31:37 PM PDT 24
Peak memory 252400 kb
Host smart-a957ecac-d583-45e9-893a-921a23f79079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864706753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3864706753
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.759297508
Short name T320
Test name
Test status
Simulation time 5974872784 ps
CPU time 16.43 seconds
Started May 09 01:30:27 PM PDT 24
Finished May 09 01:30:45 PM PDT 24
Peak memory 216264 kb
Host smart-5eff000f-f77b-472d-9bd0-2c06863006e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759297508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.759297508
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.901013679
Short name T419
Test name
Test status
Simulation time 1028577314 ps
CPU time 3.7 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:39 PM PDT 24
Peak memory 216040 kb
Host smart-b7bf9768-800b-4e35-af81-189eb3e26729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901013679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.901013679
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4161332631
Short name T10
Test name
Test status
Simulation time 144415778 ps
CPU time 1.41 seconds
Started May 09 01:30:32 PM PDT 24
Finished May 09 01:30:35 PM PDT 24
Peak memory 216260 kb
Host smart-64142c45-5a21-4ab8-ba57-72eb54cfb68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161332631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4161332631
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2814516208
Short name T783
Test name
Test status
Simulation time 30649818 ps
CPU time 0.76 seconds
Started May 09 01:30:25 PM PDT 24
Finished May 09 01:30:26 PM PDT 24
Peak memory 205712 kb
Host smart-58f13263-c747-4fe2-ba94-a70a705c7c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814516208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2814516208
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1380749507
Short name T215
Test name
Test status
Simulation time 17725398873 ps
CPU time 22.75 seconds
Started May 09 01:30:23 PM PDT 24
Finished May 09 01:30:47 PM PDT 24
Peak memory 240856 kb
Host smart-0f815c3d-1999-4f2a-beda-43a07d0a5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380749507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1380749507
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3974639783
Short name T910
Test name
Test status
Simulation time 61480165 ps
CPU time 0.72 seconds
Started May 09 01:30:37 PM PDT 24
Finished May 09 01:30:39 PM PDT 24
Peak memory 205320 kb
Host smart-5dafc179-f164-4f77-be76-19aeaa58eb41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974639783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3974639783
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2227046384
Short name T381
Test name
Test status
Simulation time 208701300 ps
CPU time 2.58 seconds
Started May 09 01:30:33 PM PDT 24
Finished May 09 01:30:37 PM PDT 24
Peak memory 233164 kb
Host smart-35cfcd1b-ec47-4663-9ecb-bc511183128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227046384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2227046384
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1117901109
Short name T687
Test name
Test status
Simulation time 68677771 ps
CPU time 0.78 seconds
Started May 09 01:30:28 PM PDT 24
Finished May 09 01:30:30 PM PDT 24
Peak memory 206380 kb
Host smart-99a9aed2-c63b-48d3-874d-b6f9a6d4cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117901109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1117901109
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2849074423
Short name T460
Test name
Test status
Simulation time 4829264199 ps
CPU time 27.25 seconds
Started May 09 01:30:33 PM PDT 24
Finished May 09 01:31:02 PM PDT 24
Peak memory 240064 kb
Host smart-c9809334-0382-40eb-8636-369945d100ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849074423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2849074423
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.240053442
Short name T526
Test name
Test status
Simulation time 538547357 ps
CPU time 14.87 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:51 PM PDT 24
Peak memory 232676 kb
Host smart-e66473aa-0cd5-4419-8d10-4c8e751dcefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240053442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.240053442
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2547955317
Short name T652
Test name
Test status
Simulation time 74432676323 ps
CPU time 183.76 seconds
Started May 09 01:30:33 PM PDT 24
Finished May 09 01:33:38 PM PDT 24
Peak memory 249796 kb
Host smart-fa15f387-5565-4e76-8c22-e523912e9cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547955317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2547955317
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2838454546
Short name T316
Test name
Test status
Simulation time 804799107 ps
CPU time 12.81 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:48 PM PDT 24
Peak memory 234940 kb
Host smart-64a25ac7-5afc-4f7b-94e7-2b05ddc9a10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838454546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2838454546
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.233805012
Short name T545
Test name
Test status
Simulation time 1717935670 ps
CPU time 5.58 seconds
Started May 09 01:30:37 PM PDT 24
Finished May 09 01:30:43 PM PDT 24
Peak memory 219384 kb
Host smart-b1a30e8f-ad35-41c3-a1c0-858059d40628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233805012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.233805012
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2073752138
Short name T960
Test name
Test status
Simulation time 393077854 ps
CPU time 12.71 seconds
Started May 09 01:30:31 PM PDT 24
Finished May 09 01:30:44 PM PDT 24
Peak memory 246552 kb
Host smart-af6febcb-0d02-42bb-8e51-2d1a730ebd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073752138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2073752138
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3685572009
Short name T283
Test name
Test status
Simulation time 691216642 ps
CPU time 4.8 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:41 PM PDT 24
Peak memory 233520 kb
Host smart-291456d5-5421-4d16-bccc-aa0e8776e8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685572009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3685572009
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3501815161
Short name T949
Test name
Test status
Simulation time 5320745059 ps
CPU time 15.34 seconds
Started May 09 01:30:37 PM PDT 24
Finished May 09 01:30:54 PM PDT 24
Peak memory 225928 kb
Host smart-b3f8f95c-03aa-4679-9ca5-94837ea20666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501815161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3501815161
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2764773888
Short name T129
Test name
Test status
Simulation time 1169012983 ps
CPU time 12.23 seconds
Started May 09 01:30:41 PM PDT 24
Finished May 09 01:30:54 PM PDT 24
Peak memory 219472 kb
Host smart-ab6ed7b5-89b2-42ac-9372-6fbc11cc1e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2764773888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2764773888
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2457876011
Short name T571
Test name
Test status
Simulation time 119177864 ps
CPU time 0.97 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:36 PM PDT 24
Peak memory 206500 kb
Host smart-f7da10af-7bfa-4158-bd54-12932adfeaa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457876011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2457876011
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3734951479
Short name T905
Test name
Test status
Simulation time 1222783458 ps
CPU time 3.39 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:39 PM PDT 24
Peak memory 207728 kb
Host smart-58b85ed9-bcc4-42cf-bf9f-10c4a2392300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734951479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3734951479
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.283497939
Short name T388
Test name
Test status
Simulation time 52912625 ps
CPU time 1.25 seconds
Started May 09 01:30:31 PM PDT 24
Finished May 09 01:30:33 PM PDT 24
Peak memory 216180 kb
Host smart-d56ea705-2e43-4d63-8934-7beecc8bb90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283497939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.283497939
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3996728787
Short name T765
Test name
Test status
Simulation time 238833170 ps
CPU time 1 seconds
Started May 09 01:30:41 PM PDT 24
Finished May 09 01:30:43 PM PDT 24
Peak memory 205956 kb
Host smart-b93bbf7f-47d9-4a0a-93e0-79ce8963f823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996728787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3996728787
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1064926106
Short name T21
Test name
Test status
Simulation time 13461399474 ps
CPU time 13.06 seconds
Started May 09 01:30:35 PM PDT 24
Finished May 09 01:30:49 PM PDT 24
Peak memory 233940 kb
Host smart-b4118d9f-c59a-4248-98e2-2ed7f844a419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064926106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1064926106
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.269256714
Short name T826
Test name
Test status
Simulation time 36567476 ps
CPU time 0.73 seconds
Started May 09 01:30:49 PM PDT 24
Finished May 09 01:30:51 PM PDT 24
Peak memory 205368 kb
Host smart-41ab3ea1-3cd9-40bb-b2d6-31a89d57400b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269256714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.269256714
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.724130383
Short name T24
Test name
Test status
Simulation time 386602814 ps
CPU time 2.19 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:38 PM PDT 24
Peak memory 219008 kb
Host smart-02ff18a4-ec58-47ac-b8ce-612d1431e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724130383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.724130383
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3931493344
Short name T816
Test name
Test status
Simulation time 18875789 ps
CPU time 0.8 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:30:36 PM PDT 24
Peak memory 206312 kb
Host smart-1ee96a30-3e94-4da9-bfa3-dba8eae586d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931493344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3931493344
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3425909738
Short name T231
Test name
Test status
Simulation time 60133218976 ps
CPU time 109.24 seconds
Started May 09 01:30:47 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 240864 kb
Host smart-2d125a0d-d3dc-485f-a8de-f4a38ae11b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425909738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3425909738
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2900758372
Short name T238
Test name
Test status
Simulation time 35258179870 ps
CPU time 111.01 seconds
Started May 09 01:30:51 PM PDT 24
Finished May 09 01:32:44 PM PDT 24
Peak memory 249356 kb
Host smart-123350d9-5411-4107-89dc-539d2567319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900758372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2900758372
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.798699518
Short name T249
Test name
Test status
Simulation time 10263134009 ps
CPU time 53.6 seconds
Started May 09 01:30:54 PM PDT 24
Finished May 09 01:31:49 PM PDT 24
Peak memory 250168 kb
Host smart-b4ad6ac1-fbab-497a-9b50-eb61db56743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798699518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.798699518
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1579478638
Short name T310
Test name
Test status
Simulation time 569275407 ps
CPU time 11.85 seconds
Started May 09 01:30:31 PM PDT 24
Finished May 09 01:30:44 PM PDT 24
Peak memory 232536 kb
Host smart-4316a215-f696-4f0f-bd58-e58315e01a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579478638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1579478638
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1684679510
Short name T665
Test name
Test status
Simulation time 1585870034 ps
CPU time 7.36 seconds
Started May 09 01:30:35 PM PDT 24
Finished May 09 01:30:44 PM PDT 24
Peak memory 218496 kb
Host smart-5790ef78-bc13-4fcc-8175-47e21f3e7de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684679510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1684679510
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3539707626
Short name T188
Test name
Test status
Simulation time 33618687 ps
CPU time 2.66 seconds
Started May 09 01:30:41 PM PDT 24
Finished May 09 01:30:44 PM PDT 24
Peak memory 232576 kb
Host smart-a67af8d1-0540-4053-9f8c-b7e29fa89943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539707626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3539707626
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.376206900
Short name T853
Test name
Test status
Simulation time 1187989213 ps
CPU time 3.74 seconds
Started May 09 01:30:33 PM PDT 24
Finished May 09 01:30:38 PM PDT 24
Peak memory 233584 kb
Host smart-841f079d-c5ec-4614-9084-419e6bd10806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376206900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.376206900
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2032679236
Short name T183
Test name
Test status
Simulation time 1207954794 ps
CPU time 6.78 seconds
Started May 09 01:30:37 PM PDT 24
Finished May 09 01:30:45 PM PDT 24
Peak memory 233500 kb
Host smart-3139fba8-25ec-441c-af7a-ebaa3e6d518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032679236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2032679236
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1877798232
Short name T772
Test name
Test status
Simulation time 933785148 ps
CPU time 3.9 seconds
Started May 09 01:30:48 PM PDT 24
Finished May 09 01:30:54 PM PDT 24
Peak memory 220212 kb
Host smart-b43914a3-866d-40a6-a6b2-005ebea43237
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877798232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1877798232
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3957710485
Short name T945
Test name
Test status
Simulation time 73459375096 ps
CPU time 204.08 seconds
Started May 09 01:30:54 PM PDT 24
Finished May 09 01:34:19 PM PDT 24
Peak memory 256240 kb
Host smart-388c2e0a-3c44-4cdf-a1d2-2e21232ff343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957710485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3957710485
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3072978097
Short name T915
Test name
Test status
Simulation time 2738833404 ps
CPU time 33.69 seconds
Started May 09 01:30:41 PM PDT 24
Finished May 09 01:31:16 PM PDT 24
Peak memory 217456 kb
Host smart-a6102213-180a-4c15-b903-ae31a7101ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072978097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3072978097
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2846465181
Short name T541
Test name
Test status
Simulation time 3086894878 ps
CPU time 10.19 seconds
Started May 09 01:30:41 PM PDT 24
Finished May 09 01:30:52 PM PDT 24
Peak memory 216136 kb
Host smart-cb5e44a7-222e-4906-9f03-6c8d4ba09dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846465181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2846465181
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3710977407
Short name T870
Test name
Test status
Simulation time 281534815 ps
CPU time 1.79 seconds
Started May 09 01:30:38 PM PDT 24
Finished May 09 01:30:40 PM PDT 24
Peak memory 216188 kb
Host smart-7a65f697-61b6-4e4e-847b-5f24a247acf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710977407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3710977407
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.641898216
Short name T856
Test name
Test status
Simulation time 103380566 ps
CPU time 0.87 seconds
Started May 09 01:30:41 PM PDT 24
Finished May 09 01:30:42 PM PDT 24
Peak memory 205912 kb
Host smart-efb373cf-921d-4dce-a52b-3aa8a5215199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641898216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.641898216
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3572448840
Short name T813
Test name
Test status
Simulation time 248561751 ps
CPU time 6.08 seconds
Started May 09 01:30:37 PM PDT 24
Finished May 09 01:30:44 PM PDT 24
Peak memory 233432 kb
Host smart-cae6c53c-9161-4c53-97b2-f9a8355efa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572448840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3572448840
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1639984654
Short name T342
Test name
Test status
Simulation time 13364692 ps
CPU time 0.7 seconds
Started May 09 01:30:50 PM PDT 24
Finished May 09 01:30:52 PM PDT 24
Peak memory 205496 kb
Host smart-5c175791-2fc1-41a9-b67d-ccc2f6acb4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639984654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1639984654
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.830753873
Short name T482
Test name
Test status
Simulation time 489238148 ps
CPU time 4.66 seconds
Started May 09 01:30:54 PM PDT 24
Finished May 09 01:31:01 PM PDT 24
Peak memory 233172 kb
Host smart-216cb385-8f43-438e-9e1b-81e5ddea44d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830753873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.830753873
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.432204072
Short name T534
Test name
Test status
Simulation time 283603880 ps
CPU time 0.8 seconds
Started May 09 01:30:55 PM PDT 24
Finished May 09 01:30:57 PM PDT 24
Peak memory 206436 kb
Host smart-8c5efbb3-7c44-45da-83b5-212e8507b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432204072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.432204072
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2508375533
Short name T947
Test name
Test status
Simulation time 22414259023 ps
CPU time 40.16 seconds
Started May 09 01:30:50 PM PDT 24
Finished May 09 01:31:32 PM PDT 24
Peak memory 235224 kb
Host smart-79d80b7c-de16-4896-b06d-a64f470caae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508375533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2508375533
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1337016112
Short name T918
Test name
Test status
Simulation time 11713281230 ps
CPU time 67.62 seconds
Started May 09 01:30:57 PM PDT 24
Finished May 09 01:32:06 PM PDT 24
Peak memory 254316 kb
Host smart-e4922f07-a7e7-4f6d-ad31-cccf335be434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337016112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1337016112
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2546070529
Short name T138
Test name
Test status
Simulation time 6057020583 ps
CPU time 51.55 seconds
Started May 09 01:30:55 PM PDT 24
Finished May 09 01:31:48 PM PDT 24
Peak memory 249048 kb
Host smart-2aa2548a-f908-444e-8473-917d657e3eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546070529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2546070529
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.858318320
Short name T653
Test name
Test status
Simulation time 241800507 ps
CPU time 5.99 seconds
Started May 09 01:30:54 PM PDT 24
Finished May 09 01:31:01 PM PDT 24
Peak memory 235204 kb
Host smart-fa72f5ae-6247-416e-9df7-2b17242cd6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858318320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.858318320
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1675728329
Short name T200
Test name
Test status
Simulation time 163541672 ps
CPU time 3.05 seconds
Started May 09 01:30:56 PM PDT 24
Finished May 09 01:31:00 PM PDT 24
Peak memory 218504 kb
Host smart-f6e716b7-54b0-475b-9380-73f11563dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675728329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1675728329
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1929817732
Short name T517
Test name
Test status
Simulation time 3507999410 ps
CPU time 6.95 seconds
Started May 09 01:30:55 PM PDT 24
Finished May 09 01:31:03 PM PDT 24
Peak memory 218412 kb
Host smart-46c8f6fa-d464-479e-846f-6cdf4a3b79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929817732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1929817732
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1292533236
Short name T743
Test name
Test status
Simulation time 125651364 ps
CPU time 2.47 seconds
Started May 09 01:30:51 PM PDT 24
Finished May 09 01:30:55 PM PDT 24
Peak memory 221296 kb
Host smart-c93cc5b8-6051-40fd-b596-05fd5729efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292533236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1292533236
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.876093711
Short name T421
Test name
Test status
Simulation time 3101123864 ps
CPU time 11.24 seconds
Started May 09 01:30:56 PM PDT 24
Finished May 09 01:31:09 PM PDT 24
Peak memory 219224 kb
Host smart-3ae29af1-6759-4ca6-9a63-68d37ac3ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876093711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.876093711
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1239238826
Short name T7
Test name
Test status
Simulation time 1488609698 ps
CPU time 17.5 seconds
Started May 09 01:30:53 PM PDT 24
Finished May 09 01:31:12 PM PDT 24
Peak memory 219308 kb
Host smart-bd82a0d4-2fd0-4c58-a65d-7d8ae5d66d87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1239238826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1239238826
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.429912160
Short name T245
Test name
Test status
Simulation time 4097588175 ps
CPU time 107.47 seconds
Started May 09 01:30:49 PM PDT 24
Finished May 09 01:32:38 PM PDT 24
Peak memory 255548 kb
Host smart-56145159-f04d-40e5-97f2-23e0ea122de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429912160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.429912160
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.223025178
Short name T493
Test name
Test status
Simulation time 5396826734 ps
CPU time 35.25 seconds
Started May 09 01:30:52 PM PDT 24
Finished May 09 01:31:29 PM PDT 24
Peak memory 216236 kb
Host smart-d2f3593a-9622-479c-851f-0f95fc9843fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223025178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.223025178
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.689803822
Short name T126
Test name
Test status
Simulation time 1861080877 ps
CPU time 5.76 seconds
Started May 09 01:30:51 PM PDT 24
Finished May 09 01:30:58 PM PDT 24
Peak memory 216120 kb
Host smart-60e5fd33-111c-47f0-b988-0181c94840fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689803822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.689803822
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4081556476
Short name T424
Test name
Test status
Simulation time 19244041 ps
CPU time 0.7 seconds
Started May 09 01:30:54 PM PDT 24
Finished May 09 01:30:56 PM PDT 24
Peak memory 205476 kb
Host smart-0d80b22b-b9e5-4d30-a3fb-a8f812defcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081556476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4081556476
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1415810209
Short name T341
Test name
Test status
Simulation time 24215959 ps
CPU time 0.79 seconds
Started May 09 01:30:51 PM PDT 24
Finished May 09 01:30:53 PM PDT 24
Peak memory 205736 kb
Host smart-c4d18ce7-fabb-4150-ab9b-b9cf4a560207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415810209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1415810209
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1574592695
Short name T672
Test name
Test status
Simulation time 201632875 ps
CPU time 4.3 seconds
Started May 09 01:30:55 PM PDT 24
Finished May 09 01:31:01 PM PDT 24
Peak memory 234336 kb
Host smart-9bd0a935-a131-4b4e-9b51-c07aef128255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574592695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1574592695
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2664520629
Short name T560
Test name
Test status
Simulation time 17526497 ps
CPU time 0.76 seconds
Started May 09 01:30:52 PM PDT 24
Finished May 09 01:30:54 PM PDT 24
Peak memory 205308 kb
Host smart-cd957b61-f883-41f0-870a-4216d922e42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664520629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2664520629
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2411978202
Short name T748
Test name
Test status
Simulation time 117077987 ps
CPU time 3.08 seconds
Started May 09 01:30:53 PM PDT 24
Finished May 09 01:30:57 PM PDT 24
Peak memory 235940 kb
Host smart-010ea946-c818-4374-953a-a34af1ce9ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411978202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2411978202
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.305540739
Short name T580
Test name
Test status
Simulation time 177833970 ps
CPU time 0.8 seconds
Started May 09 01:30:55 PM PDT 24
Finished May 09 01:30:57 PM PDT 24
Peak memory 206448 kb
Host smart-978b2148-daa6-47a1-9393-122c7d8472fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305540739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.305540739
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4165179164
Short name T35
Test name
Test status
Simulation time 44999907184 ps
CPU time 109.25 seconds
Started May 09 01:30:55 PM PDT 24
Finished May 09 01:32:46 PM PDT 24
Peak memory 237872 kb
Host smart-c98f68f4-43ee-46be-89c3-27d4c6c9ca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165179164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4165179164
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1147187322
Short name T187
Test name
Test status
Simulation time 5666855079 ps
CPU time 21.96 seconds
Started May 09 01:30:53 PM PDT 24
Finished May 09 01:31:16 PM PDT 24
Peak memory 238860 kb
Host smart-0d77c56d-54cd-4947-92b9-a97d7803328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147187322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1147187322
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4231618930
Short name T661
Test name
Test status
Simulation time 11162469457 ps
CPU time 76.86 seconds
Started May 09 01:30:57 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 249152 kb
Host smart-1206112c-8a11-4f30-9179-0ede591877aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231618930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4231618930
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.841431637
Short name T314
Test name
Test status
Simulation time 1608043990 ps
CPU time 6.89 seconds
Started May 09 01:30:53 PM PDT 24
Finished May 09 01:31:01 PM PDT 24
Peak memory 224440 kb
Host smart-8b04a0fc-c22e-4d89-86b4-153be9bd96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841431637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.841431637
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1768561594
Short name T90
Test name
Test status
Simulation time 2376580520 ps
CPU time 9.64 seconds
Started May 09 01:30:53 PM PDT 24
Finished May 09 01:31:04 PM PDT 24
Peak memory 219816 kb
Host smart-9ff07229-e0b0-45b8-afaf-2f64184590d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768561594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1768561594
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3062988607
Short name T752
Test name
Test status
Simulation time 86386035 ps
CPU time 2.51 seconds
Started May 09 01:30:52 PM PDT 24
Finished May 09 01:30:56 PM PDT 24
Peak memory 220924 kb
Host smart-cdf91619-5da9-43c1-a780-51fbc3f39def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062988607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3062988607
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.43052571
Short name T161
Test name
Test status
Simulation time 591649625 ps
CPU time 5.31 seconds
Started May 09 01:30:53 PM PDT 24
Finished May 09 01:31:00 PM PDT 24
Peak memory 232632 kb
Host smart-f2ebae42-3bae-4a01-af1e-d5afb227e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43052571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.43052571
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.280860354
Short name T203
Test name
Test status
Simulation time 1372787549 ps
CPU time 4.7 seconds
Started May 09 01:30:50 PM PDT 24
Finished May 09 01:30:56 PM PDT 24
Peak memory 233148 kb
Host smart-7480e42e-8a0e-4ae5-9274-7cca205d80e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280860354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.280860354
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.563685864
Short name T953
Test name
Test status
Simulation time 3115236267 ps
CPU time 15.08 seconds
Started May 09 01:30:56 PM PDT 24
Finished May 09 01:31:12 PM PDT 24
Peak memory 222328 kb
Host smart-05c79901-fa37-48bf-954e-0c974e1773d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=563685864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.563685864
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.890380602
Short name T324
Test name
Test status
Simulation time 17659619331 ps
CPU time 98.22 seconds
Started May 09 01:30:57 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 262796 kb
Host smart-03ea2b08-9fbe-4640-874e-d2b5083f372e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890380602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.890380602
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3507858653
Short name T577
Test name
Test status
Simulation time 2588856576 ps
CPU time 13.2 seconds
Started May 09 01:30:54 PM PDT 24
Finished May 09 01:31:09 PM PDT 24
Peak memory 216252 kb
Host smart-61be8552-59e6-4991-ba00-b6e81ac613bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507858653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3507858653
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1381302122
Short name T431
Test name
Test status
Simulation time 441853294 ps
CPU time 2.68 seconds
Started May 09 01:30:49 PM PDT 24
Finished May 09 01:30:53 PM PDT 24
Peak memory 215888 kb
Host smart-78b20341-039d-4aa1-a0c9-4c158c2b29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381302122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1381302122
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.51803781
Short name T691
Test name
Test status
Simulation time 473012675 ps
CPU time 3 seconds
Started May 09 01:30:52 PM PDT 24
Finished May 09 01:30:56 PM PDT 24
Peak memory 216436 kb
Host smart-1749caa8-311f-47c0-8fd0-a888ac45d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51803781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.51803781
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1582715490
Short name T894
Test name
Test status
Simulation time 688887431 ps
CPU time 0.84 seconds
Started May 09 01:30:56 PM PDT 24
Finished May 09 01:30:58 PM PDT 24
Peak memory 205748 kb
Host smart-dbb24cf1-af94-4425-802a-d8c1dfcf28f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582715490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1582715490
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2339054843
Short name T843
Test name
Test status
Simulation time 98184214 ps
CPU time 2.74 seconds
Started May 09 01:30:57 PM PDT 24
Finished May 09 01:31:01 PM PDT 24
Peak memory 218564 kb
Host smart-719a408f-19d7-4718-8bfd-c0cc9cb86d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339054843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2339054843
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.263361325
Short name T384
Test name
Test status
Simulation time 58041664 ps
CPU time 0.74 seconds
Started May 09 01:31:05 PM PDT 24
Finished May 09 01:31:07 PM PDT 24
Peak memory 204808 kb
Host smart-23f97c0e-a588-4e58-9806-30f9f9a6563d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263361325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.263361325
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.787807837
Short name T295
Test name
Test status
Simulation time 74370452 ps
CPU time 2.26 seconds
Started May 09 01:31:07 PM PDT 24
Finished May 09 01:31:11 PM PDT 24
Peak memory 218588 kb
Host smart-fa7aeecb-0e53-4e74-b266-b48ca967169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787807837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.787807837
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3252556632
Short name T630
Test name
Test status
Simulation time 86026962 ps
CPU time 0.84 seconds
Started May 09 01:31:06 PM PDT 24
Finished May 09 01:31:09 PM PDT 24
Peak memory 206544 kb
Host smart-15d0f89b-5b75-4d2e-81af-ec034b5859cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252556632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3252556632
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3482019989
Short name T546
Test name
Test status
Simulation time 39232884146 ps
CPU time 196.64 seconds
Started May 09 01:30:59 PM PDT 24
Finished May 09 01:34:17 PM PDT 24
Peak memory 249124 kb
Host smart-d0886e63-45b6-402b-9e98-a53d774e45ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482019989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3482019989
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3143067778
Short name T307
Test name
Test status
Simulation time 13417845062 ps
CPU time 61.7 seconds
Started May 09 01:31:07 PM PDT 24
Finished May 09 01:32:10 PM PDT 24
Peak memory 236812 kb
Host smart-7fc852a9-35c0-44ec-a6a0-b6e323040194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143067778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3143067778
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3503354132
Short name T844
Test name
Test status
Simulation time 4047630719 ps
CPU time 53.95 seconds
Started May 09 01:30:59 PM PDT 24
Finished May 09 01:31:53 PM PDT 24
Peak memory 232640 kb
Host smart-3d82b5f1-b591-47bc-b9ac-0cbb6a56dc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503354132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3503354132
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3596714745
Short name T643
Test name
Test status
Simulation time 1309055352 ps
CPU time 13.77 seconds
Started May 09 01:31:07 PM PDT 24
Finished May 09 01:31:22 PM PDT 24
Peak memory 234072 kb
Host smart-40dc60ea-14ce-4a3d-b806-18c75d3221dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596714745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3596714745
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4202030729
Short name T658
Test name
Test status
Simulation time 5601681079 ps
CPU time 19.29 seconds
Started May 09 01:31:04 PM PDT 24
Finished May 09 01:31:25 PM PDT 24
Peak memory 231632 kb
Host smart-b603ce4f-ffdf-4496-9be8-fb84d14e6971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202030729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4202030729
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1927654760
Short name T52
Test name
Test status
Simulation time 6382381477 ps
CPU time 21.58 seconds
Started May 09 01:31:08 PM PDT 24
Finished May 09 01:31:31 PM PDT 24
Peak memory 240844 kb
Host smart-b3de1c9f-0c8a-4b3e-b63c-da710c42f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927654760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1927654760
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.310430790
Short name T289
Test name
Test status
Simulation time 6624913781 ps
CPU time 8.24 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:22 PM PDT 24
Peak memory 224448 kb
Host smart-c3bd375b-66c3-4578-93db-11431720e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310430790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.310430790
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2803401879
Short name T8
Test name
Test status
Simulation time 670940074 ps
CPU time 5.62 seconds
Started May 09 01:31:06 PM PDT 24
Finished May 09 01:31:13 PM PDT 24
Peak memory 218684 kb
Host smart-7d40dcd9-b4af-4fc5-b70f-f1550fda1b32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2803401879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2803401879
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1501008461
Short name T362
Test name
Test status
Simulation time 6895698983 ps
CPU time 15.61 seconds
Started May 09 01:30:59 PM PDT 24
Finished May 09 01:31:16 PM PDT 24
Peak memory 216252 kb
Host smart-d4bb2866-5f1a-4c6d-b180-24b0f31fb840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501008461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1501008461
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3156240692
Short name T705
Test name
Test status
Simulation time 7693962072 ps
CPU time 7.92 seconds
Started May 09 01:31:06 PM PDT 24
Finished May 09 01:31:15 PM PDT 24
Peak memory 216180 kb
Host smart-be3f7911-e0c5-4949-a994-4e711e72503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156240692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3156240692
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.757756665
Short name T457
Test name
Test status
Simulation time 11715268 ps
CPU time 0.74 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:31:14 PM PDT 24
Peak memory 205776 kb
Host smart-8fcfc547-063f-4be9-8add-feab026cc606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757756665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.757756665
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2779578005
Short name T885
Test name
Test status
Simulation time 282349222 ps
CPU time 0.92 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:31:14 PM PDT 24
Peak memory 205672 kb
Host smart-8d966fb5-6a68-42fa-8fd4-024a4e2b85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779578005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2779578005
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.364167868
Short name T523
Test name
Test status
Simulation time 1410366533 ps
CPU time 8.92 seconds
Started May 09 01:31:14 PM PDT 24
Finished May 09 01:31:24 PM PDT 24
Peak memory 226472 kb
Host smart-738e5b9b-746c-40c4-b2fa-599f28898c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364167868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.364167868
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4045178609
Short name T441
Test name
Test status
Simulation time 18825225 ps
CPU time 0.74 seconds
Started May 09 01:31:06 PM PDT 24
Finished May 09 01:31:09 PM PDT 24
Peak memory 204804 kb
Host smart-82567314-8150-4e51-ad2d-5a82e5cc1ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045178609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4045178609
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2596752477
Short name T625
Test name
Test status
Simulation time 316473310 ps
CPU time 5.44 seconds
Started May 09 01:31:10 PM PDT 24
Finished May 09 01:31:17 PM PDT 24
Peak memory 234228 kb
Host smart-065b3ba8-e625-4b7d-bde4-1497c5418ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596752477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2596752477
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1097599912
Short name T621
Test name
Test status
Simulation time 19316804 ps
CPU time 0.77 seconds
Started May 09 01:31:10 PM PDT 24
Finished May 09 01:31:12 PM PDT 24
Peak memory 206548 kb
Host smart-3fe17ef4-9902-4f0e-b9ab-97b03c8e90a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097599912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1097599912
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3529658528
Short name T900
Test name
Test status
Simulation time 61695598049 ps
CPU time 105.68 seconds
Started May 09 01:31:05 PM PDT 24
Finished May 09 01:32:52 PM PDT 24
Peak memory 240888 kb
Host smart-26ca91a1-3c86-49c1-8704-862ab5adb545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529658528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3529658528
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.973789555
Short name T636
Test name
Test status
Simulation time 84099996953 ps
CPU time 186.52 seconds
Started May 09 01:31:03 PM PDT 24
Finished May 09 01:34:11 PM PDT 24
Peak memory 238552 kb
Host smart-70c5b8d4-9477-4d2a-aafa-7f549c2593c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973789555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.973789555
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1403575619
Short name T18
Test name
Test status
Simulation time 76063274266 ps
CPU time 660.41 seconds
Started May 09 01:31:06 PM PDT 24
Finished May 09 01:42:08 PM PDT 24
Peak memory 255644 kb
Host smart-8995ed75-5e6d-4b9e-b1c1-e6ebd62bef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403575619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1403575619
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1541095715
Short name T337
Test name
Test status
Simulation time 958458455 ps
CPU time 16.61 seconds
Started May 09 01:31:05 PM PDT 24
Finished May 09 01:31:23 PM PDT 24
Peak memory 240792 kb
Host smart-2977dab8-1ff6-49c8-be36-f71edf59d3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541095715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1541095715
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1224055837
Short name T477
Test name
Test status
Simulation time 76072798 ps
CPU time 2.06 seconds
Started May 09 01:31:04 PM PDT 24
Finished May 09 01:31:08 PM PDT 24
Peak memory 215992 kb
Host smart-ff0224ae-ebb8-497b-b504-7bb60b5e9308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224055837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1224055837
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.429587430
Short name T936
Test name
Test status
Simulation time 12040149662 ps
CPU time 22.65 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:31:35 PM PDT 24
Peak memory 219532 kb
Host smart-e889c7b0-74df-4561-824e-9aaf98db3934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429587430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.429587430
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1223044972
Short name T247
Test name
Test status
Simulation time 555319919 ps
CPU time 6.16 seconds
Started May 09 01:31:00 PM PDT 24
Finished May 09 01:31:07 PM PDT 24
Peak memory 235240 kb
Host smart-efa9bb1e-4d16-4c39-93f2-c83e0cabb2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223044972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1223044972
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3819752326
Short name T737
Test name
Test status
Simulation time 604198007 ps
CPU time 2.37 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:17 PM PDT 24
Peak memory 218140 kb
Host smart-f61ea2b5-6c27-45fe-b7c5-c657fc5b1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819752326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3819752326
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4180207252
Short name T715
Test name
Test status
Simulation time 952685744 ps
CPU time 6.02 seconds
Started May 09 01:31:04 PM PDT 24
Finished May 09 01:31:12 PM PDT 24
Peak memory 222088 kb
Host smart-bd919d65-f0b7-43b6-a119-d5b417a6a3b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4180207252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4180207252
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2388020414
Short name T841
Test name
Test status
Simulation time 53206078 ps
CPU time 1.19 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:15 PM PDT 24
Peak memory 207624 kb
Host smart-21834647-8c0a-4853-812f-1457f2132dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388020414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2388020414
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1500777205
Short name T954
Test name
Test status
Simulation time 5361094170 ps
CPU time 7.85 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:22 PM PDT 24
Peak memory 216112 kb
Host smart-950a6eb1-6a1d-4aa5-bbe7-7e1387f4755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500777205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1500777205
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2611147648
Short name T718
Test name
Test status
Simulation time 21836877251 ps
CPU time 18.1 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:32 PM PDT 24
Peak memory 216192 kb
Host smart-faa1a009-1e3b-471b-86d2-e25aad72447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611147648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2611147648
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1727364854
Short name T821
Test name
Test status
Simulation time 163719832 ps
CPU time 2.73 seconds
Started May 09 01:31:11 PM PDT 24
Finished May 09 01:31:15 PM PDT 24
Peak memory 216196 kb
Host smart-925457cf-cf13-4bda-b804-44f641aab540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727364854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1727364854
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.133445803
Short name T825
Test name
Test status
Simulation time 213356703 ps
CPU time 0.93 seconds
Started May 09 01:31:07 PM PDT 24
Finished May 09 01:31:10 PM PDT 24
Peak memory 206228 kb
Host smart-40397a0a-e339-4261-b94c-4ebf9579d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133445803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.133445803
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1583890432
Short name T766
Test name
Test status
Simulation time 17238632422 ps
CPU time 26.96 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:31:41 PM PDT 24
Peak memory 233848 kb
Host smart-ddbda3dd-2d00-4df4-957c-8468c622d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583890432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1583890432
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1054647704
Short name T916
Test name
Test status
Simulation time 12600726 ps
CPU time 0.7 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:31:14 PM PDT 24
Peak memory 204748 kb
Host smart-07fffa22-2158-45a1-a657-b1dfa54a6a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054647704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1054647704
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4057380841
Short name T710
Test name
Test status
Simulation time 4198913630 ps
CPU time 11.1 seconds
Started May 09 01:31:08 PM PDT 24
Finished May 09 01:31:20 PM PDT 24
Peak memory 220176 kb
Host smart-063114bc-f035-4939-a1de-496188f98505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057380841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4057380841
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4031174425
Short name T15
Test name
Test status
Simulation time 18132153 ps
CPU time 0.78 seconds
Started May 09 01:30:58 PM PDT 24
Finished May 09 01:31:00 PM PDT 24
Peak memory 206796 kb
Host smart-378c8f14-74ad-4d36-aace-dde9196416c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031174425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4031174425
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3252020335
Short name T76
Test name
Test status
Simulation time 72278078925 ps
CPU time 517.67 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:39:51 PM PDT 24
Peak memory 257148 kb
Host smart-73ff6acf-2699-434a-914d-10160fe32b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252020335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3252020335
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2508672487
Short name T229
Test name
Test status
Simulation time 444274702557 ps
CPU time 815.61 seconds
Started May 09 01:31:14 PM PDT 24
Finished May 09 01:44:51 PM PDT 24
Peak memory 257296 kb
Host smart-eb97fed4-0f74-4ce5-b2e3-d3bc82f7bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508672487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2508672487
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.392932248
Short name T935
Test name
Test status
Simulation time 26763279401 ps
CPU time 94.05 seconds
Started May 09 01:31:04 PM PDT 24
Finished May 09 01:32:40 PM PDT 24
Peak memory 249084 kb
Host smart-ce0250ae-4d92-48ec-b632-ebb8853b326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392932248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.392932248
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.719067519
Short name T609
Test name
Test status
Simulation time 446143694 ps
CPU time 10.56 seconds
Started May 09 01:31:07 PM PDT 24
Finished May 09 01:31:20 PM PDT 24
Peak memory 238684 kb
Host smart-d7e2e37e-8904-4d2c-b255-c0d4adc7d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719067519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.719067519
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2964123795
Short name T353
Test name
Test status
Simulation time 331769491 ps
CPU time 5.15 seconds
Started May 09 01:31:01 PM PDT 24
Finished May 09 01:31:07 PM PDT 24
Peak memory 234024 kb
Host smart-3eb0ebd2-55ce-4f0d-9c31-b0078011d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964123795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2964123795
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1236192691
Short name T878
Test name
Test status
Simulation time 1597345825 ps
CPU time 20.63 seconds
Started May 09 01:31:07 PM PDT 24
Finished May 09 01:31:29 PM PDT 24
Peak memory 218488 kb
Host smart-d00f14ee-604e-4240-9b57-a2aaee22ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236192691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1236192691
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1867966673
Short name T618
Test name
Test status
Simulation time 9061270695 ps
CPU time 29.89 seconds
Started May 09 01:31:02 PM PDT 24
Finished May 09 01:31:33 PM PDT 24
Peak memory 232544 kb
Host smart-751e6bc2-55c9-4c3f-bbdd-1b7ca23ed144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867966673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1867966673
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2992187359
Short name T192
Test name
Test status
Simulation time 1019676767 ps
CPU time 7.55 seconds
Started May 09 01:31:08 PM PDT 24
Finished May 09 01:31:17 PM PDT 24
Peak memory 219948 kb
Host smart-61100916-93b5-4bee-8450-d6f56aa63646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992187359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2992187359
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1306236370
Short name T714
Test name
Test status
Simulation time 999908668 ps
CPU time 9.96 seconds
Started May 09 01:30:59 PM PDT 24
Finished May 09 01:31:10 PM PDT 24
Peak memory 222952 kb
Host smart-423597d0-b480-4c94-ba73-250f418d84f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1306236370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1306236370
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1750157765
Short name T646
Test name
Test status
Simulation time 3845015683 ps
CPU time 12.5 seconds
Started May 09 01:31:02 PM PDT 24
Finished May 09 01:31:16 PM PDT 24
Peak memory 216192 kb
Host smart-0f47448a-3f57-4cf7-b50a-f724ae1183ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750157765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1750157765
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3873016894
Short name T487
Test name
Test status
Simulation time 4546723481 ps
CPU time 10.39 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:25 PM PDT 24
Peak memory 216264 kb
Host smart-230d3c5b-c9d2-44e0-bbd3-83ea3ecf988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873016894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3873016894
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.155476985
Short name T435
Test name
Test status
Simulation time 371483652 ps
CPU time 5.28 seconds
Started May 09 01:31:08 PM PDT 24
Finished May 09 01:31:15 PM PDT 24
Peak memory 216172 kb
Host smart-224b23be-f475-4f81-abc2-8e5100cb65fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155476985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.155476985
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3195555375
Short name T955
Test name
Test status
Simulation time 35191075 ps
CPU time 0.68 seconds
Started May 09 01:31:01 PM PDT 24
Finished May 09 01:31:03 PM PDT 24
Peak memory 205460 kb
Host smart-c1404697-1b53-45e1-83d1-4e78cda57a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195555375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3195555375
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.263928298
Short name T166
Test name
Test status
Simulation time 203720559 ps
CPU time 2.81 seconds
Started May 09 01:31:00 PM PDT 24
Finished May 09 01:31:04 PM PDT 24
Peak memory 216524 kb
Host smart-c6e00c36-5221-44c6-a31a-aa063b7a5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263928298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.263928298
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2340156380
Short name T820
Test name
Test status
Simulation time 38242707 ps
CPU time 0.71 seconds
Started May 09 01:31:20 PM PDT 24
Finished May 09 01:31:22 PM PDT 24
Peak memory 204788 kb
Host smart-537ed37b-93eb-4e21-b102-efd6500bfbea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340156380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2340156380
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1617079348
Short name T720
Test name
Test status
Simulation time 2813599206 ps
CPU time 15.84 seconds
Started May 09 01:31:20 PM PDT 24
Finished May 09 01:31:37 PM PDT 24
Peak memory 234448 kb
Host smart-cf68e86a-1a67-4d48-bfcd-683aca62b39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617079348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1617079348
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2117877343
Short name T587
Test name
Test status
Simulation time 66343723 ps
CPU time 0.84 seconds
Started May 09 01:31:01 PM PDT 24
Finished May 09 01:31:03 PM PDT 24
Peak memory 206504 kb
Host smart-ed8a9acf-24e6-44cc-830e-2829f63a308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117877343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2117877343
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.264472640
Short name T688
Test name
Test status
Simulation time 49186389576 ps
CPU time 211.42 seconds
Started May 09 01:31:12 PM PDT 24
Finished May 09 01:34:44 PM PDT 24
Peak memory 249056 kb
Host smart-d3edb4b9-5e63-4a9e-869c-67f8b4572045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264472640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.264472640
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3015474710
Short name T51
Test name
Test status
Simulation time 21332682935 ps
CPU time 33.25 seconds
Started May 09 01:31:15 PM PDT 24
Finished May 09 01:31:49 PM PDT 24
Peak memory 217232 kb
Host smart-5ce925b8-930e-472b-aa67-35f61c6bd448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015474710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3015474710
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2987551216
Short name T874
Test name
Test status
Simulation time 35764318969 ps
CPU time 216.69 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:34:51 PM PDT 24
Peak memory 256916 kb
Host smart-a11a7134-17d6-45d2-a6ed-2d27ca407536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987551216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2987551216
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3166458252
Short name T73
Test name
Test status
Simulation time 388582643 ps
CPU time 9.86 seconds
Started May 09 01:31:09 PM PDT 24
Finished May 09 01:31:20 PM PDT 24
Peak memory 240756 kb
Host smart-2839fa5f-ab14-4670-86a6-fde93862ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166458252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3166458252
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1423091620
Short name T524
Test name
Test status
Simulation time 4357938383 ps
CPU time 14.29 seconds
Started May 09 01:31:21 PM PDT 24
Finished May 09 01:31:36 PM PDT 24
Peak memory 218564 kb
Host smart-1d6e0e44-65a2-44e3-a4fa-c001fb430f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423091620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1423091620
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1584975064
Short name T205
Test name
Test status
Simulation time 14652687294 ps
CPU time 35.69 seconds
Started May 09 01:31:09 PM PDT 24
Finished May 09 01:31:46 PM PDT 24
Peak memory 231636 kb
Host smart-4b97c92d-7fe9-44e1-aea2-537071d2cdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584975064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1584975064
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.332130286
Short name T194
Test name
Test status
Simulation time 2299470727 ps
CPU time 5.83 seconds
Started May 09 01:31:21 PM PDT 24
Finished May 09 01:31:28 PM PDT 24
Peak memory 233632 kb
Host smart-c83362e8-e95c-4216-aa5d-cffb69d5bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332130286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.332130286
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2921996490
Short name T601
Test name
Test status
Simulation time 14428595672 ps
CPU time 12.01 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:27 PM PDT 24
Peak memory 233644 kb
Host smart-b1b50793-24f0-4854-b055-4a9a086d0659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921996490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2921996490
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1023786263
Short name T863
Test name
Test status
Simulation time 2927161047 ps
CPU time 11.46 seconds
Started May 09 01:31:21 PM PDT 24
Finished May 09 01:31:33 PM PDT 24
Peak memory 219600 kb
Host smart-78e9a249-f478-49be-9744-329749db20a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1023786263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1023786263
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1722242190
Short name T268
Test name
Test status
Simulation time 21337891136 ps
CPU time 98.17 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:32:53 PM PDT 24
Peak memory 238432 kb
Host smart-969bb1db-dd27-4352-bc1b-987c4a59432e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722242190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1722242190
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3610999065
Short name T624
Test name
Test status
Simulation time 3265410791 ps
CPU time 17.83 seconds
Started May 09 01:31:18 PM PDT 24
Finished May 09 01:31:37 PM PDT 24
Peak memory 216216 kb
Host smart-4b9de62a-e804-4e1a-831f-00ddf28303a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610999065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3610999065
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3843353329
Short name T416
Test name
Test status
Simulation time 11176144226 ps
CPU time 11.38 seconds
Started May 09 01:31:11 PM PDT 24
Finished May 09 01:31:23 PM PDT 24
Peak memory 216228 kb
Host smart-8f36d615-714d-46b6-9ac5-fa2d6e5de095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843353329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3843353329
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2965952549
Short name T846
Test name
Test status
Simulation time 11804310 ps
CPU time 0.71 seconds
Started May 09 01:31:15 PM PDT 24
Finished May 09 01:31:16 PM PDT 24
Peak memory 205508 kb
Host smart-03a64f21-ae63-4ae9-820e-cd7416a3c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965952549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2965952549
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.629416366
Short name T767
Test name
Test status
Simulation time 418569473 ps
CPU time 1.08 seconds
Started May 09 01:31:11 PM PDT 24
Finished May 09 01:31:13 PM PDT 24
Peak memory 206732 kb
Host smart-40d3678f-2b71-4d4d-8e4f-e25d7b1d7c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629416366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.629416366
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.891287922
Short name T882
Test name
Test status
Simulation time 14592406084 ps
CPU time 25.22 seconds
Started May 09 01:31:13 PM PDT 24
Finished May 09 01:31:40 PM PDT 24
Peak memory 233628 kb
Host smart-dd271641-e86d-4656-98b1-af8505e36564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891287922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.891287922
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2258931163
Short name T510
Test name
Test status
Simulation time 14238387 ps
CPU time 0.7 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:31:35 PM PDT 24
Peak memory 205312 kb
Host smart-94bc8262-e611-46ae-a4e7-3d282d481daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258931163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2258931163
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2495428420
Short name T505
Test name
Test status
Simulation time 803113631 ps
CPU time 5.51 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:31:41 PM PDT 24
Peak memory 224380 kb
Host smart-78d96e92-4420-4152-bb28-83d1bcecc5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495428420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2495428420
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.495193234
Short name T458
Test name
Test status
Simulation time 29672739 ps
CPU time 0.77 seconds
Started May 09 01:31:21 PM PDT 24
Finished May 09 01:31:22 PM PDT 24
Peak memory 206536 kb
Host smart-22a33bf6-0820-4fce-a617-eeacfb1ae2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495193234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.495193234
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3664541124
Short name T810
Test name
Test status
Simulation time 32160033377 ps
CPU time 125.11 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:33:40 PM PDT 24
Peak memory 249064 kb
Host smart-86934754-83fc-4f98-8187-36299525852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664541124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3664541124
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2790160548
Short name T471
Test name
Test status
Simulation time 13924312318 ps
CPU time 123.18 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:33:39 PM PDT 24
Peak memory 251156 kb
Host smart-28750e90-ffa4-4d4f-997a-fbf167c59c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790160548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2790160548
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1026690733
Short name T37
Test name
Test status
Simulation time 6644300825 ps
CPU time 49.02 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:32:24 PM PDT 24
Peak memory 253312 kb
Host smart-b266e709-01b2-4a2e-aa20-289bbda145f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026690733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1026690733
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.418444968
Short name T398
Test name
Test status
Simulation time 642889339 ps
CPU time 4.08 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:31:39 PM PDT 24
Peak memory 224404 kb
Host smart-b086f958-28ee-4b84-9b53-1ec492877e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418444968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.418444968
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.900112938
Short name T759
Test name
Test status
Simulation time 1010572565 ps
CPU time 7.47 seconds
Started May 09 01:31:32 PM PDT 24
Finished May 09 01:31:41 PM PDT 24
Peak memory 218476 kb
Host smart-ac299b8a-c2b3-4cc5-83ed-7af1aa51153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900112938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.900112938
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.505064208
Short name T173
Test name
Test status
Simulation time 686041817 ps
CPU time 10.63 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:31:45 PM PDT 24
Peak memory 218448 kb
Host smart-957c428c-d379-4b07-8ea5-c7b99cba55ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505064208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.505064208
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1759789581
Short name T246
Test name
Test status
Simulation time 3584289326 ps
CPU time 13.48 seconds
Started May 09 01:31:35 PM PDT 24
Finished May 09 01:31:50 PM PDT 24
Peak memory 233900 kb
Host smart-b4ff2f04-7a6e-4ff6-8a1c-ef9c8922d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759789581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1759789581
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1465796897
Short name T559
Test name
Test status
Simulation time 1592356433 ps
CPU time 4.75 seconds
Started May 09 01:31:32 PM PDT 24
Finished May 09 01:31:38 PM PDT 24
Peak memory 219584 kb
Host smart-61524140-7dd4-4adc-ba32-aac69101827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465796897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1465796897
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.633352297
Short name T698
Test name
Test status
Simulation time 804223904 ps
CPU time 10.51 seconds
Started May 09 01:31:31 PM PDT 24
Finished May 09 01:31:43 PM PDT 24
Peak memory 222688 kb
Host smart-14d5992d-c830-47ca-8888-a8e6ac616269
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=633352297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.633352297
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1379528210
Short name T158
Test name
Test status
Simulation time 87229430 ps
CPU time 0.94 seconds
Started May 09 01:31:38 PM PDT 24
Finished May 09 01:31:40 PM PDT 24
Peak memory 206852 kb
Host smart-938ac3a8-053c-444a-aee4-057ea1512486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379528210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1379528210
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2748801357
Short name T513
Test name
Test status
Simulation time 1065820201 ps
CPU time 4.76 seconds
Started May 09 01:31:35 PM PDT 24
Finished May 09 01:31:40 PM PDT 24
Peak memory 216364 kb
Host smart-c884cb98-5f3b-4db7-b14e-3ebe30d50d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748801357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2748801357
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3247210351
Short name T479
Test name
Test status
Simulation time 4084589136 ps
CPU time 12.89 seconds
Started May 09 01:31:21 PM PDT 24
Finished May 09 01:31:35 PM PDT 24
Peak memory 216156 kb
Host smart-0f9e650d-29ff-4e89-b237-812ccba4d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247210351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3247210351
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.291581947
Short name T667
Test name
Test status
Simulation time 12814260 ps
CPU time 0.73 seconds
Started May 09 01:31:31 PM PDT 24
Finished May 09 01:31:32 PM PDT 24
Peak memory 205724 kb
Host smart-3d773f69-17e0-4258-bbbb-ca9cc531f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291581947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.291581947
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1437204960
Short name T898
Test name
Test status
Simulation time 64858763 ps
CPU time 0.97 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:31:36 PM PDT 24
Peak memory 206016 kb
Host smart-1d8b1e24-1549-4857-83fd-b2cef8cd6e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437204960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1437204960
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2309827824
Short name T46
Test name
Test status
Simulation time 556458610 ps
CPU time 2.5 seconds
Started May 09 01:31:34 PM PDT 24
Finished May 09 01:31:38 PM PDT 24
Peak memory 224400 kb
Host smart-286c7aad-d8b2-4d75-b4d5-cf2e59fd68cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309827824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2309827824
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.561836406
Short name T365
Test name
Test status
Simulation time 12126895 ps
CPU time 0.68 seconds
Started May 09 01:29:43 PM PDT 24
Finished May 09 01:29:45 PM PDT 24
Peak memory 204740 kb
Host smart-29db19cf-8415-47db-a071-6c88542f667c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561836406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.561836406
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2490896941
Short name T620
Test name
Test status
Simulation time 3559516884 ps
CPU time 17.18 seconds
Started May 09 01:29:47 PM PDT 24
Finished May 09 01:30:06 PM PDT 24
Peak memory 219944 kb
Host smart-eaa7651f-0aee-4fb1-a0a4-99f7b2a9a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490896941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2490896941
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3424320050
Short name T768
Test name
Test status
Simulation time 37709912 ps
CPU time 0.76 seconds
Started May 09 01:29:37 PM PDT 24
Finished May 09 01:29:39 PM PDT 24
Peak memory 205480 kb
Host smart-89294e9f-abc8-4cf1-9290-41d1b9628461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424320050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3424320050
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1591683783
Short name T284
Test name
Test status
Simulation time 4400052835 ps
CPU time 29.04 seconds
Started May 09 01:29:53 PM PDT 24
Finished May 09 01:30:23 PM PDT 24
Peak memory 248848 kb
Host smart-1d87fe56-a66d-40f5-b3a3-e3bd81ab5bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591683783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1591683783
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1737020487
Short name T228
Test name
Test status
Simulation time 93758119827 ps
CPU time 810.32 seconds
Started May 09 01:29:53 PM PDT 24
Finished May 09 01:43:24 PM PDT 24
Peak memory 248916 kb
Host smart-e47249bd-4938-474f-a3e6-dcc507124c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737020487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1737020487
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3605657866
Short name T956
Test name
Test status
Simulation time 34594750902 ps
CPU time 71.69 seconds
Started May 09 01:29:50 PM PDT 24
Finished May 09 01:31:03 PM PDT 24
Peak memory 237960 kb
Host smart-f83a480f-82f8-43f2-a49b-a878992a612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605657866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3605657866
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4239806196
Short name T872
Test name
Test status
Simulation time 156152343 ps
CPU time 4.81 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:29:54 PM PDT 24
Peak memory 234388 kb
Host smart-5ed46154-cb4b-4482-ab49-86ef6adf1f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239806196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4239806196
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2731440453
Short name T589
Test name
Test status
Simulation time 746512040 ps
CPU time 16.37 seconds
Started May 09 01:29:53 PM PDT 24
Finished May 09 01:30:11 PM PDT 24
Peak memory 236432 kb
Host smart-4010ed07-c029-464e-91e5-aab564a5994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731440453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2731440453
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3293508636
Short name T232
Test name
Test status
Simulation time 9127963708 ps
CPU time 25.81 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:30:15 PM PDT 24
Peak memory 238524 kb
Host smart-b5f7ba1b-f4a3-4343-ab66-c728ca3c53e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293508636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3293508636
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.16322198
Short name T303
Test name
Test status
Simulation time 366895699 ps
CPU time 6.23 seconds
Started May 09 01:29:36 PM PDT 24
Finished May 09 01:29:43 PM PDT 24
Peak memory 233476 kb
Host smart-0a48fd1d-4b13-443d-bba6-2216ae8447d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16322198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.16322198
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3223890349
Short name T632
Test name
Test status
Simulation time 103854523 ps
CPU time 3.21 seconds
Started May 09 01:29:52 PM PDT 24
Finished May 09 01:29:56 PM PDT 24
Peak memory 218800 kb
Host smart-0fa8a773-7358-4d87-aaa1-8581438f5d0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223890349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3223890349
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3946467359
Short name T63
Test name
Test status
Simulation time 165001340 ps
CPU time 1.14 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:29:50 PM PDT 24
Peak memory 234676 kb
Host smart-b2f879d8-0915-4d90-8e46-1257f85586f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946467359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3946467359
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3342448001
Short name T615
Test name
Test status
Simulation time 10784546187 ps
CPU time 57.19 seconds
Started May 09 01:29:52 PM PDT 24
Finished May 09 01:30:50 PM PDT 24
Peak memory 224340 kb
Host smart-ab53322e-8355-4a25-b0cc-726b4d7ac47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342448001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3342448001
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3200470953
Short name T654
Test name
Test status
Simulation time 39490723785 ps
CPU time 40.7 seconds
Started May 09 01:29:31 PM PDT 24
Finished May 09 01:30:13 PM PDT 24
Peak memory 217596 kb
Host smart-ccffddf7-718b-46c9-9388-b3edc30deeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200470953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3200470953
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3119934847
Short name T603
Test name
Test status
Simulation time 737870008 ps
CPU time 3.66 seconds
Started May 09 01:29:37 PM PDT 24
Finished May 09 01:29:42 PM PDT 24
Peak memory 216148 kb
Host smart-a8feb016-2482-4eb9-a27b-294253cd3d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119934847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3119934847
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2572974196
Short name T690
Test name
Test status
Simulation time 89458900 ps
CPU time 0.91 seconds
Started May 09 01:29:36 PM PDT 24
Finished May 09 01:29:38 PM PDT 24
Peak memory 205704 kb
Host smart-826e56f3-5ef4-4157-8e38-f89739a6cb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572974196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2572974196
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4289787540
Short name T301
Test name
Test status
Simulation time 3012777108 ps
CPU time 13.53 seconds
Started May 09 01:29:52 PM PDT 24
Finished May 09 01:30:06 PM PDT 24
Peak memory 232508 kb
Host smart-07654f7a-2cb5-4175-aba5-70b58f03230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289787540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4289787540
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.881492513
Short name T520
Test name
Test status
Simulation time 16637592 ps
CPU time 0.73 seconds
Started May 09 01:31:42 PM PDT 24
Finished May 09 01:31:44 PM PDT 24
Peak memory 205272 kb
Host smart-f0aad98a-f33c-424e-98c8-90f78a454e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881492513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.881492513
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.253674467
Short name T446
Test name
Test status
Simulation time 850715861 ps
CPU time 4.06 seconds
Started May 09 01:31:47 PM PDT 24
Finished May 09 01:31:52 PM PDT 24
Peak memory 233468 kb
Host smart-b9fbe416-9c5f-4780-8b02-349717831ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253674467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.253674467
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3292044442
Short name T14
Test name
Test status
Simulation time 13145719 ps
CPU time 0.74 seconds
Started May 09 01:31:33 PM PDT 24
Finished May 09 01:31:34 PM PDT 24
Peak memory 205800 kb
Host smart-3993a5e2-56f5-492b-8b53-dfc3d79fa338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292044442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3292044442
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2293075933
Short name T913
Test name
Test status
Simulation time 11482908714 ps
CPU time 55.34 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:32:45 PM PDT 24
Peak memory 253308 kb
Host smart-94d5423a-74a3-4b7f-ac32-9a9e431cc1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293075933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2293075933
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.859016399
Short name T225
Test name
Test status
Simulation time 130763214681 ps
CPU time 505.6 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:40:13 PM PDT 24
Peak memory 265500 kb
Host smart-d1af11fb-9c97-4ee3-837d-a45804cbfe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859016399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.859016399
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2718212171
Short name T552
Test name
Test status
Simulation time 8346477046 ps
CPU time 30.99 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:32:21 PM PDT 24
Peak memory 224380 kb
Host smart-44149c8c-96d8-467d-a19f-423c93f0a79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718212171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2718212171
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2911303875
Short name T272
Test name
Test status
Simulation time 603947080 ps
CPU time 7.14 seconds
Started May 09 01:31:42 PM PDT 24
Finished May 09 01:31:50 PM PDT 24
Peak memory 233952 kb
Host smart-51fa42e0-0ca2-4892-b3e0-bc42b300005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911303875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2911303875
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4040090395
Short name T196
Test name
Test status
Simulation time 1349708958 ps
CPU time 10.8 seconds
Started May 09 01:31:48 PM PDT 24
Finished May 09 01:32:01 PM PDT 24
Peak memory 233576 kb
Host smart-f2ac048b-84a7-4343-936e-47add6bad697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040090395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4040090395
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1640342017
Short name T467
Test name
Test status
Simulation time 618038654 ps
CPU time 3.51 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:31:54 PM PDT 24
Peak memory 216684 kb
Host smart-8b52a594-3be8-4301-9ebf-07a17f2d5972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640342017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1640342017
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2773053135
Short name T731
Test name
Test status
Simulation time 3763657271 ps
CPU time 8.28 seconds
Started May 09 01:31:45 PM PDT 24
Finished May 09 01:31:56 PM PDT 24
Peak memory 233152 kb
Host smart-dc0f3800-79a9-4875-b8e5-e91294357859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773053135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2773053135
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1213382165
Short name T366
Test name
Test status
Simulation time 2031788073 ps
CPU time 21.8 seconds
Started May 09 01:31:45 PM PDT 24
Finished May 09 01:32:08 PM PDT 24
Peak memory 222852 kb
Host smart-2cf342c4-6cd8-4a96-af64-68caf30fde24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1213382165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1213382165
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2266416297
Short name T805
Test name
Test status
Simulation time 4088141267 ps
CPU time 56.58 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:32:44 PM PDT 24
Peak memory 249116 kb
Host smart-e3968a99-4d99-408b-8c86-ed6533ec39a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266416297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2266416297
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2613336326
Short name T514
Test name
Test status
Simulation time 51690764872 ps
CPU time 50.99 seconds
Started May 09 01:31:47 PM PDT 24
Finished May 09 01:32:39 PM PDT 24
Peak memory 215892 kb
Host smart-4c72ca64-2974-446c-a35b-503064dabc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613336326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2613336326
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4150705689
Short name T650
Test name
Test status
Simulation time 165524709 ps
CPU time 1.99 seconds
Started May 09 01:31:32 PM PDT 24
Finished May 09 01:31:35 PM PDT 24
Peak memory 216084 kb
Host smart-7630aa95-c448-4414-9138-9b40403bd036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150705689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4150705689
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3754909403
Short name T368
Test name
Test status
Simulation time 95798926 ps
CPU time 2.01 seconds
Started May 09 01:31:52 PM PDT 24
Finished May 09 01:31:55 PM PDT 24
Peak memory 216180 kb
Host smart-7f8a8832-815b-485d-97e7-9afd2ec5fb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754909403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3754909403
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1233797642
Short name T466
Test name
Test status
Simulation time 33912619 ps
CPU time 0.78 seconds
Started May 09 01:31:44 PM PDT 24
Finished May 09 01:31:46 PM PDT 24
Peak memory 205720 kb
Host smart-e848bcf5-47c5-4c4d-a7f7-e9df07a879ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233797642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1233797642
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2973433791
Short name T704
Test name
Test status
Simulation time 66970115 ps
CPU time 2.61 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:31:50 PM PDT 24
Peak memory 221128 kb
Host smart-f7952488-3ef9-4ba3-aa30-d0985091d52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973433791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2973433791
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1094596628
Short name T791
Test name
Test status
Simulation time 14143064 ps
CPU time 0.73 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:31:48 PM PDT 24
Peak memory 205676 kb
Host smart-05dd4efe-7552-49f9-80bb-b4adf953778d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094596628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1094596628
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3761336352
Short name T747
Test name
Test status
Simulation time 377682357 ps
CPU time 6.89 seconds
Started May 09 01:31:51 PM PDT 24
Finished May 09 01:31:59 PM PDT 24
Peak memory 218384 kb
Host smart-96683d49-e750-4d02-9f0f-32fc86315e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761336352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3761336352
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1284064961
Short name T438
Test name
Test status
Simulation time 13003939 ps
CPU time 0.76 seconds
Started May 09 01:31:47 PM PDT 24
Finished May 09 01:31:49 PM PDT 24
Peak memory 205096 kb
Host smart-4e3c0aaf-24b4-4597-bc66-36d14e3e7dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284064961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1284064961
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3118411371
Short name T598
Test name
Test status
Simulation time 27256677862 ps
CPU time 47.85 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:32:36 PM PDT 24
Peak memory 235264 kb
Host smart-6900db25-bedc-4508-900f-ae0a86fb614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118411371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3118411371
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2103161447
Short name T258
Test name
Test status
Simulation time 2608788202 ps
CPU time 38.28 seconds
Started May 09 01:31:47 PM PDT 24
Finished May 09 01:32:27 PM PDT 24
Peak memory 249108 kb
Host smart-077f0570-4095-4a54-acd6-b91ce83e5c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103161447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2103161447
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.72506624
Short name T255
Test name
Test status
Simulation time 15352872858 ps
CPU time 51.47 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:32:42 PM PDT 24
Peak memory 236136 kb
Host smart-a78599a2-edc1-4228-9c22-bda333829e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72506624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.72506624
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.695711927
Short name T134
Test name
Test status
Simulation time 1937042402 ps
CPU time 16.09 seconds
Started May 09 01:31:51 PM PDT 24
Finished May 09 01:32:08 PM PDT 24
Peak memory 232580 kb
Host smart-19434794-dc7a-4251-bea2-ab1c975a2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695711927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.695711927
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1173524
Short name T172
Test name
Test status
Simulation time 778973134 ps
CPU time 3.28 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:31:51 PM PDT 24
Peak memory 232612 kb
Host smart-ed6f4e8d-7c9f-4999-8797-b4b22a727b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1173524
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4128450501
Short name T562
Test name
Test status
Simulation time 1306317616 ps
CPU time 16.38 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:32:04 PM PDT 24
Peak memory 240728 kb
Host smart-25f7fa6b-2287-4c7a-af42-15b84242cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128450501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4128450501
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1528166063
Short name T400
Test name
Test status
Simulation time 2741576066 ps
CPU time 4.5 seconds
Started May 09 01:31:43 PM PDT 24
Finished May 09 01:31:49 PM PDT 24
Peak memory 218748 kb
Host smart-ffb0bfc1-4177-4da1-8f96-0eb1d69ea618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528166063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1528166063
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1661753063
Short name T49
Test name
Test status
Simulation time 2778640518 ps
CPU time 12.51 seconds
Started May 09 01:31:43 PM PDT 24
Finished May 09 01:31:57 PM PDT 24
Peak memory 226556 kb
Host smart-38dc6ca3-c4ec-4026-bd33-cd0526cd2e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661753063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1661753063
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1888727624
Short name T335
Test name
Test status
Simulation time 259422039 ps
CPU time 4.75 seconds
Started May 09 01:31:45 PM PDT 24
Finished May 09 01:31:51 PM PDT 24
Peak memory 220204 kb
Host smart-57e6aa3c-89ed-41a5-ac70-d958aae1c852
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1888727624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1888727624
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.28427522
Short name T922
Test name
Test status
Simulation time 10438771965 ps
CPU time 15.62 seconds
Started May 09 01:31:48 PM PDT 24
Finished May 09 01:32:05 PM PDT 24
Peak memory 216328 kb
Host smart-a5fa54fa-a2ea-47e3-acdf-bbb32a18ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28427522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.28427522
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.509387416
Short name T932
Test name
Test status
Simulation time 26604829 ps
CPU time 0.75 seconds
Started May 09 01:31:52 PM PDT 24
Finished May 09 01:31:53 PM PDT 24
Peak memory 205600 kb
Host smart-e98669f0-c0f2-4bc7-9464-fca8c44f4ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509387416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.509387416
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3750535985
Short name T380
Test name
Test status
Simulation time 55731626 ps
CPU time 0.96 seconds
Started May 09 01:31:42 PM PDT 24
Finished May 09 01:31:44 PM PDT 24
Peak memory 206864 kb
Host smart-10e6979d-b198-4917-8a9b-dac20ee915a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750535985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3750535985
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.40312286
Short name T574
Test name
Test status
Simulation time 252468441 ps
CPU time 0.97 seconds
Started May 09 01:31:52 PM PDT 24
Finished May 09 01:31:54 PM PDT 24
Peak memory 205712 kb
Host smart-9fc3a383-f369-45a5-b374-6c09a58fc4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40312286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.40312286
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4261461081
Short name T162
Test name
Test status
Simulation time 101229724 ps
CPU time 2.68 seconds
Started May 09 01:31:47 PM PDT 24
Finished May 09 01:31:51 PM PDT 24
Peak memory 224316 kb
Host smart-99546609-9f50-4c04-b846-e7d16f99a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261461081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4261461081
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.260030134
Short name T427
Test name
Test status
Simulation time 23851673 ps
CPU time 0.72 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:31:56 PM PDT 24
Peak memory 205364 kb
Host smart-0769675c-534e-496a-8fdc-4d40a6d680f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260030134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.260030134
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.957840232
Short name T508
Test name
Test status
Simulation time 1482716230 ps
CPU time 9.05 seconds
Started May 09 01:31:48 PM PDT 24
Finished May 09 01:31:59 PM PDT 24
Peak memory 232616 kb
Host smart-8c22763f-057e-4655-aff6-7a7f9aa8a4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957840232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.957840232
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1115504012
Short name T373
Test name
Test status
Simulation time 31986234 ps
CPU time 0.78 seconds
Started May 09 01:31:48 PM PDT 24
Finished May 09 01:31:50 PM PDT 24
Peak memory 206516 kb
Host smart-eb2254a6-a0e7-40b0-a038-9cdb68493076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115504012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1115504012
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3898434890
Short name T539
Test name
Test status
Simulation time 17933989514 ps
CPU time 146.07 seconds
Started May 09 01:31:52 PM PDT 24
Finished May 09 01:34:19 PM PDT 24
Peak memory 252988 kb
Host smart-4dbb0640-3ee7-4e8b-afec-258a4511e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898434890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3898434890
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4242974835
Short name T259
Test name
Test status
Simulation time 3895982056 ps
CPU time 27.98 seconds
Started May 09 01:31:42 PM PDT 24
Finished May 09 01:32:11 PM PDT 24
Peak memory 240892 kb
Host smart-e5a9972a-0abe-4d98-928e-f1177f3bbb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242974835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4242974835
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3933457996
Short name T749
Test name
Test status
Simulation time 10496190630 ps
CPU time 22.79 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:32:13 PM PDT 24
Peak memory 233588 kb
Host smart-7257b20f-3801-426b-82cb-96d9c5ca00bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933457996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3933457996
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2726993909
Short name T713
Test name
Test status
Simulation time 186779917 ps
CPU time 2.14 seconds
Started May 09 01:31:44 PM PDT 24
Finished May 09 01:31:47 PM PDT 24
Peak memory 215924 kb
Host smart-47928841-47fa-4d2e-8771-5eeddddacd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726993909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2726993909
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.718434057
Short name T721
Test name
Test status
Simulation time 168229808232 ps
CPU time 24.69 seconds
Started May 09 01:31:45 PM PDT 24
Finished May 09 01:32:11 PM PDT 24
Peak memory 238240 kb
Host smart-d90ff87c-c79a-4017-9c1c-75949b1c75ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718434057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.718434057
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2043962084
Short name T850
Test name
Test status
Simulation time 286106609 ps
CPU time 2.14 seconds
Started May 09 01:31:45 PM PDT 24
Finished May 09 01:31:48 PM PDT 24
Peak memory 216028 kb
Host smart-61978def-c80d-414e-9b84-07ae3922ad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043962084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2043962084
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4177913016
Short name T511
Test name
Test status
Simulation time 1462831156 ps
CPU time 10.04 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:32:05 PM PDT 24
Peak memory 222084 kb
Host smart-aac8083a-a8e2-4aef-8efc-70d25ce1e326
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4177913016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4177913016
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.13595321
Short name T154
Test name
Test status
Simulation time 31656439931 ps
CPU time 352.35 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:37:48 PM PDT 24
Peak memory 263704 kb
Host smart-e2cc007a-dcc4-4a71-a289-5dc96cbdd3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress
_all.13595321
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1453690568
Short name T595
Test name
Test status
Simulation time 3524433214 ps
CPU time 20.08 seconds
Started May 09 01:31:46 PM PDT 24
Finished May 09 01:32:08 PM PDT 24
Peak memory 216328 kb
Host smart-c1764cc9-085c-4b74-9acc-1be2982bea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453690568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1453690568
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1935195059
Short name T641
Test name
Test status
Simulation time 81924736 ps
CPU time 1.11 seconds
Started May 09 01:31:44 PM PDT 24
Finished May 09 01:31:46 PM PDT 24
Peak memory 207644 kb
Host smart-031164bc-2bb3-421d-bf5c-d68127d8c745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935195059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1935195059
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.129406474
Short name T532
Test name
Test status
Simulation time 125038368 ps
CPU time 1.27 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:31:51 PM PDT 24
Peak memory 207728 kb
Host smart-991c05e3-a1cf-4ed7-9410-861586e4b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129406474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.129406474
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1088345435
Short name T496
Test name
Test status
Simulation time 57402869 ps
CPU time 0.92 seconds
Started May 09 01:31:48 PM PDT 24
Finished May 09 01:31:51 PM PDT 24
Peak memory 205748 kb
Host smart-1cb76767-ab3f-4e2a-890e-0d2d868b1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088345435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1088345435
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1241372451
Short name T893
Test name
Test status
Simulation time 1096579272 ps
CPU time 6.12 seconds
Started May 09 01:31:49 PM PDT 24
Finished May 09 01:31:56 PM PDT 24
Peak memory 237260 kb
Host smart-11b52fcd-5c02-435a-8265-bb3530b3a483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241372451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1241372451
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1050777699
Short name T881
Test name
Test status
Simulation time 13894367 ps
CPU time 0.71 seconds
Started May 09 01:32:03 PM PDT 24
Finished May 09 01:32:04 PM PDT 24
Peak memory 205688 kb
Host smart-f6dca26f-a759-4724-9c0c-bbd339f79647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050777699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1050777699
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2777519454
Short name T802
Test name
Test status
Simulation time 440945749 ps
CPU time 5.61 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:32:00 PM PDT 24
Peak memory 219436 kb
Host smart-e9d01b16-7e7c-41ac-b449-92b130e8c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777519454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2777519454
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2149194451
Short name T502
Test name
Test status
Simulation time 14617955 ps
CPU time 0.76 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:31:57 PM PDT 24
Peak memory 205436 kb
Host smart-cf22d415-e49b-41a0-85cf-6ceeb8da1b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149194451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2149194451
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.757423124
Short name T75
Test name
Test status
Simulation time 280377496838 ps
CPU time 227.54 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:35:44 PM PDT 24
Peak memory 249120 kb
Host smart-ece462e9-75d2-4875-889a-f88472670e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757423124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.757423124
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2261638737
Short name T391
Test name
Test status
Simulation time 1796621499 ps
CPU time 4.71 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:32:01 PM PDT 24
Peak memory 224472 kb
Host smart-48f0b07d-9546-4e9a-8e5f-17d6179a9573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261638737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2261638737
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2942570594
Short name T186
Test name
Test status
Simulation time 823653128 ps
CPU time 5.93 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:32:01 PM PDT 24
Peak memory 218552 kb
Host smart-e297c784-2f0f-4076-af54-b1d4fe1b26f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942570594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2942570594
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1773816812
Short name T453
Test name
Test status
Simulation time 7335891923 ps
CPU time 18.36 seconds
Started May 09 01:31:56 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 221212 kb
Host smart-a11e77cf-a67c-4bad-b2fb-4b228a3b30ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773816812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1773816812
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3029289185
Short name T815
Test name
Test status
Simulation time 3186790661 ps
CPU time 13.55 seconds
Started May 09 01:31:56 PM PDT 24
Finished May 09 01:32:11 PM PDT 24
Peak memory 239192 kb
Host smart-583f20bc-5070-42f5-b2f8-2a5903d68b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029289185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3029289185
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2718525291
Short name T182
Test name
Test status
Simulation time 1180481366 ps
CPU time 5.12 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:32:01 PM PDT 24
Peak memory 216676 kb
Host smart-46303045-47bb-46de-b90c-510f93327311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718525291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2718525291
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4156291641
Short name T144
Test name
Test status
Simulation time 197985965 ps
CPU time 3.97 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:32:00 PM PDT 24
Peak memory 222948 kb
Host smart-df53db6c-333a-4044-84a6-5af2a3dd879e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156291641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4156291641
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.162417016
Short name T544
Test name
Test status
Simulation time 168009917 ps
CPU time 1.05 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:31:57 PM PDT 24
Peak memory 206756 kb
Host smart-ae545281-7509-4208-be5f-b6a0a74b0ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162417016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.162417016
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1871478501
Short name T481
Test name
Test status
Simulation time 2466600766 ps
CPU time 24.78 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 216280 kb
Host smart-173dcf11-99cf-483c-b367-7427e7016145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871478501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1871478501
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1780487092
Short name T590
Test name
Test status
Simulation time 15967533061 ps
CPU time 13.02 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:32:08 PM PDT 24
Peak memory 216260 kb
Host smart-52303eb0-f320-4dca-807a-47e4b2bf2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780487092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1780487092
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2935624843
Short name T680
Test name
Test status
Simulation time 31793094 ps
CPU time 0.88 seconds
Started May 09 01:31:55 PM PDT 24
Finished May 09 01:31:57 PM PDT 24
Peak memory 206672 kb
Host smart-73c314fa-b3ac-459d-bb3b-8a1f280556d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935624843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2935624843
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3149479868
Short name T72
Test name
Test status
Simulation time 28208314 ps
CPU time 0.71 seconds
Started May 09 01:31:56 PM PDT 24
Finished May 09 01:31:58 PM PDT 24
Peak memory 205736 kb
Host smart-ab3b6eef-7f7c-420b-b1d1-aa9c400f5076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149479868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3149479868
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3310397915
Short name T516
Test name
Test status
Simulation time 895568599 ps
CPU time 5.14 seconds
Started May 09 01:31:54 PM PDT 24
Finished May 09 01:32:00 PM PDT 24
Peak memory 232632 kb
Host smart-61e73a80-ae94-4359-a15a-0145b55b1242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310397915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3310397915
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1617691421
Short name T395
Test name
Test status
Simulation time 10968443 ps
CPU time 0.74 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 205200 kb
Host smart-caf289a0-0e74-424d-b2ca-9a551b92329d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617691421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1617691421
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4127808199
Short name T729
Test name
Test status
Simulation time 6638762311 ps
CPU time 12.2 seconds
Started May 09 01:32:07 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 220436 kb
Host smart-f81ae304-5956-4477-bbbd-419fd137bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127808199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4127808199
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1761988669
Short name T336
Test name
Test status
Simulation time 17471205 ps
CPU time 0.72 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 206488 kb
Host smart-96eddd5c-c220-4cc8-9cca-74e9901ed5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761988669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1761988669
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1814764515
Short name T648
Test name
Test status
Simulation time 7300741737 ps
CPU time 25.28 seconds
Started May 09 01:32:05 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 232632 kb
Host smart-f4b2d58b-13cd-4ce6-96d3-95be28cc054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814764515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1814764515
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.183235815
Short name T925
Test name
Test status
Simulation time 38277599281 ps
CPU time 123.01 seconds
Started May 09 01:32:04 PM PDT 24
Finished May 09 01:34:07 PM PDT 24
Peak memory 224304 kb
Host smart-0faae8fc-d8e6-4719-b5c6-67eeb9bfda54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183235815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.183235815
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4057451338
Short name T290
Test name
Test status
Simulation time 6088577108 ps
CPU time 100.42 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:33:47 PM PDT 24
Peak memory 249088 kb
Host smart-bbaebc27-dc2f-4cc9-a6ba-410edc283185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057451338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4057451338
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.279614788
Short name T371
Test name
Test status
Simulation time 237782254 ps
CPU time 4.59 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 224412 kb
Host smart-7fa2f72e-a68d-4e77-9688-0f0f6b2c9896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279614788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.279614788
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2907991501
Short name T719
Test name
Test status
Simulation time 1872781925 ps
CPU time 3.62 seconds
Started May 09 01:32:02 PM PDT 24
Finished May 09 01:32:06 PM PDT 24
Peak memory 224376 kb
Host smart-91b13aa0-3b55-43c6-a4f1-ce24c71f76a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907991501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2907991501
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4017653810
Short name T522
Test name
Test status
Simulation time 133310616 ps
CPU time 2.38 seconds
Started May 09 01:32:05 PM PDT 24
Finished May 09 01:32:09 PM PDT 24
Peak memory 221260 kb
Host smart-c1cf2317-249d-442b-bc88-db5fd59613eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017653810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4017653810
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3898870432
Short name T253
Test name
Test status
Simulation time 4707429923 ps
CPU time 15.22 seconds
Started May 09 01:32:10 PM PDT 24
Finished May 09 01:32:26 PM PDT 24
Peak memory 218576 kb
Host smart-179bc6e2-1756-4bce-89b7-95e4d6fbae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898870432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3898870432
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3907649782
Short name T864
Test name
Test status
Simulation time 99688385 ps
CPU time 2.04 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:09 PM PDT 24
Peak memory 216044 kb
Host smart-52743d59-a19b-4723-a7a4-4eae76a9f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907649782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3907649782
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1612260549
Short name T485
Test name
Test status
Simulation time 235347345 ps
CPU time 4.44 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:12 PM PDT 24
Peak memory 220316 kb
Host smart-379d16e0-49c3-4cf9-953f-2ebb57ddb81e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1612260549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1612260549
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2490631471
Short name T861
Test name
Test status
Simulation time 85072054 ps
CPU time 0.99 seconds
Started May 09 01:32:08 PM PDT 24
Finished May 09 01:32:10 PM PDT 24
Peak memory 206676 kb
Host smart-a30402e5-969c-4d33-a47c-7ad17af60176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490631471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2490631471
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3862895615
Short name T325
Test name
Test status
Simulation time 29040125449 ps
CPU time 43.23 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:57 PM PDT 24
Peak memory 216080 kb
Host smart-f0722207-8220-4571-bdf5-20db16e1dd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862895615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3862895615
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.596819758
Short name T83
Test name
Test status
Simulation time 14381226572 ps
CPU time 14.84 seconds
Started May 09 01:32:02 PM PDT 24
Finished May 09 01:32:18 PM PDT 24
Peak memory 216236 kb
Host smart-bd80cfe2-a44f-418e-b90d-c1523b8a9a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596819758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.596819758
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.58731003
Short name T328
Test name
Test status
Simulation time 271603807 ps
CPU time 1.37 seconds
Started May 09 01:32:07 PM PDT 24
Finished May 09 01:32:09 PM PDT 24
Peak memory 207584 kb
Host smart-ee53e751-4fec-46ba-ba8b-95b32121cf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58731003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.58731003
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3335694533
Short name T370
Test name
Test status
Simulation time 22723895 ps
CPU time 0.68 seconds
Started May 09 01:32:07 PM PDT 24
Finished May 09 01:32:08 PM PDT 24
Peak memory 205440 kb
Host smart-c8ab91c8-8a1e-46d0-9625-c4162c30debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335694533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3335694533
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3272588814
Short name T299
Test name
Test status
Simulation time 9168089379 ps
CPU time 8.59 seconds
Started May 09 01:32:05 PM PDT 24
Finished May 09 01:32:14 PM PDT 24
Peak memory 218940 kb
Host smart-1e7838d3-5124-4a55-bdc2-6a8721cb25a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272588814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3272588814
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1604897661
Short name T54
Test name
Test status
Simulation time 21609811 ps
CPU time 0.72 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 205308 kb
Host smart-8c8fca6d-9441-4f4f-aa0a-28c38ba22e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604897661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1604897661
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.201800277
Short name T87
Test name
Test status
Simulation time 1768693126 ps
CPU time 8.57 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:27 PM PDT 24
Peak memory 236428 kb
Host smart-0a05a9eb-2752-472e-bf92-ae10d9718f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201800277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.201800277
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1595793904
Short name T563
Test name
Test status
Simulation time 53362404 ps
CPU time 0.78 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:17 PM PDT 24
Peak memory 205284 kb
Host smart-63b1809d-2c1d-4558-9364-cbefe5ea2d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595793904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1595793904
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3986910028
Short name T803
Test name
Test status
Simulation time 13259119 ps
CPU time 0.73 seconds
Started May 09 01:32:07 PM PDT 24
Finished May 09 01:32:09 PM PDT 24
Peak memory 215912 kb
Host smart-915c6d4a-bb04-442d-adc2-6709fd72e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986910028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3986910028
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4082541576
Short name T848
Test name
Test status
Simulation time 4612016813 ps
CPU time 18.13 seconds
Started May 09 01:32:14 PM PDT 24
Finished May 09 01:32:34 PM PDT 24
Peak memory 224148 kb
Host smart-3aebb809-cf7e-47cf-b328-f88b76b27767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082541576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4082541576
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.114010017
Short name T722
Test name
Test status
Simulation time 2061875371 ps
CPU time 20.28 seconds
Started May 09 01:32:12 PM PDT 24
Finished May 09 01:32:33 PM PDT 24
Peak memory 219660 kb
Host smart-23155722-4232-4635-9ec9-da132e74ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114010017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.114010017
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3997384756
Short name T297
Test name
Test status
Simulation time 2498956623 ps
CPU time 6.48 seconds
Started May 09 01:32:04 PM PDT 24
Finished May 09 01:32:11 PM PDT 24
Peak memory 237604 kb
Host smart-519e3c5b-c69a-4f73-8350-810cd4048e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997384756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3997384756
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.207545731
Short name T285
Test name
Test status
Simulation time 805329997 ps
CPU time 4.81 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:12 PM PDT 24
Peak memory 218404 kb
Host smart-7036fd76-b71d-414d-a96a-f9e7234384b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207545731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.207545731
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1445947420
Short name T425
Test name
Test status
Simulation time 4931556963 ps
CPU time 11.61 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 218840 kb
Host smart-ba853873-b69b-4f40-8f58-5cbdf458e6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445947420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1445947420
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1233487248
Short name T642
Test name
Test status
Simulation time 3922311177 ps
CPU time 6.71 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:14 PM PDT 24
Peak memory 223036 kb
Host smart-3dacd470-8f3c-4e94-b53d-ad8ac755bfcc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1233487248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1233487248
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3460292540
Short name T159
Test name
Test status
Simulation time 12517223293 ps
CPU time 33.3 seconds
Started May 09 01:32:11 PM PDT 24
Finished May 09 01:32:45 PM PDT 24
Peak memory 224556 kb
Host smart-389fefe8-ed09-4aec-9cb5-e32757a8ea76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460292540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3460292540
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1759157268
Short name T911
Test name
Test status
Simulation time 1082042806 ps
CPU time 4 seconds
Started May 09 01:32:10 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 219092 kb
Host smart-baf8e3b6-d43d-4952-a848-b6416c88945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759157268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1759157268
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3758472993
Short name T344
Test name
Test status
Simulation time 10742683484 ps
CPU time 7.27 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:14 PM PDT 24
Peak memory 216148 kb
Host smart-fad4ab32-fc8d-4b19-8c1f-d417909a6d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758472993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3758472993
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2705957019
Short name T695
Test name
Test status
Simulation time 220825445 ps
CPU time 1.58 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:09 PM PDT 24
Peak memory 216180 kb
Host smart-a8716de7-fa9b-426b-afcf-1e10f61a056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705957019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2705957019
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3005673870
Short name T938
Test name
Test status
Simulation time 257176410 ps
CPU time 0.85 seconds
Started May 09 01:32:07 PM PDT 24
Finished May 09 01:32:08 PM PDT 24
Peak memory 205672 kb
Host smart-12491f3a-af46-4549-b14a-f5292f93743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005673870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3005673870
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2301019467
Short name T631
Test name
Test status
Simulation time 117788590 ps
CPU time 2.08 seconds
Started May 09 01:32:14 PM PDT 24
Finished May 09 01:32:18 PM PDT 24
Peak memory 215408 kb
Host smart-4ebb14ac-00f6-4cfb-b148-9813b076a74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301019467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2301019467
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.267060872
Short name T53
Test name
Test status
Simulation time 34863256 ps
CPU time 0.67 seconds
Started May 09 01:32:08 PM PDT 24
Finished May 09 01:32:09 PM PDT 24
Peak memory 205336 kb
Host smart-0288bd89-ff82-41e6-9dc5-ddd648cbdb97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267060872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.267060872
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4278967147
Short name T437
Test name
Test status
Simulation time 31795017 ps
CPU time 2.15 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:17 PM PDT 24
Peak memory 215848 kb
Host smart-fa97ac8a-8864-4e08-800c-dcbf5af48b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278967147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4278967147
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3074068506
Short name T469
Test name
Test status
Simulation time 54860939 ps
CPU time 0.76 seconds
Started May 09 01:32:05 PM PDT 24
Finished May 09 01:32:06 PM PDT 24
Peak memory 205504 kb
Host smart-9f06fc21-c895-4d71-8d62-c465337e6258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074068506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3074068506
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1951209003
Short name T169
Test name
Test status
Simulation time 19230072776 ps
CPU time 222.7 seconds
Started May 09 01:32:10 PM PDT 24
Finished May 09 01:35:54 PM PDT 24
Peak memory 264976 kb
Host smart-f6822152-67a4-4846-8cfb-ef7c21e1f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951209003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1951209003
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.210225401
Short name T525
Test name
Test status
Simulation time 6397901664 ps
CPU time 42.71 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:57 PM PDT 24
Peak memory 248944 kb
Host smart-d27a8bff-fda2-4c55-bb2d-91821fbc9fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210225401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.210225401
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3950547360
Short name T771
Test name
Test status
Simulation time 539158532 ps
CPU time 11.88 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:26 PM PDT 24
Peak memory 233600 kb
Host smart-c64b20bf-462d-437d-8c8a-1c5db972b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950547360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3950547360
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1931759097
Short name T287
Test name
Test status
Simulation time 943558914 ps
CPU time 4.82 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:19 PM PDT 24
Peak memory 235328 kb
Host smart-7096b1a2-e9f4-44e6-b590-1d6b3248895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931759097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1931759097
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2241688949
Short name T594
Test name
Test status
Simulation time 19203159191 ps
CPU time 23.99 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:40 PM PDT 24
Peak memory 249292 kb
Host smart-b8c91957-0e21-41c8-8604-12c57b5d2c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241688949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2241688949
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.896101284
Short name T27
Test name
Test status
Simulation time 3506189479 ps
CPU time 8.98 seconds
Started May 09 01:32:14 PM PDT 24
Finished May 09 01:32:25 PM PDT 24
Peak memory 220568 kb
Host smart-a4b6d158-d131-44b6-8b32-0d3572851ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896101284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.896101284
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1332569617
Short name T744
Test name
Test status
Simulation time 561624991 ps
CPU time 3.8 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:19 PM PDT 24
Peak memory 218212 kb
Host smart-8e029dd7-1ea8-43ab-bbaf-426f687c1b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332569617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1332569617
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1085268762
Short name T515
Test name
Test status
Simulation time 282677105 ps
CPU time 5.41 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:19 PM PDT 24
Peak memory 218420 kb
Host smart-42cad6a4-a898-475f-93b4-49084f258383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085268762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1085268762
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.578960459
Short name T197
Test name
Test status
Simulation time 15970713610 ps
CPU time 160.34 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:34:47 PM PDT 24
Peak memory 240860 kb
Host smart-08d9061c-411e-42f7-a01e-3207c7c754af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578960459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.578960459
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2409993413
Short name T725
Test name
Test status
Simulation time 3383594068 ps
CPU time 24.38 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 216280 kb
Host smart-32c5fc63-876d-4dcd-a92e-e346a65be18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409993413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2409993413
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4215104064
Short name T423
Test name
Test status
Simulation time 45313364371 ps
CPU time 17.86 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 217388 kb
Host smart-490ea787-2b0a-4dcb-bb54-2327b6613b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215104064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4215104064
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3071491095
Short name T617
Test name
Test status
Simulation time 48463443 ps
CPU time 0.83 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 205904 kb
Host smart-76b4a038-28ae-42db-b139-41d32d1708c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071491095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3071491095
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3502781818
Short name T536
Test name
Test status
Simulation time 51796609 ps
CPU time 0.88 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:17 PM PDT 24
Peak memory 205740 kb
Host smart-97223af3-b7d8-48c2-8f4e-78cec7fa2e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502781818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3502781818
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2408953852
Short name T184
Test name
Test status
Simulation time 7001892357 ps
CPU time 25.28 seconds
Started May 09 01:32:19 PM PDT 24
Finished May 09 01:32:45 PM PDT 24
Peak memory 233684 kb
Host smart-43c29479-4a94-4959-a2aa-9678082ed1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408953852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2408953852
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.531583543
Short name T494
Test name
Test status
Simulation time 14617581 ps
CPU time 0.73 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 204820 kb
Host smart-8d6d0545-e8e2-4f00-bd72-e227d0818e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531583543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.531583543
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1866278218
Short name T730
Test name
Test status
Simulation time 350782332 ps
CPU time 5.66 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:13 PM PDT 24
Peak memory 238800 kb
Host smart-0eccdeb2-3757-40fa-a57c-5181f36ecf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866278218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1866278218
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2230951271
Short name T908
Test name
Test status
Simulation time 46776443 ps
CPU time 0.79 seconds
Started May 09 01:32:19 PM PDT 24
Finished May 09 01:32:21 PM PDT 24
Peak memory 206388 kb
Host smart-a56fb19f-8b98-4348-bc60-babb78feffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230951271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2230951271
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.15190389
Short name T876
Test name
Test status
Simulation time 3723759434 ps
CPU time 49.27 seconds
Started May 09 01:32:17 PM PDT 24
Finished May 09 01:33:07 PM PDT 24
Peak memory 254152 kb
Host smart-c18e4633-b8b2-4d27-9777-5c4c1934c3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15190389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.15190389
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1461639498
Short name T507
Test name
Test status
Simulation time 9509178260 ps
CPU time 70.72 seconds
Started May 09 01:32:21 PM PDT 24
Finished May 09 01:33:32 PM PDT 24
Peak memory 249044 kb
Host smart-50ed1944-4ccf-4f1f-8627-1221ef15c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461639498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1461639498
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.107467307
Short name T315
Test name
Test status
Simulation time 2706765895 ps
CPU time 38.31 seconds
Started May 09 01:32:06 PM PDT 24
Finished May 09 01:32:46 PM PDT 24
Peak memory 240824 kb
Host smart-d329f05c-f810-4171-b21e-7e2b7ab8ccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107467307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.107467307
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2682814974
Short name T167
Test name
Test status
Simulation time 5662531759 ps
CPU time 7.73 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:22 PM PDT 24
Peak memory 221036 kb
Host smart-7fef4030-0083-427f-b8ce-4eaa4d100bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682814974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2682814974
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1065211497
Short name T798
Test name
Test status
Simulation time 10716597600 ps
CPU time 31.75 seconds
Started May 09 01:32:19 PM PDT 24
Finished May 09 01:32:52 PM PDT 24
Peak memory 224320 kb
Host smart-0bec49d0-542c-4e5f-b49b-361b65f8df9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065211497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1065211497
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2913037642
Short name T607
Test name
Test status
Simulation time 3437380494 ps
CPU time 10.81 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:26 PM PDT 24
Peak memory 219820 kb
Host smart-79281a63-028b-4db9-9da4-06e1bec12dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913037642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2913037642
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2637220159
Short name T807
Test name
Test status
Simulation time 1971900974 ps
CPU time 9.03 seconds
Started May 09 01:32:05 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 235936 kb
Host smart-c542d75e-b374-4d24-b4cb-3b762974ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637220159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2637220159
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3201960172
Short name T420
Test name
Test status
Simulation time 2627689265 ps
CPU time 8.85 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:35 PM PDT 24
Peak memory 222744 kb
Host smart-ef87946a-3151-46fb-99cd-2348a2cfee4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3201960172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3201960172
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.924623479
Short name T839
Test name
Test status
Simulation time 7365769389 ps
CPU time 81.83 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:33:50 PM PDT 24
Peak memory 264972 kb
Host smart-b2bafc76-4a9b-4931-96b9-7faff6f56b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924623479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.924623479
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.533414637
Short name T592
Test name
Test status
Simulation time 2075424189 ps
CPU time 17.04 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:35 PM PDT 24
Peak memory 216264 kb
Host smart-43b31505-189f-422d-954b-0bc454e8ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533414637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.533414637
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2742338510
Short name T928
Test name
Test status
Simulation time 3371068326 ps
CPU time 8.73 seconds
Started May 09 01:32:14 PM PDT 24
Finished May 09 01:32:24 PM PDT 24
Peak memory 215980 kb
Host smart-e0eaeee3-0d1a-412f-b028-ea36e2845197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742338510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2742338510
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4245295916
Short name T333
Test name
Test status
Simulation time 46027515 ps
CPU time 1.26 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:16 PM PDT 24
Peak memory 216144 kb
Host smart-f105b18c-be9f-4c05-b53c-563cf12e86a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245295916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4245295916
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3071559280
Short name T946
Test name
Test status
Simulation time 46217931 ps
CPU time 0.9 seconds
Started May 09 01:32:08 PM PDT 24
Finished May 09 01:32:10 PM PDT 24
Peak memory 206628 kb
Host smart-205913d6-891e-41db-8968-571076214c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071559280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3071559280
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3327236915
Short name T209
Test name
Test status
Simulation time 2371421978 ps
CPU time 17.06 seconds
Started May 09 01:32:12 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 252116 kb
Host smart-5780317c-154c-41a6-911b-31dc40598ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327236915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3327236915
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1480751490
Short name T612
Test name
Test status
Simulation time 14311098 ps
CPU time 0.73 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:28 PM PDT 24
Peak memory 205612 kb
Host smart-6947c9cc-beda-40ae-af65-32ea25fcd6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480751490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1480751490
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1047520357
Short name T501
Test name
Test status
Simulation time 936507930 ps
CPU time 7.22 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 235260 kb
Host smart-c034025a-ccec-4fb0-891e-e5f4778bd21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047520357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1047520357
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2857199614
Short name T750
Test name
Test status
Simulation time 22510386 ps
CPU time 0.75 seconds
Started May 09 01:32:19 PM PDT 24
Finished May 09 01:32:21 PM PDT 24
Peak memory 206844 kb
Host smart-7b405917-864e-4477-9197-82b939e2e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857199614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2857199614
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2301681533
Short name T308
Test name
Test status
Simulation time 3280786374 ps
CPU time 13.89 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:42 PM PDT 24
Peak memory 234796 kb
Host smart-9fef5c87-32ac-4813-918a-468e6816754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301681533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2301681533
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.515046535
Short name T917
Test name
Test status
Simulation time 222038504609 ps
CPU time 434.1 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:39:42 PM PDT 24
Peak memory 257276 kb
Host smart-9f1936bc-81c4-4566-ae39-5548d03eee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515046535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.515046535
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3186873995
Short name T623
Test name
Test status
Simulation time 4744007515 ps
CPU time 9.65 seconds
Started May 09 01:32:17 PM PDT 24
Finished May 09 01:32:27 PM PDT 24
Peak memory 249036 kb
Host smart-f15febaa-b2d6-44c3-b307-8676328f01b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186873995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3186873995
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4121339519
Short name T219
Test name
Test status
Simulation time 3392262746 ps
CPU time 32.13 seconds
Started May 09 01:32:22 PM PDT 24
Finished May 09 01:32:55 PM PDT 24
Peak memory 219456 kb
Host smart-cd75536c-0ba7-4fe9-8b6d-b0d5c8c0188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121339519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4121339519
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1497552429
Short name T405
Test name
Test status
Simulation time 8900833422 ps
CPU time 48.28 seconds
Started May 09 01:32:32 PM PDT 24
Finished May 09 01:33:22 PM PDT 24
Peak memory 234456 kb
Host smart-0b86d444-325f-41aa-9cb9-e492ddc35ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497552429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1497552429
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3830784059
Short name T330
Test name
Test status
Simulation time 77605655 ps
CPU time 2.3 seconds
Started May 09 01:32:16 PM PDT 24
Finished May 09 01:32:19 PM PDT 24
Peak memory 221540 kb
Host smart-d0505103-2cbd-424b-91a4-af5ede755934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830784059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3830784059
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3031184850
Short name T829
Test name
Test status
Simulation time 148945745 ps
CPU time 2.36 seconds
Started May 09 01:32:16 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 232620 kb
Host smart-e18b096a-7a13-4802-9d8b-52484e25daf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031184850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3031184850
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1934931624
Short name T929
Test name
Test status
Simulation time 1834895318 ps
CPU time 18.86 seconds
Started May 09 01:32:16 PM PDT 24
Finished May 09 01:32:35 PM PDT 24
Peak memory 222816 kb
Host smart-aaeba597-f30a-4544-8174-a0333172b5c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1934931624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1934931624
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2297974622
Short name T406
Test name
Test status
Simulation time 13849681 ps
CPU time 0.72 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:29 PM PDT 24
Peak memory 205664 kb
Host smart-ece3b4d3-9220-4346-8981-752fbe3923e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297974622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2297974622
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2452184770
Short name T542
Test name
Test status
Simulation time 5072374641 ps
CPU time 12.92 seconds
Started May 09 01:32:14 PM PDT 24
Finished May 09 01:32:28 PM PDT 24
Peak memory 216160 kb
Host smart-00eaa2c6-ae85-4e5e-95ae-b3eb93edb09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452184770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2452184770
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.270556871
Short name T47
Test name
Test status
Simulation time 26922184 ps
CPU time 0.88 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 206812 kb
Host smart-a8a7f2ea-a95d-4e25-b1bb-4baa810bdd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270556871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.270556871
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2206680067
Short name T674
Test name
Test status
Simulation time 61090405 ps
CPU time 0.84 seconds
Started May 09 01:32:18 PM PDT 24
Finished May 09 01:32:20 PM PDT 24
Peak memory 205732 kb
Host smart-252622c1-76e2-444a-a0af-611b44f98a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206680067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2206680067
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2795048274
Short name T220
Test name
Test status
Simulation time 401140128 ps
CPU time 3.9 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:33 PM PDT 24
Peak memory 217928 kb
Host smart-11ce0e93-f820-4200-a43e-7a6a887eadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795048274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2795048274
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4166970884
Short name T399
Test name
Test status
Simulation time 14488205 ps
CPU time 0.72 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:29 PM PDT 24
Peak memory 205276 kb
Host smart-b3b8e6a6-7b37-4bd6-8f6f-aaebc9e05692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166970884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4166970884
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2483536978
Short name T610
Test name
Test status
Simulation time 113252573 ps
CPU time 2.18 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 218736 kb
Host smart-dec3c304-f5e9-4b8f-a2b4-7e22c5293bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483536978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2483536978
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4039554021
Short name T685
Test name
Test status
Simulation time 20534537 ps
CPU time 0.78 seconds
Started May 09 01:32:13 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 206516 kb
Host smart-a67edba7-e276-4d6f-9cae-9f4bbe8b3965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039554021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4039554021
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1431103253
Short name T784
Test name
Test status
Simulation time 1749107058 ps
CPU time 14.43 seconds
Started May 09 01:32:16 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 237924 kb
Host smart-5b57a361-f60a-43a1-acca-76cc80441f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431103253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1431103253
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3203851945
Short name T193
Test name
Test status
Simulation time 11288679230 ps
CPU time 97.96 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:34:06 PM PDT 24
Peak memory 257336 kb
Host smart-21464b71-4400-46ce-b8f8-311ce870d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203851945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3203851945
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2555130668
Short name T377
Test name
Test status
Simulation time 517300786 ps
CPU time 3.76 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 232604 kb
Host smart-27dc94e1-683b-4d08-8043-74aff9a983fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555130668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2555130668
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2902447216
Short name T901
Test name
Test status
Simulation time 260560388 ps
CPU time 2.42 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:18 PM PDT 24
Peak memory 218520 kb
Host smart-f1f0b3b5-671b-4aae-bed0-7cfeb43ed1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902447216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2902447216
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1346001964
Short name T921
Test name
Test status
Simulation time 2713525595 ps
CPU time 26.92 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:56 PM PDT 24
Peak memory 234316 kb
Host smart-1bce0c17-9118-4109-a416-8ec201d2f16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346001964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1346001964
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4077047755
Short name T638
Test name
Test status
Simulation time 2920330535 ps
CPU time 12.13 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:41 PM PDT 24
Peak memory 224468 kb
Host smart-a7ebdc3e-0cfe-4a07-b15c-e06185ec0a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077047755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4077047755
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4074125846
Short name T796
Test name
Test status
Simulation time 309566229 ps
CPU time 5.37 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:34 PM PDT 24
Peak memory 238164 kb
Host smart-6c84bd7f-b47d-4037-b80f-58f6d25be9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074125846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4074125846
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3042865308
Short name T447
Test name
Test status
Simulation time 1408956346 ps
CPU time 15.09 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 222168 kb
Host smart-70c1c471-cfb4-40a0-8e8f-4fb14c1d55a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3042865308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3042865308
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2333882045
Short name T40
Test name
Test status
Simulation time 6524271507 ps
CPU time 87.23 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:33:55 PM PDT 24
Peak memory 256692 kb
Host smart-2c75f326-d923-4b02-b9f1-e6bcebf1aeb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333882045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2333882045
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.622145553
Short name T782
Test name
Test status
Simulation time 5807815941 ps
CPU time 27.64 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:44 PM PDT 24
Peak memory 216300 kb
Host smart-21c67ff8-6463-4a98-995c-5f41e7c2f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622145553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.622145553
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1406077587
Short name T452
Test name
Test status
Simulation time 36812824 ps
CPU time 0.7 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 205636 kb
Host smart-64296480-0023-49b4-a4cc-4525ce71d2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406077587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1406077587
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.40471474
Short name T738
Test name
Test status
Simulation time 52600780 ps
CPU time 1.64 seconds
Started May 09 01:32:15 PM PDT 24
Finished May 09 01:32:17 PM PDT 24
Peak memory 216132 kb
Host smart-65b778d8-9485-4bd3-90f8-e7e534fd3118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40471474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.40471474
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2457467683
Short name T385
Test name
Test status
Simulation time 23635065 ps
CPU time 0.79 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 205768 kb
Host smart-58f91296-a5b4-4138-835a-ecca938170a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457467683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2457467683
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1267732830
Short name T824
Test name
Test status
Simulation time 159688124 ps
CPU time 3.12 seconds
Started May 09 01:32:27 PM PDT 24
Finished May 09 01:32:33 PM PDT 24
Peak memory 224488 kb
Host smart-88101f42-4be6-4b15-9307-c6d07e5c5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267732830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1267732830
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.755200427
Short name T356
Test name
Test status
Simulation time 14616986 ps
CPU time 0.76 seconds
Started May 09 01:29:45 PM PDT 24
Finished May 09 01:29:46 PM PDT 24
Peak memory 204776 kb
Host smart-f02df8b9-d146-4bd2-8efe-960ec0a77638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755200427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.755200427
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3405750802
Short name T693
Test name
Test status
Simulation time 678342480 ps
CPU time 7.56 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:29:57 PM PDT 24
Peak memory 232588 kb
Host smart-e3126dac-47e4-49ad-9e56-d1d4c7f1f0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405750802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3405750802
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1898400219
Short name T556
Test name
Test status
Simulation time 39711679 ps
CPU time 0.75 seconds
Started May 09 01:29:47 PM PDT 24
Finished May 09 01:29:49 PM PDT 24
Peak memory 205476 kb
Host smart-ba4b9405-0a49-4f15-a2fa-ea60fc75bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898400219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1898400219
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3013099826
Short name T240
Test name
Test status
Simulation time 9289336208 ps
CPU time 64.44 seconds
Started May 09 01:29:43 PM PDT 24
Finished May 09 01:30:48 PM PDT 24
Peak memory 251516 kb
Host smart-cfe3db74-6e5c-4afb-82c9-9ee8dd30c840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013099826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3013099826
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2733404324
Short name T410
Test name
Test status
Simulation time 2892304819 ps
CPU time 16.63 seconds
Started May 09 01:29:46 PM PDT 24
Finished May 09 01:30:03 PM PDT 24
Peak memory 217344 kb
Host smart-3d88fe52-f1f2-4466-957d-ea7610bff581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733404324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2733404324
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1249802772
Short name T940
Test name
Test status
Simulation time 6042228861 ps
CPU time 56.64 seconds
Started May 09 01:29:43 PM PDT 24
Finished May 09 01:30:40 PM PDT 24
Peak memory 239428 kb
Host smart-3dadb03b-e34a-44e7-8f5e-69f5c917acf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249802772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1249802772
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3170875005
Short name T363
Test name
Test status
Simulation time 328147151 ps
CPU time 3.19 seconds
Started May 09 01:29:49 PM PDT 24
Finished May 09 01:29:54 PM PDT 24
Peak memory 232500 kb
Host smart-9bf8ea5b-ceee-4b79-b339-e06155cd093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170875005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3170875005
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3164957711
Short name T859
Test name
Test status
Simulation time 366431212 ps
CPU time 2.82 seconds
Started May 09 01:29:51 PM PDT 24
Finished May 09 01:29:54 PM PDT 24
Peak memory 224368 kb
Host smart-4b897a65-5183-486c-affe-d1a115599dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164957711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3164957711
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1500136183
Short name T448
Test name
Test status
Simulation time 2312050039 ps
CPU time 8.8 seconds
Started May 09 01:29:49 PM PDT 24
Finished May 09 01:29:59 PM PDT 24
Peak memory 238872 kb
Host smart-5e1786ea-b856-45df-9a8a-92561394d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500136183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1500136183
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1206032504
Short name T281
Test name
Test status
Simulation time 213230593 ps
CPU time 3.8 seconds
Started May 09 01:29:53 PM PDT 24
Finished May 09 01:29:58 PM PDT 24
Peak memory 233200 kb
Host smart-a97a5e11-6ed3-4f05-adc6-7d4395b18b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206032504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1206032504
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3716266273
Short name T491
Test name
Test status
Simulation time 7759774455 ps
CPU time 11.48 seconds
Started May 09 01:29:49 PM PDT 24
Finished May 09 01:30:02 PM PDT 24
Peak memory 225848 kb
Host smart-8c9aef72-7dd1-4364-8ba9-7227daf12b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716266273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3716266273
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3745786420
Short name T733
Test name
Test status
Simulation time 1290435945 ps
CPU time 16.15 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:30:05 PM PDT 24
Peak memory 219824 kb
Host smart-e2f99995-94d6-4e84-b04e-30eee9d80c2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3745786420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3745786420
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.307141151
Short name T65
Test name
Test status
Simulation time 55974253 ps
CPU time 0.99 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:29:56 PM PDT 24
Peak memory 234680 kb
Host smart-f28f147a-1258-43de-bb96-8846e7d0a309
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307141151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.307141151
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.363081152
Short name T198
Test name
Test status
Simulation time 125119713266 ps
CPU time 641.77 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:40:37 PM PDT 24
Peak memory 253924 kb
Host smart-0e888dfa-7cde-4a6f-8c7f-ff6faf56766b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363081152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.363081152
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.818608686
Short name T575
Test name
Test status
Simulation time 6866056461 ps
CPU time 24.69 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:30:14 PM PDT 24
Peak memory 216208 kb
Host smart-7d7005fb-8a1a-4e7b-ab0f-9f17b0b9b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818608686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.818608686
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2338536491
Short name T763
Test name
Test status
Simulation time 3322168212 ps
CPU time 6.13 seconds
Started May 09 01:29:49 PM PDT 24
Finished May 09 01:29:56 PM PDT 24
Peak memory 216184 kb
Host smart-6e36d4dd-d01f-4f14-9f86-02c4d0d25627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338536491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2338536491
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1743290978
Short name T67
Test name
Test status
Simulation time 138090600 ps
CPU time 4.71 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:30:00 PM PDT 24
Peak memory 216192 kb
Host smart-20d87eee-a227-4c2d-a9b7-c48663e4e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743290978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1743290978
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.236681702
Short name T845
Test name
Test status
Simulation time 217157234 ps
CPU time 0.71 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:29:50 PM PDT 24
Peak memory 205744 kb
Host smart-8288274a-1e58-45e2-992a-9a07ff9b546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236681702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.236681702
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3774201712
Short name T827
Test name
Test status
Simulation time 71736436700 ps
CPU time 31.5 seconds
Started May 09 01:29:53 PM PDT 24
Finished May 09 01:30:25 PM PDT 24
Peak memory 228144 kb
Host smart-601b3335-fe22-487d-a3f4-4db9a11e538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774201712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3774201712
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1697817711
Short name T585
Test name
Test status
Simulation time 42648842 ps
CPU time 0.74 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:32:39 PM PDT 24
Peak memory 205724 kb
Host smart-cb8bbf14-32f5-4300-b649-1e3ae16571b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697817711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1697817711
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.655638754
Short name T569
Test name
Test status
Simulation time 1413536524 ps
CPU time 13.69 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 219660 kb
Host smart-a7d513b3-a267-49d5-81bd-e647ba752a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655638754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.655638754
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1040339933
Short name T593
Test name
Test status
Simulation time 38582560 ps
CPU time 0.77 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:28 PM PDT 24
Peak memory 205408 kb
Host smart-956798e7-a58f-4878-b651-5911b5642088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040339933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1040339933
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2951284162
Short name T723
Test name
Test status
Simulation time 1171955501 ps
CPU time 5.5 seconds
Started May 09 01:32:28 PM PDT 24
Finished May 09 01:32:36 PM PDT 24
Peak memory 224408 kb
Host smart-6defda2b-0d41-4ebe-8a9c-f65d1068fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951284162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2951284162
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.79642177
Short name T474
Test name
Test status
Simulation time 8610495897 ps
CPU time 80.75 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:33:49 PM PDT 24
Peak memory 253400 kb
Host smart-481b32f7-c899-45fb-b76f-db0c3fd60f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79642177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.79642177
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1603700842
Short name T43
Test name
Test status
Simulation time 99881850872 ps
CPU time 185.52 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:35:35 PM PDT 24
Peak memory 253376 kb
Host smart-2c7311c1-be21-4af9-9a69-6b53b798f1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603700842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1603700842
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3054890836
Short name T890
Test name
Test status
Simulation time 111758819 ps
CPU time 4.35 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 232596 kb
Host smart-b79e85fd-9766-4e65-a08c-f6705e089dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054890836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3054890836
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2192126999
Short name T828
Test name
Test status
Simulation time 9541659157 ps
CPU time 20.75 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:49 PM PDT 24
Peak memory 235452 kb
Host smart-7acb44c7-d978-4688-864a-43a1f58bc7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192126999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2192126999
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2140280171
Short name T656
Test name
Test status
Simulation time 1222783142 ps
CPU time 14.42 seconds
Started May 09 01:32:38 PM PDT 24
Finished May 09 01:32:54 PM PDT 24
Peak memory 237496 kb
Host smart-d163725d-a67a-40f6-bd8d-31b4a51ebeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140280171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2140280171
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1405658203
Short name T277
Test name
Test status
Simulation time 9726941885 ps
CPU time 18.65 seconds
Started May 09 01:32:24 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 234376 kb
Host smart-ae1dbfe6-c781-4210-9ea6-a2b22a7d6284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405658203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1405658203
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1965060021
Short name T269
Test name
Test status
Simulation time 2334988929 ps
CPU time 7.27 seconds
Started May 09 01:32:23 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 233676 kb
Host smart-64c569d3-aa67-42f8-ba7b-03fb7521427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965060021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1965060021
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2087046231
Short name T662
Test name
Test status
Simulation time 4019563688 ps
CPU time 11.29 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:41 PM PDT 24
Peak memory 218808 kb
Host smart-449be311-309d-430c-83e0-bb2106e1ea6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087046231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2087046231
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.805718940
Short name T686
Test name
Test status
Simulation time 4346331191 ps
CPU time 70.69 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:33:38 PM PDT 24
Peak memory 254076 kb
Host smart-0fd9449e-363e-4e03-8cc0-87563a4d2dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805718940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.805718940
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.491743478
Short name T434
Test name
Test status
Simulation time 618530133 ps
CPU time 6.64 seconds
Started May 09 01:32:27 PM PDT 24
Finished May 09 01:32:36 PM PDT 24
Peak memory 216520 kb
Host smart-3c848b5d-2c87-4c3d-8bf8-bc51ad7aea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491743478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.491743478
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3107906383
Short name T865
Test name
Test status
Simulation time 1909216992 ps
CPU time 2.81 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 216048 kb
Host smart-23eba681-43bf-47f9-a327-827175c5863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107906383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3107906383
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.699800786
Short name T751
Test name
Test status
Simulation time 147654317 ps
CPU time 4.64 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 216188 kb
Host smart-35993f16-0d61-4d13-8996-5fe859d81e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699800786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.699800786
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.572922312
Short name T629
Test name
Test status
Simulation time 182614373 ps
CPU time 0.98 seconds
Started May 09 01:32:37 PM PDT 24
Finished May 09 01:32:40 PM PDT 24
Peak memory 206148 kb
Host smart-c74ad739-cb01-4cde-b605-1542412e8376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572922312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.572922312
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3830469138
Short name T669
Test name
Test status
Simulation time 1810168128 ps
CPU time 5.63 seconds
Started May 09 01:32:28 PM PDT 24
Finished May 09 01:32:36 PM PDT 24
Peak memory 227464 kb
Host smart-73a0ad85-27ed-4ce0-82ab-68c51ed51479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830469138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3830469138
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.263025129
Short name T55
Test name
Test status
Simulation time 38417907 ps
CPU time 0.72 seconds
Started May 09 01:32:24 PM PDT 24
Finished May 09 01:32:26 PM PDT 24
Peak memory 204808 kb
Host smart-2e230a1d-fc30-43f5-b7bb-c07965993dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263025129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.263025129
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2882164945
Short name T707
Test name
Test status
Simulation time 166551148 ps
CPU time 2.1 seconds
Started May 09 01:32:38 PM PDT 24
Finished May 09 01:32:42 PM PDT 24
Peak memory 218504 kb
Host smart-2633abfe-68f7-4aa0-85b7-97533502e7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882164945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2882164945
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2946007745
Short name T127
Test name
Test status
Simulation time 12823834 ps
CPU time 0.73 seconds
Started May 09 01:32:25 PM PDT 24
Finished May 09 01:32:29 PM PDT 24
Peak memory 205536 kb
Host smart-3aebca1d-38f5-4416-8f50-3b0f18ae82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946007745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2946007745
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.151822646
Short name T329
Test name
Test status
Simulation time 17461718 ps
CPU time 0.8 seconds
Started May 09 01:32:24 PM PDT 24
Finished May 09 01:32:26 PM PDT 24
Peak memory 215940 kb
Host smart-12edf532-19e1-443b-8296-d9c6948ba0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151822646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.151822646
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2852928825
Short name T567
Test name
Test status
Simulation time 927111810 ps
CPU time 14.7 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:44 PM PDT 24
Peak memory 217116 kb
Host smart-b7f51e43-7de2-40c4-8751-fc40b5a218d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852928825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2852928825
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2882066118
Short name T842
Test name
Test status
Simulation time 112897181 ps
CPU time 0.98 seconds
Started May 09 01:32:28 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 216920 kb
Host smart-713e98d5-3c84-4be0-8253-db1824bd1d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882066118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2882066118
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4252140463
Short name T770
Test name
Test status
Simulation time 1016039819 ps
CPU time 12.63 seconds
Started May 09 01:32:30 PM PDT 24
Finished May 09 01:32:44 PM PDT 24
Peak memory 224416 kb
Host smart-bcef2370-dada-4e84-a728-868be9ac2942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252140463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4252140463
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4209623512
Short name T296
Test name
Test status
Simulation time 1847700119 ps
CPU time 5.91 seconds
Started May 09 01:32:38 PM PDT 24
Finished May 09 01:32:46 PM PDT 24
Peak memory 218396 kb
Host smart-11ac5b5e-15e4-4ac1-9431-78cb75fb7e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209623512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4209623512
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.989638088
Short name T426
Test name
Test status
Simulation time 161959433 ps
CPU time 3.87 seconds
Started May 09 01:32:37 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 233792 kb
Host smart-46bcbf3f-ce30-40fc-a452-62fe98f34ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989638088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.989638088
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2403177008
Short name T408
Test name
Test status
Simulation time 6509499018 ps
CPU time 9.35 seconds
Started May 09 01:32:38 PM PDT 24
Finished May 09 01:32:49 PM PDT 24
Peak memory 229188 kb
Host smart-5a6c41cf-5e3b-451e-beb9-c37861f7e7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403177008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2403177008
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4235326994
Short name T343
Test name
Test status
Simulation time 4751707693 ps
CPU time 13.62 seconds
Started May 09 01:32:27 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 222836 kb
Host smart-063c8664-44c1-4804-adf1-e47d63bccd66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4235326994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4235326994
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1226057355
Short name T586
Test name
Test status
Simulation time 47356480855 ps
CPU time 124.43 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:34:34 PM PDT 24
Peak memory 253204 kb
Host smart-0dd92278-f176-47f8-96f0-3191e3151125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226057355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1226057355
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1237753015
Short name T2
Test name
Test status
Simulation time 8563587013 ps
CPU time 19.45 seconds
Started May 09 01:32:27 PM PDT 24
Finished May 09 01:32:49 PM PDT 24
Peak memory 216232 kb
Host smart-e3da2ec8-f448-4d67-85a2-bb7ef9f98293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237753015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1237753015
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.280550683
Short name T326
Test name
Test status
Simulation time 22566871906 ps
CPU time 19.67 seconds
Started May 09 01:32:31 PM PDT 24
Finished May 09 01:32:53 PM PDT 24
Peak memory 216272 kb
Host smart-4e316546-9b99-4ffe-bece-0e43dfc7e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280550683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.280550683
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1763338427
Short name T412
Test name
Test status
Simulation time 48776297 ps
CPU time 0.89 seconds
Started May 09 01:32:28 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 206980 kb
Host smart-df32498a-0788-4f21-8548-dfc7230190c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763338427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1763338427
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3106334770
Short name T676
Test name
Test status
Simulation time 49373631 ps
CPU time 0.86 seconds
Started May 09 01:32:31 PM PDT 24
Finished May 09 01:32:34 PM PDT 24
Peak memory 205752 kb
Host smart-79791fd4-0de3-4711-845f-9415cb6c2d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106334770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3106334770
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4184198914
Short name T331
Test name
Test status
Simulation time 84631596 ps
CPU time 2.48 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 220880 kb
Host smart-def76c12-8c95-4165-b745-b2db9a9f0940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184198914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4184198914
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1172413908
Short name T745
Test name
Test status
Simulation time 37812776 ps
CPU time 0.69 seconds
Started May 09 01:32:35 PM PDT 24
Finished May 09 01:32:38 PM PDT 24
Peak memory 205392 kb
Host smart-f941c128-9ef1-40f6-805d-a4a62503abcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172413908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1172413908
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1099423663
Short name T702
Test name
Test status
Simulation time 178100686 ps
CPU time 2.37 seconds
Started May 09 01:32:33 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 233328 kb
Host smart-a128365f-d8a3-4c92-9689-0597a498ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099423663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1099423663
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1037585153
Short name T804
Test name
Test status
Simulation time 16756074 ps
CPU time 0.75 seconds
Started May 09 01:32:30 PM PDT 24
Finished May 09 01:32:32 PM PDT 24
Peak memory 205408 kb
Host smart-8bd699c7-992a-49db-88cb-31ef1cbb349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037585153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1037585153
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3130992247
Short name T241
Test name
Test status
Simulation time 77922534536 ps
CPU time 99.01 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:34:20 PM PDT 24
Peak memory 248956 kb
Host smart-b0029bc4-4690-48e9-82c2-9000fdb5c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130992247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3130992247
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2719421181
Short name T895
Test name
Test status
Simulation time 3316628345 ps
CPU time 25.07 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:33:03 PM PDT 24
Peak memory 219264 kb
Host smart-15976c5b-5454-4a99-a82b-273998d7d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719421181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2719421181
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.696918207
Short name T439
Test name
Test status
Simulation time 4511289955 ps
CPU time 13.03 seconds
Started May 09 01:32:35 PM PDT 24
Finished May 09 01:32:50 PM PDT 24
Peak memory 233016 kb
Host smart-347d0862-b16b-4b20-abef-328fbce7f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696918207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.696918207
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4229160254
Short name T86
Test name
Test status
Simulation time 26951060295 ps
CPU time 85.3 seconds
Started May 09 01:32:37 PM PDT 24
Finished May 09 01:34:04 PM PDT 24
Peak memory 249904 kb
Host smart-09e661de-e0ee-44e9-a2c3-484ce3dccf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229160254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4229160254
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3719859589
Short name T392
Test name
Test status
Simulation time 1454259822 ps
CPU time 3.32 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:32:41 PM PDT 24
Peak memory 224360 kb
Host smart-17c6eefd-2928-410c-b0a2-ac2b933aaf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719859589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3719859589
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1171982640
Short name T199
Test name
Test status
Simulation time 52306730733 ps
CPU time 32.64 seconds
Started May 09 01:32:33 PM PDT 24
Finished May 09 01:33:07 PM PDT 24
Peak memory 223548 kb
Host smart-b03ec772-6f11-456b-9563-2722e8dd4147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171982640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1171982640
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1939082899
Short name T822
Test name
Test status
Simulation time 1535049507 ps
CPU time 7.16 seconds
Started May 09 01:32:31 PM PDT 24
Finished May 09 01:32:41 PM PDT 24
Peak memory 239948 kb
Host smart-e6e9186e-5907-4fcf-86a5-db2e2d691673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939082899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1939082899
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3843854124
Short name T208
Test name
Test status
Simulation time 540185204 ps
CPU time 7.07 seconds
Started May 09 01:32:30 PM PDT 24
Finished May 09 01:32:38 PM PDT 24
Peak memory 233732 kb
Host smart-3d842b50-1f16-4a4e-80ec-311305cb25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843854124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3843854124
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3920929683
Short name T461
Test name
Test status
Simulation time 6454144622 ps
CPU time 13.09 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:33:05 PM PDT 24
Peak memory 219140 kb
Host smart-952e571f-a740-41f6-ae43-0c2dd18c17d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920929683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3920929683
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3918415845
Short name T36
Test name
Test status
Simulation time 4309089277 ps
CPU time 26.65 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:33:18 PM PDT 24
Peak memory 240628 kb
Host smart-31bbcb5f-2e6d-45fe-9071-7037dc854261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918415845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3918415845
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2871909273
Short name T739
Test name
Test status
Simulation time 4039984052 ps
CPU time 11.35 seconds
Started May 09 01:32:29 PM PDT 24
Finished May 09 01:32:42 PM PDT 24
Peak memory 216180 kb
Host smart-88baf720-15fd-4ab6-ad6f-ae243fd032e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871909273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2871909273
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2628929673
Short name T795
Test name
Test status
Simulation time 5171579325 ps
CPU time 6.13 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:35 PM PDT 24
Peak memory 216228 kb
Host smart-5509febb-7300-4693-9cc8-405cfd523167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628929673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2628929673
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3359486082
Short name T48
Test name
Test status
Simulation time 35093939 ps
CPU time 0.67 seconds
Started May 09 01:32:26 PM PDT 24
Finished May 09 01:32:30 PM PDT 24
Peak memory 205528 kb
Host smart-bab774b3-c02a-4ca7-85a0-40359967396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359486082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3359486082
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2667351709
Short name T85
Test name
Test status
Simulation time 65224772 ps
CPU time 0.9 seconds
Started May 09 01:32:27 PM PDT 24
Finished May 09 01:32:31 PM PDT 24
Peak memory 205672 kb
Host smart-5cf883fc-8b00-4230-a3bb-51bc2cedd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667351709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2667351709
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3643499340
Short name T727
Test name
Test status
Simulation time 16836346274 ps
CPU time 22.18 seconds
Started May 09 01:32:40 PM PDT 24
Finished May 09 01:33:04 PM PDT 24
Peak memory 234716 kb
Host smart-b8a5fa95-3bb1-4519-974c-4fe6a0e5dc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643499340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3643499340
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1327722776
Short name T847
Test name
Test status
Simulation time 35759629 ps
CPU time 0.72 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:32:39 PM PDT 24
Peak memory 205688 kb
Host smart-b63c3218-7ff7-4147-b8a5-3cf8ac121065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327722776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1327722776
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1494823451
Short name T799
Test name
Test status
Simulation time 1088785625 ps
CPU time 7.26 seconds
Started May 09 01:32:34 PM PDT 24
Finished May 09 01:32:42 PM PDT 24
Peak memory 238888 kb
Host smart-401b1228-267b-47a8-866d-e898437f588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494823451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1494823451
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4125323146
Short name T572
Test name
Test status
Simulation time 14766568 ps
CPU time 0.77 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:32:51 PM PDT 24
Peak memory 206528 kb
Host smart-e1d2e942-e684-400d-ad0b-1ba504dff08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125323146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4125323146
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2138339396
Short name T181
Test name
Test status
Simulation time 58359790866 ps
CPU time 434.37 seconds
Started May 09 01:32:41 PM PDT 24
Finished May 09 01:39:56 PM PDT 24
Peak memory 248996 kb
Host smart-09b5d2e0-73b2-4b2e-96f7-e646789779c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138339396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2138339396
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2572642334
Short name T244
Test name
Test status
Simulation time 65151332839 ps
CPU time 292.55 seconds
Started May 09 01:32:40 PM PDT 24
Finished May 09 01:37:34 PM PDT 24
Peak memory 252596 kb
Host smart-4a333157-dea5-44ee-89af-00b8d9bd8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572642334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2572642334
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3427261586
Short name T755
Test name
Test status
Simulation time 3318075741 ps
CPU time 51.57 seconds
Started May 09 01:32:37 PM PDT 24
Finished May 09 01:33:30 PM PDT 24
Peak memory 232648 kb
Host smart-70d6b473-8778-4b20-b19d-9a1e6d0259d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427261586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3427261586
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1044829945
Short name T677
Test name
Test status
Simulation time 11901404592 ps
CPU time 11.18 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:32:49 PM PDT 24
Peak memory 234104 kb
Host smart-a812c45c-5a58-4327-a772-02e3f9299b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044829945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1044829945
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.395636243
Short name T867
Test name
Test status
Simulation time 645670570 ps
CPU time 14.54 seconds
Started May 09 01:32:35 PM PDT 24
Finished May 09 01:32:50 PM PDT 24
Peak memory 232136 kb
Host smart-0dea28da-6a58-45d5-94ee-e11fc6d6ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395636243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.395636243
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3603989948
Short name T242
Test name
Test status
Simulation time 953120162 ps
CPU time 8.35 seconds
Started May 09 01:32:42 PM PDT 24
Finished May 09 01:32:51 PM PDT 24
Peak memory 228824 kb
Host smart-7671f973-a80e-495e-9e32-4d3694011e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603989948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3603989948
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2580314510
Short name T660
Test name
Test status
Simulation time 3432206118 ps
CPU time 4.77 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:45 PM PDT 24
Peak memory 218704 kb
Host smart-7678c111-d440-4815-96fb-eee3198102df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580314510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2580314510
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2261814852
Short name T68
Test name
Test status
Simulation time 1029556232 ps
CPU time 13.5 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:54 PM PDT 24
Peak memory 222616 kb
Host smart-0b9138af-daea-4ca9-ae33-7a1618381bd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2261814852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2261814852
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3213861888
Short name T855
Test name
Test status
Simulation time 1825318998 ps
CPU time 9.75 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:51 PM PDT 24
Peak memory 216196 kb
Host smart-7dfe4606-c579-48e8-9ad2-c1681b6a2202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213861888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3213861888
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1433320969
Short name T789
Test name
Test status
Simulation time 18813172477 ps
CPU time 14.09 seconds
Started May 09 01:32:34 PM PDT 24
Finished May 09 01:32:49 PM PDT 24
Peak memory 216200 kb
Host smart-31eef5f1-e700-4c97-879d-f0d7f328e11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433320969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1433320969
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.772711348
Short name T671
Test name
Test status
Simulation time 20849631 ps
CPU time 0.66 seconds
Started May 09 01:32:45 PM PDT 24
Finished May 09 01:32:47 PM PDT 24
Peak memory 205552 kb
Host smart-d9dcf20d-d594-4e22-bcd1-079717718db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772711348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.772711348
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1836942418
Short name T488
Test name
Test status
Simulation time 87375299 ps
CPU time 0.84 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:32:53 PM PDT 24
Peak memory 205744 kb
Host smart-4e8481c8-f0b3-4123-81ab-9bcd7d963a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836942418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1836942418
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4288747150
Short name T6
Test name
Test status
Simulation time 12016046806 ps
CPU time 12.34 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:53 PM PDT 24
Peak memory 232688 kb
Host smart-ea650eb5-5fcc-4573-8775-4c23fbc61aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288747150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4288747150
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2065842445
Short name T349
Test name
Test status
Simulation time 43881922 ps
CPU time 0.73 seconds
Started May 09 01:32:42 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 205556 kb
Host smart-e630d0a7-3f3f-4b6e-8310-a4baf3fa862b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065842445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2065842445
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.353755164
Short name T774
Test name
Test status
Simulation time 581326053 ps
CPU time 3.62 seconds
Started May 09 01:32:45 PM PDT 24
Finished May 09 01:32:50 PM PDT 24
Peak memory 234624 kb
Host smart-0e282257-6f14-4f04-9f33-8af10789bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353755164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.353755164
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3409107298
Short name T800
Test name
Test status
Simulation time 23029134 ps
CPU time 0.82 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:32:54 PM PDT 24
Peak memory 206832 kb
Host smart-243c57d9-a30b-4198-94e9-9f9689e0cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409107298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3409107298
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3630356574
Short name T581
Test name
Test status
Simulation time 28557162737 ps
CPU time 53.78 seconds
Started May 09 01:32:37 PM PDT 24
Finished May 09 01:33:33 PM PDT 24
Peak memory 240856 kb
Host smart-315a0441-121f-4052-bcf5-39c4fe924975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630356574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3630356574
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.964971926
Short name T20
Test name
Test status
Simulation time 3101816197 ps
CPU time 25.6 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:33:18 PM PDT 24
Peak memory 217424 kb
Host smart-368a5746-3eb8-4bd2-963e-0f1766ed0830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964971926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.964971926
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3087485965
Short name T136
Test name
Test status
Simulation time 14508192314 ps
CPU time 47.08 seconds
Started May 09 01:32:35 PM PDT 24
Finished May 09 01:33:24 PM PDT 24
Peak memory 249164 kb
Host smart-5de33ec1-42f4-4b62-811d-76d0d5d8705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087485965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3087485965
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2128950214
Short name T50
Test name
Test status
Simulation time 2224736264 ps
CPU time 44.33 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:33:25 PM PDT 24
Peak memory 232676 kb
Host smart-2bd5f690-5309-4c58-a575-f0d8c509cbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128950214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2128950214
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1519479338
Short name T174
Test name
Test status
Simulation time 2960947247 ps
CPU time 9.14 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:49 PM PDT 24
Peak memory 218476 kb
Host smart-ab25219c-5072-46e3-9761-9ecb86f3e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519479338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1519479338
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2312147425
Short name T644
Test name
Test status
Simulation time 39765068 ps
CPU time 2.3 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 218652 kb
Host smart-a484934a-156b-4f37-a337-72bdc6212d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312147425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2312147425
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2792458136
Short name T670
Test name
Test status
Simulation time 731506108 ps
CPU time 7.49 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:32:45 PM PDT 24
Peak memory 233488 kb
Host smart-9e5c2914-d425-4919-bd6c-79de760f9eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792458136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2792458136
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3371051072
Short name T582
Test name
Test status
Simulation time 1714215521 ps
CPU time 5.38 seconds
Started May 09 01:32:38 PM PDT 24
Finished May 09 01:32:45 PM PDT 24
Peak memory 235044 kb
Host smart-af1eb472-9421-47db-81c3-814ddff71bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371051072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3371051072
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1343892298
Short name T785
Test name
Test status
Simulation time 2030539916 ps
CPU time 19.77 seconds
Started May 09 01:32:36 PM PDT 24
Finished May 09 01:32:57 PM PDT 24
Peak memory 222712 kb
Host smart-0ba3b040-f36c-4731-81f2-cd131d7ff5ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1343892298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1343892298
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.268222399
Short name T358
Test name
Test status
Simulation time 12461348977 ps
CPU time 23.66 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 216252 kb
Host smart-834e1351-4401-4ae6-a0bb-534137863064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268222399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.268222399
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.158975487
Short name T387
Test name
Test status
Simulation time 3232857364 ps
CPU time 11.86 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:53 PM PDT 24
Peak memory 216168 kb
Host smart-fdaeb5bd-9e01-4bdc-a620-f1eff8771d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158975487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.158975487
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2360899151
Short name T360
Test name
Test status
Simulation time 16424937 ps
CPU time 0.74 seconds
Started May 09 01:32:35 PM PDT 24
Finished May 09 01:32:37 PM PDT 24
Peak memory 205812 kb
Host smart-6e5baeab-ce5f-439b-a9c5-01810f17d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360899151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2360899151
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2642069827
Short name T635
Test name
Test status
Simulation time 138121310 ps
CPU time 0.82 seconds
Started May 09 01:32:38 PM PDT 24
Finished May 09 01:32:41 PM PDT 24
Peak memory 205776 kb
Host smart-4cc5b857-369a-42c1-ad92-9d8114ecf367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642069827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2642069827
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3751861435
Short name T211
Test name
Test status
Simulation time 2427775119 ps
CPU time 10.16 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:51 PM PDT 24
Peak memory 234392 kb
Host smart-404f7bb7-94aa-47de-939e-28b043e48e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751861435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3751861435
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.555299666
Short name T724
Test name
Test status
Simulation time 46566080 ps
CPU time 0.71 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:32:54 PM PDT 24
Peak memory 205336 kb
Host smart-cb308409-5117-4ce4-9e62-98b803f6072e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555299666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.555299666
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.820978843
Short name T88
Test name
Test status
Simulation time 8251593692 ps
CPU time 19.34 seconds
Started May 09 01:32:55 PM PDT 24
Finished May 09 01:33:15 PM PDT 24
Peak memory 219792 kb
Host smart-48665f9d-c50c-4df8-a00b-493d90563120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820978843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.820978843
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.431932112
Short name T909
Test name
Test status
Simulation time 48008462 ps
CPU time 0.79 seconds
Started May 09 01:32:42 PM PDT 24
Finished May 09 01:32:43 PM PDT 24
Peak memory 205444 kb
Host smart-7539f2d9-4366-4735-b9f0-bce10daa05ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431932112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.431932112
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1348493963
Short name T681
Test name
Test status
Simulation time 5400416992 ps
CPU time 71.4 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:34:05 PM PDT 24
Peak memory 256548 kb
Host smart-44cb166b-acac-41e1-b183-70ff64bbe78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348493963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1348493963
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.810132072
Short name T561
Test name
Test status
Simulation time 30926127737 ps
CPU time 96.2 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:34:29 PM PDT 24
Peak memory 252544 kb
Host smart-1f053ce2-5f30-4726-9f01-cd8b0fae3696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810132072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.810132072
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3659741813
Short name T521
Test name
Test status
Simulation time 330825591 ps
CPU time 8.5 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:33:02 PM PDT 24
Peak memory 233016 kb
Host smart-b9106ccd-49fd-4a12-9b63-8edf69574d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659741813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3659741813
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3862313277
Short name T478
Test name
Test status
Simulation time 104668936793 ps
CPU time 87.56 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:34:22 PM PDT 24
Peak memory 235660 kb
Host smart-f3275f9d-8489-4fd6-a93e-36de264d5280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862313277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3862313277
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1356995206
Short name T69
Test name
Test status
Simulation time 620420743 ps
CPU time 5.49 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:33:00 PM PDT 24
Peak memory 218504 kb
Host smart-724e3e17-bf52-47f5-a8d8-c58eb506caa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356995206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1356995206
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3301951457
Short name T472
Test name
Test status
Simulation time 29599241484 ps
CPU time 23.83 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:33:17 PM PDT 24
Peak memory 240156 kb
Host smart-dcd20c75-eb90-439f-933d-e4d00d122c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301951457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3301951457
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.605207826
Short name T131
Test name
Test status
Simulation time 60150207 ps
CPU time 3.29 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:32:57 PM PDT 24
Peak memory 219116 kb
Host smart-2f3ff8dd-51c2-4f8f-a8d7-71a3c0432c5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605207826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.605207826
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4184404493
Short name T137
Test name
Test status
Simulation time 102460437886 ps
CPU time 223.62 seconds
Started May 09 01:32:54 PM PDT 24
Finished May 09 01:36:39 PM PDT 24
Peak memory 249456 kb
Host smart-4327db7d-434d-4666-bd82-5e49cbe3446f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184404493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4184404493
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1263295583
Short name T318
Test name
Test status
Simulation time 10242882980 ps
CPU time 52.76 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:33:44 PM PDT 24
Peak memory 216256 kb
Host smart-ea52e161-aa44-47aa-9f29-787392ad3648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263295583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1263295583
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2698846947
Short name T369
Test name
Test status
Simulation time 3397364295 ps
CPU time 5.9 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:46 PM PDT 24
Peak memory 216228 kb
Host smart-b6779d6b-10bb-45dd-b73d-e0d52f1a6f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698846947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2698846947
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3405681812
Short name T657
Test name
Test status
Simulation time 245309966 ps
CPU time 3.23 seconds
Started May 09 01:32:37 PM PDT 24
Finished May 09 01:32:42 PM PDT 24
Peak memory 216164 kb
Host smart-ac32c46e-8fdd-444e-b24e-c3701912f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405681812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3405681812
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2530449789
Short name T626
Test name
Test status
Simulation time 60422945 ps
CPU time 0.82 seconds
Started May 09 01:32:39 PM PDT 24
Finished May 09 01:32:41 PM PDT 24
Peak memory 205708 kb
Host smart-675cb652-f314-4f06-a5af-c32669bdb491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530449789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2530449789
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2637101417
Short name T531
Test name
Test status
Simulation time 29408273763 ps
CPU time 22.61 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 226940 kb
Host smart-c217aadf-03fa-45a8-9606-3ce0a9539701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637101417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2637101417
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3774299740
Short name T382
Test name
Test status
Simulation time 26306056 ps
CPU time 0.76 seconds
Started May 09 01:33:05 PM PDT 24
Finished May 09 01:33:07 PM PDT 24
Peak memory 205340 kb
Host smart-ba9fb052-de37-4544-80a1-5f3cbd3f7209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774299740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3774299740
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1276049538
Short name T683
Test name
Test status
Simulation time 1363745603 ps
CPU time 13.14 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:33:06 PM PDT 24
Peak memory 234548 kb
Host smart-a3b2bcb9-9a87-4ed0-9d43-b427e5ab0fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276049538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1276049538
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.590807917
Short name T886
Test name
Test status
Simulation time 60094056 ps
CPU time 0.8 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:32:55 PM PDT 24
Peak memory 205772 kb
Host smart-9378e95c-3cdb-4746-bfae-c9efcddb3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590807917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.590807917
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4293609601
Short name T530
Test name
Test status
Simulation time 12177723 ps
CPU time 0.77 seconds
Started May 09 01:33:04 PM PDT 24
Finished May 09 01:33:06 PM PDT 24
Peak memory 215936 kb
Host smart-26e6c755-c0a8-44fd-bd08-fa01da173dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293609601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4293609601
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2609028482
Short name T726
Test name
Test status
Simulation time 400043018 ps
CPU time 4.61 seconds
Started May 09 01:33:05 PM PDT 24
Finished May 09 01:33:10 PM PDT 24
Peak memory 233724 kb
Host smart-b178a20d-65e2-42c6-85cf-4b8443a85a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609028482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2609028482
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2584904875
Short name T565
Test name
Test status
Simulation time 35281471902 ps
CPU time 295.37 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:38:03 PM PDT 24
Peak memory 249144 kb
Host smart-667574fb-269f-42fe-b97e-af4d7bce085c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584904875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2584904875
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3423014285
Short name T509
Test name
Test status
Simulation time 268414281 ps
CPU time 5.44 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:32:58 PM PDT 24
Peak memory 237420 kb
Host smart-da7e8e41-1631-4db8-b9eb-048286f86986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423014285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3423014285
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3377816913
Short name T655
Test name
Test status
Simulation time 779121838 ps
CPU time 5.94 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:33:00 PM PDT 24
Peak memory 234492 kb
Host smart-e40f91a4-5451-4067-98fe-63e86a73bd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377816913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3377816913
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1026119401
Short name T455
Test name
Test status
Simulation time 2629851209 ps
CPU time 8.88 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:33:03 PM PDT 24
Peak memory 223048 kb
Host smart-c8e085e5-82fd-462d-aff4-350fad6bebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026119401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1026119401
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3462651287
Short name T160
Test name
Test status
Simulation time 4248208736 ps
CPU time 9.13 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:33:03 PM PDT 24
Peak memory 218488 kb
Host smart-8bd9f742-028b-4f3b-b214-6755516e4825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462651287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3462651287
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.915486397
Short name T596
Test name
Test status
Simulation time 112546090362 ps
CPU time 33.2 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:33:27 PM PDT 24
Peak memory 236608 kb
Host smart-834446ce-4ff7-4295-97d7-be4c43f290a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915486397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.915486397
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3990392767
Short name T551
Test name
Test status
Simulation time 1011840295 ps
CPU time 12.8 seconds
Started May 09 01:32:52 PM PDT 24
Finished May 09 01:33:06 PM PDT 24
Peak memory 219708 kb
Host smart-14c6435a-5844-4374-ba48-748ff282bdf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990392767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3990392767
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.324044443
Short name T157
Test name
Test status
Simulation time 196238861 ps
CPU time 1.11 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 206796 kb
Host smart-decef5fe-9544-4a76-8a76-73521d6abef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324044443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.324044443
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.806943501
Short name T465
Test name
Test status
Simulation time 6926006691 ps
CPU time 24.43 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 216276 kb
Host smart-07d7a60d-cfda-4e73-8b69-a221ca191d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806943501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.806943501
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1576960884
Short name T504
Test name
Test status
Simulation time 2371583423 ps
CPU time 7.53 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:32:59 PM PDT 24
Peak memory 216184 kb
Host smart-302c815f-e6ed-4b18-aa2f-8f819f670faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576960884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1576960884
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.219107811
Short name T130
Test name
Test status
Simulation time 517036934 ps
CPU time 4.5 seconds
Started May 09 01:32:50 PM PDT 24
Finished May 09 01:32:56 PM PDT 24
Peak memory 216224 kb
Host smart-5089ef5f-5d03-4d5c-b486-d902a3a4fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219107811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.219107811
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2785638750
Short name T790
Test name
Test status
Simulation time 30099489 ps
CPU time 0.87 seconds
Started May 09 01:32:51 PM PDT 24
Finished May 09 01:32:53 PM PDT 24
Peak memory 205744 kb
Host smart-8c7ab98b-8f56-440e-8c17-29e80b3bc67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785638750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2785638750
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1900326289
Short name T271
Test name
Test status
Simulation time 237263449 ps
CPU time 3.92 seconds
Started May 09 01:32:53 PM PDT 24
Finished May 09 01:32:58 PM PDT 24
Peak memory 218692 kb
Host smart-e81ea569-c878-4fd0-bc01-dbb0bce99465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900326289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1900326289
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.514775857
Short name T627
Test name
Test status
Simulation time 11710576 ps
CPU time 0.69 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 204800 kb
Host smart-c37a7cd5-4adc-4486-be4e-11a17b35a053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514775857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.514775857
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2022052853
Short name T645
Test name
Test status
Simulation time 121880063 ps
CPU time 2.43 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 221516 kb
Host smart-5768b7db-22f2-4cfd-b9f6-092b7a6676d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022052853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2022052853
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4070988724
Short name T379
Test name
Test status
Simulation time 53647414 ps
CPU time 0.8 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 206440 kb
Host smart-fd0150ca-1c70-4e1d-a274-2ee1916a8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070988724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4070988724
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2645082594
Short name T26
Test name
Test status
Simulation time 10624764626 ps
CPU time 113.34 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:35:01 PM PDT 24
Peak memory 252812 kb
Host smart-ec0f1167-e003-494d-bfcc-a89f969dbbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645082594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2645082594
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4284881298
Short name T764
Test name
Test status
Simulation time 53273958432 ps
CPU time 176.65 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:36:08 PM PDT 24
Peak memory 249048 kb
Host smart-56d8faab-4aa1-4d35-8ead-ed5b19e90360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284881298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4284881298
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2777069311
Short name T293
Test name
Test status
Simulation time 1323836476 ps
CPU time 23.1 seconds
Started May 09 01:33:09 PM PDT 24
Finished May 09 01:33:33 PM PDT 24
Peak memory 220960 kb
Host smart-3a032985-18d8-4226-a89d-290d7f4a6ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777069311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2777069311
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2915772306
Short name T896
Test name
Test status
Simulation time 1420774613 ps
CPU time 24.3 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:33:31 PM PDT 24
Peak memory 224464 kb
Host smart-48abf1e5-4809-46b2-86ba-9e8acb239019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915772306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2915772306
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2087860567
Short name T495
Test name
Test status
Simulation time 1109371446 ps
CPU time 16.36 seconds
Started May 09 01:33:05 PM PDT 24
Finished May 09 01:33:22 PM PDT 24
Peak memory 218532 kb
Host smart-af56550c-45eb-4f2a-97e4-9cefe7de41e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087860567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2087860567
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.638568541
Short name T12
Test name
Test status
Simulation time 8123895988 ps
CPU time 22.25 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:33:30 PM PDT 24
Peak memory 238116 kb
Host smart-1072b3cd-53a6-4d99-8cfc-d3e4ccba82c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638568541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.638568541
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3508941322
Short name T950
Test name
Test status
Simulation time 1873484753 ps
CPU time 14.35 seconds
Started May 09 01:33:04 PM PDT 24
Finished May 09 01:33:19 PM PDT 24
Peak memory 233244 kb
Host smart-11811626-2177-419c-9d87-02eefacc4e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508941322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3508941322
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3103156529
Short name T207
Test name
Test status
Simulation time 750324116 ps
CPU time 6.61 seconds
Started May 09 01:33:02 PM PDT 24
Finished May 09 01:33:10 PM PDT 24
Peak memory 226540 kb
Host smart-10bd0e3d-7447-4ace-aa3b-71234fcb6ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103156529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3103156529
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3281996903
Short name T891
Test name
Test status
Simulation time 7213644851 ps
CPU time 7.03 seconds
Started May 09 01:33:15 PM PDT 24
Finished May 09 01:33:24 PM PDT 24
Peak memory 218396 kb
Host smart-31bd8583-ce24-4f9b-99bf-1a04ff6d4848
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3281996903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3281996903
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2207846129
Short name T41
Test name
Test status
Simulation time 48737681455 ps
CPU time 253.16 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:37:21 PM PDT 24
Peak memory 250612 kb
Host smart-f90027fb-848f-4018-ab37-e41f337c38ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207846129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2207846129
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2441247174
Short name T578
Test name
Test status
Simulation time 2064869298 ps
CPU time 11.66 seconds
Started May 09 01:33:05 PM PDT 24
Finished May 09 01:33:17 PM PDT 24
Peak memory 216312 kb
Host smart-01633b96-f8b8-4620-b540-dd82affcdd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441247174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2441247174
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2956604863
Short name T639
Test name
Test status
Simulation time 3312334991 ps
CPU time 4.38 seconds
Started May 09 01:33:09 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 216216 kb
Host smart-9615772d-088b-4063-8a33-dcd161b89820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956604863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2956604863
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1938686793
Short name T432
Test name
Test status
Simulation time 151226399 ps
CPU time 1.37 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:13 PM PDT 24
Peak memory 216036 kb
Host smart-7a0ce123-662d-460e-b686-d049fb69f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938686793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1938686793
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.443213780
Short name T576
Test name
Test status
Simulation time 31440317 ps
CPU time 0.83 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 205644 kb
Host smart-0d685ca1-0fc6-4166-b00e-63302d17e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443213780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.443213780
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2258128447
Short name T920
Test name
Test status
Simulation time 644434262 ps
CPU time 8.11 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 218388 kb
Host smart-d06d3346-8e85-45b2-9d21-05316c2fc50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258128447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2258128447
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3908596655
Short name T500
Test name
Test status
Simulation time 12694631 ps
CPU time 0.71 seconds
Started May 09 01:33:05 PM PDT 24
Finished May 09 01:33:06 PM PDT 24
Peak memory 204776 kb
Host smart-66cb929e-bcdc-46ba-aec1-231ef437389a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908596655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3908596655
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1814042177
Short name T616
Test name
Test status
Simulation time 198703506 ps
CPU time 2.45 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 218516 kb
Host smart-b9152474-d94b-42ef-a6c4-878094616148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814042177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1814042177
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.976811215
Short name T819
Test name
Test status
Simulation time 15898270 ps
CPU time 0.78 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 206508 kb
Host smart-c4938634-8ccb-4f1e-be54-26adba3025f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976811215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.976811215
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4094554018
Short name T165
Test name
Test status
Simulation time 50093981704 ps
CPU time 169.14 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:36:02 PM PDT 24
Peak memory 239384 kb
Host smart-f4f229f3-40c2-428a-9219-c382d8cf14fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094554018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4094554018
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3539852211
Short name T740
Test name
Test status
Simulation time 969071771 ps
CPU time 15.7 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:33:28 PM PDT 24
Peak memory 223360 kb
Host smart-24168d32-ff4f-4a79-81e8-83f7ac751e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539852211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3539852211
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2426154267
Short name T943
Test name
Test status
Simulation time 29335471125 ps
CPU time 272.75 seconds
Started May 09 01:33:15 PM PDT 24
Finished May 09 01:37:49 PM PDT 24
Peak memory 256680 kb
Host smart-148c0da8-fefa-47c7-9330-ad90b961bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426154267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2426154267
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2582568163
Short name T604
Test name
Test status
Simulation time 6612763104 ps
CPU time 45.81 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:33:58 PM PDT 24
Peak memory 249032 kb
Host smart-bbe5cbf3-0743-448e-8200-626ddc15fd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582568163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2582568163
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3644280262
Short name T70
Test name
Test status
Simulation time 548505658 ps
CPU time 7.46 seconds
Started May 09 01:33:04 PM PDT 24
Finished May 09 01:33:12 PM PDT 24
Peak memory 235212 kb
Host smart-358cee6b-77e3-4bdb-9de1-e61e66d60e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644280262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3644280262
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4171174075
Short name T468
Test name
Test status
Simulation time 729716150 ps
CPU time 5.18 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:13 PM PDT 24
Peak memory 232500 kb
Host smart-c8fe733f-4af6-43ef-aacb-cce12dfd4fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171174075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4171174075
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.681463808
Short name T866
Test name
Test status
Simulation time 11639123998 ps
CPU time 9.87 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:33:17 PM PDT 24
Peak memory 227672 kb
Host smart-3f5f9f1d-00bd-4f12-9301-05888b83af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681463808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.681463808
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.703722489
Short name T924
Test name
Test status
Simulation time 8030650448 ps
CPU time 25.56 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:33 PM PDT 24
Peak memory 239868 kb
Host smart-dbfcdf2e-9c34-47a3-88d5-a6c2e6fc9d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703722489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.703722489
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3424027867
Short name T818
Test name
Test status
Simulation time 1301941778 ps
CPU time 13.29 seconds
Started May 09 01:33:14 PM PDT 24
Finished May 09 01:33:28 PM PDT 24
Peak memory 222180 kb
Host smart-48f0e030-c697-426d-b488-b1411049a0c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3424027867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3424027867
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3029626171
Short name T711
Test name
Test status
Simulation time 26622552185 ps
CPU time 88.3 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:34:40 PM PDT 24
Peak memory 249544 kb
Host smart-e5b70ec6-2dad-4e6b-a125-a63f4fd35f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029626171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3029626171
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2336717297
Short name T888
Test name
Test status
Simulation time 18050607344 ps
CPU time 46.44 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:33:54 PM PDT 24
Peak memory 216304 kb
Host smart-1770f4db-bbc7-48b9-8b44-b6cfe904d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336717297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2336717297
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4277071824
Short name T858
Test name
Test status
Simulation time 716587391 ps
CPU time 1.75 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:13 PM PDT 24
Peak memory 206772 kb
Host smart-d758324e-e2ff-4590-aa4b-326c0ccc9ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277071824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4277071824
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2460322651
Short name T570
Test name
Test status
Simulation time 350268497 ps
CPU time 5.97 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:33:19 PM PDT 24
Peak memory 216300 kb
Host smart-e8def18b-3fd9-4ce4-860a-48a074ff1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460322651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2460322651
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1828482831
Short name T375
Test name
Test status
Simulation time 88178447 ps
CPU time 0.91 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:33:14 PM PDT 24
Peak memory 205756 kb
Host smart-9e6bb203-4381-4859-98f2-9b64b31af3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828482831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1828482831
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.445681518
Short name T418
Test name
Test status
Simulation time 3422206203 ps
CPU time 11.88 seconds
Started May 09 01:33:05 PM PDT 24
Finished May 09 01:33:18 PM PDT 24
Peak memory 220008 kb
Host smart-9b938973-469d-4ddb-9592-d0d34e39226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445681518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.445681518
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.783489823
Short name T376
Test name
Test status
Simulation time 14773829 ps
CPU time 0.71 seconds
Started May 09 01:33:13 PM PDT 24
Finished May 09 01:33:15 PM PDT 24
Peak memory 204828 kb
Host smart-297551fb-81fc-4a43-a8c2-55d4ed5291d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783489823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.783489823
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3757224799
Short name T837
Test name
Test status
Simulation time 1946948290 ps
CPU time 5.07 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:33:12 PM PDT 24
Peak memory 218628 kb
Host smart-795c2260-9633-49c0-acc9-bd9871daa64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757224799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3757224799
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.994975079
Short name T519
Test name
Test status
Simulation time 65374982 ps
CPU time 0.78 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:08 PM PDT 24
Peak memory 206792 kb
Host smart-0cbd8be4-77f7-4b72-875c-7c51cc1b39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994975079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.994975079
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3873515386
Short name T899
Test name
Test status
Simulation time 23767907 ps
CPU time 0.76 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:12 PM PDT 24
Peak memory 215864 kb
Host smart-28ac374c-2180-4278-bc9c-558a309a9e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873515386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3873515386
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1205834219
Short name T4
Test name
Test status
Simulation time 29312587044 ps
CPU time 289.33 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:38:01 PM PDT 24
Peak memory 255860 kb
Host smart-a2f916db-96d3-4365-87ac-b8295c8a3338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205834219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1205834219
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2700294504
Short name T317
Test name
Test status
Simulation time 62556137176 ps
CPU time 93.87 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:34:45 PM PDT 24
Peak memory 236044 kb
Host smart-cb87c73c-9a44-413a-b495-bbb22e212a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700294504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2700294504
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1071288714
Short name T599
Test name
Test status
Simulation time 993748399 ps
CPU time 13.15 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:33:25 PM PDT 24
Peak memory 224480 kb
Host smart-2aa2787f-626a-4d7c-8281-2da719bdabf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071288714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1071288714
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1470193948
Short name T89
Test name
Test status
Simulation time 2217417449 ps
CPU time 5.94 seconds
Started May 09 01:33:13 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 232720 kb
Host smart-ac15e01e-600d-4eb7-8de0-fa2591ef4ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470193948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1470193948
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.995073393
Short name T309
Test name
Test status
Simulation time 18976292946 ps
CPU time 171.62 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:36:02 PM PDT 24
Peak memory 246196 kb
Host smart-c955f23a-808b-4a24-9eb0-caa4b4ce1682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995073393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.995073393
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1306808431
Short name T786
Test name
Test status
Simulation time 2606485496 ps
CPU time 7.51 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 218412 kb
Host smart-ac9a010d-dbf4-4df4-8ed4-a807851eb0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306808431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1306808431
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.648847955
Short name T216
Test name
Test status
Simulation time 194882075 ps
CPU time 3.81 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:33:17 PM PDT 24
Peak memory 233568 kb
Host smart-c47223c9-9a04-4e73-88f6-b38a7173cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648847955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.648847955
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1244875340
Short name T428
Test name
Test status
Simulation time 4126420721 ps
CPU time 12.3 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:33:25 PM PDT 24
Peak memory 218764 kb
Host smart-0a4aa013-645a-4d14-84a0-1737d07650df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1244875340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1244875340
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1730298863
Short name T77
Test name
Test status
Simulation time 26711658554 ps
CPU time 153.56 seconds
Started May 09 01:33:12 PM PDT 24
Finished May 09 01:35:47 PM PDT 24
Peak memory 271608 kb
Host smart-29d856e6-d243-4d10-959e-fd7d3957f006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730298863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1730298863
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.697337377
Short name T480
Test name
Test status
Simulation time 2732629762 ps
CPU time 18.82 seconds
Started May 09 01:33:09 PM PDT 24
Finished May 09 01:33:29 PM PDT 24
Peak memory 216180 kb
Host smart-21e46937-725a-4fbe-accd-bc1abfad3ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697337377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.697337377
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3704092184
Short name T449
Test name
Test status
Simulation time 388540287 ps
CPU time 1.91 seconds
Started May 09 01:33:06 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 207508 kb
Host smart-260d3f45-6219-4b77-93ec-67b90ed83c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704092184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3704092184
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.63978275
Short name T404
Test name
Test status
Simulation time 19138964 ps
CPU time 0.91 seconds
Started May 09 01:33:09 PM PDT 24
Finished May 09 01:33:11 PM PDT 24
Peak memory 206972 kb
Host smart-009ef997-2e36-42a0-9354-0adb25f2326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63978275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.63978275
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2253921178
Short name T927
Test name
Test status
Simulation time 16995326 ps
CPU time 0.72 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 205656 kb
Host smart-b08b6e67-ba68-4cf4-8af9-34859c777fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253921178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2253921178
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4004231850
Short name T797
Test name
Test status
Simulation time 3259367395 ps
CPU time 14.92 seconds
Started May 09 01:33:04 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 228468 kb
Host smart-f6a200b2-8938-4e4a-a227-c39c8837e4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004231850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4004231850
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3947247406
Short name T961
Test name
Test status
Simulation time 40923506 ps
CPU time 0.73 seconds
Started May 09 01:30:02 PM PDT 24
Finished May 09 01:30:04 PM PDT 24
Peak memory 204792 kb
Host smart-8b20f62d-eb06-4c75-930a-353ac6d6f08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947247406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
947247406
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.989614505
Short name T100
Test name
Test status
Simulation time 92870947 ps
CPU time 2.24 seconds
Started May 09 01:29:57 PM PDT 24
Finished May 09 01:30:00 PM PDT 24
Peak memory 218472 kb
Host smart-c9d8137f-0a63-45b0-a37b-30db960347ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989614505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.989614505
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1942213834
Short name T340
Test name
Test status
Simulation time 19499907 ps
CPU time 0.76 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:29:49 PM PDT 24
Peak memory 206828 kb
Host smart-b28f3320-0ed1-4d04-8c50-6765c18e61a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942213834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1942213834
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4246724569
Short name T294
Test name
Test status
Simulation time 4708002269 ps
CPU time 33.27 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:30:29 PM PDT 24
Peak memory 240840 kb
Host smart-6f88b917-f772-4ce5-b8e9-c83cc2d877f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246724569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4246724569
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2239059331
Short name T239
Test name
Test status
Simulation time 148262755603 ps
CPU time 348.78 seconds
Started May 09 01:30:01 PM PDT 24
Finished May 09 01:35:51 PM PDT 24
Peak memory 260224 kb
Host smart-226a3e02-3018-4bdb-aa82-9f4ad1ce6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239059331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2239059331
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1627320251
Short name T248
Test name
Test status
Simulation time 16328472665 ps
CPU time 86.96 seconds
Started May 09 01:29:56 PM PDT 24
Finished May 09 01:31:24 PM PDT 24
Peak memory 249144 kb
Host smart-ed136dbd-1fe4-4bee-aa43-4c9f82020e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627320251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1627320251
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3354886628
Short name T450
Test name
Test status
Simulation time 406751254 ps
CPU time 3.4 seconds
Started May 09 01:30:00 PM PDT 24
Finished May 09 01:30:05 PM PDT 24
Peak memory 232620 kb
Host smart-eab0b2a2-9d4d-4d06-8cce-d1a941f8c412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354886628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3354886628
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.58764097
Short name T304
Test name
Test status
Simulation time 2247697210 ps
CPU time 15.95 seconds
Started May 09 01:29:49 PM PDT 24
Finished May 09 01:30:06 PM PDT 24
Peak memory 234088 kb
Host smart-a4fde0b5-4cdf-4f4a-bdf3-7c36ce42f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58764097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.58764097
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.638855712
Short name T443
Test name
Test status
Simulation time 136892088 ps
CPU time 2.46 seconds
Started May 09 01:30:01 PM PDT 24
Finished May 09 01:30:04 PM PDT 24
Peak memory 232640 kb
Host smart-374874bf-0e66-4ca5-8472-3d7acd61b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638855712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.638855712
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1060301695
Short name T202
Test name
Test status
Simulation time 440247701 ps
CPU time 4.06 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:30:00 PM PDT 24
Peak memory 235024 kb
Host smart-b5750e7e-ddf1-4be9-b706-0c4fe29fe5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060301695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1060301695
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.656558823
Short name T278
Test name
Test status
Simulation time 2106639876 ps
CPU time 8.19 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:30:03 PM PDT 24
Peak memory 240496 kb
Host smart-8849527c-7079-4734-8b91-d0ba8c2a5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656558823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.656558823
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2172402316
Short name T354
Test name
Test status
Simulation time 384841069 ps
CPU time 4.36 seconds
Started May 09 01:30:00 PM PDT 24
Finished May 09 01:30:06 PM PDT 24
Peak memory 222964 kb
Host smart-b1445bd5-e6f4-419f-bc85-28df46a1cac8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172402316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2172402316
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3642608176
Short name T62
Test name
Test status
Simulation time 289469759 ps
CPU time 0.98 seconds
Started May 09 01:29:52 PM PDT 24
Finished May 09 01:29:54 PM PDT 24
Peak memory 234592 kb
Host smart-7c81307a-50df-4027-a273-e6836b1ff9ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642608176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3642608176
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2901881229
Short name T628
Test name
Test status
Simulation time 61038395 ps
CPU time 1.19 seconds
Started May 09 01:29:59 PM PDT 24
Finished May 09 01:30:01 PM PDT 24
Peak memory 207028 kb
Host smart-e08a0cfb-aeaf-467e-a01d-eb9338a44cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901881229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2901881229
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.343071492
Short name T732
Test name
Test status
Simulation time 2036359793 ps
CPU time 15.18 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:30:04 PM PDT 24
Peak memory 216252 kb
Host smart-0ef397a8-9c12-43e9-919b-ea1943620e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343071492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.343071492
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.426036161
Short name T647
Test name
Test status
Simulation time 699693494 ps
CPU time 5.6 seconds
Started May 09 01:29:48 PM PDT 24
Finished May 09 01:29:55 PM PDT 24
Peak memory 216100 kb
Host smart-a0b9ebba-26c9-4bbb-a317-73e126732408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426036161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.426036161
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3027034256
Short name T735
Test name
Test status
Simulation time 463905257 ps
CPU time 2.01 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:29:58 PM PDT 24
Peak memory 215996 kb
Host smart-afa6711d-23b1-41f2-a4e1-9bb0b5a5c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027034256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3027034256
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3176617424
Short name T579
Test name
Test status
Simulation time 63738048 ps
CPU time 0.89 seconds
Started May 09 01:29:43 PM PDT 24
Finished May 09 01:29:44 PM PDT 24
Peak memory 205756 kb
Host smart-273d5059-d107-4dfa-b378-4165db9cba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176617424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3176617424
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3158348164
Short name T280
Test name
Test status
Simulation time 2409560189 ps
CPU time 5.87 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:05 PM PDT 24
Peak memory 219292 kb
Host smart-f61626ca-6ef3-4185-96da-523349d70859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158348164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3158348164
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.126935366
Short name T415
Test name
Test status
Simulation time 37611785 ps
CPU time 0.71 seconds
Started May 09 01:33:17 PM PDT 24
Finished May 09 01:33:19 PM PDT 24
Peak memory 205600 kb
Host smart-31d1d7cd-8a22-480b-ae4e-0cff339e93b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126935366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.126935366
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3357694874
Short name T709
Test name
Test status
Simulation time 2619575972 ps
CPU time 8.47 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 234748 kb
Host smart-c3a0276b-9249-49e8-884d-bb3aface5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357694874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3357694874
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.196804860
Short name T914
Test name
Test status
Simulation time 90899078 ps
CPU time 0.76 seconds
Started May 09 01:33:11 PM PDT 24
Finished May 09 01:33:13 PM PDT 24
Peak memory 206552 kb
Host smart-db77f83c-7dd0-4ca3-8c17-3874b61d27b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196804860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.196804860
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3181383480
Short name T357
Test name
Test status
Simulation time 1063568728 ps
CPU time 4.16 seconds
Started May 09 01:33:14 PM PDT 24
Finished May 09 01:33:19 PM PDT 24
Peak memory 224408 kb
Host smart-370d6708-45a8-453e-b224-b6b97a144ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181383480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3181383480
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1480798788
Short name T547
Test name
Test status
Simulation time 1661557057 ps
CPU time 47.69 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:34:08 PM PDT 24
Peak memory 249184 kb
Host smart-c458a4ea-5f90-4ea2-8744-9828ca84ee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480798788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1480798788
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.529431297
Short name T948
Test name
Test status
Simulation time 1563230420 ps
CPU time 19.18 seconds
Started May 09 01:33:20 PM PDT 24
Finished May 09 01:33:40 PM PDT 24
Peak memory 217172 kb
Host smart-27fa4fe5-ce18-4bb4-96e7-26805d961a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529431297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.529431297
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3713373356
Short name T313
Test name
Test status
Simulation time 126042606 ps
CPU time 4.08 seconds
Started May 09 01:33:15 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 232584 kb
Host smart-b8be8451-943e-4251-8eb9-fe62ab9cbde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713373356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3713373356
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1410169782
Short name T679
Test name
Test status
Simulation time 8286603571 ps
CPU time 8.22 seconds
Started May 09 01:33:13 PM PDT 24
Finished May 09 01:33:22 PM PDT 24
Peak memory 234020 kb
Host smart-d652c6d6-1b9c-40ea-b798-0779c27d051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410169782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1410169782
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1691223902
Short name T944
Test name
Test status
Simulation time 21063852217 ps
CPU time 77.74 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:34:26 PM PDT 24
Peak memory 224248 kb
Host smart-203563a6-b5bf-4a72-a63b-bf2cf087c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691223902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1691223902
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3458795796
Short name T171
Test name
Test status
Simulation time 1041264507 ps
CPU time 4.01 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 233512 kb
Host smart-9de1aa60-8561-4aa6-a711-1d88bf817bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458795796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3458795796
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1763008406
Short name T814
Test name
Test status
Simulation time 545597206 ps
CPU time 4.03 seconds
Started May 09 01:33:10 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 233400 kb
Host smart-4a81c477-8483-4b3c-b28e-484f2e056162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763008406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1763008406
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1404693903
Short name T879
Test name
Test status
Simulation time 1359033299 ps
CPU time 10.7 seconds
Started May 09 01:33:14 PM PDT 24
Finished May 09 01:33:26 PM PDT 24
Peak memory 221396 kb
Host smart-5dcaa740-aefa-4dcf-b257-cb8bfceb0df8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1404693903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1404693903
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2104120412
Short name T42
Test name
Test status
Simulation time 7599508975 ps
CPU time 112.05 seconds
Started May 09 01:33:27 PM PDT 24
Finished May 09 01:35:20 PM PDT 24
Peak memory 252548 kb
Host smart-aaddbef4-74f4-4921-84d0-fd1848fad15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104120412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2104120412
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.455256331
Short name T930
Test name
Test status
Simulation time 227520579 ps
CPU time 2.23 seconds
Started May 09 01:33:13 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 216384 kb
Host smart-2e6097b5-1853-4289-978c-39aa3a023836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455256331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.455256331
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2186136309
Short name T812
Test name
Test status
Simulation time 7559176976 ps
CPU time 9.17 seconds
Started May 09 01:33:15 PM PDT 24
Finished May 09 01:33:26 PM PDT 24
Peak memory 216156 kb
Host smart-4ab17e0a-971f-42a5-8b65-87fd5fa18030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186136309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2186136309
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3657869217
Short name T958
Test name
Test status
Simulation time 67955237 ps
CPU time 1.07 seconds
Started May 09 01:33:07 PM PDT 24
Finished May 09 01:33:09 PM PDT 24
Peak memory 216096 kb
Host smart-73c64dc9-d706-4b3a-84cd-af7f067f49ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657869217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3657869217
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1704957035
Short name T389
Test name
Test status
Simulation time 54674646 ps
CPU time 0.89 seconds
Started May 09 01:33:14 PM PDT 24
Finished May 09 01:33:16 PM PDT 24
Peak memory 205724 kb
Host smart-cb92bed9-4bfa-487a-9778-2c1ac50736dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704957035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1704957035
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2791524747
Short name T204
Test name
Test status
Simulation time 3256554929 ps
CPU time 13.32 seconds
Started May 09 01:33:13 PM PDT 24
Finished May 09 01:33:27 PM PDT 24
Peak memory 227220 kb
Host smart-a1c19b5d-a5a8-4ac1-afbd-7856057d7927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791524747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2791524747
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1207952711
Short name T367
Test name
Test status
Simulation time 47652356 ps
CPU time 0.72 seconds
Started May 09 01:33:19 PM PDT 24
Finished May 09 01:33:21 PM PDT 24
Peak memory 204780 kb
Host smart-3955dd62-9545-4849-8878-05ebd9c6444d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207952711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1207952711
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.653544851
Short name T178
Test name
Test status
Simulation time 1511859201 ps
CPU time 18.26 seconds
Started May 09 01:33:23 PM PDT 24
Finished May 09 01:33:42 PM PDT 24
Peak memory 219632 kb
Host smart-db743176-c31d-40b9-aa03-73d98b094009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653544851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.653544851
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.281341515
Short name T583
Test name
Test status
Simulation time 17604109 ps
CPU time 0.8 seconds
Started May 09 01:33:22 PM PDT 24
Finished May 09 01:33:24 PM PDT 24
Peak memory 206468 kb
Host smart-a487a4a5-5f74-4c64-b8c2-fd632584021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281341515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.281341515
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.188498847
Short name T393
Test name
Test status
Simulation time 20118997 ps
CPU time 0.8 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 215876 kb
Host smart-8870014d-96da-4c4b-9d41-afeac4aa2db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188498847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.188498847
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.751244774
Short name T754
Test name
Test status
Simulation time 11372168186 ps
CPU time 43.58 seconds
Started May 09 01:33:17 PM PDT 24
Finished May 09 01:34:02 PM PDT 24
Peak memory 250076 kb
Host smart-4dc203af-696e-450d-a288-e6f00a123ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751244774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.751244774
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1054541226
Short name T640
Test name
Test status
Simulation time 645681416 ps
CPU time 12.27 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:35 PM PDT 24
Peak memory 224384 kb
Host smart-de15f801-c603-4967-9bd5-11586eba2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054541226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1054541226
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2721784984
Short name T275
Test name
Test status
Simulation time 1201265936 ps
CPU time 4.66 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:27 PM PDT 24
Peak memory 224328 kb
Host smart-7864feee-881a-4253-be92-80522e79f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721784984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2721784984
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3674039019
Short name T600
Test name
Test status
Simulation time 1169798639 ps
CPU time 10.25 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:32 PM PDT 24
Peak memory 220340 kb
Host smart-01ef1d4f-869f-4dd9-bfc5-35226f58f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674039019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3674039019
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3689227146
Short name T787
Test name
Test status
Simulation time 1083358634 ps
CPU time 6.13 seconds
Started May 09 01:33:22 PM PDT 24
Finished May 09 01:33:29 PM PDT 24
Peak memory 216680 kb
Host smart-46c303dc-8181-4a1e-867f-0cc31cfbe183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689227146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3689227146
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1588193493
Short name T550
Test name
Test status
Simulation time 1779566821 ps
CPU time 12.69 seconds
Started May 09 01:33:17 PM PDT 24
Finished May 09 01:33:30 PM PDT 24
Peak memory 238604 kb
Host smart-209f13c5-e6cc-4043-a477-ba3148d576e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588193493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1588193493
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3922528612
Short name T875
Test name
Test status
Simulation time 292678933 ps
CPU time 3.44 seconds
Started May 09 01:33:22 PM PDT 24
Finished May 09 01:33:26 PM PDT 24
Peak memory 219080 kb
Host smart-5596872e-9fd6-412a-817e-e412b1cf6ee1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3922528612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3922528612
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3571765481
Short name T74
Test name
Test status
Simulation time 92166754609 ps
CPU time 439.22 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:40:41 PM PDT 24
Peak memory 251960 kb
Host smart-68789bbf-1f0b-4600-ae28-b0b176a11ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571765481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3571765481
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.103939993
Short name T792
Test name
Test status
Simulation time 2785490377 ps
CPU time 17.15 seconds
Started May 09 01:33:15 PM PDT 24
Finished May 09 01:33:33 PM PDT 24
Peak memory 216316 kb
Host smart-ebccd71e-79de-4242-a3bb-773887b55c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103939993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.103939993
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3147636823
Short name T941
Test name
Test status
Simulation time 1788863957 ps
CPU time 3.3 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:33:23 PM PDT 24
Peak memory 216188 kb
Host smart-d7c6b683-5353-4827-9aa9-a8bfe5304c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147636823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3147636823
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3184666372
Short name T442
Test name
Test status
Simulation time 70568644 ps
CPU time 0.8 seconds
Started May 09 01:33:17 PM PDT 24
Finished May 09 01:33:19 PM PDT 24
Peak memory 205788 kb
Host smart-7e5aa556-bc89-4d2f-a267-988a73fd2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184666372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3184666372
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2910898946
Short name T889
Test name
Test status
Simulation time 65187145 ps
CPU time 0.84 seconds
Started May 09 01:33:26 PM PDT 24
Finished May 09 01:33:28 PM PDT 24
Peak memory 205552 kb
Host smart-13781148-ef6c-4315-8f85-566fe14a106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910898946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2910898946
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1814260019
Short name T217
Test name
Test status
Simulation time 4028656744 ps
CPU time 13.02 seconds
Started May 09 01:33:19 PM PDT 24
Finished May 09 01:33:34 PM PDT 24
Peak memory 234732 kb
Host smart-0e2b7ac6-0206-4e73-9aa3-cd70030a7553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814260019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1814260019
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2115027112
Short name T852
Test name
Test status
Simulation time 15424191 ps
CPU time 0.73 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:33:21 PM PDT 24
Peak memory 204716 kb
Host smart-548fb8c5-962b-4f3e-8fa5-6c63c27c06e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115027112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2115027112
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2074755382
Short name T728
Test name
Test status
Simulation time 1165035405 ps
CPU time 9.46 seconds
Started May 09 03:33:35 PM PDT 24
Finished May 09 03:33:46 PM PDT 24
Peak memory 218864 kb
Host smart-27748089-6699-4182-b08b-1820ab1746f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074755382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2074755382
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3641162351
Short name T761
Test name
Test status
Simulation time 42166121 ps
CPU time 0.79 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:23 PM PDT 24
Peak memory 206556 kb
Host smart-79ba5bf1-4f1e-4641-893c-020b12e05c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641162351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3641162351
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3854957644
Short name T897
Test name
Test status
Simulation time 5968998615 ps
CPU time 44.2 seconds
Started May 09 03:01:42 PM PDT 24
Finished May 09 03:02:29 PM PDT 24
Peak memory 249128 kb
Host smart-0bec29f4-ab66-4f46-9bd1-60764dcd7300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854957644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3854957644
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2011197685
Short name T84
Test name
Test status
Simulation time 9642401694 ps
CPU time 73.25 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:26:24 PM PDT 24
Peak memory 249420 kb
Host smart-a132dd4f-89bd-4f55-9db8-0f183630bdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011197685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2011197685
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2790858142
Short name T243
Test name
Test status
Simulation time 175918485532 ps
CPU time 142.07 seconds
Started May 09 01:33:20 PM PDT 24
Finished May 09 01:35:43 PM PDT 24
Peak memory 240952 kb
Host smart-f04d58a8-efd4-4b8b-8442-4581267b1f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790858142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2790858142
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3467540139
Short name T907
Test name
Test status
Simulation time 418204914 ps
CPU time 6.13 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:29 PM PDT 24
Peak memory 233380 kb
Host smart-4873f7cb-0470-4f45-9fa0-81d4c8f32481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467540139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3467540139
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2491700102
Short name T92
Test name
Test status
Simulation time 801367702 ps
CPU time 14.05 seconds
Started May 09 01:33:17 PM PDT 24
Finished May 09 01:33:32 PM PDT 24
Peak memory 233904 kb
Host smart-3881c428-9dd6-4aaa-ab26-67e33463450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491700102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2491700102
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3836154400
Short name T66
Test name
Test status
Simulation time 43408503267 ps
CPU time 16.44 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:33:36 PM PDT 24
Peak memory 218804 kb
Host smart-1238656b-86f0-4d54-8ce9-9c3b033e89cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836154400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3836154400
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3284267567
Short name T414
Test name
Test status
Simulation time 375688870 ps
CPU time 2.11 seconds
Started May 09 01:33:20 PM PDT 24
Finished May 09 01:33:23 PM PDT 24
Peak memory 216036 kb
Host smart-2b717b76-7883-43b7-a41c-20969d25e217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284267567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3284267567
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2593052436
Short name T456
Test name
Test status
Simulation time 8344033682 ps
CPU time 24.22 seconds
Started May 09 03:05:32 PM PDT 24
Finished May 09 03:05:58 PM PDT 24
Peak memory 219172 kb
Host smart-60f910b4-fe2f-4d2c-9be9-845d83db4e5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2593052436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2593052436
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3479573736
Short name T234
Test name
Test status
Simulation time 123946254335 ps
CPU time 229.36 seconds
Started May 09 01:33:25 PM PDT 24
Finished May 09 01:37:15 PM PDT 24
Peak memory 247644 kb
Host smart-01394117-4411-431d-aceb-c457318522e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479573736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3479573736
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1161401821
Short name T347
Test name
Test status
Simulation time 1552972513 ps
CPU time 1.75 seconds
Started May 09 01:33:20 PM PDT 24
Finished May 09 01:33:23 PM PDT 24
Peak memory 216176 kb
Host smart-f4732882-fc49-4fa3-b99c-7b3cc7990158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161401821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1161401821
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3241823162
Short name T445
Test name
Test status
Simulation time 7017862528 ps
CPU time 18.53 seconds
Started May 09 01:33:20 PM PDT 24
Finished May 09 01:33:39 PM PDT 24
Peak memory 216184 kb
Host smart-1279ae20-6f86-403d-85f6-be63e88f9b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241823162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3241823162
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2802476438
Short name T34
Test name
Test status
Simulation time 701533312 ps
CPU time 2.25 seconds
Started May 09 01:33:16 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 216372 kb
Host smart-1fd6aa27-85ec-45d5-a5c2-9d2ec47f79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802476438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2802476438
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.708041982
Short name T17
Test name
Test status
Simulation time 19484068 ps
CPU time 0.7 seconds
Started May 09 01:33:19 PM PDT 24
Finished May 09 01:33:21 PM PDT 24
Peak memory 205740 kb
Host smart-5f5543a3-9f26-4c4e-8172-7122f0393e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708041982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.708041982
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3932894929
Short name T777
Test name
Test status
Simulation time 15511622820 ps
CPU time 12.38 seconds
Started May 09 03:35:14 PM PDT 24
Finished May 09 03:35:28 PM PDT 24
Peak memory 224480 kb
Host smart-f368ae08-a223-4b85-9186-6d808b72e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932894929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3932894929
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.337310873
Short name T684
Test name
Test status
Simulation time 13365936 ps
CPU time 0.77 seconds
Started May 09 01:33:24 PM PDT 24
Finished May 09 01:33:26 PM PDT 24
Peak memory 205316 kb
Host smart-abdb830c-71ad-415f-b5b9-d6de30472ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337310873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.337310873
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1394667631
Short name T558
Test name
Test status
Simulation time 2513910919 ps
CPU time 20.36 seconds
Started May 09 01:33:15 PM PDT 24
Finished May 09 01:33:36 PM PDT 24
Peak memory 219856 kb
Host smart-ee3a8d9f-7fd1-4322-9eba-a526a787e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394667631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1394667631
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2828642337
Short name T778
Test name
Test status
Simulation time 15064283 ps
CPU time 0.75 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:33:20 PM PDT 24
Peak memory 205420 kb
Host smart-8c36dbae-9fa5-484b-a9a3-ad6db75496e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828642337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2828642337
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3953026888
Short name T256
Test name
Test status
Simulation time 127219079424 ps
CPU time 236.33 seconds
Started May 09 01:33:24 PM PDT 24
Finished May 09 01:37:22 PM PDT 24
Peak memory 250072 kb
Host smart-43f85ca7-8b5f-4e44-8b18-f21c9c140efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953026888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3953026888
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1204443931
Short name T252
Test name
Test status
Simulation time 45714083438 ps
CPU time 84.13 seconds
Started May 09 01:33:25 PM PDT 24
Finished May 09 01:34:50 PM PDT 24
Peak memory 253804 kb
Host smart-19d5ea5e-2ea1-430a-97da-c1eb837e4891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204443931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1204443931
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2330008025
Short name T251
Test name
Test status
Simulation time 128351594309 ps
CPU time 267.09 seconds
Started May 09 01:33:23 PM PDT 24
Finished May 09 01:37:52 PM PDT 24
Peak memory 250140 kb
Host smart-412d1107-76ce-46c8-910e-f581c5243842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330008025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2330008025
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2445447699
Short name T475
Test name
Test status
Simulation time 4822753129 ps
CPU time 21.02 seconds
Started May 09 01:33:26 PM PDT 24
Finished May 09 01:33:49 PM PDT 24
Peak memory 224112 kb
Host smart-73ebc3d5-1a4c-41f1-938c-efb0628e3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445447699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2445447699
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3488535435
Short name T407
Test name
Test status
Simulation time 2254882124 ps
CPU time 13.05 seconds
Started May 09 01:33:22 PM PDT 24
Finished May 09 01:33:36 PM PDT 24
Peak memory 233916 kb
Host smart-551a0dc2-3c84-492c-908a-77fd1cc78225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488535435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3488535435
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.207065659
Short name T566
Test name
Test status
Simulation time 12185517415 ps
CPU time 44.61 seconds
Started May 09 01:33:18 PM PDT 24
Finished May 09 01:34:04 PM PDT 24
Peak memory 234404 kb
Host smart-f2512de5-7f6a-4436-a3a7-9948493a9d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207065659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.207065659
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1882231302
Short name T780
Test name
Test status
Simulation time 734856132 ps
CPU time 3.04 seconds
Started May 09 01:33:25 PM PDT 24
Finished May 09 01:33:29 PM PDT 24
Peak memory 224296 kb
Host smart-66e57c34-61ab-432a-b549-7bd4f7177165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882231302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1882231302
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2099960949
Short name T191
Test name
Test status
Simulation time 513817825 ps
CPU time 4.5 seconds
Started May 09 01:33:26 PM PDT 24
Finished May 09 01:33:32 PM PDT 24
Peak memory 232844 kb
Host smart-a7836635-b038-4916-b90f-099dd897a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099960949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2099960949
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1811423163
Short name T338
Test name
Test status
Simulation time 1695265138 ps
CPU time 5.82 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:28 PM PDT 24
Peak memory 218992 kb
Host smart-2bd939b5-a51e-4501-b3b0-a8a9b1bf3af3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811423163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1811423163
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3199154308
Short name T801
Test name
Test status
Simulation time 34245954 ps
CPU time 0.85 seconds
Started May 09 01:33:24 PM PDT 24
Finished May 09 01:33:26 PM PDT 24
Peak memory 206800 kb
Host smart-420164ba-b533-40ac-9c5b-ebf469059f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199154308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3199154308
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2360762187
Short name T931
Test name
Test status
Simulation time 2672928363 ps
CPU time 14.66 seconds
Started May 09 01:33:24 PM PDT 24
Finished May 09 01:33:39 PM PDT 24
Peak memory 216380 kb
Host smart-0ab31606-7686-493b-b388-3550811b714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360762187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2360762187
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1889155504
Short name T374
Test name
Test status
Simulation time 20265380639 ps
CPU time 15.14 seconds
Started May 09 01:33:25 PM PDT 24
Finished May 09 01:33:41 PM PDT 24
Peak memory 216228 kb
Host smart-4d91bbbb-2d01-413d-b0a1-78c570127b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889155504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1889155504
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3333783538
Short name T959
Test name
Test status
Simulation time 330213507 ps
CPU time 1.74 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:24 PM PDT 24
Peak memory 216160 kb
Host smart-6f1be0f5-81af-4c21-955e-99607463d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333783538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3333783538
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2475576756
Short name T903
Test name
Test status
Simulation time 80695366 ps
CPU time 0.87 seconds
Started May 09 01:33:16 PM PDT 24
Finished May 09 01:33:18 PM PDT 24
Peak memory 205724 kb
Host smart-5cba563b-5236-4536-b937-0335c1c909d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475576756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2475576756
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3999285738
Short name T553
Test name
Test status
Simulation time 128411581 ps
CPU time 2.34 seconds
Started May 09 01:33:21 PM PDT 24
Finished May 09 01:33:25 PM PDT 24
Peak memory 221304 kb
Host smart-23c71603-abf2-4a7e-9830-7a457246d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999285738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3999285738
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2874441730
Short name T372
Test name
Test status
Simulation time 26944836 ps
CPU time 0.67 seconds
Started May 09 01:33:32 PM PDT 24
Finished May 09 01:33:34 PM PDT 24
Peak memory 204708 kb
Host smart-544cbe1a-88fc-4e71-aef1-e33462e0b608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874441730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2874441730
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1672123282
Short name T637
Test name
Test status
Simulation time 556510594 ps
CPU time 3.49 seconds
Started May 09 01:33:31 PM PDT 24
Finished May 09 01:33:35 PM PDT 24
Peak memory 218772 kb
Host smart-41788f7b-f293-48ba-892b-7ffaa0413548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672123282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1672123282
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2440007691
Short name T779
Test name
Test status
Simulation time 123665639 ps
CPU time 0.74 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:33:35 PM PDT 24
Peak memory 205512 kb
Host smart-6175d3e8-de44-4ac0-a825-8567f4b56e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440007691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2440007691
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.144814066
Short name T675
Test name
Test status
Simulation time 76890924393 ps
CPU time 76.39 seconds
Started May 09 01:33:32 PM PDT 24
Finished May 09 01:34:50 PM PDT 24
Peak memory 249028 kb
Host smart-79c4c923-3a35-43d6-ae56-f00841b3d877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144814066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.144814066
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.141898867
Short name T135
Test name
Test status
Simulation time 26105419268 ps
CPU time 262.66 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:37:58 PM PDT 24
Peak memory 262904 kb
Host smart-37506248-13c7-4ede-96ca-c3766c1d05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141898867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.141898867
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2847418506
Short name T512
Test name
Test status
Simulation time 1633936753 ps
CPU time 12.83 seconds
Started May 09 01:33:40 PM PDT 24
Finished May 09 01:33:54 PM PDT 24
Peak memory 233640 kb
Host smart-81a64361-a82e-498b-bfdd-602aee292d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847418506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2847418506
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3237618505
Short name T926
Test name
Test status
Simulation time 7811328863 ps
CPU time 8.8 seconds
Started May 09 01:33:35 PM PDT 24
Finished May 09 01:33:45 PM PDT 24
Peak memory 233808 kb
Host smart-63534ee9-ba85-498e-9da7-c4b575d39f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237618505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3237618505
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4005275418
Short name T176
Test name
Test status
Simulation time 1137220676 ps
CPU time 12.57 seconds
Started May 09 01:33:31 PM PDT 24
Finished May 09 01:33:45 PM PDT 24
Peak memory 227548 kb
Host smart-f3257542-50d5-4d90-bbe5-ad5cf92ba505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005275418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4005275418
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.961730015
Short name T170
Test name
Test status
Simulation time 227449848 ps
CPU time 4.44 seconds
Started May 09 01:33:30 PM PDT 24
Finished May 09 01:33:36 PM PDT 24
Peak memory 233036 kb
Host smart-ba33e377-ed6e-407a-b603-2d0a016f3d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961730015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.961730015
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3246682345
Short name T836
Test name
Test status
Simulation time 1191152827 ps
CPU time 9.85 seconds
Started May 09 01:33:31 PM PDT 24
Finished May 09 01:33:43 PM PDT 24
Peak memory 240584 kb
Host smart-083f2a99-ed2e-46a4-a934-f99a17025adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246682345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3246682345
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1477109625
Short name T470
Test name
Test status
Simulation time 7514219500 ps
CPU time 13.05 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:33:48 PM PDT 24
Peak memory 220048 kb
Host smart-457c0651-5a94-4750-bac7-f2c1a9d10016
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1477109625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1477109625
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.710873513
Short name T663
Test name
Test status
Simulation time 2445066821 ps
CPU time 11.79 seconds
Started May 09 01:33:36 PM PDT 24
Finished May 09 01:33:49 PM PDT 24
Peak memory 216252 kb
Host smart-1e595a37-16f3-42d4-9abd-fffee855ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710873513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.710873513
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.669902185
Short name T411
Test name
Test status
Simulation time 12755491867 ps
CPU time 9.92 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:33:45 PM PDT 24
Peak memory 216300 kb
Host smart-36adbe7a-6207-4cac-9e0d-39b6e70f7359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669902185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.669902185
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1991712575
Short name T717
Test name
Test status
Simulation time 30691478 ps
CPU time 1.09 seconds
Started May 09 01:33:32 PM PDT 24
Finished May 09 01:33:35 PM PDT 24
Peak memory 208084 kb
Host smart-2416a416-bf43-43d0-9815-1f857f0eb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991712575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1991712575
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1217190914
Short name T742
Test name
Test status
Simulation time 119053501 ps
CPU time 0.79 seconds
Started May 09 01:33:31 PM PDT 24
Finished May 09 01:33:34 PM PDT 24
Peak memory 205752 kb
Host smart-04d7e18a-6370-4945-a016-d58e7e02a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217190914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1217190914
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1298245065
Short name T540
Test name
Test status
Simulation time 2026452163 ps
CPU time 5.93 seconds
Started May 09 01:33:42 PM PDT 24
Finished May 09 01:33:49 PM PDT 24
Peak memory 240736 kb
Host smart-4b778aa1-1aaa-4768-b70e-517b6cf1eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298245065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1298245065
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1767596079
Short name T339
Test name
Test status
Simulation time 12783276 ps
CPU time 0.71 seconds
Started May 09 01:33:44 PM PDT 24
Finished May 09 01:33:46 PM PDT 24
Peak memory 205340 kb
Host smart-e94e21cb-63a1-469f-9a44-57017d458f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767596079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1767596079
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2622782766
Short name T549
Test name
Test status
Simulation time 125047823 ps
CPU time 3.86 seconds
Started May 09 01:33:36 PM PDT 24
Finished May 09 01:33:41 PM PDT 24
Peak memory 234112 kb
Host smart-427724a8-6497-4c63-8d3f-84da2e42d29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622782766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2622782766
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3246329175
Short name T622
Test name
Test status
Simulation time 13149982 ps
CPU time 0.75 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:33:36 PM PDT 24
Peak memory 206844 kb
Host smart-82acf974-13ed-44d9-9668-92242e5b185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246329175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3246329175
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1641099976
Short name T906
Test name
Test status
Simulation time 7357597042 ps
CPU time 30.6 seconds
Started May 09 01:33:52 PM PDT 24
Finished May 09 01:34:24 PM PDT 24
Peak memory 251008 kb
Host smart-dce871a2-0e6a-4857-a67d-fca997a54a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641099976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1641099976
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4093276447
Short name T543
Test name
Test status
Simulation time 30388636265 ps
CPU time 136.8 seconds
Started May 09 01:33:39 PM PDT 24
Finished May 09 01:35:57 PM PDT 24
Peak memory 249132 kb
Host smart-efe5b5c5-a13f-4d50-8340-cfa056fa16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093276447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4093276447
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4059847610
Short name T132
Test name
Test status
Simulation time 35318543651 ps
CPU time 94.04 seconds
Started May 09 01:33:52 PM PDT 24
Finished May 09 01:35:28 PM PDT 24
Peak memory 273660 kb
Host smart-a13fd73f-48fb-4a54-9174-0cfe2629eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059847610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4059847610
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2476890559
Short name T762
Test name
Test status
Simulation time 5206170297 ps
CPU time 19.99 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:33:55 PM PDT 24
Peak memory 232664 kb
Host smart-bf56d9c0-8559-4822-8696-6cfe349ea808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476890559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2476890559
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1632812960
Short name T413
Test name
Test status
Simulation time 293022980 ps
CPU time 6.57 seconds
Started May 09 01:33:41 PM PDT 24
Finished May 09 01:33:48 PM PDT 24
Peak memory 233944 kb
Host smart-08e1cea2-7b77-4904-8d8f-cd9ba702056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632812960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1632812960
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.171104391
Short name T939
Test name
Test status
Simulation time 1939875207 ps
CPU time 26.77 seconds
Started May 09 01:33:42 PM PDT 24
Finished May 09 01:34:10 PM PDT 24
Peak memory 238764 kb
Host smart-d61ebc25-30d0-447f-b2b3-cc11f033cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171104391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.171104391
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1903650598
Short name T862
Test name
Test status
Simulation time 3028569872 ps
CPU time 7.17 seconds
Started May 09 01:33:40 PM PDT 24
Finished May 09 01:33:49 PM PDT 24
Peak memory 228664 kb
Host smart-2be24d47-0c64-408b-b285-ff2d306bbc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903650598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1903650598
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1370333719
Short name T838
Test name
Test status
Simulation time 2172364397 ps
CPU time 10.75 seconds
Started May 09 01:33:40 PM PDT 24
Finished May 09 01:33:52 PM PDT 24
Peak memory 240060 kb
Host smart-0245b63d-42d0-41cc-833f-b4f2195b2ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370333719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1370333719
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.616286857
Short name T557
Test name
Test status
Simulation time 4859950509 ps
CPU time 13.71 seconds
Started May 09 01:33:51 PM PDT 24
Finished May 09 01:34:07 PM PDT 24
Peak memory 223000 kb
Host smart-e3972032-837e-4650-bd4a-e75a4cdc8699
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616286857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.616286857
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.367803493
Short name T364
Test name
Test status
Simulation time 51163211 ps
CPU time 0.97 seconds
Started May 09 01:33:39 PM PDT 24
Finished May 09 01:33:41 PM PDT 24
Peak memory 207052 kb
Host smart-c092b9a4-ff85-47cf-bf52-cb3922cfbf09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367803493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.367803493
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.360541109
Short name T322
Test name
Test status
Simulation time 14178306124 ps
CPU time 18.19 seconds
Started May 09 01:33:39 PM PDT 24
Finished May 09 01:33:59 PM PDT 24
Peak memory 216308 kb
Host smart-77b58bda-5e55-4364-a876-2303ed159d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360541109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.360541109
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.563780123
Short name T788
Test name
Test status
Simulation time 9448267555 ps
CPU time 15.23 seconds
Started May 09 01:33:42 PM PDT 24
Finished May 09 01:33:58 PM PDT 24
Peak memory 216172 kb
Host smart-169e1382-6ee9-4972-a3e2-29173d1f4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563780123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.563780123
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3707061999
Short name T588
Test name
Test status
Simulation time 217789100 ps
CPU time 1.83 seconds
Started May 09 01:33:41 PM PDT 24
Finished May 09 01:33:44 PM PDT 24
Peak memory 216208 kb
Host smart-11a4e879-4ac5-4bde-9dd4-8b8b08a5d198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707061999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3707061999
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2211472091
Short name T851
Test name
Test status
Simulation time 45020439 ps
CPU time 0.87 seconds
Started May 09 01:33:31 PM PDT 24
Finished May 09 01:33:33 PM PDT 24
Peak memory 206772 kb
Host smart-43ac9bbf-47d3-43e3-b088-de339c5463d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211472091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2211472091
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4224423726
Short name T831
Test name
Test status
Simulation time 195446179 ps
CPU time 3.16 seconds
Started May 09 01:33:34 PM PDT 24
Finished May 09 01:33:38 PM PDT 24
Peak memory 217860 kb
Host smart-f7b49ba2-0c52-470b-9a0d-b13d999a129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224423726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4224423726
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.123310987
Short name T489
Test name
Test status
Simulation time 15386325 ps
CPU time 0.76 seconds
Started May 09 01:33:53 PM PDT 24
Finished May 09 01:33:55 PM PDT 24
Peak memory 205276 kb
Host smart-53e8bef3-1a4c-4000-a54b-ec3bce20fb2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123310987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.123310987
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2072783904
Short name T305
Test name
Test status
Simulation time 251208572 ps
CPU time 4.76 seconds
Started May 09 01:33:51 PM PDT 24
Finished May 09 01:33:58 PM PDT 24
Peak memory 220348 kb
Host smart-d94fbc84-3ac2-42e0-bcf4-f26a3e6ea95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072783904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2072783904
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4176092946
Short name T345
Test name
Test status
Simulation time 53801799 ps
CPU time 0.74 seconds
Started May 09 01:33:51 PM PDT 24
Finished May 09 01:33:54 PM PDT 24
Peak memory 206512 kb
Host smart-2eb030d6-9e3d-46e5-b901-98128e8a40d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176092946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4176092946
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4080769224
Short name T276
Test name
Test status
Simulation time 4282033160 ps
CPU time 25.2 seconds
Started May 09 01:33:58 PM PDT 24
Finished May 09 01:34:25 PM PDT 24
Peak memory 234792 kb
Host smart-8ba68b1b-04db-4ade-b2d5-260386e4b11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080769224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4080769224
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1400679209
Short name T634
Test name
Test status
Simulation time 8198897323 ps
CPU time 51.44 seconds
Started May 09 01:33:50 PM PDT 24
Finished May 09 01:34:44 PM PDT 24
Peak memory 256232 kb
Host smart-af398030-6dd5-40df-803a-028334c95d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400679209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1400679209
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1840320113
Short name T179
Test name
Test status
Simulation time 58584432185 ps
CPU time 130.34 seconds
Started May 09 01:33:48 PM PDT 24
Finished May 09 01:36:00 PM PDT 24
Peak memory 251372 kb
Host smart-1903196b-c7f9-4489-8c14-abf1d46c81a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840320113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1840320113
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2693107277
Short name T351
Test name
Test status
Simulation time 419429414 ps
CPU time 6.07 seconds
Started May 09 01:33:50 PM PDT 24
Finished May 09 01:33:57 PM PDT 24
Peak memory 224492 kb
Host smart-f4ade18e-0345-4eeb-bc79-0d3d660ceb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693107277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2693107277
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.816481905
Short name T396
Test name
Test status
Simulation time 16055169917 ps
CPU time 20.87 seconds
Started May 09 01:33:44 PM PDT 24
Finished May 09 01:34:06 PM PDT 24
Peak memory 233020 kb
Host smart-19d16f2a-cfef-4358-8994-ef92375ef14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816481905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.816481905
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2943875857
Short name T937
Test name
Test status
Simulation time 7011568482 ps
CPU time 25.83 seconds
Started May 09 01:33:53 PM PDT 24
Finished May 09 01:34:20 PM PDT 24
Peak memory 224432 kb
Host smart-bccc75d3-a98a-4de9-8992-468a18a805bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943875857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2943875857
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.117329385
Short name T175
Test name
Test status
Simulation time 1191805709 ps
CPU time 7.78 seconds
Started May 09 01:33:53 PM PDT 24
Finished May 09 01:34:02 PM PDT 24
Peak memory 218644 kb
Host smart-7838f597-a717-4cb0-ac35-e9eb439be3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117329385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.117329385
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3226361887
Short name T93
Test name
Test status
Simulation time 15817070434 ps
CPU time 16.75 seconds
Started May 09 01:33:52 PM PDT 24
Finished May 09 01:34:10 PM PDT 24
Peak memory 240832 kb
Host smart-6d7702c7-3d21-490c-b398-da847f23eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226361887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3226361887
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.759806350
Short name T33
Test name
Test status
Simulation time 740801269 ps
CPU time 10.58 seconds
Started May 09 01:33:51 PM PDT 24
Finished May 09 01:34:03 PM PDT 24
Peak memory 219960 kb
Host smart-5f90ac78-9ac6-4127-8440-4ebdb67fa065
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=759806350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.759806350
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.358653522
Short name T840
Test name
Test status
Simulation time 19707420487 ps
CPU time 58.56 seconds
Started May 09 01:33:49 PM PDT 24
Finished May 09 01:34:49 PM PDT 24
Peak memory 249172 kb
Host smart-3e58ca02-08e9-4859-a940-c565391b02cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358653522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.358653522
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.212564409
Short name T451
Test name
Test status
Simulation time 19527874 ps
CPU time 0.71 seconds
Started May 09 01:33:42 PM PDT 24
Finished May 09 01:33:43 PM PDT 24
Peak memory 205620 kb
Host smart-3e52840b-a2fa-4ba5-957e-e765071b868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212564409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.212564409
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1154455395
Short name T869
Test name
Test status
Simulation time 2851153230 ps
CPU time 4.12 seconds
Started May 09 01:33:38 PM PDT 24
Finished May 09 01:33:43 PM PDT 24
Peak memory 216132 kb
Host smart-7964b115-a8dc-4cdc-af38-4deb786d6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154455395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1154455395
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2429371331
Short name T887
Test name
Test status
Simulation time 15373694 ps
CPU time 0.68 seconds
Started May 09 01:33:53 PM PDT 24
Finished May 09 01:33:55 PM PDT 24
Peak memory 205524 kb
Host smart-8b2a5718-fe62-46f5-afb6-0f47e81135ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429371331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2429371331
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.364296150
Short name T409
Test name
Test status
Simulation time 38590685 ps
CPU time 0.69 seconds
Started May 09 01:33:37 PM PDT 24
Finished May 09 01:33:39 PM PDT 24
Peak memory 205564 kb
Host smart-ac14ed98-6030-4df4-967c-3a48b77be337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364296150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.364296150
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.138589428
Short name T736
Test name
Test status
Simulation time 1046251684 ps
CPU time 6.53 seconds
Started May 09 01:33:52 PM PDT 24
Finished May 09 01:34:00 PM PDT 24
Peak memory 224116 kb
Host smart-aebbffca-b602-4210-9605-74a42d775c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138589428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.138589428
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2705740815
Short name T527
Test name
Test status
Simulation time 75920497 ps
CPU time 0.74 seconds
Started May 09 01:34:04 PM PDT 24
Finished May 09 01:34:05 PM PDT 24
Peak memory 205616 kb
Host smart-fb9de63e-7ea6-4e32-82d9-3f74ce49faec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705740815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2705740815
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2854779567
Short name T873
Test name
Test status
Simulation time 751596204 ps
CPU time 2.35 seconds
Started May 09 01:34:00 PM PDT 24
Finished May 09 01:34:04 PM PDT 24
Peak memory 216096 kb
Host smart-4d4e7f77-6673-4ae9-8228-85294f22e729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854779567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2854779567
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1331491616
Short name T430
Test name
Test status
Simulation time 73858083 ps
CPU time 0.76 seconds
Started May 09 01:33:50 PM PDT 24
Finished May 09 01:33:52 PM PDT 24
Peak memory 205844 kb
Host smart-04b815e4-3981-4fa0-9ac6-c4d316ec67d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331491616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1331491616
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1293559200
Short name T957
Test name
Test status
Simulation time 9810241537 ps
CPU time 78.99 seconds
Started May 09 01:34:06 PM PDT 24
Finished May 09 01:35:26 PM PDT 24
Peak memory 249024 kb
Host smart-0d6502ec-1a66-43db-a548-50d906c82cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293559200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1293559200
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3158582795
Short name T44
Test name
Test status
Simulation time 1450086750 ps
CPU time 37.49 seconds
Started May 09 01:34:02 PM PDT 24
Finished May 09 01:34:41 PM PDT 24
Peak memory 237924 kb
Host smart-34b7a623-d771-48f1-8f7a-3a27afd07470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158582795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3158582795
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.553276971
Short name T606
Test name
Test status
Simulation time 579522905 ps
CPU time 14.06 seconds
Started May 09 01:34:08 PM PDT 24
Finished May 09 01:34:23 PM PDT 24
Peak memory 233876 kb
Host smart-c30413ab-6455-4126-afb8-265de7ca3a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553276971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.553276971
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2094265903
Short name T535
Test name
Test status
Simulation time 361068520 ps
CPU time 7 seconds
Started May 09 01:34:04 PM PDT 24
Finished May 09 01:34:12 PM PDT 24
Peak memory 218376 kb
Host smart-c5586a88-530d-4c1b-8b7d-5c8c3f7603ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094265903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2094265903
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2742720346
Short name T302
Test name
Test status
Simulation time 34265731248 ps
CPU time 32.4 seconds
Started May 09 01:34:04 PM PDT 24
Finished May 09 01:34:37 PM PDT 24
Peak memory 240632 kb
Host smart-d083da2c-ab1e-4c27-92ad-0466aa0deece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742720346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2742720346
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.772973799
Short name T459
Test name
Test status
Simulation time 1394557937 ps
CPU time 6.1 seconds
Started May 09 01:33:50 PM PDT 24
Finished May 09 01:33:58 PM PDT 24
Peak memory 233068 kb
Host smart-ae0863a7-481b-4290-8706-2f34b72d7eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772973799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.772973799
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4051287113
Short name T355
Test name
Test status
Simulation time 2094349976 ps
CPU time 7.7 seconds
Started May 09 01:33:59 PM PDT 24
Finished May 09 01:34:08 PM PDT 24
Peak memory 222880 kb
Host smart-87f98e0a-abef-48b2-8013-5c727512ddb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051287113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4051287113
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2041418950
Short name T221
Test name
Test status
Simulation time 261255053523 ps
CPU time 171.62 seconds
Started May 09 01:34:06 PM PDT 24
Finished May 09 01:36:58 PM PDT 24
Peak memory 249076 kb
Host smart-bbd8a472-9cd2-423a-8d6e-319a17e4dad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041418950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2041418950
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2720240819
Short name T499
Test name
Test status
Simulation time 22225083 ps
CPU time 0.72 seconds
Started May 09 01:33:50 PM PDT 24
Finished May 09 01:33:53 PM PDT 24
Peak memory 205528 kb
Host smart-22b7550b-3fc6-48f5-85ad-c2995c0072bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720240819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2720240819
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3453161965
Short name T361
Test name
Test status
Simulation time 7012573055 ps
CPU time 5.13 seconds
Started May 09 01:33:59 PM PDT 24
Finished May 09 01:34:05 PM PDT 24
Peak memory 216232 kb
Host smart-6483ed68-4a2d-4ffd-a608-820ebbc9f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453161965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3453161965
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2033676594
Short name T692
Test name
Test status
Simulation time 79132085 ps
CPU time 1.63 seconds
Started May 09 01:33:51 PM PDT 24
Finished May 09 01:33:55 PM PDT 24
Peak memory 216084 kb
Host smart-ea4e7a90-0dda-4d24-901d-23b1132eb602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033676594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2033676594
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.557693096
Short name T464
Test name
Test status
Simulation time 37984486 ps
CPU time 0.83 seconds
Started May 09 01:33:50 PM PDT 24
Finished May 09 01:33:53 PM PDT 24
Peak memory 205768 kb
Host smart-ba7f3b5d-dd78-4750-a342-0ebcdc8ea39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557693096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.557693096
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3461711084
Short name T401
Test name
Test status
Simulation time 5711626243 ps
CPU time 19.3 seconds
Started May 09 01:34:07 PM PDT 24
Finished May 09 01:34:28 PM PDT 24
Peak memory 239560 kb
Host smart-df050e94-411a-4c6c-8e51-e8f0a381f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461711084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3461711084
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2569154507
Short name T877
Test name
Test status
Simulation time 14432849 ps
CPU time 0.69 seconds
Started May 09 01:34:15 PM PDT 24
Finished May 09 01:34:17 PM PDT 24
Peak memory 205676 kb
Host smart-1368eb52-0dca-41ca-ad45-7c52f50c488c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569154507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2569154507
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1389393131
Short name T613
Test name
Test status
Simulation time 904807777 ps
CPU time 2.42 seconds
Started May 09 01:34:02 PM PDT 24
Finished May 09 01:34:06 PM PDT 24
Peak memory 215984 kb
Host smart-afc51dfb-2988-4614-b062-712e5b7b895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389393131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1389393131
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1360997996
Short name T394
Test name
Test status
Simulation time 60511307 ps
CPU time 0.76 seconds
Started May 09 01:34:04 PM PDT 24
Finished May 09 01:34:06 PM PDT 24
Peak memory 206544 kb
Host smart-3abcb13f-921d-4296-9fea-2c788f04ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360997996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1360997996
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3479499552
Short name T902
Test name
Test status
Simulation time 65037894019 ps
CPU time 126.61 seconds
Started May 09 01:34:05 PM PDT 24
Finished May 09 01:36:12 PM PDT 24
Peak memory 249052 kb
Host smart-9f3165af-3791-4f63-9285-f29afc21ec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479499552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3479499552
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2428636540
Short name T952
Test name
Test status
Simulation time 40488349315 ps
CPU time 109.03 seconds
Started May 09 01:34:08 PM PDT 24
Finished May 09 01:35:57 PM PDT 24
Peak memory 252928 kb
Host smart-d50ab1a8-a85a-4b9b-86ce-9698d84afa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428636540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2428636540
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.87433283
Short name T701
Test name
Test status
Simulation time 11622143035 ps
CPU time 46.99 seconds
Started May 09 01:34:06 PM PDT 24
Finished May 09 01:34:54 PM PDT 24
Peak memory 240828 kb
Host smart-dcaf1f73-85dd-4fb7-b2c2-4e07bb40bdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87433283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.87433283
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.643236778
Short name T218
Test name
Test status
Simulation time 298559338 ps
CPU time 4.39 seconds
Started May 09 01:34:08 PM PDT 24
Finished May 09 01:34:13 PM PDT 24
Peak memory 218804 kb
Host smart-bff3124e-d81d-4259-8f6d-710b252a665e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643236778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.643236778
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.948370552
Short name T694
Test name
Test status
Simulation time 3986104330 ps
CPU time 13.86 seconds
Started May 09 01:33:59 PM PDT 24
Finished May 09 01:34:14 PM PDT 24
Peak memory 235820 kb
Host smart-8358067c-21fd-47e1-82c4-d745713df159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948370552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.948370552
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.173833200
Short name T28
Test name
Test status
Simulation time 792473854 ps
CPU time 10.9 seconds
Started May 09 01:34:04 PM PDT 24
Finished May 09 01:34:16 PM PDT 24
Peak memory 239844 kb
Host smart-a8327e1b-54b5-4745-9974-0e75c5d13d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173833200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.173833200
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.678967880
Short name T682
Test name
Test status
Simulation time 449884547 ps
CPU time 2.43 seconds
Started May 09 01:34:04 PM PDT 24
Finished May 09 01:34:08 PM PDT 24
Peak memory 224420 kb
Host smart-9ed4e805-28a1-4e42-8413-4ff99e83403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678967880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.678967880
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.800223632
Short name T756
Test name
Test status
Simulation time 6807972400 ps
CPU time 13.23 seconds
Started May 09 01:34:08 PM PDT 24
Finished May 09 01:34:22 PM PDT 24
Peak memory 222864 kb
Host smart-68d05a3c-cc13-4abd-af10-783a90fc04fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800223632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.800223632
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1966679584
Short name T712
Test name
Test status
Simulation time 113429548 ps
CPU time 1.03 seconds
Started May 09 01:34:06 PM PDT 24
Finished May 09 01:34:08 PM PDT 24
Peak memory 207068 kb
Host smart-6bb1455d-4d1f-4056-8dff-f3b3916dc9af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966679584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1966679584
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2814823164
Short name T323
Test name
Test status
Simulation time 3931649673 ps
CPU time 21.99 seconds
Started May 09 01:34:01 PM PDT 24
Finished May 09 01:34:25 PM PDT 24
Peak memory 216180 kb
Host smart-fd1d0b0a-5990-4a80-b7a0-bb960fac5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814823164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2814823164
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1253862807
Short name T533
Test name
Test status
Simulation time 15024969 ps
CPU time 0.7 seconds
Started May 09 01:34:06 PM PDT 24
Finished May 09 01:34:07 PM PDT 24
Peak memory 205576 kb
Host smart-4f967b42-07c8-4e09-9439-755d5cfa4996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253862807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1253862807
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1593207159
Short name T673
Test name
Test status
Simulation time 441213426 ps
CPU time 3.95 seconds
Started May 09 01:34:00 PM PDT 24
Finished May 09 01:34:05 PM PDT 24
Peak memory 216180 kb
Host smart-831de77b-3bd1-471a-8112-ef87a22ec400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593207159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1593207159
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1761980551
Short name T492
Test name
Test status
Simulation time 111956187 ps
CPU time 1.03 seconds
Started May 09 01:34:00 PM PDT 24
Finished May 09 01:34:02 PM PDT 24
Peak memory 206772 kb
Host smart-a1ccca98-c6fd-4a10-927c-f48e97b79c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761980551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1761980551
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3433924587
Short name T298
Test name
Test status
Simulation time 7916264994 ps
CPU time 11.74 seconds
Started May 09 01:34:05 PM PDT 24
Finished May 09 01:34:18 PM PDT 24
Peak memory 235232 kb
Host smart-4e5fb2b1-de58-4eaa-b0de-0a65da2e4073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433924587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3433924587
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2406943910
Short name T678
Test name
Test status
Simulation time 13638281 ps
CPU time 0.72 seconds
Started May 09 01:34:13 PM PDT 24
Finished May 09 01:34:15 PM PDT 24
Peak memory 204768 kb
Host smart-8db71eac-e302-4108-a1ff-82c661841c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406943910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2406943910
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3419288995
Short name T892
Test name
Test status
Simulation time 360949334 ps
CPU time 5.94 seconds
Started May 09 01:34:13 PM PDT 24
Finished May 09 01:34:20 PM PDT 24
Peak memory 233768 kb
Host smart-58d759de-f917-485d-b833-7077c5a0e7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419288995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3419288995
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2908567488
Short name T403
Test name
Test status
Simulation time 33073006 ps
CPU time 0.78 seconds
Started May 09 01:34:17 PM PDT 24
Finished May 09 01:34:19 PM PDT 24
Peak memory 205824 kb
Host smart-578c2d39-2337-47e9-a87e-55aae1419eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908567488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2908567488
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1183982642
Short name T619
Test name
Test status
Simulation time 48608743386 ps
CPU time 44.6 seconds
Started May 09 01:34:15 PM PDT 24
Finished May 09 01:35:00 PM PDT 24
Peak memory 235644 kb
Host smart-93854df6-f7c9-4a0a-be2a-01bf0237c53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183982642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1183982642
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.109139912
Short name T486
Test name
Test status
Simulation time 8499762920 ps
CPU time 58.05 seconds
Started May 09 01:34:13 PM PDT 24
Finished May 09 01:35:12 PM PDT 24
Peak memory 249156 kb
Host smart-a0f6eb69-dc7d-4a22-8716-f094d32a4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109139912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.109139912
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.105911955
Short name T484
Test name
Test status
Simulation time 62848700 ps
CPU time 2.47 seconds
Started May 09 01:34:14 PM PDT 24
Finished May 09 01:34:17 PM PDT 24
Peak memory 232608 kb
Host smart-b565ea4f-4e63-4aa8-b31e-2b9e34c7e30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105911955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.105911955
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1469602297
Short name T773
Test name
Test status
Simulation time 143188215 ps
CPU time 3.18 seconds
Started May 09 01:34:14 PM PDT 24
Finished May 09 01:34:18 PM PDT 24
Peak memory 218832 kb
Host smart-074b9609-9b8d-4847-a0a7-bede3a1b031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469602297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1469602297
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1897679606
Short name T288
Test name
Test status
Simulation time 35259947414 ps
CPU time 28.94 seconds
Started May 09 01:34:15 PM PDT 24
Finished May 09 01:34:45 PM PDT 24
Peak memory 235272 kb
Host smart-f63914c1-2917-49d0-8abb-e5475c200799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897679606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1897679606
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1986419943
Short name T306
Test name
Test status
Simulation time 16462737567 ps
CPU time 21.9 seconds
Started May 09 01:34:19 PM PDT 24
Finished May 09 01:34:41 PM PDT 24
Peak memory 236692 kb
Host smart-cc68740b-9bf8-4b0e-bf72-980ec99704c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986419943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1986419943
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2380577658
Short name T417
Test name
Test status
Simulation time 2299637874 ps
CPU time 12.02 seconds
Started May 09 01:34:14 PM PDT 24
Finished May 09 01:34:27 PM PDT 24
Peak memory 232680 kb
Host smart-6c58063e-03d6-4c4e-b66b-83df2983ecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380577658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2380577658
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.826023834
Short name T348
Test name
Test status
Simulation time 118078081 ps
CPU time 3.53 seconds
Started May 09 01:34:17 PM PDT 24
Finished May 09 01:34:22 PM PDT 24
Peak memory 222696 kb
Host smart-e0a49f49-5ecd-4fbe-a208-b4be78fef90c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=826023834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.826023834
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3699219051
Short name T60
Test name
Test status
Simulation time 6219750176 ps
CPU time 50.24 seconds
Started May 09 01:34:16 PM PDT 24
Finished May 09 01:35:07 PM PDT 24
Peak memory 224436 kb
Host smart-64c2e91d-f43f-42e3-a1d9-0cfab1bf01d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699219051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3699219051
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3692530804
Short name T857
Test name
Test status
Simulation time 4867510736 ps
CPU time 23.63 seconds
Started May 09 01:34:30 PM PDT 24
Finished May 09 01:34:55 PM PDT 24
Peak memory 216564 kb
Host smart-a3c2d7ee-1823-4fe1-aa18-b56aacbe9031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692530804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3692530804
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1301150679
Short name T444
Test name
Test status
Simulation time 728662143 ps
CPU time 5.78 seconds
Started May 09 01:34:14 PM PDT 24
Finished May 09 01:34:21 PM PDT 24
Peak memory 216108 kb
Host smart-e68b1cd2-6f03-4b4c-b386-14265a857b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301150679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1301150679
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2772678649
Short name T884
Test name
Test status
Simulation time 23099362 ps
CPU time 0.92 seconds
Started May 09 01:34:12 PM PDT 24
Finished May 09 01:34:14 PM PDT 24
Peak memory 206596 kb
Host smart-829ad3b3-1765-4bf5-9059-8166de700988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772678649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2772678649
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2374649335
Short name T605
Test name
Test status
Simulation time 15132608 ps
CPU time 0.72 seconds
Started May 09 01:34:18 PM PDT 24
Finished May 09 01:34:20 PM PDT 24
Peak memory 205728 kb
Host smart-d4ea0bd0-5e5d-4b2d-82c7-c9482214faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374649335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2374649335
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3181475528
Short name T584
Test name
Test status
Simulation time 1249415694 ps
CPU time 2.85 seconds
Started May 09 01:34:12 PM PDT 24
Finished May 09 01:34:15 PM PDT 24
Peak memory 232588 kb
Host smart-a4d256d2-197d-467e-9bcb-17917e939ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181475528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3181475528
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2172574480
Short name T497
Test name
Test status
Simulation time 20196116 ps
CPU time 0.78 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:00 PM PDT 24
Peak memory 205372 kb
Host smart-7020e706-d54c-44aa-840e-60bafcf9c256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172574480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
172574480
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2489705102
Short name T346
Test name
Test status
Simulation time 207295991 ps
CPU time 2.33 seconds
Started May 09 01:30:02 PM PDT 24
Finished May 09 01:30:05 PM PDT 24
Peak memory 215944 kb
Host smart-6417d63c-68a5-45ed-acf5-653b22755946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489705102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2489705102
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3739139742
Short name T528
Test name
Test status
Simulation time 22988244 ps
CPU time 0.77 seconds
Started May 09 01:30:01 PM PDT 24
Finished May 09 01:30:03 PM PDT 24
Peak memory 206516 kb
Host smart-42cb1315-124e-45a8-9e4c-1c03932ae9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739139742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3739139742
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3018340373
Short name T292
Test name
Test status
Simulation time 6273064476 ps
CPU time 45.63 seconds
Started May 09 01:29:57 PM PDT 24
Finished May 09 01:30:43 PM PDT 24
Peak memory 249444 kb
Host smart-a631ed15-6cf3-4e0a-9b33-6e3974cb32aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018340373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3018340373
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2676952328
Short name T402
Test name
Test status
Simulation time 4747635278 ps
CPU time 25.79 seconds
Started May 09 01:29:59 PM PDT 24
Finished May 09 01:30:26 PM PDT 24
Peak memory 217296 kb
Host smart-ce0bf364-7e06-4e57-96ea-df6d425c71cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676952328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2676952328
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1056462403
Short name T236
Test name
Test status
Simulation time 17609536070 ps
CPU time 98.01 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:31:34 PM PDT 24
Peak memory 257240 kb
Host smart-6823d2bb-24e4-459b-8bb5-2f81a3da825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056462403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1056462403
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.430036552
Short name T128
Test name
Test status
Simulation time 9888279750 ps
CPU time 35.08 seconds
Started May 09 01:30:00 PM PDT 24
Finished May 09 01:30:37 PM PDT 24
Peak memory 234816 kb
Host smart-d6806db5-704b-40b9-afb3-d9f36da529d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430036552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.430036552
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1027594749
Short name T282
Test name
Test status
Simulation time 3351216924 ps
CPU time 14.55 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:14 PM PDT 24
Peak memory 234428 kb
Host smart-31693be9-2776-4882-8a4c-92cbd22e0354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027594749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1027594749
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3503156137
Short name T279
Test name
Test status
Simulation time 3658722844 ps
CPU time 34.41 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:30:30 PM PDT 24
Peak memory 249324 kb
Host smart-85710354-8e23-4263-8e43-6878ac4099db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503156137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3503156137
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3497788264
Short name T597
Test name
Test status
Simulation time 712982655 ps
CPU time 3.02 seconds
Started May 09 01:29:55 PM PDT 24
Finished May 09 01:29:59 PM PDT 24
Peak memory 232656 kb
Host smart-8433604a-185b-423c-9d91-4becdadf6ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497788264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3497788264
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3862823192
Short name T591
Test name
Test status
Simulation time 31482087 ps
CPU time 2.05 seconds
Started May 09 01:30:00 PM PDT 24
Finished May 09 01:30:03 PM PDT 24
Peak memory 216044 kb
Host smart-b01d875d-0292-4ff5-8f76-26a75d2794b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862823192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3862823192
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1116676776
Short name T490
Test name
Test status
Simulation time 2337276185 ps
CPU time 7.17 seconds
Started May 09 01:29:56 PM PDT 24
Finished May 09 01:30:04 PM PDT 24
Peak memory 218652 kb
Host smart-6053368d-349b-4026-acc1-a002733948bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1116676776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1116676776
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.173244208
Short name T454
Test name
Test status
Simulation time 5708313009 ps
CPU time 70.21 seconds
Started May 09 01:29:54 PM PDT 24
Finished May 09 01:31:05 PM PDT 24
Peak memory 257212 kb
Host smart-2e5e4492-0823-46c1-ace7-1c3a43ba1d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173244208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.173244208
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3798983686
Short name T860
Test name
Test status
Simulation time 7612417553 ps
CPU time 14.84 seconds
Started May 09 01:29:59 PM PDT 24
Finished May 09 01:30:15 PM PDT 24
Peak memory 215756 kb
Host smart-0767d4f1-71e2-415f-9e2d-0096465d4d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798983686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3798983686
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4054484841
Short name T760
Test name
Test status
Simulation time 5207873867 ps
CPU time 8.03 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:07 PM PDT 24
Peak memory 216144 kb
Host smart-cdbfb3a7-38b3-4845-8406-d8e3ea184bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054484841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4054484841
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.583984474
Short name T386
Test name
Test status
Simulation time 101740819 ps
CPU time 1.27 seconds
Started May 09 01:29:59 PM PDT 24
Finished May 09 01:30:01 PM PDT 24
Peak memory 207276 kb
Host smart-048a1acc-8750-48a9-a0e3-113c142ea87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583984474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.583984474
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3790660726
Short name T503
Test name
Test status
Simulation time 67961786 ps
CPU time 0.88 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:00 PM PDT 24
Peak memory 205668 kb
Host smart-969e8319-6ed0-4469-bbde-3638f5009d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790660726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3790660726
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3484615059
Short name T833
Test name
Test status
Simulation time 1289270361 ps
CPU time 8 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:07 PM PDT 24
Peak memory 233516 kb
Host smart-b1bd4be9-7b9f-4d58-be52-e159913a636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484615059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3484615059
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3486097960
Short name T602
Test name
Test status
Simulation time 43072250 ps
CPU time 0.79 seconds
Started May 09 01:30:04 PM PDT 24
Finished May 09 01:30:05 PM PDT 24
Peak memory 205368 kb
Host smart-3923f7a9-f7f2-4cb5-91f2-d2cefb00198e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486097960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
486097960
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1544464525
Short name T212
Test name
Test status
Simulation time 403387578 ps
CPU time 6.86 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:17 PM PDT 24
Peak memory 233616 kb
Host smart-d96e0714-e3a4-4a18-a760-48fa4891ea97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544464525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1544464525
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.923629950
Short name T5
Test name
Test status
Simulation time 62397360 ps
CPU time 0.87 seconds
Started May 09 01:30:00 PM PDT 24
Finished May 09 01:30:03 PM PDT 24
Peak memory 206492 kb
Host smart-c565560c-942e-4c0c-bb47-55ebb611ca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923629950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.923629950
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3237308435
Short name T312
Test name
Test status
Simulation time 612846178 ps
CPU time 12.87 seconds
Started May 09 01:30:13 PM PDT 24
Finished May 09 01:30:27 PM PDT 24
Peak memory 234672 kb
Host smart-2c23d6a9-04f0-40bc-9e60-d997fc0dab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237308435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3237308435
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2882799893
Short name T809
Test name
Test status
Simulation time 671682443 ps
CPU time 4.6 seconds
Started May 09 01:30:12 PM PDT 24
Finished May 09 01:30:18 PM PDT 24
Peak memory 234456 kb
Host smart-f15ebc71-be74-4c01-927d-075a58a6dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882799893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2882799893
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3717940217
Short name T794
Test name
Test status
Simulation time 13448603726 ps
CPU time 25.05 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:35 PM PDT 24
Peak memory 235172 kb
Host smart-48e0352e-4e11-4f61-9060-2fe2a4f3970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717940217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3717940217
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3904002744
Short name T904
Test name
Test status
Simulation time 98149437 ps
CPU time 2.43 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:12 PM PDT 24
Peak memory 218220 kb
Host smart-dd737086-22db-4772-8ce0-14f8d72dea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904002744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3904002744
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2021674976
Short name T741
Test name
Test status
Simulation time 362069443 ps
CPU time 4.01 seconds
Started May 09 01:30:05 PM PDT 24
Finished May 09 01:30:10 PM PDT 24
Peak memory 216696 kb
Host smart-93ff349c-9dcb-4075-a6e8-d4c3daa1fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021674976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2021674976
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3909864921
Short name T140
Test name
Test status
Simulation time 4205853925 ps
CPU time 15.21 seconds
Started May 09 01:30:13 PM PDT 24
Finished May 09 01:30:30 PM PDT 24
Peak memory 222832 kb
Host smart-16fd33a1-8f1f-4042-89f8-a347adc7da4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909864921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3909864921
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4217403572
Short name T806
Test name
Test status
Simulation time 28088998070 ps
CPU time 239.39 seconds
Started May 09 01:30:10 PM PDT 24
Finished May 09 01:34:11 PM PDT 24
Peak memory 249340 kb
Host smart-4a190721-e075-43c0-9d4f-67ae8869282d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217403572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4217403572
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2645104505
Short name T321
Test name
Test status
Simulation time 6879990029 ps
CPU time 14.85 seconds
Started May 09 01:29:58 PM PDT 24
Finished May 09 01:30:14 PM PDT 24
Peak memory 216292 kb
Host smart-77db5081-7859-4640-bc8a-3d476716a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645104505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2645104505
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1949728052
Short name T696
Test name
Test status
Simulation time 2904384641 ps
CPU time 8.26 seconds
Started May 09 01:30:01 PM PDT 24
Finished May 09 01:30:10 PM PDT 24
Peak memory 216164 kb
Host smart-0c00bca6-aa60-48ff-b9ac-8c8faf23e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949728052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1949728052
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2112724492
Short name T483
Test name
Test status
Simulation time 87967692 ps
CPU time 1.1 seconds
Started May 09 01:30:10 PM PDT 24
Finished May 09 01:30:12 PM PDT 24
Peak memory 207204 kb
Host smart-c88fb0c2-57de-4181-9495-6023d725c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112724492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2112724492
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2238911744
Short name T868
Test name
Test status
Simulation time 85641721 ps
CPU time 0.81 seconds
Started May 09 01:30:08 PM PDT 24
Finished May 09 01:30:10 PM PDT 24
Peak memory 205780 kb
Host smart-9e180c41-9d5e-40fc-a336-3a34d22333a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238911744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2238911744
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1597859884
Short name T608
Test name
Test status
Simulation time 2943234560 ps
CPU time 3.65 seconds
Started May 09 01:30:10 PM PDT 24
Finished May 09 01:30:15 PM PDT 24
Peak memory 234248 kb
Host smart-b9be74ca-2df1-4351-85c9-cc3ec49f0759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597859884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1597859884
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2870413312
Short name T659
Test name
Test status
Simulation time 38843118 ps
CPU time 0.7 seconds
Started May 09 01:30:13 PM PDT 24
Finished May 09 01:30:15 PM PDT 24
Peak memory 205308 kb
Host smart-2700e9ae-431b-4709-b167-ea707c67a79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870413312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
870413312
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3049594693
Short name T206
Test name
Test status
Simulation time 6891084486 ps
CPU time 21.33 seconds
Started May 09 01:30:12 PM PDT 24
Finished May 09 01:30:34 PM PDT 24
Peak memory 220160 kb
Host smart-80e289fd-10df-4e83-bbc8-1189f93e3779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049594693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3049594693
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1412764636
Short name T883
Test name
Test status
Simulation time 57989114 ps
CPU time 0.76 seconds
Started May 09 01:30:02 PM PDT 24
Finished May 09 01:30:04 PM PDT 24
Peak memory 205496 kb
Host smart-af440088-89e9-4554-92a9-d78f0699435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412764636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1412764636
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.620576699
Short name T871
Test name
Test status
Simulation time 31053723312 ps
CPU time 113.02 seconds
Started May 09 01:30:06 PM PDT 24
Finished May 09 01:32:00 PM PDT 24
Peak memory 249080 kb
Host smart-c76490b0-1e5d-4e9a-9456-c5b65c166654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620576699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.620576699
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2778015542
Short name T250
Test name
Test status
Simulation time 300393732203 ps
CPU time 750.45 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:42:41 PM PDT 24
Peak memory 265452 kb
Host smart-bd24987c-429c-4040-8aac-cc9a2b9327aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778015542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2778015542
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2550994373
Short name T257
Test name
Test status
Simulation time 465927706369 ps
CPU time 470.41 seconds
Started May 09 01:30:07 PM PDT 24
Finished May 09 01:37:58 PM PDT 24
Peak memory 256220 kb
Host smart-361d9aae-e7bf-4b15-8af6-600405f3c427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550994373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2550994373
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3430495060
Short name T538
Test name
Test status
Simulation time 648775002 ps
CPU time 7.86 seconds
Started May 09 01:30:12 PM PDT 24
Finished May 09 01:30:21 PM PDT 24
Peak memory 240732 kb
Host smart-63a37cf8-1621-4a57-a53d-914e283d2619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430495060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3430495060
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.35114436
Short name T498
Test name
Test status
Simulation time 115808093 ps
CPU time 2.49 seconds
Started May 09 01:30:10 PM PDT 24
Finished May 09 01:30:13 PM PDT 24
Peak memory 220976 kb
Host smart-7d2844f9-73a6-47ae-b091-f59803807536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35114436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.35114436
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3524477083
Short name T823
Test name
Test status
Simulation time 117118000095 ps
CPU time 94.58 seconds
Started May 09 01:30:07 PM PDT 24
Finished May 09 01:31:42 PM PDT 24
Peak memory 232248 kb
Host smart-59636162-1aec-41f8-ba00-ff969a111c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524477083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3524477083
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2720493168
Short name T611
Test name
Test status
Simulation time 2659059240 ps
CPU time 7.19 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:18 PM PDT 24
Peak memory 235464 kb
Host smart-be856e12-5a5e-4da0-a404-152e93a679ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720493168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2720493168
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2364616897
Short name T274
Test name
Test status
Simulation time 9300064285 ps
CPU time 15.95 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:26 PM PDT 24
Peak memory 218552 kb
Host smart-332dd165-e74a-4ffe-abbe-ab0f1c3700a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364616897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2364616897
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3784507843
Short name T849
Test name
Test status
Simulation time 1629880919 ps
CPU time 10.47 seconds
Started May 09 01:30:12 PM PDT 24
Finished May 09 01:30:23 PM PDT 24
Peak memory 218568 kb
Host smart-667989d7-94a2-4abf-90d8-129dac9de87c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3784507843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3784507843
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4111392881
Short name T155
Test name
Test status
Simulation time 164885381540 ps
CPU time 419.54 seconds
Started May 09 01:30:12 PM PDT 24
Finished May 09 01:37:13 PM PDT 24
Peak memory 266048 kb
Host smart-265915d9-6663-4bfe-98f6-50417c4b1832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111392881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4111392881
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3459124403
Short name T568
Test name
Test status
Simulation time 3604909702 ps
CPU time 19.22 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:30 PM PDT 24
Peak memory 219848 kb
Host smart-03c5ad5b-e15c-4aff-853f-89966ee4f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459124403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3459124403
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4088790149
Short name T352
Test name
Test status
Simulation time 736547171 ps
CPU time 6.28 seconds
Started May 09 01:30:09 PM PDT 24
Finished May 09 01:30:17 PM PDT 24
Peak memory 216108 kb
Host smart-b02f8234-13d2-4f67-98dc-a5fce758217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088790149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4088790149
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2360285221
Short name T668
Test name
Test status
Simulation time 215218710 ps
CPU time 3.44 seconds
Started May 09 01:30:06 PM PDT 24
Finished May 09 01:30:10 PM PDT 24
Peak memory 216332 kb
Host smart-f37e2887-7821-4de7-969c-09111f50bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360285221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2360285221
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2600417254
Short name T775
Test name
Test status
Simulation time 52620496 ps
CPU time 0.82 seconds
Started May 09 01:30:08 PM PDT 24
Finished May 09 01:30:09 PM PDT 24
Peak memory 205708 kb
Host smart-c29aeb1e-db97-4a1e-815d-df8ca25dd75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600417254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2600417254
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1183247530
Short name T919
Test name
Test status
Simulation time 488945524 ps
CPU time 4.68 seconds
Started May 09 01:30:03 PM PDT 24
Finished May 09 01:30:08 PM PDT 24
Peak memory 217228 kb
Host smart-09232f0e-655c-4c74-af1a-4f324b5b5945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183247530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1183247530
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4073918796
Short name T462
Test name
Test status
Simulation time 42115131 ps
CPU time 0.73 seconds
Started May 09 01:30:15 PM PDT 24
Finished May 09 01:30:16 PM PDT 24
Peak memory 205288 kb
Host smart-0bac7cce-988c-4236-8343-955d0e60ba3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073918796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
073918796
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3455445228
Short name T933
Test name
Test status
Simulation time 109610043 ps
CPU time 2.3 seconds
Started May 09 01:30:14 PM PDT 24
Finished May 09 01:30:18 PM PDT 24
Peak memory 221028 kb
Host smart-7bdfe721-dbb8-48e7-b72a-9dd977eb8f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455445228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3455445228
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1715647633
Short name T832
Test name
Test status
Simulation time 24845719 ps
CPU time 0.76 seconds
Started May 09 01:30:10 PM PDT 24
Finished May 09 01:30:12 PM PDT 24
Peak memory 205828 kb
Host smart-450e41d0-6b4b-4b55-9c29-9e7f5934688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715647633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1715647633
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.535248111
Short name T746
Test name
Test status
Simulation time 154347510238 ps
CPU time 114.08 seconds
Started May 09 01:30:19 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 252872 kb
Host smart-cdbd843b-16f7-4e04-8d72-dc1cd9756ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535248111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.535248111
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1465935898
Short name T706
Test name
Test status
Simulation time 31944491853 ps
CPU time 92.65 seconds
Started May 09 01:30:17 PM PDT 24
Finished May 09 01:31:51 PM PDT 24
Peak memory 250156 kb
Host smart-6bab0074-01a7-4052-8dc4-b1bc3da701b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465935898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1465935898
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3441522484
Short name T319
Test name
Test status
Simulation time 56476897703 ps
CPU time 88.46 seconds
Started May 09 01:30:19 PM PDT 24
Finished May 09 01:31:48 PM PDT 24
Peak memory 249316 kb
Host smart-64c21647-3d43-40e5-bdac-900711246271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441522484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3441522484
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2499609250
Short name T529
Test name
Test status
Simulation time 773123743 ps
CPU time 17.6 seconds
Started May 09 01:30:17 PM PDT 24
Finished May 09 01:30:36 PM PDT 24
Peak memory 234568 kb
Host smart-f2960866-b70a-44be-b93f-4c54a58878d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499609250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2499609250
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2337125761
Short name T286
Test name
Test status
Simulation time 13230310404 ps
CPU time 34.54 seconds
Started May 09 01:30:19 PM PDT 24
Finished May 09 01:30:55 PM PDT 24
Peak memory 219400 kb
Host smart-f36dcb70-43ec-47f3-8157-6be41a2d475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337125761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2337125761
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1876382380
Short name T332
Test name
Test status
Simulation time 102164240 ps
CPU time 2.06 seconds
Started May 09 01:30:19 PM PDT 24
Finished May 09 01:30:22 PM PDT 24
Peak memory 215908 kb
Host smart-9271ad64-6363-4648-a5ff-ea7869bcb745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876382380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1876382380
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.891864895
Short name T422
Test name
Test status
Simulation time 666078211 ps
CPU time 5.79 seconds
Started May 09 01:30:17 PM PDT 24
Finished May 09 01:30:23 PM PDT 24
Peak memory 219484 kb
Host smart-54c1139a-04d1-439c-9d5a-449155a424d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891864895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
891864895
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2113349521
Short name T300
Test name
Test status
Simulation time 13852680450 ps
CPU time 10.49 seconds
Started May 09 01:30:08 PM PDT 24
Finished May 09 01:30:20 PM PDT 24
Peak memory 219684 kb
Host smart-224f1520-507b-479a-b45b-bb9a119d1f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113349521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2113349521
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1781886333
Short name T143
Test name
Test status
Simulation time 262159200 ps
CPU time 4.05 seconds
Started May 09 01:30:21 PM PDT 24
Finished May 09 01:30:26 PM PDT 24
Peak memory 218796 kb
Host smart-30a2bbef-7c72-47b7-9af2-c9a39819723d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781886333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1781886333
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3295079116
Short name T700
Test name
Test status
Simulation time 170303362 ps
CPU time 0.97 seconds
Started May 09 01:30:15 PM PDT 24
Finished May 09 01:30:17 PM PDT 24
Peak memory 206536 kb
Host smart-109accbc-b04f-4ebc-9195-e6f59c2271f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295079116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3295079116
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3492267520
Short name T811
Test name
Test status
Simulation time 2632628841 ps
CPU time 5.23 seconds
Started May 09 01:30:08 PM PDT 24
Finished May 09 01:30:14 PM PDT 24
Peak memory 216244 kb
Host smart-06c7f5d7-9427-4fb8-996b-740d02b54498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492267520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3492267520
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1790099947
Short name T564
Test name
Test status
Simulation time 2275112782 ps
CPU time 7.26 seconds
Started May 09 01:30:11 PM PDT 24
Finished May 09 01:30:19 PM PDT 24
Peak memory 216184 kb
Host smart-a2699c4a-e308-4e02-a105-27c921b7e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790099947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1790099947
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4251000028
Short name T350
Test name
Test status
Simulation time 32144989 ps
CPU time 0.69 seconds
Started May 09 01:30:13 PM PDT 24
Finished May 09 01:30:15 PM PDT 24
Peak memory 205480 kb
Host smart-eb74e86d-1a2c-4325-8fbd-7341f74c93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251000028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4251000028
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2097216633
Short name T951
Test name
Test status
Simulation time 25772134 ps
CPU time 0.77 seconds
Started May 09 01:30:11 PM PDT 24
Finished May 09 01:30:13 PM PDT 24
Peak memory 205708 kb
Host smart-044e3cab-d074-4f1c-8aae-6d1e22ee88f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097216633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2097216633
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1431580282
Short name T273
Test name
Test status
Simulation time 179770083 ps
CPU time 4.03 seconds
Started May 09 01:30:14 PM PDT 24
Finished May 09 01:30:19 PM PDT 24
Peak memory 218784 kb
Host smart-6e2221b1-5c00-461c-b2c6-5fc65c849f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431580282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1431580282
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1527366882
Short name T854
Test name
Test status
Simulation time 26879294 ps
CPU time 0.82 seconds
Started May 09 01:30:35 PM PDT 24
Finished May 09 01:30:38 PM PDT 24
Peak memory 205576 kb
Host smart-347a04d8-7c8b-4d6a-bb58-8ae74d119d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527366882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
527366882
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4021200823
Short name T213
Test name
Test status
Simulation time 241770157 ps
CPU time 2.88 seconds
Started May 09 01:30:18 PM PDT 24
Finished May 09 01:30:22 PM PDT 24
Peak memory 219380 kb
Host smart-e480bc1e-3692-422f-b9d5-1c97972078cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021200823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4021200823
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.125442443
Short name T758
Test name
Test status
Simulation time 18429098 ps
CPU time 0.79 seconds
Started May 09 01:30:18 PM PDT 24
Finished May 09 01:30:20 PM PDT 24
Peak memory 206836 kb
Host smart-810b7d10-a964-437d-bc46-5cbdf394a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125442443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.125442443
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3016737800
Short name T689
Test name
Test status
Simulation time 1936419740 ps
CPU time 35.02 seconds
Started May 09 01:30:26 PM PDT 24
Finished May 09 01:31:02 PM PDT 24
Peak memory 248620 kb
Host smart-b4952c76-ee60-4a76-8608-c21a24ff3906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016737800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3016737800
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3649749198
Short name T817
Test name
Test status
Simulation time 17497289643 ps
CPU time 98.85 seconds
Started May 09 01:30:35 PM PDT 24
Finished May 09 01:32:15 PM PDT 24
Peak memory 240628 kb
Host smart-78bf6080-961c-4a2a-922e-68d479dea072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649749198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3649749198
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2301003346
Short name T38
Test name
Test status
Simulation time 156419497335 ps
CPU time 354 seconds
Started May 09 01:30:34 PM PDT 24
Finished May 09 01:36:30 PM PDT 24
Peak memory 251468 kb
Host smart-70d8484f-7f74-49af-b7c2-cfd8438827da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301003346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2301003346
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1496858464
Short name T476
Test name
Test status
Simulation time 121869877 ps
CPU time 4.06 seconds
Started May 09 01:30:25 PM PDT 24
Finished May 09 01:30:29 PM PDT 24
Peak memory 232568 kb
Host smart-83106bb9-43ff-4006-b477-36c10439de10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496858464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1496858464
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2842168639
Short name T912
Test name
Test status
Simulation time 338544965 ps
CPU time 3.17 seconds
Started May 09 01:30:19 PM PDT 24
Finished May 09 01:30:23 PM PDT 24
Peak memory 233736 kb
Host smart-51938d9f-1a3c-4953-8b78-032add77b1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842168639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2842168639
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2760033060
Short name T573
Test name
Test status
Simulation time 1724097951 ps
CPU time 2.77 seconds
Started May 09 01:30:18 PM PDT 24
Finished May 09 01:30:22 PM PDT 24
Peak memory 217816 kb
Host smart-49c082e7-1138-4835-bc24-48cac6b01841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760033060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2760033060
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.644361424
Short name T436
Test name
Test status
Simulation time 34109021 ps
CPU time 2.44 seconds
Started May 09 01:30:16 PM PDT 24
Finished May 09 01:30:20 PM PDT 24
Peak memory 221352 kb
Host smart-9cccb422-80bd-41af-8dd7-d075059a78a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644361424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
644361424
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2986192000
Short name T757
Test name
Test status
Simulation time 421126908 ps
CPU time 2.33 seconds
Started May 09 01:30:13 PM PDT 24
Finished May 09 01:30:17 PM PDT 24
Peak memory 218592 kb
Host smart-db9b0628-8b97-4eb4-9c23-3faf0ff36f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986192000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2986192000
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.955938048
Short name T934
Test name
Test status
Simulation time 522853493 ps
CPU time 7.52 seconds
Started May 09 01:30:28 PM PDT 24
Finished May 09 01:30:36 PM PDT 24
Peak memory 219956 kb
Host smart-6f88f727-1d01-405a-a0e6-5ee968c27812
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955938048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.955938048
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3591823401
Short name T189
Test name
Test status
Simulation time 14485693360 ps
CPU time 119.72 seconds
Started May 09 01:30:23 PM PDT 24
Finished May 09 01:32:23 PM PDT 24
Peak memory 257328 kb
Host smart-86e33812-64c3-4ef7-97d8-9d2f633df81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591823401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3591823401
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.97373578
Short name T359
Test name
Test status
Simulation time 5115596452 ps
CPU time 32.77 seconds
Started May 09 01:30:17 PM PDT 24
Finished May 09 01:30:50 PM PDT 24
Peak memory 216244 kb
Host smart-7df0c2e3-36d8-4c29-b62a-e81a31e52268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97373578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.97373578
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1245165989
Short name T649
Test name
Test status
Simulation time 1988894859 ps
CPU time 7.37 seconds
Started May 09 01:30:16 PM PDT 24
Finished May 09 01:30:25 PM PDT 24
Peak memory 216068 kb
Host smart-0734da03-1472-48a4-a1f2-7caeccbba45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245165989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1245165989
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2761342449
Short name T537
Test name
Test status
Simulation time 64410835 ps
CPU time 3.32 seconds
Started May 09 01:30:17 PM PDT 24
Finished May 09 01:30:21 PM PDT 24
Peak memory 216180 kb
Host smart-25dfb7e4-c364-4f71-be60-c66d2f84379f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761342449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2761342449
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.424670915
Short name T433
Test name
Test status
Simulation time 54571569 ps
CPU time 0.82 seconds
Started May 09 01:30:19 PM PDT 24
Finished May 09 01:30:21 PM PDT 24
Peak memory 205660 kb
Host smart-45848eb2-32e6-4e6c-9d65-4734087a6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424670915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.424670915
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1634822253
Short name T776
Test name
Test status
Simulation time 912409988 ps
CPU time 6.72 seconds
Started May 09 01:30:18 PM PDT 24
Finished May 09 01:30:26 PM PDT 24
Peak memory 248788 kb
Host smart-749488e2-8bf3-4e98-abd0-83cf1067cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634822253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1634822253
Directory /workspace/9.spi_device_upload/latest
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