Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3575209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3908649

1

T1

3496

T3

874

T4

1689

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4175011	1			T1	3240		T2	1		T3	3
values[0x0]	1654328	1			T1	913		T3	420		T4	480
values[0x1]	1654519	1			T1	997		T3	456		T4	415

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2527084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4956774

1

T1

3814

T3

876

T4

1840

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28501	1			T1	19		T5	47		T8	86
valid_sources[0x01]	30208	1			T1	25		T4	3		T5	55
valid_sources[0x02]	28946	1			T1	25		T4	3		T5	58
valid_sources[0x03]	29448	1			T1	35		T4	10		T5	65
valid_sources[0x04]	27215	1			T1	10		T5	48		T8	112
valid_sources[0x05]	32091	1			T1	13		T4	16		T5	74
valid_sources[0x06]	27878	1			T1	33		T5	48		T8	110
valid_sources[0x07]	27393	1			T1	12		T4	3		T5	67
valid_sources[0x08]	26818	1			T1	20		T4	17		T5	69
valid_sources[0x09]	26979	1			T1	14		T4	14		T5	63
valid_sources[0x0a]	27087	1			T1	10		T4	3		T5	58
valid_sources[0x0b]	29473	1			T1	9		T4	16		T5	43
valid_sources[0x0c]	32146	1			T1	16		T4	4		T5	66
valid_sources[0x0d]	25663	1			T1	21		T5	43		T8	131
valid_sources[0x0e]	26673	1			T1	33		T4	26		T5	67
valid_sources[0x0f]	29258	1			T1	24		T5	55		T8	153
valid_sources[0x10]	24893	1			T1	10		T3	12		T5	55
valid_sources[0x11]	29913	1			T1	16		T3	1		T5	52
valid_sources[0x12]	28755	1			T1	16		T4	10		T5	53
valid_sources[0x13]	30521	1			T1	17		T5	79		T8	137
valid_sources[0x14]	29102	1			T1	47		T5	49		T8	99
valid_sources[0x15]	28620	1			T1	20		T3	32		T4	15
valid_sources[0x16]	33100	1			T1	24		T4	1		T5	61
valid_sources[0x17]	30430	1			T1	26		T4	19		T5	70
valid_sources[0x18]	27656	1			T1	29		T3	16		T5	58
valid_sources[0x19]	26077	1			T1	20		T5	68		T8	94
valid_sources[0x1a]	27937	1			T1	25		T4	13		T5	87
valid_sources[0x1b]	27030	1			T1	17		T5	48		T8	85
valid_sources[0x1c]	26244	1			T1	38		T5	47		T8	148
valid_sources[0x1d]	50876	1			T1	30		T5	79		T8	69
valid_sources[0x1e]	25492	1			T1	14		T4	10		T5	76
valid_sources[0x1f]	26410	1			T1	25		T4	5		T5	45
valid_sources[0x20]	37522	1			T1	17		T4	14		T5	59
valid_sources[0x21]	31504	1			T1	26		T4	23		T5	63
valid_sources[0x22]	27462	1			T1	30		T4	49		T5	53
valid_sources[0x23]	28772	1			T1	13		T4	22		T5	61
valid_sources[0x24]	41394	1			T1	19		T4	19		T5	66
valid_sources[0x25]	30942	1			T1	20		T4	1		T5	68
valid_sources[0x26]	24006	1			T1	13		T4	3		T5	59
valid_sources[0x27]	30241	1			T1	15		T4	11		T5	61
valid_sources[0x28]	25945	1			T1	28		T4	2		T5	64
valid_sources[0x29]	26861	1			T1	18		T4	21		T5	68
valid_sources[0x2a]	33425	1			T1	22		T4	36		T5	63
valid_sources[0x2b]	25528	1			T1	25		T3	50		T5	36
valid_sources[0x2c]	35062	1			T1	9		T3	9		T4	5
valid_sources[0x2d]	29212	1			T1	23		T5	52		T8	76
valid_sources[0x2e]	29052	1			T1	24		T4	5		T5	51
valid_sources[0x2f]	30434	1			T1	13		T5	67		T8	82
valid_sources[0x30]	27860	1			T1	27		T4	19		T5	73
valid_sources[0x31]	33550	1			T1	22		T4	1		T5	76
valid_sources[0x32]	29525	1			T1	32		T4	3		T5	42
valid_sources[0x33]	30324	1			T1	21		T4	8		T5	61
valid_sources[0x34]	28927	1			T1	22		T4	7		T5	40
valid_sources[0x35]	33160	1			T1	23		T5	50		T8	101
valid_sources[0x36]	29600	1			T1	15		T3	17		T4	8
valid_sources[0x37]	25602	1			T1	12		T5	62		T8	99
valid_sources[0x38]	27125	1			T1	20		T5	71		T8	105
valid_sources[0x39]	27724	1			T1	15		T4	16		T5	41
valid_sources[0x3a]	27355	1			T1	18		T4	6		T5	41
valid_sources[0x3b]	29198	1			T1	17		T4	8		T5	56
valid_sources[0x3c]	29384	1			T1	13		T4	4		T5	56
valid_sources[0x3d]	27261	1			T1	20		T5	50		T8	76
valid_sources[0x3e]	30925	1			T1	35		T4	1		T5	70
valid_sources[0x3f]	29280	1			T1	30		T4	4		T5	74
valid_sources[0x40]	25690	1			T1	15		T5	64		T8	136
valid_sources[0x41]	26298	1			T1	38		T3	48		T5	37
valid_sources[0x42]	27786	1			T1	26		T3	1		T4	8
valid_sources[0x43]	30472	1			T1	22		T3	10		T4	13
valid_sources[0x44]	29949	1			T1	14		T3	1		T4	9
valid_sources[0x45]	28974	1			T1	26		T3	3		T4	9
valid_sources[0x46]	28162	1			T1	19		T5	41		T8	84
valid_sources[0x47]	26780	1			T1	6		T4	22		T5	60
valid_sources[0x48]	29532	1			T1	31		T4	19		T5	67
valid_sources[0x49]	26405	1			T1	12		T4	13		T5	93
valid_sources[0x4a]	28775	1			T1	20		T4	8		T5	54
valid_sources[0x4b]	29850	1			T1	25		T4	5		T5	46
valid_sources[0x4c]	28584	1			T1	31		T5	55		T8	107
valid_sources[0x4d]	27909	1			T1	20		T4	8		T5	76
valid_sources[0x4e]	25580	1			T1	32		T3	6		T4	24
valid_sources[0x4f]	29274	1			T1	7		T4	7		T5	47
valid_sources[0x50]	26764	1			T1	23		T4	3		T5	53
valid_sources[0x51]	29042	1			T1	24		T4	8		T5	48
valid_sources[0x52]	25427	1			T1	12		T4	2		T5	69
valid_sources[0x53]	26234	1			T1	27		T4	21		T5	39
valid_sources[0x54]	30716	1			T1	12		T4	3		T5	73
valid_sources[0x55]	26426	1			T1	38		T5	37		T8	99
valid_sources[0x56]	30973	1			T1	25		T3	2		T4	26
valid_sources[0x57]	25704	1			T1	15		T3	1		T4	2
valid_sources[0x58]	57925	1			T1	20		T3	5		T4	16
valid_sources[0x59]	27646	1			T1	29		T3	12		T4	9
valid_sources[0x5a]	28411	1			T1	22		T4	21		T5	74
valid_sources[0x5b]	27302	1			T1	28		T4	4		T5	40
valid_sources[0x5c]	28151	1			T1	14		T4	7		T5	62
valid_sources[0x5d]	34407	1			T1	21		T5	43		T6	3
valid_sources[0x5e]	31500	1			T1	15		T4	10		T5	74
valid_sources[0x5f]	40110	1			T1	24		T4	16		T5	73
valid_sources[0x60]	26806	1			T1	15		T4	13		T5	38
valid_sources[0x61]	32200	1			T1	12		T4	12		T5	49
valid_sources[0x62]	26718	1			T1	8		T4	23		T5	33
valid_sources[0x63]	33698	1			T1	16		T4	30		T5	49
valid_sources[0x64]	29295	1			T1	18		T4	6		T5	50
valid_sources[0x65]	27910	1			T1	15		T4	9		T5	49
valid_sources[0x66]	28978	1			T1	27		T4	3		T5	48
valid_sources[0x67]	25982	1			T1	30		T4	3		T5	45
valid_sources[0x68]	28206	1			T1	30		T4	19		T5	63
valid_sources[0x69]	26781	1			T1	15		T4	17		T5	47
valid_sources[0x6a]	28572	1			T1	7		T4	4		T5	79
valid_sources[0x6b]	26558	1			T1	33		T4	1		T5	57
valid_sources[0x6c]	26789	1			T1	14		T4	5		T5	50
valid_sources[0x6d]	31080	1			T1	24		T3	9		T4	9
valid_sources[0x6e]	30223	1			T1	16		T5	38		T8	82
valid_sources[0x6f]	62662	1			T1	28		T5	65		T8	78
valid_sources[0x70]	31802	1			T1	27		T3	19		T4	47
valid_sources[0x71]	25584	1			T1	9		T4	2		T5	71
valid_sources[0x72]	27922	1			T1	11		T3	4		T4	32
valid_sources[0x73]	26432	1			T1	27		T3	6		T5	85
valid_sources[0x74]	29924	1			T1	19		T4	5		T5	84
valid_sources[0x75]	25274	1			T1	23		T4	20		T5	44
valid_sources[0x76]	26894	1			T1	15		T3	7		T4	7
valid_sources[0x77]	28951	1			T1	16		T4	20		T5	65
valid_sources[0x78]	30424	1			T1	11		T5	52		T8	146
valid_sources[0x79]	28068	1			T1	7		T3	5		T4	21
valid_sources[0x7a]	28499	1			T1	9		T4	22		T5	46
valid_sources[0x7b]	30350	1			T1	14		T4	8		T5	66
valid_sources[0x7c]	31773	1			T1	24		T5	60		T8	109
valid_sources[0x7d]	28665	1			T1	24		T4	4		T5	41
valid_sources[0x7e]	30213	1			T1	32		T3	34		T4	1
valid_sources[0x7f]	27775	1			T1	17		T4	22		T5	46
valid_sources[0x80]	32581	1			T1	17		T4	4		T5	61

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

938095

1

T1

1592

T4

801

T5

825

values[0x0]

all_enables

biggest_size

1497111

1

T1

910

T3

419

T4

478

values[0x1]

all_enables

biggest_size

1473443

1

T1

994

T3

455

T4

410