Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3597869

1

T1

1654

T2

1

T3

5

full_word

3910005

1

T1

3496

T3

874

T4

1689

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7507514	1			T1	5150		T2	1		T3	879
auto[TlIntgErrCmd]	128	1			T89	7		T88	5		T90	3
auto[TlIntgErrData]	120	1			T89	7		T88	1		T90	6
auto[TlIntgErrBoth]	112	1			T89	6		T88	4		T90	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4178639

1

T1

3240

T2

1

T3

3

auto[1]

3329235

1

T1

1910

T3

876

T4

895

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3240098	1			T1	1648		T2	1		T3	3
auto[TlIntgErrNone]	partial	auto[1]	357446	1			T1	6		T3	2		T4	7
auto[TlIntgErrNone]	full_word	auto[0]	938395	1			T1	1592		T4	801		T5	825
auto[TlIntgErrNone]	full_word	auto[1]	2971575	1			T1	1904		T3	874		T4	888
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T89	3		T88	2		T90	1
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T89	4		T88	3		T90	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T260	1		T261	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T144	1		T257	2		T259	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T89	3		T90	3		T256	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T89	3		T88	1		T90	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T256	2		T258	1		T260	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T89	1		T257	1		T259	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T89	2		T256	3		T144	2
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T89	4		T88	3		T90	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T259	1		T262	2		T263	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T88	1		T257	2		T262	3