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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.92 98.30 94.11 98.61 89.36 97.06 95.83 98.17


Total test records in report: 1081
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T817 /workspace/coverage/default/35.spi_device_read_buffer_direct.134833378 May 12 01:03:54 PM PDT 24 May 12 01:03:59 PM PDT 24 143190798 ps
T818 /workspace/coverage/default/8.spi_device_flash_and_tpm.570887867 May 12 01:02:01 PM PDT 24 May 12 01:02:51 PM PDT 24 10152712612 ps
T250 /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3962268447 May 12 01:04:09 PM PDT 24 May 12 01:06:21 PM PDT 24 42877839198 ps
T819 /workspace/coverage/default/6.spi_device_cfg_cmd.1843335312 May 12 01:02:02 PM PDT 24 May 12 01:02:07 PM PDT 24 3296821800 ps
T820 /workspace/coverage/default/1.spi_device_flash_and_tpm.3009630646 May 12 01:01:27 PM PDT 24 May 12 01:01:30 PM PDT 24 901752080 ps
T821 /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1540453149 May 12 01:02:27 PM PDT 24 May 12 01:02:36 PM PDT 24 12495474939 ps
T245 /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1959867647 May 12 01:03:32 PM PDT 24 May 12 01:03:37 PM PDT 24 666911811 ps
T822 /workspace/coverage/default/29.spi_device_read_buffer_direct.1385192250 May 12 01:03:32 PM PDT 24 May 12 01:03:43 PM PDT 24 4588251211 ps
T823 /workspace/coverage/default/7.spi_device_mailbox.1150006861 May 12 01:01:59 PM PDT 24 May 12 01:02:20 PM PDT 24 23803805018 ps
T824 /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2729548717 May 12 01:03:24 PM PDT 24 May 12 01:03:31 PM PDT 24 4038208651 ps
T825 /workspace/coverage/default/3.spi_device_cfg_cmd.1586531563 May 12 01:01:38 PM PDT 24 May 12 01:01:43 PM PDT 24 943453250 ps
T826 /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2198425135 May 12 01:02:55 PM PDT 24 May 12 01:03:02 PM PDT 24 1656033388 ps
T827 /workspace/coverage/default/42.spi_device_mailbox.2350168498 May 12 01:04:18 PM PDT 24 May 12 01:04:26 PM PDT 24 1626784211 ps
T828 /workspace/coverage/default/20.spi_device_flash_mode.2624388204 May 12 01:02:56 PM PDT 24 May 12 01:03:11 PM PDT 24 543688346 ps
T829 /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1762424091 May 12 01:04:04 PM PDT 24 May 12 01:04:08 PM PDT 24 752068731 ps
T830 /workspace/coverage/default/25.spi_device_flash_and_tpm.211929553 May 12 01:03:15 PM PDT 24 May 12 01:04:55 PM PDT 24 36959918479 ps
T244 /workspace/coverage/default/11.spi_device_flash_and_tpm.1294938458 May 12 01:02:13 PM PDT 24 May 12 01:04:59 PM PDT 24 15337217904 ps
T831 /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2428189839 May 12 01:02:32 PM PDT 24 May 12 01:02:35 PM PDT 24 765572014 ps
T832 /workspace/coverage/default/11.spi_device_alert_test.2130402680 May 12 01:02:16 PM PDT 24 May 12 01:02:18 PM PDT 24 50502305 ps
T833 /workspace/coverage/default/16.spi_device_tpm_all.3990904550 May 12 01:02:33 PM PDT 24 May 12 01:02:47 PM PDT 24 3229464055 ps
T834 /workspace/coverage/default/28.spi_device_flash_and_tpm.1474659602 May 12 01:03:27 PM PDT 24 May 12 01:05:05 PM PDT 24 5331903229 ps
T835 /workspace/coverage/default/48.spi_device_mailbox.2176140680 May 12 01:04:41 PM PDT 24 May 12 01:04:44 PM PDT 24 209334597 ps
T836 /workspace/coverage/default/9.spi_device_tpm_sts_read.290903020 May 12 01:02:02 PM PDT 24 May 12 01:02:04 PM PDT 24 122140240 ps
T837 /workspace/coverage/default/43.spi_device_read_buffer_direct.2953320164 May 12 01:04:23 PM PDT 24 May 12 01:04:28 PM PDT 24 775135107 ps
T838 /workspace/coverage/default/40.spi_device_alert_test.556719547 May 12 01:04:16 PM PDT 24 May 12 01:04:18 PM PDT 24 46419227 ps
T131 /workspace/coverage/default/12.spi_device_stress_all.3250370817 May 12 01:02:22 PM PDT 24 May 12 01:05:05 PM PDT 24 12981975372 ps
T839 /workspace/coverage/default/43.spi_device_mailbox.1856095613 May 12 01:04:19 PM PDT 24 May 12 01:05:59 PM PDT 24 27391060957 ps
T840 /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2055110229 May 12 01:02:40 PM PDT 24 May 12 01:04:26 PM PDT 24 41984975677 ps
T841 /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3603929961 May 12 01:02:11 PM PDT 24 May 12 01:02:18 PM PDT 24 5119959380 ps
T842 /workspace/coverage/default/30.spi_device_flash_mode.3458314982 May 12 01:03:33 PM PDT 24 May 12 01:03:58 PM PDT 24 1547911638 ps
T843 /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.530163039 May 12 01:01:36 PM PDT 24 May 12 01:01:43 PM PDT 24 3385124458 ps
T844 /workspace/coverage/default/25.spi_device_tpm_all.486867691 May 12 01:03:11 PM PDT 24 May 12 01:03:24 PM PDT 24 8021169755 ps
T249 /workspace/coverage/default/14.spi_device_stress_all.1949055870 May 12 01:02:27 PM PDT 24 May 12 01:05:00 PM PDT 24 15532151292 ps
T845 /workspace/coverage/default/38.spi_device_read_buffer_direct.3899316826 May 12 01:04:05 PM PDT 24 May 12 01:04:09 PM PDT 24 74447974 ps
T846 /workspace/coverage/default/21.spi_device_alert_test.2565861487 May 12 01:03:00 PM PDT 24 May 12 01:03:01 PM PDT 24 17136551 ps
T847 /workspace/coverage/default/10.spi_device_tpm_all.1040669639 May 12 01:02:13 PM PDT 24 May 12 01:02:18 PM PDT 24 266382785 ps
T223 /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3109335403 May 12 01:04:00 PM PDT 24 May 12 01:10:19 PM PDT 24 37661319347 ps
T848 /workspace/coverage/default/26.spi_device_mailbox.3818743145 May 12 01:03:15 PM PDT 24 May 12 01:03:24 PM PDT 24 1015226476 ps
T849 /workspace/coverage/default/46.spi_device_cfg_cmd.916446722 May 12 01:04:32 PM PDT 24 May 12 01:04:35 PM PDT 24 172025598 ps
T850 /workspace/coverage/default/37.spi_device_flash_all.860023059 May 12 01:04:01 PM PDT 24 May 12 01:04:59 PM PDT 24 25055897193 ps
T851 /workspace/coverage/default/35.spi_device_cfg_cmd.2371513725 May 12 01:03:55 PM PDT 24 May 12 01:03:58 PM PDT 24 147074370 ps
T852 /workspace/coverage/default/41.spi_device_tpm_all.2539331051 May 12 01:04:16 PM PDT 24 May 12 01:04:41 PM PDT 24 12946565651 ps
T853 /workspace/coverage/default/48.spi_device_flash_mode.2019098604 May 12 01:04:43 PM PDT 24 May 12 01:04:55 PM PDT 24 970436926 ps
T854 /workspace/coverage/default/13.spi_device_tpm_sts_read.3051410784 May 12 01:02:22 PM PDT 24 May 12 01:02:24 PM PDT 24 74819560 ps
T855 /workspace/coverage/default/15.spi_device_csb_read.1448257923 May 12 01:02:30 PM PDT 24 May 12 01:02:31 PM PDT 24 19385082 ps
T856 /workspace/coverage/default/39.spi_device_intercept.1931534874 May 12 01:04:06 PM PDT 24 May 12 01:04:11 PM PDT 24 109789353 ps
T857 /workspace/coverage/default/45.spi_device_alert_test.2822834586 May 12 01:04:30 PM PDT 24 May 12 01:04:31 PM PDT 24 16667821 ps
T858 /workspace/coverage/default/20.spi_device_tpm_rw.3819580187 May 12 01:02:54 PM PDT 24 May 12 01:02:56 PM PDT 24 12912691 ps
T859 /workspace/coverage/default/47.spi_device_intercept.2405881405 May 12 01:04:40 PM PDT 24 May 12 01:04:43 PM PDT 24 304188325 ps
T860 /workspace/coverage/default/46.spi_device_flash_mode.946040579 May 12 01:04:34 PM PDT 24 May 12 01:04:40 PM PDT 24 568753682 ps
T861 /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4055087417 May 12 01:04:02 PM PDT 24 May 12 01:04:27 PM PDT 24 9083459611 ps
T862 /workspace/coverage/default/31.spi_device_upload.2665490645 May 12 01:03:34 PM PDT 24 May 12 01:03:38 PM PDT 24 80532805 ps
T863 /workspace/coverage/default/6.spi_device_flash_mode.2836611181 May 12 01:01:53 PM PDT 24 May 12 01:01:57 PM PDT 24 142206751 ps
T864 /workspace/coverage/default/22.spi_device_tpm_all.869440887 May 12 01:02:59 PM PDT 24 May 12 01:03:24 PM PDT 24 14360358292 ps
T865 /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.341691125 May 12 01:04:25 PM PDT 24 May 12 01:04:41 PM PDT 24 9922085171 ps
T866 /workspace/coverage/default/36.spi_device_tpm_all.3905485587 May 12 01:03:57 PM PDT 24 May 12 01:03:58 PM PDT 24 35042401 ps
T867 /workspace/coverage/default/19.spi_device_tpm_sts_read.4286957119 May 12 01:02:50 PM PDT 24 May 12 01:02:51 PM PDT 24 123346495 ps
T868 /workspace/coverage/default/12.spi_device_tpm_all.1621632115 May 12 01:02:17 PM PDT 24 May 12 01:02:35 PM PDT 24 16473261266 ps
T869 /workspace/coverage/default/41.spi_device_flash_all.3305261396 May 12 01:04:20 PM PDT 24 May 12 01:05:37 PM PDT 24 34717372029 ps
T870 /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2965900057 May 12 01:01:52 PM PDT 24 May 12 01:01:57 PM PDT 24 485130211 ps
T871 /workspace/coverage/default/21.spi_device_tpm_all.938644567 May 12 01:02:55 PM PDT 24 May 12 01:03:50 PM PDT 24 17877365405 ps
T872 /workspace/coverage/default/24.spi_device_intercept.4112875422 May 12 01:03:07 PM PDT 24 May 12 01:03:09 PM PDT 24 106274222 ps
T873 /workspace/coverage/default/40.spi_device_stress_all.2438230755 May 12 01:04:16 PM PDT 24 May 12 01:06:17 PM PDT 24 5884710685 ps
T874 /workspace/coverage/default/36.spi_device_flash_all.3063951268 May 12 01:03:56 PM PDT 24 May 12 01:04:50 PM PDT 24 31573929509 ps
T875 /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3554413937 May 12 01:01:53 PM PDT 24 May 12 01:01:59 PM PDT 24 306190365 ps
T876 /workspace/coverage/default/39.spi_device_read_buffer_direct.3091031831 May 12 01:04:19 PM PDT 24 May 12 01:04:25 PM PDT 24 405936021 ps
T877 /workspace/coverage/default/49.spi_device_tpm_rw.1021204820 May 12 01:04:45 PM PDT 24 May 12 01:04:47 PM PDT 24 83320782 ps
T878 /workspace/coverage/default/29.spi_device_flash_all.3719066049 May 12 01:03:32 PM PDT 24 May 12 01:06:15 PM PDT 24 19465813123 ps
T879 /workspace/coverage/default/35.spi_device_mailbox.3269834088 May 12 01:03:56 PM PDT 24 May 12 01:05:11 PM PDT 24 6902195333 ps
T880 /workspace/coverage/default/43.spi_device_intercept.1656966915 May 12 01:04:19 PM PDT 24 May 12 01:04:25 PM PDT 24 348766473 ps
T881 /workspace/coverage/default/32.spi_device_csb_read.3527981025 May 12 01:03:40 PM PDT 24 May 12 01:03:41 PM PDT 24 49337517 ps
T882 /workspace/coverage/default/47.spi_device_stress_all.3931059172 May 12 01:04:38 PM PDT 24 May 12 01:07:18 PM PDT 24 15428490404 ps
T304 /workspace/coverage/default/22.spi_device_flash_mode.3001686648 May 12 01:03:03 PM PDT 24 May 12 01:03:09 PM PDT 24 231740039 ps
T243 /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2420384411 May 12 01:02:43 PM PDT 24 May 12 01:12:33 PM PDT 24 72469377276 ps
T883 /workspace/coverage/default/1.spi_device_tpm_sts_read.2952349784 May 12 01:01:30 PM PDT 24 May 12 01:01:31 PM PDT 24 328145515 ps
T884 /workspace/coverage/default/28.spi_device_mailbox.3978681449 May 12 01:03:27 PM PDT 24 May 12 01:03:32 PM PDT 24 122369382 ps
T885 /workspace/coverage/default/42.spi_device_alert_test.853772990 May 12 01:04:19 PM PDT 24 May 12 01:04:21 PM PDT 24 75124254 ps
T886 /workspace/coverage/default/33.spi_device_cfg_cmd.131718593 May 12 01:03:53 PM PDT 24 May 12 01:04:04 PM PDT 24 1696524040 ps
T887 /workspace/coverage/default/48.spi_device_csb_read.3500445651 May 12 01:04:40 PM PDT 24 May 12 01:04:41 PM PDT 24 81066165 ps
T888 /workspace/coverage/default/20.spi_device_flash_and_tpm.2389254532 May 12 01:02:56 PM PDT 24 May 12 01:03:58 PM PDT 24 5046239483 ps
T889 /workspace/coverage/default/48.spi_device_intercept.1076296022 May 12 01:04:40 PM PDT 24 May 12 01:04:50 PM PDT 24 3784040851 ps
T890 /workspace/coverage/default/40.spi_device_intercept.461392930 May 12 01:04:14 PM PDT 24 May 12 01:04:27 PM PDT 24 1197612069 ps
T891 /workspace/coverage/default/28.spi_device_tpm_sts_read.3249748393 May 12 01:03:24 PM PDT 24 May 12 01:03:26 PM PDT 24 137977180 ps
T892 /workspace/coverage/default/48.spi_device_alert_test.1148389361 May 12 01:04:48 PM PDT 24 May 12 01:04:49 PM PDT 24 31845141 ps
T232 /workspace/coverage/default/19.spi_device_flash_all.1698357089 May 12 01:02:50 PM PDT 24 May 12 01:03:37 PM PDT 24 6038860530 ps
T893 /workspace/coverage/default/19.spi_device_tpm_all.1154743005 May 12 01:02:49 PM PDT 24 May 12 01:03:24 PM PDT 24 48308036704 ps
T894 /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3835998483 May 12 01:03:24 PM PDT 24 May 12 01:03:27 PM PDT 24 74055180 ps
T895 /workspace/coverage/default/3.spi_device_intercept.903019509 May 12 01:01:37 PM PDT 24 May 12 01:01:45 PM PDT 24 2277867878 ps
T896 /workspace/coverage/default/6.spi_device_tpm_rw.3216460568 May 12 01:02:02 PM PDT 24 May 12 01:02:04 PM PDT 24 451832330 ps
T897 /workspace/coverage/default/33.spi_device_flash_all.1139318137 May 12 01:03:52 PM PDT 24 May 12 01:04:16 PM PDT 24 14885444573 ps
T898 /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1472612518 May 12 01:02:44 PM PDT 24 May 12 01:02:51 PM PDT 24 458156173 ps
T899 /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2154042026 May 12 01:04:17 PM PDT 24 May 12 01:05:58 PM PDT 24 5599371233 ps
T900 /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2432213595 May 12 01:01:31 PM PDT 24 May 12 01:01:35 PM PDT 24 986135422 ps
T901 /workspace/coverage/default/25.spi_device_stress_all.2354936546 May 12 01:03:16 PM PDT 24 May 12 01:05:04 PM PDT 24 18558558857 ps
T902 /workspace/coverage/default/30.spi_device_tpm_sts_read.1170658431 May 12 01:03:32 PM PDT 24 May 12 01:03:33 PM PDT 24 282666396 ps
T903 /workspace/coverage/default/32.spi_device_mailbox.3575447815 May 12 01:03:47 PM PDT 24 May 12 01:05:16 PM PDT 24 62730253492 ps
T904 /workspace/coverage/default/44.spi_device_tpm_rw.267957189 May 12 01:04:22 PM PDT 24 May 12 01:04:25 PM PDT 24 110173762 ps
T251 /workspace/coverage/default/47.spi_device_flash_and_tpm.1993984706 May 12 01:04:40 PM PDT 24 May 12 01:14:49 PM PDT 24 217549397069 ps
T905 /workspace/coverage/default/9.spi_device_flash_all.1268337343 May 12 01:02:13 PM PDT 24 May 12 01:09:01 PM PDT 24 118186651682 ps
T906 /workspace/coverage/default/5.spi_device_alert_test.2315056247 May 12 01:01:48 PM PDT 24 May 12 01:01:50 PM PDT 24 15031824 ps
T907 /workspace/coverage/default/6.spi_device_mailbox.1703436552 May 12 01:01:53 PM PDT 24 May 12 01:02:57 PM PDT 24 7048912905 ps
T908 /workspace/coverage/default/32.spi_device_stress_all.330818568 May 12 01:03:44 PM PDT 24 May 12 01:03:45 PM PDT 24 41547467 ps
T909 /workspace/coverage/default/3.spi_device_read_buffer_direct.356236386 May 12 01:01:38 PM PDT 24 May 12 01:01:51 PM PDT 24 16379711522 ps
T910 /workspace/coverage/default/23.spi_device_pass_cmd_filtering.680331983 May 12 01:03:03 PM PDT 24 May 12 01:03:43 PM PDT 24 30139769663 ps
T911 /workspace/coverage/default/33.spi_device_flash_mode.549781115 May 12 01:03:53 PM PDT 24 May 12 01:04:52 PM PDT 24 3531671791 ps
T912 /workspace/coverage/default/8.spi_device_tpm_sts_read.1809677349 May 12 01:01:58 PM PDT 24 May 12 01:01:59 PM PDT 24 102582794 ps
T913 /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2307295902 May 12 01:03:16 PM PDT 24 May 12 01:03:43 PM PDT 24 9634669664 ps
T914 /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2452568473 May 12 01:04:21 PM PDT 24 May 12 01:04:44 PM PDT 24 13672188501 ps
T915 /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2910627558 May 12 01:03:41 PM PDT 24 May 12 01:03:59 PM PDT 24 27253874359 ps
T242 /workspace/coverage/default/45.spi_device_flash_all.3306969328 May 12 01:04:28 PM PDT 24 May 12 01:11:49 PM PDT 24 238618943781 ps
T916 /workspace/coverage/default/14.spi_device_alert_test.3052422133 May 12 01:02:29 PM PDT 24 May 12 01:02:30 PM PDT 24 45897515 ps
T917 /workspace/coverage/default/29.spi_device_tpm_all.4158850997 May 12 01:03:30 PM PDT 24 May 12 01:04:01 PM PDT 24 16860433890 ps
T918 /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4243972718 May 12 01:03:26 PM PDT 24 May 12 01:03:53 PM PDT 24 117076113895 ps
T227 /workspace/coverage/default/17.spi_device_stress_all.1564839691 May 12 01:02:42 PM PDT 24 May 12 01:18:50 PM PDT 24 372461709124 ps
T919 /workspace/coverage/default/25.spi_device_tpm_rw.3216289028 May 12 01:03:10 PM PDT 24 May 12 01:03:12 PM PDT 24 11578508 ps
T920 /workspace/coverage/default/17.spi_device_mailbox.1727174080 May 12 01:02:40 PM PDT 24 May 12 01:02:55 PM PDT 24 2976867989 ps
T921 /workspace/coverage/default/48.spi_device_cfg_cmd.1253070684 May 12 01:04:41 PM PDT 24 May 12 01:04:44 PM PDT 24 31870557 ps
T922 /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3678371828 May 12 01:03:56 PM PDT 24 May 12 01:04:07 PM PDT 24 2451094404 ps
T923 /workspace/coverage/default/17.spi_device_upload.3751694967 May 12 01:02:44 PM PDT 24 May 12 01:02:48 PM PDT 24 221737882 ps
T924 /workspace/coverage/default/14.spi_device_upload.1551358345 May 12 01:02:27 PM PDT 24 May 12 01:02:37 PM PDT 24 1803669784 ps
T925 /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1436286977 May 12 01:04:31 PM PDT 24 May 12 01:04:34 PM PDT 24 150028596 ps
T926 /workspace/coverage/default/41.spi_device_upload.3058395693 May 12 01:04:13 PM PDT 24 May 12 01:04:35 PM PDT 24 25156032703 ps
T927 /workspace/coverage/default/18.spi_device_cfg_cmd.3586300680 May 12 01:02:43 PM PDT 24 May 12 01:02:51 PM PDT 24 2136661385 ps
T928 /workspace/coverage/default/39.spi_device_stress_all.1766367554 May 12 01:04:12 PM PDT 24 May 12 01:06:46 PM PDT 24 43534551758 ps
T929 /workspace/coverage/default/19.spi_device_csb_read.424605557 May 12 01:02:48 PM PDT 24 May 12 01:02:50 PM PDT 24 15498608 ps
T930 /workspace/coverage/default/21.spi_device_stress_all.2520084463 May 12 01:03:00 PM PDT 24 May 12 01:04:42 PM PDT 24 17000985944 ps
T931 /workspace/coverage/default/42.spi_device_read_buffer_direct.4121864492 May 12 01:04:20 PM PDT 24 May 12 01:04:25 PM PDT 24 236508999 ps
T932 /workspace/coverage/default/28.spi_device_tpm_rw.2410782244 May 12 01:03:21 PM PDT 24 May 12 01:03:23 PM PDT 24 263089561 ps
T933 /workspace/coverage/default/38.spi_device_tpm_sts_read.2616478543 May 12 01:04:07 PM PDT 24 May 12 01:04:08 PM PDT 24 35803641 ps
T934 /workspace/coverage/default/9.spi_device_alert_test.3133536290 May 12 01:02:10 PM PDT 24 May 12 01:02:11 PM PDT 24 52429892 ps
T935 /workspace/coverage/default/32.spi_device_flash_mode.1996642954 May 12 01:03:41 PM PDT 24 May 12 01:03:48 PM PDT 24 140548910 ps
T936 /workspace/coverage/default/23.spi_device_flash_mode.3959556215 May 12 01:03:07 PM PDT 24 May 12 01:03:10 PM PDT 24 608438308 ps
T937 /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.800846750 May 12 01:03:46 PM PDT 24 May 12 01:04:03 PM PDT 24 16163269137 ps
T938 /workspace/coverage/default/32.spi_device_read_buffer_direct.4251244900 May 12 01:03:41 PM PDT 24 May 12 01:03:48 PM PDT 24 3841442190 ps
T939 /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2042634343 May 12 01:02:23 PM PDT 24 May 12 01:02:48 PM PDT 24 52511985952 ps
T940 /workspace/coverage/default/13.spi_device_tpm_rw.2024766532 May 12 01:02:21 PM PDT 24 May 12 01:02:23 PM PDT 24 111097094 ps
T941 /workspace/coverage/default/18.spi_device_flash_mode.533882062 May 12 01:02:44 PM PDT 24 May 12 01:02:52 PM PDT 24 288666080 ps
T942 /workspace/coverage/default/37.spi_device_tpm_all.3719316361 May 12 01:04:01 PM PDT 24 May 12 01:04:15 PM PDT 24 10217483516 ps
T253 /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4003766378 May 12 01:03:47 PM PDT 24 May 12 01:04:04 PM PDT 24 27569614539 ps
T943 /workspace/coverage/default/22.spi_device_tpm_rw.2446821054 May 12 01:03:02 PM PDT 24 May 12 01:03:03 PM PDT 24 53057731 ps
T944 /workspace/coverage/default/9.spi_device_flash_mode.4196228277 May 12 01:02:11 PM PDT 24 May 12 01:02:24 PM PDT 24 2957182333 ps
T945 /workspace/coverage/default/0.spi_device_flash_all.3937473553 May 12 01:01:23 PM PDT 24 May 12 01:03:50 PM PDT 24 20713573748 ps
T946 /workspace/coverage/default/25.spi_device_flash_all.429688902 May 12 01:03:11 PM PDT 24 May 12 01:04:00 PM PDT 24 4367107869 ps
T947 /workspace/coverage/default/13.spi_device_alert_test.1080168312 May 12 01:02:22 PM PDT 24 May 12 01:02:24 PM PDT 24 26299368 ps
T948 /workspace/coverage/default/35.spi_device_stress_all.2734208368 May 12 01:04:03 PM PDT 24 May 12 01:14:34 PM PDT 24 67398471924 ps
T271 /workspace/coverage/default/37.spi_device_intercept.3934962932 May 12 01:04:01 PM PDT 24 May 12 01:04:26 PM PDT 24 18229322717 ps
T949 /workspace/coverage/default/23.spi_device_mailbox.3919157119 May 12 01:03:06 PM PDT 24 May 12 01:03:22 PM PDT 24 15262938555 ps
T950 /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2448672415 May 12 01:04:43 PM PDT 24 May 12 01:04:50 PM PDT 24 1242548535 ps
T951 /workspace/coverage/default/5.spi_device_mailbox.4149666082 May 12 01:01:48 PM PDT 24 May 12 01:02:14 PM PDT 24 4359127870 ps
T952 /workspace/coverage/default/32.spi_device_alert_test.2634688543 May 12 01:03:41 PM PDT 24 May 12 01:03:43 PM PDT 24 50024571 ps
T953 /workspace/coverage/default/14.spi_device_cfg_cmd.1412384648 May 12 01:02:28 PM PDT 24 May 12 01:02:33 PM PDT 24 776489181 ps
T954 /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1547324255 May 12 01:03:17 PM PDT 24 May 12 01:03:36 PM PDT 24 6791156814 ps
T955 /workspace/coverage/default/23.spi_device_read_buffer_direct.2651714583 May 12 01:03:05 PM PDT 24 May 12 01:03:17 PM PDT 24 2168522338 ps
T956 /workspace/coverage/default/34.spi_device_flash_all.945291307 May 12 01:03:53 PM PDT 24 May 12 01:07:07 PM PDT 24 95170681670 ps
T957 /workspace/coverage/default/11.spi_device_csb_read.1264804437 May 12 01:02:12 PM PDT 24 May 12 01:02:13 PM PDT 24 13590746 ps
T958 /workspace/coverage/default/29.spi_device_upload.715852842 May 12 01:03:26 PM PDT 24 May 12 01:03:30 PM PDT 24 322277619 ps
T959 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3462800475 May 12 12:57:57 PM PDT 24 May 12 12:57:59 PM PDT 24 53983862 ps
T960 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.553224223 May 12 12:58:06 PM PDT 24 May 12 12:58:11 PM PDT 24 58711974 ps
T60 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2187374869 May 12 12:58:08 PM PDT 24 May 12 12:58:13 PM PDT 24 264451470 ps
T73 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2138698184 May 12 12:57:52 PM PDT 24 May 12 12:57:54 PM PDT 24 41916664 ps
T961 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2655116492 May 12 12:58:00 PM PDT 24 May 12 12:58:02 PM PDT 24 24683227 ps
T962 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.626311283 May 12 12:58:01 PM PDT 24 May 12 12:58:02 PM PDT 24 12699562 ps
T141 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.916760242 May 12 12:57:59 PM PDT 24 May 12 12:58:02 PM PDT 24 75361590 ps
T963 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2912339293 May 12 12:58:11 PM PDT 24 May 12 12:58:14 PM PDT 24 63217774 ps
T964 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4124760993 May 12 12:58:13 PM PDT 24 May 12 12:58:16 PM PDT 24 37573500 ps
T61 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2973491843 May 12 12:57:49 PM PDT 24 May 12 12:57:53 PM PDT 24 111207440 ps
T107 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3187413926 May 12 12:58:02 PM PDT 24 May 12 12:58:04 PM PDT 24 47123278 ps
T142 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4290528703 May 12 12:57:55 PM PDT 24 May 12 12:58:05 PM PDT 24 1750859269 ps
T965 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.288687575 May 12 12:57:57 PM PDT 24 May 12 12:57:58 PM PDT 24 13125020 ps
T966 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1899998355 May 12 12:58:05 PM PDT 24 May 12 12:58:09 PM PDT 24 134463581 ps
T967 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1558180779 May 12 12:58:16 PM PDT 24 May 12 12:58:18 PM PDT 24 25694862 ps
T968 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1192198595 May 12 12:57:44 PM PDT 24 May 12 12:57:46 PM PDT 24 45946576 ps
T62 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2016264755 May 12 12:58:11 PM PDT 24 May 12 12:58:19 PM PDT 24 839479299 ps
T87 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2988486296 May 12 12:58:02 PM PDT 24 May 12 12:58:06 PM PDT 24 462888417 ps
T969 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3889960611 May 12 12:58:05 PM PDT 24 May 12 12:58:06 PM PDT 24 24431997 ps
T970 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3100311456 May 12 12:58:00 PM PDT 24 May 12 12:58:02 PM PDT 24 17083159 ps
T99 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4233470493 May 12 12:57:49 PM PDT 24 May 12 12:57:53 PM PDT 24 103622724 ps
T971 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2608862792 May 12 12:57:49 PM PDT 24 May 12 12:57:53 PM PDT 24 98693250 ps
T972 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.561832103 May 12 12:57:46 PM PDT 24 May 12 12:57:48 PM PDT 24 42303382 ps
T143 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2405748909 May 12 12:57:53 PM PDT 24 May 12 12:57:57 PM PDT 24 2461547115 ps
T973 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.175442979 May 12 12:58:20 PM PDT 24 May 12 12:58:21 PM PDT 24 27694613 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2420757643 May 12 12:57:58 PM PDT 24 May 12 12:58:02 PM PDT 24 76532496 ps
T89 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.375987404 May 12 12:58:05 PM PDT 24 May 12 12:58:20 PM PDT 24 1015318527 ps
T974 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2574956430 May 12 12:58:03 PM PDT 24 May 12 12:58:05 PM PDT 24 65498623 ps
T103 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.417730646 May 12 12:58:04 PM PDT 24 May 12 12:58:08 PM PDT 24 140595290 ps
T88 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2782311175 May 12 12:58:12 PM PDT 24 May 12 12:58:20 PM PDT 24 101457648 ps
T975 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1347060777 May 12 12:57:50 PM PDT 24 May 12 12:57:51 PM PDT 24 12010779 ps
T976 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1340813605 May 12 12:57:54 PM PDT 24 May 12 12:57:55 PM PDT 24 14713212 ps
T977 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.572719900 May 12 12:57:51 PM PDT 24 May 12 12:57:52 PM PDT 24 11172907 ps
T978 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1751795246 May 12 12:58:21 PM PDT 24 May 12 12:58:23 PM PDT 24 192678782 ps
T90 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.898161966 May 12 12:58:02 PM PDT 24 May 12 12:58:09 PM PDT 24 188905955 ps
T979 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.349273395 May 12 12:58:07 PM PDT 24 May 12 12:58:10 PM PDT 24 19789577 ps
T980 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1594417909 May 12 12:58:05 PM PDT 24 May 12 12:58:08 PM PDT 24 80723820 ps
T981 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3819131944 May 12 12:58:07 PM PDT 24 May 12 12:58:09 PM PDT 24 32411443 ps
T982 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.276825549 May 12 12:58:06 PM PDT 24 May 12 12:58:11 PM PDT 24 118504469 ps
T983 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3056167001 May 12 12:58:24 PM PDT 24 May 12 12:58:25 PM PDT 24 102679594 ps
T74 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3101339039 May 12 12:57:52 PM PDT 24 May 12 12:57:54 PM PDT 24 31034949 ps
T108 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2373584278 May 12 12:57:42 PM PDT 24 May 12 12:57:51 PM PDT 24 1564975758 ps
T984 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.573803154 May 12 12:58:21 PM PDT 24 May 12 12:58:23 PM PDT 24 17425960 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2606861755 May 12 12:58:06 PM PDT 24 May 12 12:58:10 PM PDT 24 403217789 ps
T256 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1527479201 May 12 12:57:59 PM PDT 24 May 12 12:58:21 PM PDT 24 842869475 ps
T985 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3666001844 May 12 12:58:07 PM PDT 24 May 12 12:58:10 PM PDT 24 71064223 ps
T144 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3243359362 May 12 12:57:57 PM PDT 24 May 12 12:58:06 PM PDT 24 1366765835 ps
T986 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3471457924 May 12 12:58:10 PM PDT 24 May 12 12:58:15 PM PDT 24 52104997 ps
T987 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.152080916 May 12 12:58:15 PM PDT 24 May 12 12:58:17 PM PDT 24 18323210 ps
T988 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3615099381 May 12 12:58:09 PM PDT 24 May 12 12:58:13 PM PDT 24 89949928 ps
T100 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.64162551 May 12 12:57:45 PM PDT 24 May 12 12:57:49 PM PDT 24 154120628 ps
T145 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1055521983 May 12 12:57:56 PM PDT 24 May 12 12:58:01 PM PDT 24 209286418 ps
T109 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4255558556 May 12 12:58:08 PM PDT 24 May 12 12:58:12 PM PDT 24 240477048 ps
T989 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2095998523 May 12 12:57:53 PM PDT 24 May 12 12:58:18 PM PDT 24 23988162737 ps
T990 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3072146134 May 12 12:57:49 PM PDT 24 May 12 12:57:52 PM PDT 24 64452467 ps
T101 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.267660852 May 12 12:57:38 PM PDT 24 May 12 12:57:40 PM PDT 24 47957134 ps
T991 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3560472338 May 12 12:58:09 PM PDT 24 May 12 12:58:12 PM PDT 24 258859292 ps
T992 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3341057755 May 12 12:58:23 PM PDT 24 May 12 12:58:24 PM PDT 24 42631338 ps
T993 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2452208554 May 12 12:58:08 PM PDT 24 May 12 12:58:12 PM PDT 24 39561775 ps
T994 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.578014543 May 12 12:58:01 PM PDT 24 May 12 12:58:02 PM PDT 24 86124006 ps
T995 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3841530081 May 12 12:58:19 PM PDT 24 May 12 12:58:20 PM PDT 24 48454733 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.531388411 May 12 12:57:50 PM PDT 24 May 12 12:57:52 PM PDT 24 74632180 ps
T996 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3131855329 May 12 12:57:54 PM PDT 24 May 12 12:57:58 PM PDT 24 156019972 ps
T75 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.779990109 May 12 12:57:42 PM PDT 24 May 12 12:57:43 PM PDT 24 62970839 ps
T997 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1241677061 May 12 12:57:46 PM PDT 24 May 12 12:57:49 PM PDT 24 37536972 ps
T95 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3358471614 May 12 12:58:07 PM PDT 24 May 12 12:58:13 PM PDT 24 636211430 ps
T998 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2951228752 May 12 12:57:44 PM PDT 24 May 12 12:57:47 PM PDT 24 81043128 ps
T96 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1820410821 May 12 12:57:57 PM PDT 24 May 12 12:58:02 PM PDT 24 166809364 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3493992585 May 12 12:57:54 PM PDT 24 May 12 12:57:56 PM PDT 24 30054704 ps
T999 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3248362746 May 12 12:58:11 PM PDT 24 May 12 12:58:14 PM PDT 24 36548269 ps
T1000 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.252540807 May 12 12:57:54 PM PDT 24 May 12 12:57:57 PM PDT 24 52551485 ps
T1001 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2886070160 May 12 12:57:49 PM PDT 24 May 12 12:57:51 PM PDT 24 29007666 ps
T93 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1248075348 May 12 12:58:03 PM PDT 24 May 12 12:58:08 PM PDT 24 300803300 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3649938862 May 12 12:57:49 PM PDT 24 May 12 12:58:01 PM PDT 24 743465538 ps
T1002 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2924547174 May 12 12:58:04 PM PDT 24 May 12 12:58:07 PM PDT 24 89850303 ps
T1003 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3039426457 May 12 12:58:14 PM PDT 24 May 12 12:58:16 PM PDT 24 21195895 ps
T97 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.527594826 May 12 12:58:09 PM PDT 24 May 12 12:58:14 PM PDT 24 68691869 ps
T1004 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1244420295 May 12 12:57:59 PM PDT 24 May 12 12:58:03 PM PDT 24 224243040 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.931084659 May 12 12:57:30 PM PDT 24 May 12 12:57:33 PM PDT 24 51490148 ps
T94 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4148823348 May 12 12:58:06 PM PDT 24 May 12 12:58:10 PM PDT 24 427090702 ps
T114 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.187211246 May 12 12:58:08 PM PDT 24 May 12 12:58:17 PM PDT 24 39143070 ps
T1005 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.842078672 May 12 12:58:14 PM PDT 24 May 12 12:58:16 PM PDT 24 41721389 ps
T1006 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3035134656 May 12 12:58:03 PM PDT 24 May 12 12:58:43 PM PDT 24 3769342894 ps
T1007 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1193171376 May 12 12:58:02 PM PDT 24 May 12 12:58:05 PM PDT 24 54077318 ps
T1008 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3965350739 May 12 12:58:09 PM PDT 24 May 12 12:58:12 PM PDT 24 31993548 ps
T257 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.920364300 May 12 12:58:09 PM PDT 24 May 12 12:58:37 PM PDT 24 2157025918 ps
T1009 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4022647218 May 12 12:58:08 PM PDT 24 May 12 12:58:11 PM PDT 24 29995335 ps
T98 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3501526507 May 12 12:58:15 PM PDT 24 May 12 12:58:20 PM PDT 24 811914254 ps
T1010 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2477167933 May 12 12:57:59 PM PDT 24 May 12 12:58:02 PM PDT 24 44018349 ps
T115 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2316706521 May 12 12:57:51 PM PDT 24 May 12 12:57:55 PM PDT 24 189151005 ps
T259 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.619350011 May 12 12:57:39 PM PDT 24 May 12 12:57:53 PM PDT 24 644659013 ps
T116 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3387327587 May 12 12:58:03 PM PDT 24 May 12 12:58:07 PM PDT 24 425833263 ps
T1011 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1808817482 May 12 12:58:11 PM PDT 24 May 12 12:58:17 PM PDT 24 254711363 ps
T258 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3763541008 May 12 12:58:08 PM PDT 24 May 12 12:58:18 PM PDT 24 323351071 ps
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