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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.92 98.30 94.11 98.61 89.36 97.06 95.83 98.17


Total test records in report: 1081
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T1012 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.533226388 May 12 12:58:07 PM PDT 24 May 12 12:58:10 PM PDT 24 23077660 ps
T1013 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1736257257 May 12 12:58:05 PM PDT 24 May 12 12:58:06 PM PDT 24 16531102 ps
T1014 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3513209043 May 12 12:57:50 PM PDT 24 May 12 12:57:51 PM PDT 24 63990184 ps
T1015 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.463887225 May 12 12:57:56 PM PDT 24 May 12 12:57:58 PM PDT 24 84494565 ps
T1016 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1900720600 May 12 12:58:12 PM PDT 24 May 12 12:58:15 PM PDT 24 43277427 ps
T1017 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.491127502 May 12 12:57:49 PM PDT 24 May 12 12:57:52 PM PDT 24 28947963 ps
T117 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1416583147 May 12 12:58:00 PM PDT 24 May 12 12:58:03 PM PDT 24 424013468 ps
T1018 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2503400528 May 12 12:58:04 PM PDT 24 May 12 12:58:09 PM PDT 24 207058316 ps
T1019 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.130116218 May 12 12:58:14 PM PDT 24 May 12 12:58:34 PM PDT 24 1878218153 ps
T1020 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.564396119 May 12 12:58:08 PM PDT 24 May 12 12:58:12 PM PDT 24 26090863 ps
T76 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4110510968 May 12 12:57:56 PM PDT 24 May 12 12:57:58 PM PDT 24 130336754 ps
T262 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2753769501 May 12 12:58:05 PM PDT 24 May 12 12:58:27 PM PDT 24 1030463679 ps
T1021 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2992653991 May 12 12:58:14 PM PDT 24 May 12 12:58:17 PM PDT 24 465924402 ps
T1022 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2487795424 May 12 12:58:06 PM PDT 24 May 12 12:58:08 PM PDT 24 16909590 ps
T1023 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4213150150 May 12 12:58:02 PM PDT 24 May 12 12:58:04 PM PDT 24 127883082 ps
T1024 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3707654338 May 12 12:57:51 PM PDT 24 May 12 12:57:55 PM PDT 24 143823301 ps
T1025 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3058361527 May 12 12:58:03 PM PDT 24 May 12 12:58:06 PM PDT 24 114435349 ps
T1026 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2159531417 May 12 12:58:14 PM PDT 24 May 12 12:58:16 PM PDT 24 33280092 ps
T118 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4021313630 May 12 12:58:09 PM PDT 24 May 12 12:58:14 PM PDT 24 39148018 ps
T1027 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1593297879 May 12 12:58:04 PM PDT 24 May 12 12:58:08 PM PDT 24 1867054732 ps
T1028 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1263575985 May 12 12:57:52 PM PDT 24 May 12 12:57:59 PM PDT 24 100266096 ps
T1029 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1027710382 May 12 12:58:05 PM PDT 24 May 12 12:58:06 PM PDT 24 51780893 ps
T1030 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3215468566 May 12 12:57:56 PM PDT 24 May 12 12:57:58 PM PDT 24 13181724 ps
T1031 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3484990440 May 12 12:58:12 PM PDT 24 May 12 12:58:15 PM PDT 24 41296801 ps
T260 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.364928612 May 12 12:57:52 PM PDT 24 May 12 12:58:01 PM PDT 24 305789918 ps
T1032 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4242447610 May 12 12:58:08 PM PDT 24 May 12 12:58:12 PM PDT 24 61984115 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.23583854 May 12 12:57:55 PM PDT 24 May 12 12:57:56 PM PDT 24 44826972 ps
T1034 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3418302335 May 12 12:58:18 PM PDT 24 May 12 12:58:21 PM PDT 24 74286866 ps
T119 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3523891129 May 12 12:57:49 PM PDT 24 May 12 12:57:52 PM PDT 24 505133587 ps
T1035 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2995466571 May 12 12:58:08 PM PDT 24 May 12 12:58:14 PM PDT 24 228156473 ps
T1036 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1485330426 May 12 12:58:14 PM PDT 24 May 12 12:58:16 PM PDT 24 34532360 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.86038460 May 12 12:57:45 PM PDT 24 May 12 12:57:47 PM PDT 24 43516080 ps
T1038 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1800878048 May 12 12:58:14 PM PDT 24 May 12 12:58:16 PM PDT 24 48246249 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2954621879 May 12 12:58:08 PM PDT 24 May 12 12:58:14 PM PDT 24 2861473002 ps
T1040 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1136959204 May 12 12:58:01 PM PDT 24 May 12 12:58:04 PM PDT 24 80938594 ps
T1041 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.414563056 May 12 12:57:57 PM PDT 24 May 12 12:58:01 PM PDT 24 292303576 ps
T1042 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4284700299 May 12 12:58:21 PM PDT 24 May 12 12:58:23 PM PDT 24 51899476 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3266182154 May 12 12:57:55 PM PDT 24 May 12 12:58:01 PM PDT 24 503778040 ps
T254 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.101698878 May 12 12:57:56 PM PDT 24 May 12 12:58:01 PM PDT 24 61437360 ps
T1044 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.84360161 May 12 12:57:59 PM PDT 24 May 12 12:58:00 PM PDT 24 15969672 ps
T1045 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.127738913 May 12 12:58:08 PM PDT 24 May 12 12:58:11 PM PDT 24 102885337 ps
T1046 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3957109823 May 12 12:58:09 PM PDT 24 May 12 12:58:17 PM PDT 24 181221528 ps
T120 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.28918504 May 12 12:57:58 PM PDT 24 May 12 12:58:14 PM PDT 24 2410328051 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2582038387 May 12 12:58:05 PM PDT 24 May 12 12:58:09 PM PDT 24 43555123 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.455230235 May 12 12:57:53 PM PDT 24 May 12 12:57:56 PM PDT 24 36371928 ps
T255 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3310985035 May 12 12:58:05 PM PDT 24 May 12 12:58:12 PM PDT 24 191637683 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.854905181 May 12 12:57:44 PM PDT 24 May 12 12:57:48 PM PDT 24 348538910 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.641795955 May 12 12:58:07 PM PDT 24 May 12 12:58:17 PM PDT 24 1365116343 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.151582521 May 12 12:57:58 PM PDT 24 May 12 12:58:00 PM PDT 24 158248878 ps
T1052 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3725836122 May 12 12:58:10 PM PDT 24 May 12 12:58:13 PM PDT 24 12127278 ps
T1053 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.769974931 May 12 12:58:09 PM PDT 24 May 12 12:58:14 PM PDT 24 39414348 ps
T1054 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1222255404 May 12 12:58:07 PM PDT 24 May 12 12:58:17 PM PDT 24 2183636085 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.873751100 May 12 12:58:08 PM PDT 24 May 12 12:58:13 PM PDT 24 254538681 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2812176450 May 12 12:57:45 PM PDT 24 May 12 12:57:55 PM PDT 24 882604419 ps
T263 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1366976306 May 12 12:57:46 PM PDT 24 May 12 12:57:59 PM PDT 24 800327914 ps
T261 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2546372505 May 12 12:58:07 PM PDT 24 May 12 12:58:23 PM PDT 24 3403207613 ps
T1057 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.346040284 May 12 12:58:09 PM PDT 24 May 12 12:58:14 PM PDT 24 264407579 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3809075804 May 12 12:57:55 PM PDT 24 May 12 12:57:58 PM PDT 24 226645918 ps
T1059 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1822105666 May 12 12:58:09 PM PDT 24 May 12 12:58:13 PM PDT 24 34958581 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.471084147 May 12 12:57:50 PM PDT 24 May 12 12:57:52 PM PDT 24 95625279 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.619182511 May 12 12:57:35 PM PDT 24 May 12 12:57:39 PM PDT 24 390600949 ps
T1062 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3834302755 May 12 12:58:06 PM PDT 24 May 12 12:58:10 PM PDT 24 119293312 ps
T1063 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.888276197 May 12 12:57:56 PM PDT 24 May 12 12:57:58 PM PDT 24 205691849 ps
T1064 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3220772169 May 12 12:58:13 PM PDT 24 May 12 12:58:16 PM PDT 24 620851261 ps
T1065 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2505040045 May 12 12:58:07 PM PDT 24 May 12 12:58:10 PM PDT 24 14504504 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2923906071 May 12 12:58:03 PM PDT 24 May 12 12:58:11 PM PDT 24 112903358 ps
T1067 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.207478572 May 12 12:58:08 PM PDT 24 May 12 12:58:35 PM PDT 24 4689399033 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2229186856 May 12 12:57:48 PM PDT 24 May 12 12:57:52 PM PDT 24 88874924 ps
T1069 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3609709171 May 12 12:57:48 PM PDT 24 May 12 12:57:52 PM PDT 24 210130344 ps
T1070 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3538356841 May 12 12:58:15 PM PDT 24 May 12 12:58:17 PM PDT 24 19333425 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3054624121 May 12 12:57:55 PM PDT 24 May 12 12:57:57 PM PDT 24 386555065 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2278935406 May 12 12:58:04 PM PDT 24 May 12 12:58:13 PM PDT 24 1714280217 ps
T1073 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1636698791 May 12 12:58:09 PM PDT 24 May 12 12:58:16 PM PDT 24 218776395 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.889660210 May 12 12:57:55 PM PDT 24 May 12 12:57:58 PM PDT 24 235906051 ps
T1075 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3112954675 May 12 12:58:17 PM PDT 24 May 12 12:58:20 PM PDT 24 247521341 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3008059036 May 12 12:57:45 PM PDT 24 May 12 12:58:04 PM PDT 24 346109290 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.332554887 May 12 12:57:50 PM PDT 24 May 12 12:58:07 PM PDT 24 2891791743 ps
T1078 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.131282395 May 12 12:58:06 PM PDT 24 May 12 12:58:08 PM PDT 24 14053352 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1235194315 May 12 12:58:00 PM PDT 24 May 12 12:58:14 PM PDT 24 913373749 ps
T1080 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1320448834 May 12 12:58:08 PM PDT 24 May 12 12:58:13 PM PDT 24 301789538 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3702055364 May 12 12:57:48 PM PDT 24 May 12 12:58:01 PM PDT 24 710784485 ps

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2642815897
Short name T8
Test name
Test status
Simulation time 77587573758 ps
CPU time 129.64 seconds
Started May 12 01:01:46 PM PDT 24
Finished May 12 01:03:56 PM PDT 24
Peak memory 252180 kb
Host smart-8cae3dce-6dba-4638-847b-96d0e14e5bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642815897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2642815897
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3264015064
Short name T38
Test name
Test status
Simulation time 9439349088 ps
CPU time 122.53 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:03:51 PM PDT 24
Peak memory 265380 kb
Host smart-a813821b-b8f9-4d99-8d82-d0a029508805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264015064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3264015064
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2703764678
Short name T34
Test name
Test status
Simulation time 72903380602 ps
CPU time 723.3 seconds
Started May 12 01:03:31 PM PDT 24
Finished May 12 01:15:35 PM PDT 24
Peak memory 258388 kb
Host smart-2f855fba-4b6e-4ecc-81f2-0236c3734f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703764678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2703764678
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.417730646
Short name T103
Test name
Test status
Simulation time 140595290 ps
CPU time 3.59 seconds
Started May 12 12:58:04 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 216888 kb
Host smart-d968d536-338b-4e93-be6d-ef544078c884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417730646 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.417730646
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3046055214
Short name T177
Test name
Test status
Simulation time 488791899125 ps
CPU time 731.84 seconds
Started May 12 01:01:59 PM PDT 24
Finished May 12 01:14:11 PM PDT 24
Peak memory 272436 kb
Host smart-0ca06db0-2500-4d70-8e80-bd376a843f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046055214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3046055214
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3689576443
Short name T29
Test name
Test status
Simulation time 4044539526 ps
CPU time 97.71 seconds
Started May 12 01:04:31 PM PDT 24
Finished May 12 01:06:10 PM PDT 24
Peak memory 253356 kb
Host smart-105df7f9-1f35-42b2-a1df-3743a258a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689576443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3689576443
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.773542809
Short name T65
Test name
Test status
Simulation time 26818607 ps
CPU time 0.73 seconds
Started May 12 01:01:20 PM PDT 24
Finished May 12 01:01:21 PM PDT 24
Peak memory 216288 kb
Host smart-14b9e3ec-8843-451c-a8e2-7a4be7a8023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773542809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.773542809
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1613682937
Short name T24
Test name
Test status
Simulation time 66033362614 ps
CPU time 606.18 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:14:00 PM PDT 24
Peak memory 263800 kb
Host smart-34dda312-9be4-45ed-88d7-c9a51f925ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613682937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1613682937
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2668879098
Short name T2
Test name
Test status
Simulation time 293348524 ps
CPU time 1.2 seconds
Started May 12 01:01:30 PM PDT 24
Finished May 12 01:01:32 PM PDT 24
Peak memory 234872 kb
Host smart-c9f7fc8c-37e7-49c7-a480-1c6888264c08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668879098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2668879098
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2582140969
Short name T236
Test name
Test status
Simulation time 83469464883 ps
CPU time 669.85 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:14:37 PM PDT 24
Peak memory 269588 kb
Host smart-a1449939-7e3d-49c4-9184-b0f884e81215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582140969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2582140969
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1941729687
Short name T11
Test name
Test status
Simulation time 372923308691 ps
CPU time 415.86 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:09:10 PM PDT 24
Peak memory 252712 kb
Host smart-df44a577-7111-452a-b6ac-df99def123d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941729687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1941729687
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1717028603
Short name T25
Test name
Test status
Simulation time 36072929279 ps
CPU time 269.83 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:05:53 PM PDT 24
Peak memory 273544 kb
Host smart-17dcec93-4971-4e09-b3bc-77af4f37e20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717028603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1717028603
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1550255282
Short name T41
Test name
Test status
Simulation time 1870640577 ps
CPU time 9.78 seconds
Started May 12 01:01:34 PM PDT 24
Finished May 12 01:01:44 PM PDT 24
Peak memory 240576 kb
Host smart-82e21f27-d872-4a63-85fc-e3009eef9705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550255282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1550255282
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1500063359
Short name T35
Test name
Test status
Simulation time 80156376120 ps
CPU time 202.33 seconds
Started May 12 01:03:52 PM PDT 24
Finished May 12 01:07:15 PM PDT 24
Peak memory 255944 kb
Host smart-ef080209-2c30-425c-8749-e2bf5b79c4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500063359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1500063359
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.920364300
Short name T257
Test name
Test status
Simulation time 2157025918 ps
CPU time 12.38 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:37 PM PDT 24
Peak memory 215144 kb
Host smart-e32b737c-b007-4072-a08c-41f57289ee7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920364300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.920364300
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.457652962
Short name T146
Test name
Test status
Simulation time 30454140305 ps
CPU time 309.31 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:08:04 PM PDT 24
Peak memory 257272 kb
Host smart-41542821-7bb0-48cc-8c42-7fa64cb70ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457652962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.457652962
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1248075348
Short name T93
Test name
Test status
Simulation time 300803300 ps
CPU time 4.56 seconds
Started May 12 12:58:03 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 215236 kb
Host smart-b9378e92-bb56-4806-a53a-dd5b55414cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248075348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1248075348
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3649938862
Short name T112
Test name
Test status
Simulation time 743465538 ps
CPU time 11.59 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 206804 kb
Host smart-5c799c1d-e15a-40e9-a815-bb1ddd833cbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649938862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3649938862
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2091103655
Short name T224
Test name
Test status
Simulation time 26675348841 ps
CPU time 276.54 seconds
Started May 12 01:04:04 PM PDT 24
Finished May 12 01:08:41 PM PDT 24
Peak memory 256684 kb
Host smart-683d58c9-9fd3-4aaa-94c6-bbeed3397c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091103655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2091103655
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.366988962
Short name T308
Test name
Test status
Simulation time 5097940786 ps
CPU time 27.25 seconds
Started May 12 01:04:47 PM PDT 24
Finished May 12 01:05:15 PM PDT 24
Peak memory 216028 kb
Host smart-97459148-cd90-41a4-862a-4d55b785d16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366988962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.366988962
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.560695678
Short name T164
Test name
Test status
Simulation time 5074464193 ps
CPU time 86.9 seconds
Started May 12 01:03:05 PM PDT 24
Finished May 12 01:04:33 PM PDT 24
Peak memory 261332 kb
Host smart-710e62ee-866e-47f8-96f0-276aa54de348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560695678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.560695678
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1411850532
Short name T178
Test name
Test status
Simulation time 7485210822 ps
CPU time 92.82 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:05:38 PM PDT 24
Peak memory 269560 kb
Host smart-52bc5e17-04a4-40b6-85cb-ede3a94e88f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411850532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1411850532
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1942045949
Short name T51
Test name
Test status
Simulation time 53562875894 ps
CPU time 315.77 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:08:12 PM PDT 24
Peak memory 248964 kb
Host smart-ca990188-3a7f-4434-8a05-1c6f84e073bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942045949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1942045949
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2788010082
Short name T18
Test name
Test status
Simulation time 240075476 ps
CPU time 0.87 seconds
Started May 12 01:03:03 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 206140 kb
Host smart-1767768e-d6f1-4a40-96d2-147bed450aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788010082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2788010082
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1294938458
Short name T244
Test name
Test status
Simulation time 15337217904 ps
CPU time 165.45 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:04:59 PM PDT 24
Peak memory 265404 kb
Host smart-3f766262-31c4-4aa1-8af4-e6bc52736283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294938458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1294938458
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2133028142
Short name T45
Test name
Test status
Simulation time 22036662838 ps
CPU time 215.58 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:06:26 PM PDT 24
Peak memory 282212 kb
Host smart-311784f6-16ae-46c4-9fbf-a9add5c9c4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133028142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2133028142
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2516070912
Short name T167
Test name
Test status
Simulation time 9685762570 ps
CPU time 59 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:03:12 PM PDT 24
Peak memory 248956 kb
Host smart-acdac345-f2c2-4a8e-ac10-9003926f0408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516070912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2516070912
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.923403741
Short name T57
Test name
Test status
Simulation time 14391215 ps
CPU time 0.73 seconds
Started May 12 01:01:28 PM PDT 24
Finished May 12 01:01:29 PM PDT 24
Peak memory 204632 kb
Host smart-9684dd8e-df15-44a0-b941-690f1d0f7d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923403741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.923403741
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1132203836
Short name T32
Test name
Test status
Simulation time 9959370570 ps
CPU time 117.72 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:04:52 PM PDT 24
Peak memory 256212 kb
Host smart-f09a8875-933f-4081-b64c-81c8645e4925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132203836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1132203836
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.965170393
Short name T221
Test name
Test status
Simulation time 95441911561 ps
CPU time 466.94 seconds
Started May 12 01:01:29 PM PDT 24
Finished May 12 01:09:16 PM PDT 24
Peak memory 256836 kb
Host smart-17821857-3f8d-403f-bc36-22516111fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965170393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
965170393
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2438341705
Short name T234
Test name
Test status
Simulation time 1916802078 ps
CPU time 43.08 seconds
Started May 12 01:04:18 PM PDT 24
Finished May 12 01:05:03 PM PDT 24
Peak memory 256668 kb
Host smart-ef04f56b-bf0a-404d-b58f-9649c3cd9bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438341705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2438341705
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2516811281
Short name T138
Test name
Test status
Simulation time 3688114220 ps
CPU time 52.94 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 232820 kb
Host smart-1cbc8e08-d41d-4988-88a7-6bea404e4822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516811281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2516811281
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3361185937
Short name T126
Test name
Test status
Simulation time 587901868682 ps
CPU time 405.83 seconds
Started May 12 01:03:18 PM PDT 24
Finished May 12 01:10:04 PM PDT 24
Peak memory 257196 kb
Host smart-143c6bb1-d426-4220-b29d-3410669f9950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361185937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3361185937
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.364928612
Short name T260
Test name
Test status
Simulation time 305789918 ps
CPU time 8.03 seconds
Started May 12 12:57:52 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 215052 kb
Host smart-8e21b66a-0de7-4b5f-8d34-9f2326f970eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364928612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.364928612
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.694762544
Short name T306
Test name
Test status
Simulation time 149811019 ps
CPU time 6.35 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:01:29 PM PDT 24
Peak memory 224308 kb
Host smart-d208fa81-6eab-460e-aeed-e76a46fd9919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694762544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.694762544
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3421735677
Short name T152
Test name
Test status
Simulation time 104359295119 ps
CPU time 224.15 seconds
Started May 12 01:01:30 PM PDT 24
Finished May 12 01:05:14 PM PDT 24
Peak memory 289524 kb
Host smart-9dc1f521-d913-42f5-8e16-aaa243049092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421735677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3421735677
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.180786110
Short name T248
Test name
Test status
Simulation time 45203556467 ps
CPU time 519.61 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:10:58 PM PDT 24
Peak memory 284568 kb
Host smart-d48b7eb2-3be0-434b-8ea8-3068859bd44b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180786110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.180786110
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.54679560
Short name T80
Test name
Test status
Simulation time 989950760 ps
CPU time 10.57 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:22 PM PDT 24
Peak memory 233800 kb
Host smart-42f41d8d-b42e-48cd-8734-20b74c7c6fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54679560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.54679560
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3673378510
Short name T78
Test name
Test status
Simulation time 35878510514 ps
CPU time 50.2 seconds
Started May 12 01:02:39 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 216280 kb
Host smart-2a724d61-b8e6-4a44-a23d-59123c84c7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673378510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3673378510
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1036844291
Short name T187
Test name
Test status
Simulation time 2446560698 ps
CPU time 27.19 seconds
Started May 12 01:02:55 PM PDT 24
Finished May 12 01:03:22 PM PDT 24
Peak memory 219384 kb
Host smart-d78d2aa4-131b-4c49-bd47-d458750cdfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036844291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1036844291
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2016264755
Short name T62
Test name
Test status
Simulation time 839479299 ps
CPU time 5.4 seconds
Started May 12 12:58:11 PM PDT 24
Finished May 12 12:58:19 PM PDT 24
Peak memory 215292 kb
Host smart-e9745ef2-c467-4bbb-baea-d979a2de2c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016264755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2016264755
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1366976306
Short name T263
Test name
Test status
Simulation time 800327914 ps
CPU time 11.93 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:59 PM PDT 24
Peak memory 215136 kb
Host smart-73bf2962-b2f8-4334-b0fc-d06826a8ff2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366976306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1366976306
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2679102696
Short name T241
Test name
Test status
Simulation time 4955838565 ps
CPU time 134.78 seconds
Started May 12 01:02:14 PM PDT 24
Finished May 12 01:04:30 PM PDT 24
Peak memory 262812 kb
Host smart-036b9fff-7220-4b54-8683-fb5444422331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679102696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2679102696
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1976561573
Short name T28
Test name
Test status
Simulation time 7102131144 ps
CPU time 96.86 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:03:54 PM PDT 24
Peak memory 267820 kb
Host smart-e0e9cdf1-19f1-4b01-aa78-6bc81c8905d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976561573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1976561573
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4228445181
Short name T72
Test name
Test status
Simulation time 367092289276 ps
CPU time 195.52 seconds
Started May 12 01:02:16 PM PDT 24
Finished May 12 01:05:32 PM PDT 24
Peak memory 256140 kb
Host smart-0524d145-3605-405f-bce7-6a9d9db4616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228445181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4228445181
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.533882062
Short name T941
Test name
Test status
Simulation time 288666080 ps
CPU time 7.34 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:52 PM PDT 24
Peak memory 224344 kb
Host smart-9cdc3cf5-6cdb-4cda-a259-9168c57dd6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533882062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.533882062
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2313236927
Short name T192
Test name
Test status
Simulation time 5152392854 ps
CPU time 59.54 seconds
Started May 12 01:03:22 PM PDT 24
Finished May 12 01:04:22 PM PDT 24
Peak memory 251872 kb
Host smart-1a9d6310-6705-4b32-86a2-27e71a1883c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313236927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2313236927
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_upload.1413673115
Short name T270
Test name
Test status
Simulation time 1058742499 ps
CPU time 6.13 seconds
Started May 12 01:03:47 PM PDT 24
Finished May 12 01:03:53 PM PDT 24
Peak memory 218604 kb
Host smart-118112ad-8255-4d93-9b41-d37bc921e289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413673115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1413673115
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3955315849
Short name T228
Test name
Test status
Simulation time 5325866295 ps
CPU time 77.3 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:05:23 PM PDT 24
Peak memory 248976 kb
Host smart-16256996-0a26-425d-81ad-c6d1e89856fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955315849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3955315849
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4110510968
Short name T76
Test name
Test status
Simulation time 130336754 ps
CPU time 1.19 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 206844 kb
Host smart-3ff27022-5496-4d2c-9d36-33bc57b64fb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110510968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4110510968
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3809075804
Short name T1058
Test name
Test status
Simulation time 226645918 ps
CPU time 3.11 seconds
Started May 12 12:57:55 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 215296 kb
Host smart-bee75cc4-7fd7-4c0c-8b28-6f9d5e142e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809075804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3809075804
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2373584278
Short name T108
Test name
Test status
Simulation time 1564975758 ps
CPU time 8.76 seconds
Started May 12 12:57:42 PM PDT 24
Finished May 12 12:57:51 PM PDT 24
Peak memory 206808 kb
Host smart-689036fe-6f9c-4707-8d5c-3561a36009c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373584278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2373584278
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3609709171
Short name T1069
Test name
Test status
Simulation time 210130344 ps
CPU time 3.49 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 217608 kb
Host smart-cc834a45-fee9-4835-a944-e6dde09db1ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609709171 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3609709171
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3523891129
Short name T119
Test name
Test status
Simulation time 505133587 ps
CPU time 2.5 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 206768 kb
Host smart-beb0a5a2-210b-401c-a954-8a023ddce0c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523891129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
523891129
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.561832103
Short name T972
Test name
Test status
Simulation time 42303382 ps
CPU time 0.7 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:48 PM PDT 24
Peak memory 203748 kb
Host smart-36ff2b88-92d2-4296-9e1e-22feb04e5181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561832103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.561832103
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.531388411
Short name T110
Test name
Test status
Simulation time 74632180 ps
CPU time 1.63 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 215160 kb
Host smart-06cdc6ae-d2cc-40fd-9c4d-3644370f19ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531388411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.531388411
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3215468566
Short name T1030
Test name
Test status
Simulation time 13181724 ps
CPU time 0.66 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 203728 kb
Host smart-04bcf759-4046-40ce-b114-f0367bb25c66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215468566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3215468566
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1055521983
Short name T145
Test name
Test status
Simulation time 209286418 ps
CPU time 4.25 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 215132 kb
Host smart-58e644ac-3b8b-418d-bafd-e61ba394d30a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055521983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1055521983
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3707654338
Short name T1024
Test name
Test status
Simulation time 143823301 ps
CPU time 4.03 seconds
Started May 12 12:57:51 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 215348 kb
Host smart-b34100ec-a6f3-4d64-b0a6-c53d7c7bc5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707654338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
707654338
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4290528703
Short name T142
Test name
Test status
Simulation time 1750859269 ps
CPU time 9.19 seconds
Started May 12 12:57:55 PM PDT 24
Finished May 12 12:58:05 PM PDT 24
Peak memory 215032 kb
Host smart-d3dffd73-6283-4fe2-97ba-eb75d7cce787
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290528703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4290528703
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1235194315
Short name T1079
Test name
Test status
Simulation time 913373749 ps
CPU time 13.47 seconds
Started May 12 12:58:00 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 206780 kb
Host smart-534b4797-4f94-4271-90f9-dc19f4725109
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235194315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1235194315
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.86038460
Short name T1037
Test name
Test status
Simulation time 43516080 ps
CPU time 1.36 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:47 PM PDT 24
Peak memory 216036 kb
Host smart-764dd433-f404-4447-b089-5b6d2ac84abf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86038460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
hw_reset.86038460
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.267660852
Short name T101
Test name
Test status
Simulation time 47957134 ps
CPU time 1.68 seconds
Started May 12 12:57:38 PM PDT 24
Finished May 12 12:57:40 PM PDT 24
Peak memory 216200 kb
Host smart-a6d0d32c-e6dd-4976-bff3-9ed27c6d3d2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267660852 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.267660852
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.187211246
Short name T114
Test name
Test status
Simulation time 39143070 ps
CPU time 2.58 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 215008 kb
Host smart-97590d1d-ce35-457d-98a1-285c7aeb33d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187211246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.187211246
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3462800475
Short name T959
Test name
Test status
Simulation time 53983862 ps
CPU time 0.76 seconds
Started May 12 12:57:57 PM PDT 24
Finished May 12 12:57:59 PM PDT 24
Peak memory 203468 kb
Host smart-1f106560-3c1b-466f-9d4d-a6e4b06f2af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462800475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
462800475
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.931084659
Short name T113
Test name
Test status
Simulation time 51490148 ps
CPU time 1.71 seconds
Started May 12 12:57:30 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 215216 kb
Host smart-fa8d7e3d-1c3f-47f7-b139-3cca5294920e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931084659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.931084659
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.626311283
Short name T962
Test name
Test status
Simulation time 12699562 ps
CPU time 0.65 seconds
Started May 12 12:58:01 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 203308 kb
Host smart-b919c937-a2bb-4fc4-938c-7807675989c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626311283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.626311283
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.619182511
Short name T1061
Test name
Test status
Simulation time 390600949 ps
CPU time 3.13 seconds
Started May 12 12:57:35 PM PDT 24
Finished May 12 12:57:39 PM PDT 24
Peak memory 215068 kb
Host smart-80bfba3b-0a77-484f-aff0-e5f3c05db868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619182511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.619182511
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2229186856
Short name T1068
Test name
Test status
Simulation time 88874924 ps
CPU time 2.77 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 215448 kb
Host smart-b6a13b10-517d-479a-91ad-3fc1b217074f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229186856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
229186856
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.619350011
Short name T259
Test name
Test status
Simulation time 644659013 ps
CPU time 14.45 seconds
Started May 12 12:57:39 PM PDT 24
Finished May 12 12:57:53 PM PDT 24
Peak memory 215988 kb
Host smart-476e2872-da31-4f60-995f-68ace8a1ae87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619350011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.619350011
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2477167933
Short name T1010
Test name
Test status
Simulation time 44018349 ps
CPU time 1.72 seconds
Started May 12 12:57:59 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 216232 kb
Host smart-025dd0fe-d38e-41ed-b638-bae2efa6e986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477167933 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2477167933
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.346040284
Short name T1057
Test name
Test status
Simulation time 264407579 ps
CPU time 2.86 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 215104 kb
Host smart-54b00218-2076-42dc-a7b1-85b35c07696e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346040284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.346040284
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.578014543
Short name T994
Test name
Test status
Simulation time 86124006 ps
CPU time 0.76 seconds
Started May 12 12:58:01 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 203728 kb
Host smart-cd1ebcc5-9d0a-4a92-a170-ceeb6ae9e067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578014543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.578014543
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.873751100
Short name T1055
Test name
Test status
Simulation time 254538681 ps
CPU time 1.85 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 215048 kb
Host smart-227be17c-ef5c-417d-bb19-159cddc3ee31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873751100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.873751100
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.130116218
Short name T1019
Test name
Test status
Simulation time 1878218153 ps
CPU time 18.43 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:34 PM PDT 24
Peak memory 215524 kb
Host smart-33bfceb0-2a73-4c74-b817-92efa8140b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130116218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.130116218
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3054624121
Short name T1071
Test name
Test status
Simulation time 386555065 ps
CPU time 1.43 seconds
Started May 12 12:57:55 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 215168 kb
Host smart-17339ddb-7b15-4d91-adb1-26a7b5acdc87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054624121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3054624121
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.769974931
Short name T1053
Test name
Test status
Simulation time 39414348 ps
CPU time 2.33 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 206812 kb
Host smart-7b465f11-1992-4fda-a981-6d5f0a9c4ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769974931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.769974931
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.127738913
Short name T1045
Test name
Test status
Simulation time 102885337 ps
CPU time 0.68 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:11 PM PDT 24
Peak memory 203436 kb
Host smart-88b4afa1-27b5-4d2c-bc7c-b18d4285eac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127738913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.127738913
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1899998355
Short name T966
Test name
Test status
Simulation time 134463581 ps
CPU time 2.64 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:09 PM PDT 24
Peak memory 215184 kb
Host smart-ee3ea8ec-782d-4cb2-92e5-de23764a607f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899998355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1899998355
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1136959204
Short name T1040
Test name
Test status
Simulation time 80938594 ps
CPU time 2.12 seconds
Started May 12 12:58:01 PM PDT 24
Finished May 12 12:58:04 PM PDT 24
Peak memory 215544 kb
Host smart-940851a1-3210-40a6-a02b-2633fa916419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136959204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1136959204
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3008059036
Short name T1076
Test name
Test status
Simulation time 346109290 ps
CPU time 17.56 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:58:04 PM PDT 24
Peak memory 215136 kb
Host smart-25b2cd23-9da9-4afa-9fc3-28ab30a68578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008059036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3008059036
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2924547174
Short name T1002
Test name
Test status
Simulation time 89850303 ps
CPU time 2.4 seconds
Started May 12 12:58:04 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 216812 kb
Host smart-629bf3c4-3ad7-4fae-acec-2da5e28ed490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924547174 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2924547174
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2992653991
Short name T1021
Test name
Test status
Simulation time 465924402 ps
CPU time 2.01 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 215024 kb
Host smart-0ca4934e-f895-4942-81d9-1bfcde25e775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992653991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2992653991
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2886070160
Short name T1001
Test name
Test status
Simulation time 29007666 ps
CPU time 0.69 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:51 PM PDT 24
Peak memory 203472 kb
Host smart-c1a47ccd-e95b-4a4c-bea7-5911ed97eb4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886070160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2886070160
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2995466571
Short name T1035
Test name
Test status
Simulation time 228156473 ps
CPU time 3.9 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 215084 kb
Host smart-6b05caef-21a3-4d72-b8ae-924f18f3a5d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995466571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2995466571
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3957109823
Short name T1046
Test name
Test status
Simulation time 181221528 ps
CPU time 4.82 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 216924 kb
Host smart-37643559-6467-4789-bc9a-97eba5395af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957109823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3957109823
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1527479201
Short name T256
Test name
Test status
Simulation time 842869475 ps
CPU time 20.95 seconds
Started May 12 12:57:59 PM PDT 24
Finished May 12 12:58:21 PM PDT 24
Peak memory 215828 kb
Host smart-77e34bc7-9b68-43be-9424-d2e6a799e228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527479201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1527479201
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2503400528
Short name T1018
Test name
Test status
Simulation time 207058316 ps
CPU time 4.02 seconds
Started May 12 12:58:04 PM PDT 24
Finished May 12 12:58:09 PM PDT 24
Peak memory 216608 kb
Host smart-eff5ab74-3191-419e-88ec-246e1ee48854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503400528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2503400528
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3387327587
Short name T116
Test name
Test status
Simulation time 425833263 ps
CPU time 2.74 seconds
Started May 12 12:58:03 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 215084 kb
Host smart-4dce1379-1bfd-48df-8073-0230e2c9c25e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387327587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3387327587
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1340813605
Short name T976
Test name
Test status
Simulation time 14713212 ps
CPU time 0.71 seconds
Started May 12 12:57:54 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 203472 kb
Host smart-9b98051f-6eb5-407a-aee1-ee91b53015a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340813605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1340813605
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.564396119
Short name T1020
Test name
Test status
Simulation time 26090863 ps
CPU time 1.74 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 215084 kb
Host smart-0c465c7c-bcf7-4e64-864e-dd32c0d450c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564396119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.564396119
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2988486296
Short name T87
Test name
Test status
Simulation time 462888417 ps
CPU time 3.2 seconds
Started May 12 12:58:02 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 215292 kb
Host smart-818e9134-d003-4ef6-a5d3-f6a763edde97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988486296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2988486296
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3763541008
Short name T258
Test name
Test status
Simulation time 323351071 ps
CPU time 7.7 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:18 PM PDT 24
Peak memory 215160 kb
Host smart-5b7d03ff-52dc-4345-adea-fc089b529bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763541008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3763541008
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.252540807
Short name T1000
Test name
Test status
Simulation time 52551485 ps
CPU time 1.79 seconds
Started May 12 12:57:54 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 215248 kb
Host smart-0580edd2-e2cb-484a-ac95-e047ef83d757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252540807 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.252540807
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.916760242
Short name T141
Test name
Test status
Simulation time 75361590 ps
CPU time 2 seconds
Started May 12 12:57:59 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 215168 kb
Host smart-cdf38094-54cc-4844-ab55-d03df813c7b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916760242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.916760242
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4022647218
Short name T1009
Test name
Test status
Simulation time 29995335 ps
CPU time 0.74 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:11 PM PDT 24
Peak memory 203756 kb
Host smart-b46c98f4-290a-4a61-8bcd-9eace67b2d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022647218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4022647218
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.414563056
Short name T1041
Test name
Test status
Simulation time 292303576 ps
CPU time 2.86 seconds
Started May 12 12:57:57 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 215084 kb
Host smart-78619e76-4ae0-4418-8488-c0fd72b13ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414563056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.414563056
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3310985035
Short name T255
Test name
Test status
Simulation time 191637683 ps
CPU time 4.99 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 216276 kb
Host smart-3627bd01-ed5e-4e86-be13-642dbef8062d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310985035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3310985035
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1222255404
Short name T1054
Test name
Test status
Simulation time 2183636085 ps
CPU time 7.47 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 215912 kb
Host smart-33e8d4a7-b2f4-4ebe-8965-10e5f2dd1c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222255404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1222255404
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3358471614
Short name T95
Test name
Test status
Simulation time 636211430 ps
CPU time 3.8 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 216948 kb
Host smart-5f346ceb-729f-4376-af7a-42f132e37a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358471614 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3358471614
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4021313630
Short name T118
Test name
Test status
Simulation time 39148018 ps
CPU time 2.33 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 215024 kb
Host smart-da5b6ebf-a660-4337-9858-c8fb5d872ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021313630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4021313630
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2159531417
Short name T1026
Test name
Test status
Simulation time 33280092 ps
CPU time 0.74 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 203468 kb
Host smart-afb1fb9a-4754-42d1-8b54-cb9dc4a6dd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159531417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2159531417
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1594417909
Short name T980
Test name
Test status
Simulation time 80723820 ps
CPU time 2.55 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 215104 kb
Host smart-c9ed6140-e627-4f13-9623-e18cddef5d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594417909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1594417909
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3501526507
Short name T98
Test name
Test status
Simulation time 811914254 ps
CPU time 3.1 seconds
Started May 12 12:58:15 PM PDT 24
Finished May 12 12:58:20 PM PDT 24
Peak memory 215608 kb
Host smart-9dd20fc9-5016-4990-bedf-57366d9accc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501526507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3501526507
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.375987404
Short name T89
Test name
Test status
Simulation time 1015318527 ps
CPU time 13.72 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:20 PM PDT 24
Peak memory 215100 kb
Host smart-fe645049-90c1-4678-919c-f1b8ec28b3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375987404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.375987404
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1808817482
Short name T1011
Test name
Test status
Simulation time 254711363 ps
CPU time 3.47 seconds
Started May 12 12:58:11 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 217012 kb
Host smart-09f6825e-ded9-4e90-a934-c68dca0ed1a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808817482 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1808817482
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1320448834
Short name T1080
Test name
Test status
Simulation time 301789538 ps
CPU time 2.01 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 206820 kb
Host smart-eed5d4ad-907a-4ee9-9327-4b5cf3ff4166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320448834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1320448834
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.349273395
Short name T979
Test name
Test status
Simulation time 19789577 ps
CPU time 0.73 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 203880 kb
Host smart-83a67be1-1efd-4677-ab25-91575718fbe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349273395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.349273395
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1193171376
Short name T1007
Test name
Test status
Simulation time 54077318 ps
CPU time 1.83 seconds
Started May 12 12:58:02 PM PDT 24
Finished May 12 12:58:05 PM PDT 24
Peak memory 215020 kb
Host smart-80e4c65e-d5ef-49e6-98ba-4bda21bfef84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193171376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1193171376
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.641795955
Short name T1050
Test name
Test status
Simulation time 1365116343 ps
CPU time 7.7 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 215424 kb
Host smart-745b08f6-b54e-4bc5-a1a4-07c29310d899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641795955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.641795955
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.888276197
Short name T1063
Test name
Test status
Simulation time 205691849 ps
CPU time 1.62 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 215212 kb
Host smart-6ec97620-630a-4885-955c-c96e2967d958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888276197 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.888276197
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4255558556
Short name T109
Test name
Test status
Simulation time 240477048 ps
CPU time 1.75 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 214988 kb
Host smart-c1ba5d25-f06d-452d-bece-c5b482234fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255558556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4255558556
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3725836122
Short name T1052
Test name
Test status
Simulation time 12127278 ps
CPU time 0.75 seconds
Started May 12 12:58:10 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 203748 kb
Host smart-00d5ddca-0591-4d8b-8d76-98760e410348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725836122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3725836122
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.463887225
Short name T1015
Test name
Test status
Simulation time 84494565 ps
CPU time 1.64 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 214996 kb
Host smart-e1fc6169-a063-4502-bfc7-35b79042172a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463887225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.463887225
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.527594826
Short name T97
Test name
Test status
Simulation time 68691869 ps
CPU time 2.24 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 215516 kb
Host smart-cb1c0f7a-5a5a-4b4d-9895-71b79137cf2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527594826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.527594826
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2782311175
Short name T88
Test name
Test status
Simulation time 101457648 ps
CPU time 6.31 seconds
Started May 12 12:58:12 PM PDT 24
Finished May 12 12:58:20 PM PDT 24
Peak memory 215048 kb
Host smart-df69c73e-5be4-48d8-bf56-ec0cf7ef3562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782311175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2782311175
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4242447610
Short name T1032
Test name
Test status
Simulation time 61984115 ps
CPU time 1.82 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 215212 kb
Host smart-0938b048-ce39-4047-95ef-ff593dba9e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242447610 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4242447610
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3112954675
Short name T1075
Test name
Test status
Simulation time 247521341 ps
CPU time 2 seconds
Started May 12 12:58:17 PM PDT 24
Finished May 12 12:58:20 PM PDT 24
Peak memory 206836 kb
Host smart-9bb82816-69c0-4987-baff-24c02217fcb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112954675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3112954675
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.175442979
Short name T973
Test name
Test status
Simulation time 27694613 ps
CPU time 0.72 seconds
Started May 12 12:58:20 PM PDT 24
Finished May 12 12:58:21 PM PDT 24
Peak memory 203728 kb
Host smart-3b1a543e-663d-44cc-be0d-593ce4749e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175442979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.175442979
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1593297879
Short name T1027
Test name
Test status
Simulation time 1867054732 ps
CPU time 3.11 seconds
Started May 12 12:58:04 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 215100 kb
Host smart-e83cdd9c-4386-415b-895a-d1538eab9edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593297879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1593297879
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.207478572
Short name T1067
Test name
Test status
Simulation time 4689399033 ps
CPU time 24.09 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:35 PM PDT 24
Peak memory 215168 kb
Host smart-fd3c7edd-2fd8-4583-87e1-ac22f57d8906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207478572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.207478572
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1636698791
Short name T1073
Test name
Test status
Simulation time 218776395 ps
CPU time 3.54 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 218012 kb
Host smart-88c377e1-3ea7-4bb3-8875-615d72048f72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636698791 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1636698791
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3471457924
Short name T986
Test name
Test status
Simulation time 52104997 ps
CPU time 2.35 seconds
Started May 12 12:58:10 PM PDT 24
Finished May 12 12:58:15 PM PDT 24
Peak memory 215060 kb
Host smart-cdac3742-d5b7-4cba-8409-511d16d25f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471457924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3471457924
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2487795424
Short name T1022
Test name
Test status
Simulation time 16909590 ps
CPU time 0.67 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 203876 kb
Host smart-f41bcdfa-2865-4b62-89e1-b04d18324355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487795424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2487795424
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3418302335
Short name T1034
Test name
Test status
Simulation time 74286866 ps
CPU time 1.88 seconds
Started May 12 12:58:18 PM PDT 24
Finished May 12 12:58:21 PM PDT 24
Peak memory 215108 kb
Host smart-d662c39d-4f6c-4c29-aa87-1c33635d2a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418302335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3418302335
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2187374869
Short name T60
Test name
Test status
Simulation time 264451470 ps
CPU time 1.87 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 215348 kb
Host smart-2c89e75a-dc45-4aef-a872-fa53d992c827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187374869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2187374869
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2923906071
Short name T1066
Test name
Test status
Simulation time 112903358 ps
CPU time 6.94 seconds
Started May 12 12:58:03 PM PDT 24
Finished May 12 12:58:11 PM PDT 24
Peak memory 206808 kb
Host smart-0bc6dbb3-cba0-494c-903e-db3857a0b20d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923906071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2923906071
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3702055364
Short name T1081
Test name
Test status
Simulation time 710784485 ps
CPU time 11.97 seconds
Started May 12 12:57:48 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 206812 kb
Host smart-662bb4a6-eaef-4358-b5b2-f035a0f35a82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702055364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3702055364
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.779990109
Short name T75
Test name
Test status
Simulation time 62970839 ps
CPU time 0.95 seconds
Started May 12 12:57:42 PM PDT 24
Finished May 12 12:57:43 PM PDT 24
Peak memory 206604 kb
Host smart-a1e1ecd4-a026-424c-adb1-e9c522809ec2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779990109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.779990109
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2606861755
Short name T104
Test name
Test status
Simulation time 403217789 ps
CPU time 2.78 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 217020 kb
Host smart-8160da62-bd9a-4ae4-9211-efa94bbb8122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606861755 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2606861755
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2316706521
Short name T115
Test name
Test status
Simulation time 189151005 ps
CPU time 2.93 seconds
Started May 12 12:57:51 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 214996 kb
Host smart-9f92aa0d-da72-4648-956a-da1ff291b6e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316706521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
316706521
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3513209043
Short name T1014
Test name
Test status
Simulation time 63990184 ps
CPU time 0.75 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:57:51 PM PDT 24
Peak memory 203536 kb
Host smart-e4036c05-6483-45e5-9496-33ffc2272b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513209043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
513209043
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.151582521
Short name T1051
Test name
Test status
Simulation time 158248878 ps
CPU time 1.69 seconds
Started May 12 12:57:58 PM PDT 24
Finished May 12 12:58:00 PM PDT 24
Peak memory 215188 kb
Host smart-c41565d9-f88d-4777-83c6-cc608e93ef6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151582521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.151582521
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.288687575
Short name T965
Test name
Test status
Simulation time 13125020 ps
CPU time 0.64 seconds
Started May 12 12:57:57 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 203332 kb
Host smart-526c69e3-e5d1-47f9-8c2b-9070f3e99cb9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288687575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.288687575
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2405748909
Short name T143
Test name
Test status
Simulation time 2461547115 ps
CPU time 3.46 seconds
Started May 12 12:57:53 PM PDT 24
Finished May 12 12:57:57 PM PDT 24
Peak memory 215740 kb
Host smart-da2ec40d-2ce2-4e9a-af7a-9c42699a630c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405748909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2405748909
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.455230235
Short name T1048
Test name
Test status
Simulation time 36371928 ps
CPU time 2.24 seconds
Started May 12 12:57:53 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 215308 kb
Host smart-0fee0d3d-c274-4226-97ce-7b437f08805a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455230235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.455230235
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.332554887
Short name T1077
Test name
Test status
Simulation time 2891791743 ps
CPU time 16.16 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 215204 kb
Host smart-26d0a033-7985-4e0c-9886-9f3e3beb27db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332554887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.332554887
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3484990440
Short name T1031
Test name
Test status
Simulation time 41296801 ps
CPU time 0.73 seconds
Started May 12 12:58:12 PM PDT 24
Finished May 12 12:58:15 PM PDT 24
Peak memory 203472 kb
Host smart-a7368600-767d-4bde-8483-a141749e4e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484990440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3484990440
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1558180779
Short name T967
Test name
Test status
Simulation time 25694862 ps
CPU time 0.71 seconds
Started May 12 12:58:16 PM PDT 24
Finished May 12 12:58:18 PM PDT 24
Peak memory 203572 kb
Host smart-e69d04e7-15d6-4531-b445-84244f9b4d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558180779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1558180779
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3560472338
Short name T991
Test name
Test status
Simulation time 258859292 ps
CPU time 0.72 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 203456 kb
Host smart-ba326a4d-b0f6-4282-8f28-b65428e5748b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560472338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3560472338
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2505040045
Short name T1065
Test name
Test status
Simulation time 14504504 ps
CPU time 0.75 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 203800 kb
Host smart-08193250-07fe-41ac-86fc-5366d096d0a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505040045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2505040045
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.573803154
Short name T984
Test name
Test status
Simulation time 17425960 ps
CPU time 0.69 seconds
Started May 12 12:58:21 PM PDT 24
Finished May 12 12:58:23 PM PDT 24
Peak memory 203476 kb
Host smart-69105bde-8030-4ca1-b697-f65344f44c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573803154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.573803154
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3248362746
Short name T999
Test name
Test status
Simulation time 36548269 ps
CPU time 0.73 seconds
Started May 12 12:58:11 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 202984 kb
Host smart-56f84b76-d7e8-4a3b-bb6a-6540314cb0bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248362746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3248362746
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3666001844
Short name T985
Test name
Test status
Simulation time 71064223 ps
CPU time 0.74 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 203428 kb
Host smart-defd2002-1cd8-4718-8132-ff2ccde8d338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666001844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3666001844
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4124760993
Short name T964
Test name
Test status
Simulation time 37573500 ps
CPU time 0.71 seconds
Started May 12 12:58:13 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 203868 kb
Host smart-ba6fd49c-8dea-40f9-9de5-225b79b0a190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124760993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4124760993
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1900720600
Short name T1016
Test name
Test status
Simulation time 43277427 ps
CPU time 0.71 seconds
Started May 12 12:58:12 PM PDT 24
Finished May 12 12:58:15 PM PDT 24
Peak memory 203868 kb
Host smart-26d03b9c-78ba-40fd-9234-a8971be162e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900720600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1900720600
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4284700299
Short name T1042
Test name
Test status
Simulation time 51899476 ps
CPU time 0.78 seconds
Started May 12 12:58:21 PM PDT 24
Finished May 12 12:58:23 PM PDT 24
Peak memory 203756 kb
Host smart-db3f0933-f2f7-47ee-b8ef-7527d17d0fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284700299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4284700299
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.28918504
Short name T120
Test name
Test status
Simulation time 2410328051 ps
CPU time 15.43 seconds
Started May 12 12:57:58 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 215024 kb
Host smart-80af780d-7737-4dab-9846-64d9ae196de4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28918504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
aliasing.28918504
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2095998523
Short name T989
Test name
Test status
Simulation time 23988162737 ps
CPU time 24.27 seconds
Started May 12 12:57:53 PM PDT 24
Finished May 12 12:58:18 PM PDT 24
Peak memory 215096 kb
Host smart-e6c13d8a-eacd-4cff-9629-04a4e7086335
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095998523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2095998523
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3101339039
Short name T74
Test name
Test status
Simulation time 31034949 ps
CPU time 1.24 seconds
Started May 12 12:57:52 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 216272 kb
Host smart-7f6ca7ba-f8c6-42d1-bafe-dd693a2d6a94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101339039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3101339039
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3131855329
Short name T996
Test name
Test status
Simulation time 156019972 ps
CPU time 3.73 seconds
Started May 12 12:57:54 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 217576 kb
Host smart-04da2b85-d686-40ab-9a3b-9c75e3f180fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131855329 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3131855329
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1241677061
Short name T997
Test name
Test status
Simulation time 37536972 ps
CPU time 2.39 seconds
Started May 12 12:57:46 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 215016 kb
Host smart-e75a2faf-aff2-40e0-96b1-5f990b7f1ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241677061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
241677061
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1192198595
Short name T968
Test name
Test status
Simulation time 45946576 ps
CPU time 0.69 seconds
Started May 12 12:57:44 PM PDT 24
Finished May 12 12:57:46 PM PDT 24
Peak memory 203428 kb
Host smart-ba31d5dc-117c-4d89-817a-75edee8f6dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192198595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
192198595
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3187413926
Short name T107
Test name
Test status
Simulation time 47123278 ps
CPU time 1.73 seconds
Started May 12 12:58:02 PM PDT 24
Finished May 12 12:58:04 PM PDT 24
Peak memory 215228 kb
Host smart-a8800037-d974-4b3e-9ed2-a0b72e6b5313
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187413926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3187413926
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.23583854
Short name T1033
Test name
Test status
Simulation time 44826972 ps
CPU time 0.69 seconds
Started May 12 12:57:55 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 203672 kb
Host smart-22aa9f90-55d3-4e6f-8660-e994cfcc7bf5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23583854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_
walk.23583854
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2954621879
Short name T1039
Test name
Test status
Simulation time 2861473002 ps
CPU time 3.21 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 215068 kb
Host smart-59f1e129-4762-43b2-bd9c-0e1f53528b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954621879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2954621879
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1820410821
Short name T96
Test name
Test status
Simulation time 166809364 ps
CPU time 3.95 seconds
Started May 12 12:57:57 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 215280 kb
Host smart-706f2595-bb72-4590-9ceb-7ac3c2a97d26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820410821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
820410821
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1263575985
Short name T1028
Test name
Test status
Simulation time 100266096 ps
CPU time 6.42 seconds
Started May 12 12:57:52 PM PDT 24
Finished May 12 12:57:59 PM PDT 24
Peak memory 215168 kb
Host smart-0282e131-5134-424c-bba4-bbacd325fe00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263575985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1263575985
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.842078672
Short name T1005
Test name
Test status
Simulation time 41721389 ps
CPU time 0.7 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 203500 kb
Host smart-9ad7b18c-2e79-421e-90cf-1ce2fe702a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842078672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.842078672
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1736257257
Short name T1013
Test name
Test status
Simulation time 16531102 ps
CPU time 0.73 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 203732 kb
Host smart-4c58f6ae-3182-457f-ac0d-a93d686af033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736257257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1736257257
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3100311456
Short name T970
Test name
Test status
Simulation time 17083159 ps
CPU time 0.75 seconds
Started May 12 12:58:00 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 203824 kb
Host smart-16775962-d521-4795-854a-b2c97244e1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100311456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3100311456
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.131282395
Short name T1078
Test name
Test status
Simulation time 14053352 ps
CPU time 0.76 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:08 PM PDT 24
Peak memory 203456 kb
Host smart-7a1b8a79-8700-4c57-8a99-f1a87cfed00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131282395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.131282395
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2912339293
Short name T963
Test name
Test status
Simulation time 63217774 ps
CPU time 0.71 seconds
Started May 12 12:58:11 PM PDT 24
Finished May 12 12:58:14 PM PDT 24
Peak memory 203324 kb
Host smart-3be2c2a7-7b59-405e-afa5-4b265046a644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912339293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2912339293
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3615099381
Short name T988
Test name
Test status
Simulation time 89949928 ps
CPU time 0.68 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 203448 kb
Host smart-898f43c9-5abd-45e7-a22b-0de9aed35c5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615099381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3615099381
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3341057755
Short name T992
Test name
Test status
Simulation time 42631338 ps
CPU time 0.73 seconds
Started May 12 12:58:23 PM PDT 24
Finished May 12 12:58:24 PM PDT 24
Peak memory 203472 kb
Host smart-3065ba23-08f5-4f21-aad8-821ea4c2ea0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341057755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3341057755
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3056167001
Short name T983
Test name
Test status
Simulation time 102679594 ps
CPU time 0.68 seconds
Started May 12 12:58:24 PM PDT 24
Finished May 12 12:58:25 PM PDT 24
Peak memory 203476 kb
Host smart-45cf3113-c1e1-45c4-ac55-6b8a1da0e9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056167001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3056167001
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3819131944
Short name T981
Test name
Test status
Simulation time 32411443 ps
CPU time 0.7 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:09 PM PDT 24
Peak memory 203432 kb
Host smart-66e9599c-6040-442c-be3a-88fa5e4067cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819131944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3819131944
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1822105666
Short name T1059
Test name
Test status
Simulation time 34958581 ps
CPU time 0.74 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 203488 kb
Host smart-ed709c82-2c03-4979-a59c-90774f7f3c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822105666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1822105666
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2812176450
Short name T1056
Test name
Test status
Simulation time 882604419 ps
CPU time 9.15 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:55 PM PDT 24
Peak memory 214972 kb
Host smart-69424e6d-2043-4644-b58e-7e3772fea3c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812176450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2812176450
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3035134656
Short name T1006
Test name
Test status
Simulation time 3769342894 ps
CPU time 38.3 seconds
Started May 12 12:58:03 PM PDT 24
Finished May 12 12:58:43 PM PDT 24
Peak memory 206916 kb
Host smart-ea6917e3-7ee4-4af9-a1ed-b2ed696ef28e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035134656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3035134656
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2138698184
Short name T73
Test name
Test status
Simulation time 41916664 ps
CPU time 1.38 seconds
Started May 12 12:57:52 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 206704 kb
Host smart-9acb12de-ac6b-4526-9b32-70d7ed513aab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138698184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2138698184
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4233470493
Short name T99
Test name
Test status
Simulation time 103622724 ps
CPU time 2.59 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:53 PM PDT 24
Peak memory 216496 kb
Host smart-85bb2e9c-217d-4c75-80a2-8013f2c9909a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233470493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4233470493
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.471084147
Short name T1060
Test name
Test status
Simulation time 95625279 ps
CPU time 1.42 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 215172 kb
Host smart-51199773-50ef-4fce-8998-7b0586976c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471084147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.471084147
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.572719900
Short name T977
Test name
Test status
Simulation time 11172907 ps
CPU time 0.69 seconds
Started May 12 12:57:51 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 203436 kb
Host smart-51ccd6d8-b446-4cb4-b3e1-2ae2ce19aba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572719900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.572719900
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.889660210
Short name T1074
Test name
Test status
Simulation time 235906051 ps
CPU time 2.17 seconds
Started May 12 12:57:55 PM PDT 24
Finished May 12 12:57:58 PM PDT 24
Peak memory 215080 kb
Host smart-e64ecb1b-892e-4904-85ca-2f267db10102
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889660210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.889660210
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2574956430
Short name T974
Test name
Test status
Simulation time 65498623 ps
CPU time 0.68 seconds
Started May 12 12:58:03 PM PDT 24
Finished May 12 12:58:05 PM PDT 24
Peak memory 203404 kb
Host smart-19a5a465-1313-49cd-b5fa-2ca17630e47b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574956430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2574956430
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.553224223
Short name T960
Test name
Test status
Simulation time 58711974 ps
CPU time 3.58 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:11 PM PDT 24
Peak memory 215160 kb
Host smart-481f59e1-aeab-43eb-9c81-c8ce051bba3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553224223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.553224223
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.854905181
Short name T1049
Test name
Test status
Simulation time 348538910 ps
CPU time 2.56 seconds
Started May 12 12:57:44 PM PDT 24
Finished May 12 12:57:48 PM PDT 24
Peak memory 216328 kb
Host smart-cd22aa42-0a0f-484d-a98d-0ca3c7023b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854905181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.854905181
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2546372505
Short name T261
Test name
Test status
Simulation time 3403207613 ps
CPU time 14.03 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:23 PM PDT 24
Peak memory 215528 kb
Host smart-59dc40ee-1b88-46aa-9385-f6cd22e10213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546372505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2546372505
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2452208554
Short name T993
Test name
Test status
Simulation time 39561775 ps
CPU time 0.72 seconds
Started May 12 12:58:08 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 203440 kb
Host smart-6ae42320-8380-4fd8-9772-2dd88b8605d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452208554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2452208554
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1485330426
Short name T1036
Test name
Test status
Simulation time 34532360 ps
CPU time 0.71 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 203492 kb
Host smart-d384c33c-fa83-4a72-aa4f-76dec0b41ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485330426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1485330426
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.533226388
Short name T1012
Test name
Test status
Simulation time 23077660 ps
CPU time 0.73 seconds
Started May 12 12:58:07 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 203436 kb
Host smart-62e6b8cc-a74a-4d12-a9ac-3c79d27f0af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533226388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.533226388
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1751795246
Short name T978
Test name
Test status
Simulation time 192678782 ps
CPU time 0.75 seconds
Started May 12 12:58:21 PM PDT 24
Finished May 12 12:58:23 PM PDT 24
Peak memory 203744 kb
Host smart-6bfd3b65-675c-4630-acf3-8f1db8fd3369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751795246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1751795246
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3889960611
Short name T969
Test name
Test status
Simulation time 24431997 ps
CPU time 0.69 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 203464 kb
Host smart-dcba9756-b741-473d-afa0-769627de1182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889960611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3889960611
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3538356841
Short name T1070
Test name
Test status
Simulation time 19333425 ps
CPU time 0.76 seconds
Started May 12 12:58:15 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 203776 kb
Host smart-9673deae-5699-4d5f-8cc7-1baa72dbd479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538356841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3538356841
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3039426457
Short name T1003
Test name
Test status
Simulation time 21195895 ps
CPU time 0.79 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 203428 kb
Host smart-8878a918-16d0-4316-a750-54985ac5f046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039426457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3039426457
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3841530081
Short name T995
Test name
Test status
Simulation time 48454733 ps
CPU time 0.73 seconds
Started May 12 12:58:19 PM PDT 24
Finished May 12 12:58:20 PM PDT 24
Peak memory 203508 kb
Host smart-e2d62434-2052-4f12-8128-f93e4dcc4620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841530081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3841530081
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.152080916
Short name T987
Test name
Test status
Simulation time 18323210 ps
CPU time 0.76 seconds
Started May 12 12:58:15 PM PDT 24
Finished May 12 12:58:17 PM PDT 24
Peak memory 203752 kb
Host smart-80e2faf2-5967-4952-badb-1b0e102d6350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152080916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.152080916
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3965350739
Short name T1008
Test name
Test status
Simulation time 31993548 ps
CPU time 0.76 seconds
Started May 12 12:58:09 PM PDT 24
Finished May 12 12:58:12 PM PDT 24
Peak memory 203408 kb
Host smart-119c470f-ab4f-4f80-a722-c42d3aa2cb79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965350739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3965350739
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2973491843
Short name T61
Test name
Test status
Simulation time 111207440 ps
CPU time 3.05 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:53 PM PDT 24
Peak memory 216508 kb
Host smart-03bd00d9-5628-4523-bbb5-d524cdaaa886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973491843 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2973491843
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2582038387
Short name T1047
Test name
Test status
Simulation time 43555123 ps
CPU time 2.63 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:09 PM PDT 24
Peak memory 215044 kb
Host smart-4a9f26f6-7ca1-4847-b1c8-7ec6069455c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582038387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
582038387
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1347060777
Short name T975
Test name
Test status
Simulation time 12010779 ps
CPU time 0.71 seconds
Started May 12 12:57:50 PM PDT 24
Finished May 12 12:57:51 PM PDT 24
Peak memory 203552 kb
Host smart-252624b2-062a-4b1c-af00-3a31ba758c65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347060777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
347060777
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2608862792
Short name T971
Test name
Test status
Simulation time 98693250 ps
CPU time 2.77 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:53 PM PDT 24
Peak memory 215096 kb
Host smart-81648de7-2ca6-4439-acf3-ea01af5b8b37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608862792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2608862792
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3266182154
Short name T1043
Test name
Test status
Simulation time 503778040 ps
CPU time 4.73 seconds
Started May 12 12:57:55 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 215392 kb
Host smart-8f42e0ed-d532-4b05-a863-b6df860a5be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266182154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
266182154
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3243359362
Short name T144
Test name
Test status
Simulation time 1366765835 ps
CPU time 8.05 seconds
Started May 12 12:57:57 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 215004 kb
Host smart-ed878352-f4cc-449b-9a56-910c250086d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243359362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3243359362
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2951228752
Short name T998
Test name
Test status
Simulation time 81043128 ps
CPU time 2.17 seconds
Started May 12 12:57:44 PM PDT 24
Finished May 12 12:57:47 PM PDT 24
Peak memory 215028 kb
Host smart-5edf5c0b-0a8f-43d6-ad47-326c878786d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951228752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
951228752
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.84360161
Short name T1044
Test name
Test status
Simulation time 15969672 ps
CPU time 0.69 seconds
Started May 12 12:57:59 PM PDT 24
Finished May 12 12:58:00 PM PDT 24
Peak memory 203536 kb
Host smart-aed8824d-6596-42ed-88a2-09718c854aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84360161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.84360161
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3072146134
Short name T990
Test name
Test status
Simulation time 64452467 ps
CPU time 1.86 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 206932 kb
Host smart-e7ffa3ca-e546-4f11-aa3d-07d5e437f02b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072146134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3072146134
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4148823348
Short name T94
Test name
Test status
Simulation time 427090702 ps
CPU time 3.25 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 215292 kb
Host smart-e658e50b-ac08-4cde-a3de-41e4b13012ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148823348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
148823348
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.64162551
Short name T100
Test name
Test status
Simulation time 154120628 ps
CPU time 3.12 seconds
Started May 12 12:57:45 PM PDT 24
Finished May 12 12:57:49 PM PDT 24
Peak memory 216520 kb
Host smart-e62cd27f-4231-4f39-a620-cb7b8a6261bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64162551 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.64162551
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3493992585
Short name T111
Test name
Test status
Simulation time 30054704 ps
CPU time 1.3 seconds
Started May 12 12:57:54 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 206924 kb
Host smart-ceb4537b-3c88-468a-860e-9c95c3604cfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493992585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
493992585
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1027710382
Short name T1029
Test name
Test status
Simulation time 51780893 ps
CPU time 0.7 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 203740 kb
Host smart-1c9b0284-2312-491c-a137-5ddc20713808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027710382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
027710382
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.276825549
Short name T982
Test name
Test status
Simulation time 118504469 ps
CPU time 3.56 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:11 PM PDT 24
Peak memory 215124 kb
Host smart-5dfaa470-2887-43b3-a2ee-941b3c4719f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276825549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.276825549
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.491127502
Short name T1017
Test name
Test status
Simulation time 28947963 ps
CPU time 1.48 seconds
Started May 12 12:57:49 PM PDT 24
Finished May 12 12:57:52 PM PDT 24
Peak memory 215208 kb
Host smart-925c25a6-c934-43d9-864b-6a17f3e70636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491127502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.491127502
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.898161966
Short name T90
Test name
Test status
Simulation time 188905955 ps
CPU time 6.67 seconds
Started May 12 12:58:02 PM PDT 24
Finished May 12 12:58:09 PM PDT 24
Peak memory 215508 kb
Host smart-00e8d260-90cc-492e-bf8d-273a650e9de5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898161966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.898161966
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2420757643
Short name T102
Test name
Test status
Simulation time 76532496 ps
CPU time 2.89 seconds
Started May 12 12:57:58 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 217648 kb
Host smart-2a5a3bf0-cf6f-4763-8407-d5134b90e71b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420757643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2420757643
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1416583147
Short name T117
Test name
Test status
Simulation time 424013468 ps
CPU time 2.59 seconds
Started May 12 12:58:00 PM PDT 24
Finished May 12 12:58:03 PM PDT 24
Peak memory 215048 kb
Host smart-ea1452fc-d8f2-48e1-812a-ced43dadcba7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416583147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
416583147
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1800878048
Short name T1038
Test name
Test status
Simulation time 48246249 ps
CPU time 0.73 seconds
Started May 12 12:58:14 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 203424 kb
Host smart-4349896b-9db0-4bd6-9210-1fdf67a5cc71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800878048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
800878048
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1244420295
Short name T1004
Test name
Test status
Simulation time 224243040 ps
CPU time 3.46 seconds
Started May 12 12:57:59 PM PDT 24
Finished May 12 12:58:03 PM PDT 24
Peak memory 215120 kb
Host smart-bf65eaaf-ab8c-40c4-b59e-2f9c3304f82c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244420295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1244420295
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.101698878
Short name T254
Test name
Test status
Simulation time 61437360 ps
CPU time 3.95 seconds
Started May 12 12:57:56 PM PDT 24
Finished May 12 12:58:01 PM PDT 24
Peak memory 215244 kb
Host smart-f4fcdd96-af2b-4c6c-9077-0d21a7f0354b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101698878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.101698878
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2753769501
Short name T262
Test name
Test status
Simulation time 1030463679 ps
CPU time 21.39 seconds
Started May 12 12:58:05 PM PDT 24
Finished May 12 12:58:27 PM PDT 24
Peak memory 215100 kb
Host smart-67074745-514e-468c-a35a-ccc6eac328ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753769501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2753769501
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4213150150
Short name T1023
Test name
Test status
Simulation time 127883082 ps
CPU time 1.73 seconds
Started May 12 12:58:02 PM PDT 24
Finished May 12 12:58:04 PM PDT 24
Peak memory 215540 kb
Host smart-2a23a8f3-2ac8-4075-b8bd-2a305702fbbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213150150 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4213150150
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3220772169
Short name T1064
Test name
Test status
Simulation time 620851261 ps
CPU time 1.31 seconds
Started May 12 12:58:13 PM PDT 24
Finished May 12 12:58:16 PM PDT 24
Peak memory 206744 kb
Host smart-5dcc7ed3-ee39-4327-803c-d9ddea173194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220772169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
220772169
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2655116492
Short name T961
Test name
Test status
Simulation time 24683227 ps
CPU time 0.73 seconds
Started May 12 12:58:00 PM PDT 24
Finished May 12 12:58:02 PM PDT 24
Peak memory 203720 kb
Host smart-fdb87631-9643-42cd-a763-c334a314b47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655116492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
655116492
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3834302755
Short name T1062
Test name
Test status
Simulation time 119293312 ps
CPU time 1.79 seconds
Started May 12 12:58:06 PM PDT 24
Finished May 12 12:58:10 PM PDT 24
Peak memory 215060 kb
Host smart-28da5b50-3567-42d4-9be7-a27b2e7ce39e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834302755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3834302755
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3058361527
Short name T1025
Test name
Test status
Simulation time 114435349 ps
CPU time 3.17 seconds
Started May 12 12:58:03 PM PDT 24
Finished May 12 12:58:06 PM PDT 24
Peak memory 215308 kb
Host smart-b154fd89-3769-4896-90a3-86c2f4c09326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058361527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
058361527
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2278935406
Short name T1072
Test name
Test status
Simulation time 1714280217 ps
CPU time 8.52 seconds
Started May 12 12:58:04 PM PDT 24
Finished May 12 12:58:13 PM PDT 24
Peak memory 215072 kb
Host smart-280fad6d-70e6-4c01-8dd3-7892598bfb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278935406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2278935406
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1180628138
Short name T82
Test name
Test status
Simulation time 593373250 ps
CPU time 4.34 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:01:28 PM PDT 24
Peak memory 218196 kb
Host smart-e50bb5a3-a012-4d15-8544-4ffc538112af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180628138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1180628138
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.168700982
Short name T363
Test name
Test status
Simulation time 52051728 ps
CPU time 0.79 seconds
Started May 12 01:01:20 PM PDT 24
Finished May 12 01:01:21 PM PDT 24
Peak memory 206668 kb
Host smart-b8c44d81-df82-4741-b23f-517816d80595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168700982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.168700982
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3937473553
Short name T945
Test name
Test status
Simulation time 20713573748 ps
CPU time 146.12 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:03:50 PM PDT 24
Peak memory 256540 kb
Host smart-4790d12c-871f-4c32-a999-500a333ea857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937473553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3937473553
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1587356437
Short name T128
Test name
Test status
Simulation time 10738875816 ps
CPU time 168 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:04:12 PM PDT 24
Peak memory 250832 kb
Host smart-eaf1ad9f-8abb-4131-a6d1-92f6bb4894d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587356437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1587356437
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.925834835
Short name T617
Test name
Test status
Simulation time 3023973173 ps
CPU time 44.41 seconds
Started May 12 01:01:25 PM PDT 24
Finished May 12 01:02:09 PM PDT 24
Peak memory 240828 kb
Host smart-e69471ef-0623-49f6-ba4d-891b4d1ca71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925834835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
925834835
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1969580860
Short name T408
Test name
Test status
Simulation time 1035841456 ps
CPU time 4.07 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:01:28 PM PDT 24
Peak memory 232564 kb
Host smart-9b864d8d-4678-4eea-adf3-72b114ea8991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969580860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1969580860
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1746685290
Short name T666
Test name
Test status
Simulation time 599059910 ps
CPU time 3.89 seconds
Started May 12 01:01:24 PM PDT 24
Finished May 12 01:01:28 PM PDT 24
Peak memory 218340 kb
Host smart-43aae1c3-3cf3-48e3-ba10-4a6f135b7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746685290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1746685290
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1422021315
Short name T610
Test name
Test status
Simulation time 2478774321 ps
CPU time 7.33 seconds
Started May 12 01:01:22 PM PDT 24
Finished May 12 01:01:30 PM PDT 24
Peak memory 233388 kb
Host smart-79b41678-ebdd-4b32-bb78-295610a1a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422021315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1422021315
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1747055475
Short name T14
Test name
Test status
Simulation time 23163691096 ps
CPU time 12.47 seconds
Started May 12 01:01:22 PM PDT 24
Finished May 12 01:01:35 PM PDT 24
Peak memory 229652 kb
Host smart-958c0488-15fe-4a1d-8817-9af0cec1e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747055475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1747055475
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1845146932
Short name T461
Test name
Test status
Simulation time 69053348 ps
CPU time 3.85 seconds
Started May 12 01:01:24 PM PDT 24
Finished May 12 01:01:28 PM PDT 24
Peak memory 222572 kb
Host smart-3e9fa5f3-0e4b-4f1a-99b4-66ad99fd6952
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1845146932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1845146932
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.94827462
Short name T66
Test name
Test status
Simulation time 123881141 ps
CPU time 1.01 seconds
Started May 12 01:01:24 PM PDT 24
Finished May 12 01:01:26 PM PDT 24
Peak memory 234480 kb
Host smart-b2763f4e-179d-44c4-b1df-ec7abff60f47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94827462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.94827462
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2554476139
Short name T624
Test name
Test status
Simulation time 866535325 ps
CPU time 13.03 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:01:36 PM PDT 24
Peak memory 218784 kb
Host smart-080bda32-907b-45a4-8aa3-98b9a337f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554476139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2554476139
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1871839570
Short name T717
Test name
Test status
Simulation time 11879248405 ps
CPU time 8.88 seconds
Started May 12 01:01:24 PM PDT 24
Finished May 12 01:01:34 PM PDT 24
Peak memory 216084 kb
Host smart-7447e321-ef2c-4ea6-b83a-8241a83f9c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871839570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1871839570
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2821250178
Short name T445
Test name
Test status
Simulation time 256895572 ps
CPU time 1.4 seconds
Started May 12 01:01:23 PM PDT 24
Finished May 12 01:01:25 PM PDT 24
Peak memory 216148 kb
Host smart-baea7a76-963c-4506-9a5f-9be5592feab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821250178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2821250178
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3715452658
Short name T615
Test name
Test status
Simulation time 201872687 ps
CPU time 0.85 seconds
Started May 12 01:01:22 PM PDT 24
Finished May 12 01:01:23 PM PDT 24
Peak memory 205580 kb
Host smart-9550645a-70fa-4ef3-8b39-3fadb12f5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715452658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3715452658
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3503838148
Short name T735
Test name
Test status
Simulation time 220821407 ps
CPU time 4.14 seconds
Started May 12 01:01:24 PM PDT 24
Finished May 12 01:01:28 PM PDT 24
Peak memory 234012 kb
Host smart-e6b32f99-9d59-4369-b678-98fe9c916961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503838148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3503838148
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3555839885
Short name T493
Test name
Test status
Simulation time 34234796 ps
CPU time 0.73 seconds
Started May 12 01:01:33 PM PDT 24
Finished May 12 01:01:34 PM PDT 24
Peak memory 204620 kb
Host smart-5efc1c3e-9d1b-458c-9fa7-91ca7017f983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555839885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
555839885
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1912005404
Short name T782
Test name
Test status
Simulation time 247914876 ps
CPU time 3.43 seconds
Started May 12 01:01:30 PM PDT 24
Finished May 12 01:01:34 PM PDT 24
Peak memory 218604 kb
Host smart-00510677-fa37-467d-a5da-f0a7ee335cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912005404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1912005404
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1169839252
Short name T511
Test name
Test status
Simulation time 15563656 ps
CPU time 0.75 seconds
Started May 12 01:01:30 PM PDT 24
Finished May 12 01:01:31 PM PDT 24
Peak memory 205296 kb
Host smart-5729f728-48f6-4b6f-bdae-9715a80e4c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169839252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1169839252
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1989104184
Short name T211
Test name
Test status
Simulation time 9753800016 ps
CPU time 39.92 seconds
Started May 12 01:01:28 PM PDT 24
Finished May 12 01:02:08 PM PDT 24
Peak memory 224416 kb
Host smart-24ac722c-97bf-4ddd-8e7c-af0434463593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989104184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1989104184
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3009630646
Short name T820
Test name
Test status
Simulation time 901752080 ps
CPU time 2.77 seconds
Started May 12 01:01:27 PM PDT 24
Finished May 12 01:01:30 PM PDT 24
Peak memory 217156 kb
Host smart-5942da3b-f679-45bc-a1ed-583a2a535ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009630646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3009630646
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2962447025
Short name T357
Test name
Test status
Simulation time 364328019 ps
CPU time 3.24 seconds
Started May 12 01:01:27 PM PDT 24
Finished May 12 01:01:31 PM PDT 24
Peak memory 224200 kb
Host smart-a31774ce-cb19-4c90-b09f-a229f4134fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962447025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2962447025
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.842257369
Short name T736
Test name
Test status
Simulation time 1032226061 ps
CPU time 10.18 seconds
Started May 12 01:01:29 PM PDT 24
Finished May 12 01:01:39 PM PDT 24
Peak memory 236620 kb
Host smart-4030a3b0-a7d5-4a4b-9b88-d3c58b6585c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842257369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.842257369
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2250884327
Short name T200
Test name
Test status
Simulation time 39521150475 ps
CPU time 84.77 seconds
Started May 12 01:01:28 PM PDT 24
Finished May 12 01:02:53 PM PDT 24
Peak memory 218376 kb
Host smart-90a05a0f-6a53-4b6a-bca9-46511df7b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250884327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2250884327
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1240907356
Short name T342
Test name
Test status
Simulation time 111097821 ps
CPU time 2.34 seconds
Started May 12 01:01:28 PM PDT 24
Finished May 12 01:01:31 PM PDT 24
Peak memory 220728 kb
Host smart-e2dce012-9364-4b9d-9d07-ccd5ced96c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240907356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1240907356
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2432213595
Short name T900
Test name
Test status
Simulation time 986135422 ps
CPU time 3.19 seconds
Started May 12 01:01:31 PM PDT 24
Finished May 12 01:01:35 PM PDT 24
Peak memory 233292 kb
Host smart-18814777-b724-4787-9715-35d22b44e818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432213595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2432213595
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3865796259
Short name T367
Test name
Test status
Simulation time 826618041 ps
CPU time 4.84 seconds
Started May 12 01:01:31 PM PDT 24
Finished May 12 01:01:37 PM PDT 24
Peak memory 222304 kb
Host smart-ebad4aab-f38f-4ea1-bede-9606baf28641
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3865796259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3865796259
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2788866101
Short name T556
Test name
Test status
Simulation time 12745794043 ps
CPU time 23.21 seconds
Started May 12 01:01:31 PM PDT 24
Finished May 12 01:01:55 PM PDT 24
Peak memory 216128 kb
Host smart-6af8b205-a977-4666-b3a5-fe3aaf741ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788866101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2788866101
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3943521881
Short name T79
Test name
Test status
Simulation time 8339687587 ps
CPU time 6.52 seconds
Started May 12 01:01:29 PM PDT 24
Finished May 12 01:01:36 PM PDT 24
Peak memory 216088 kb
Host smart-2bb2246f-3dfb-44c5-94f1-df51e5fea7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943521881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3943521881
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1370783696
Short name T581
Test name
Test status
Simulation time 42445107 ps
CPU time 1.38 seconds
Started May 12 01:01:29 PM PDT 24
Finished May 12 01:01:30 PM PDT 24
Peak memory 207784 kb
Host smart-0d970218-5b39-42fa-ba98-2b7ffa5247a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370783696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1370783696
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2952349784
Short name T883
Test name
Test status
Simulation time 328145515 ps
CPU time 0.97 seconds
Started May 12 01:01:30 PM PDT 24
Finished May 12 01:01:31 PM PDT 24
Peak memory 205912 kb
Host smart-be205f14-739f-4a89-8ab9-1d82eb4fff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952349784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2952349784
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2364422413
Short name T275
Test name
Test status
Simulation time 15585264793 ps
CPU time 13.78 seconds
Started May 12 01:01:30 PM PDT 24
Finished May 12 01:01:44 PM PDT 24
Peak memory 227512 kb
Host smart-058315a0-040d-411f-b840-b35216960a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364422413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2364422413
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.666176995
Short name T526
Test name
Test status
Simulation time 21692058 ps
CPU time 0.74 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:02:14 PM PDT 24
Peak memory 205244 kb
Host smart-1c7c2086-3562-4cae-b20e-582b52632d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666176995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.666176995
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.146857588
Short name T436
Test name
Test status
Simulation time 238668141 ps
CPU time 4.12 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:14 PM PDT 24
Peak memory 218468 kb
Host smart-ad7e2221-f0ea-46b5-afb6-b1f061bbcac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146857588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.146857588
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2616594971
Short name T471
Test name
Test status
Simulation time 62130840 ps
CPU time 0.82 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:11 PM PDT 24
Peak memory 206624 kb
Host smart-8d03f2b5-8e14-4eaa-bc5e-d7ee82494deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616594971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2616594971
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.502009356
Short name T81
Test name
Test status
Simulation time 110454595 ps
CPU time 5.79 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:02:19 PM PDT 24
Peak memory 232428 kb
Host smart-64653746-eed8-46b4-8b05-9bdbb4ec71da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502009356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.502009356
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2451857671
Short name T4
Test name
Test status
Simulation time 583242022 ps
CPU time 7.57 seconds
Started May 12 01:02:10 PM PDT 24
Finished May 12 01:02:18 PM PDT 24
Peak memory 235068 kb
Host smart-3c687756-2fa3-4c98-8c20-99a3c98cbb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451857671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2451857671
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.662086532
Short name T562
Test name
Test status
Simulation time 131253616 ps
CPU time 2.57 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:14 PM PDT 24
Peak memory 221400 kb
Host smart-6063512c-0055-4116-8e96-e9efd2d2772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662086532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.662086532
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2786088817
Short name T803
Test name
Test status
Simulation time 115133507721 ps
CPU time 23.57 seconds
Started May 12 01:02:08 PM PDT 24
Finished May 12 01:02:32 PM PDT 24
Peak memory 235612 kb
Host smart-69878deb-ed2b-462d-8884-000d1ea21805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786088817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2786088817
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3603929961
Short name T841
Test name
Test status
Simulation time 5119959380 ps
CPU time 6.62 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:18 PM PDT 24
Peak memory 235460 kb
Host smart-74a5f815-e494-40f5-be79-f9fc2542f2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603929961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3603929961
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.976449087
Short name T334
Test name
Test status
Simulation time 1199708057 ps
CPU time 16.83 seconds
Started May 12 01:02:08 PM PDT 24
Finished May 12 01:02:25 PM PDT 24
Peak memory 219756 kb
Host smart-4ee4d111-4ab6-4442-b729-6a32c7f8ab39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=976449087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.976449087
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3349503808
Short name T797
Test name
Test status
Simulation time 15497478662 ps
CPU time 69.1 seconds
Started May 12 01:02:14 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 248948 kb
Host smart-6350dd5d-e6d1-4ddf-8e36-f26c9e382dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349503808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3349503808
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1040669639
Short name T847
Test name
Test status
Simulation time 266382785 ps
CPU time 4.55 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:02:18 PM PDT 24
Peak memory 216376 kb
Host smart-030e66cd-20f5-4c81-bfb0-52476f65c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040669639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1040669639
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1033983193
Short name T319
Test name
Test status
Simulation time 3158548405 ps
CPU time 12.91 seconds
Started May 12 01:02:07 PM PDT 24
Finished May 12 01:02:21 PM PDT 24
Peak memory 216124 kb
Host smart-5ee43d76-ba85-4f49-9305-4b0904adeea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033983193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1033983193
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3652552365
Short name T658
Test name
Test status
Simulation time 65746314 ps
CPU time 1.12 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:12 PM PDT 24
Peak memory 207704 kb
Host smart-89f573ea-65d9-4dd7-b015-19abc772ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652552365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3652552365
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2903762818
Short name T377
Test name
Test status
Simulation time 47239189 ps
CPU time 0.75 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:12 PM PDT 24
Peak memory 205560 kb
Host smart-388e65aa-2f3b-4cfa-933f-1c153f27ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903762818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2903762818
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3509581215
Short name T105
Test name
Test status
Simulation time 447178107 ps
CPU time 4.97 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:15 PM PDT 24
Peak memory 233764 kb
Host smart-270d9e17-31a1-4de6-9f24-ff997b9101db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509581215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3509581215
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2130402680
Short name T832
Test name
Test status
Simulation time 50502305 ps
CPU time 0.75 seconds
Started May 12 01:02:16 PM PDT 24
Finished May 12 01:02:18 PM PDT 24
Peak memory 204520 kb
Host smart-50af4f8e-0349-41c5-a900-41c6a2312b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130402680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2130402680
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1264804437
Short name T957
Test name
Test status
Simulation time 13590746 ps
CPU time 0.81 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:13 PM PDT 24
Peak memory 206328 kb
Host smart-58808522-1a2f-4a06-b478-c8edbf862669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264804437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1264804437
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4063951952
Short name T662
Test name
Test status
Simulation time 52201582237 ps
CPU time 93.99 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:03:48 PM PDT 24
Peak memory 240768 kb
Host smart-ccee9941-2e03-46c5-b5ad-293a3d36300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063951952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4063951952
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2793345143
Short name T349
Test name
Test status
Simulation time 645653643 ps
CPU time 9.88 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 224256 kb
Host smart-5efd0121-d6d1-4a03-802b-ea04159137b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793345143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2793345143
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1674780720
Short name T762
Test name
Test status
Simulation time 590282643 ps
CPU time 3.99 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:16 PM PDT 24
Peak memory 219600 kb
Host smart-bcf04427-5e99-49c6-890c-96da70540a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674780720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1674780720
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4073799854
Short name T591
Test name
Test status
Simulation time 893602473 ps
CPU time 10.57 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:23 PM PDT 24
Peak memory 237592 kb
Host smart-7234327b-4cc3-4211-b00b-e28ca02896cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073799854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4073799854
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1103176111
Short name T239
Test name
Test status
Simulation time 505468748 ps
CPU time 5.52 seconds
Started May 12 01:02:14 PM PDT 24
Finished May 12 01:02:20 PM PDT 24
Peak memory 233024 kb
Host smart-db0f03ed-bd24-4d17-865c-3834a9baa1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103176111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1103176111
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3034457437
Short name T401
Test name
Test status
Simulation time 29900500927 ps
CPU time 21.1 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 224276 kb
Host smart-c0974512-edc7-48dd-953d-a525262e9707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034457437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3034457437
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1868700945
Short name T371
Test name
Test status
Simulation time 1174571856 ps
CPU time 7.22 seconds
Started May 12 01:02:14 PM PDT 24
Finished May 12 01:02:22 PM PDT 24
Peak memory 221928 kb
Host smart-c190f9c2-8ce3-4fbf-b029-aae662c09121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1868700945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1868700945
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3010425710
Short name T432
Test name
Test status
Simulation time 7612727621 ps
CPU time 18.62 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:32 PM PDT 24
Peak memory 216216 kb
Host smart-820c2413-2221-47fd-8f31-f3ef6250f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010425710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3010425710
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2438668364
Short name T571
Test name
Test status
Simulation time 85552145 ps
CPU time 1.14 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:13 PM PDT 24
Peak memory 207792 kb
Host smart-be13e269-ed10-427b-9e1d-3f86d623616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438668364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2438668364
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3687127308
Short name T460
Test name
Test status
Simulation time 108907335 ps
CPU time 1.7 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:14 PM PDT 24
Peak memory 215992 kb
Host smart-12461d5e-259d-4ee0-97eb-fe17c57cea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687127308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3687127308
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3665169957
Short name T789
Test name
Test status
Simulation time 83164757 ps
CPU time 0.86 seconds
Started May 12 01:02:14 PM PDT 24
Finished May 12 01:02:16 PM PDT 24
Peak memory 206596 kb
Host smart-5458abab-dd8a-47a2-8390-ba3f12520070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665169957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3665169957
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1059486382
Short name T210
Test name
Test status
Simulation time 8805119062 ps
CPU time 7.93 seconds
Started May 12 01:02:12 PM PDT 24
Finished May 12 01:02:21 PM PDT 24
Peak memory 218504 kb
Host smart-1e512456-830c-4287-a23d-8295bed58593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059486382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1059486382
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1898443606
Short name T417
Test name
Test status
Simulation time 63722088 ps
CPU time 0.71 seconds
Started May 12 01:02:25 PM PDT 24
Finished May 12 01:02:26 PM PDT 24
Peak memory 205508 kb
Host smart-12a21fe7-5f3c-4364-aa4b-358664542f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898443606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1898443606
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1475703421
Short name T693
Test name
Test status
Simulation time 394079159 ps
CPU time 3.09 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:02:20 PM PDT 24
Peak memory 235552 kb
Host smart-553fc57f-46d4-4f08-98e8-92bdd8970389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475703421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1475703421
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3082107313
Short name T640
Test name
Test status
Simulation time 31059370 ps
CPU time 0.8 seconds
Started May 12 01:02:19 PM PDT 24
Finished May 12 01:02:20 PM PDT 24
Peak memory 206336 kb
Host smart-9ee8292e-a644-44fb-badd-53673c78dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082107313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3082107313
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3095934856
Short name T731
Test name
Test status
Simulation time 15490073244 ps
CPU time 169.62 seconds
Started May 12 01:02:21 PM PDT 24
Finished May 12 01:05:12 PM PDT 24
Peak memory 256720 kb
Host smart-e309508e-0a88-4a97-a585-780131924c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095934856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3095934856
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2042634343
Short name T939
Test name
Test status
Simulation time 52511985952 ps
CPU time 24.4 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:48 PM PDT 24
Peak memory 217308 kb
Host smart-cfaf533a-48b8-46dd-8a31-c9c8b1c99fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042634343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2042634343
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2068343171
Short name T403
Test name
Test status
Simulation time 215342719 ps
CPU time 3.49 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:27 PM PDT 24
Peak memory 224252 kb
Host smart-7526265d-6aa0-46ad-a77d-672dd846f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068343171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2068343171
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4053073944
Short name T268
Test name
Test status
Simulation time 940951157 ps
CPU time 5.26 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:02:23 PM PDT 24
Peak memory 224332 kb
Host smart-c18e11cf-a281-4e14-a877-ef3ffee71b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053073944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4053073944
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2214954389
Short name T122
Test name
Test status
Simulation time 91826368 ps
CPU time 2.52 seconds
Started May 12 01:02:18 PM PDT 24
Finished May 12 01:02:21 PM PDT 24
Peak memory 221296 kb
Host smart-2e0170f6-ec61-4507-840c-a18ad2a27974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214954389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2214954389
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2404114821
Short name T418
Test name
Test status
Simulation time 2545486464 ps
CPU time 5.11 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:02:22 PM PDT 24
Peak memory 233044 kb
Host smart-5755a9d2-694c-4f42-9132-5be06ee761da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404114821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2404114821
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4056095131
Short name T804
Test name
Test status
Simulation time 487443613 ps
CPU time 7.76 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:32 PM PDT 24
Peak memory 228088 kb
Host smart-aad67852-949e-4de3-98a6-4d0364f20db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056095131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4056095131
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3044823352
Short name T340
Test name
Test status
Simulation time 17836168362 ps
CPU time 13.39 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:02:31 PM PDT 24
Peak memory 218932 kb
Host smart-851ade21-46a2-4dbc-87cb-541b82a7a81e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3044823352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3044823352
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3250370817
Short name T131
Test name
Test status
Simulation time 12981975372 ps
CPU time 162.36 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:05:05 PM PDT 24
Peak memory 249016 kb
Host smart-da902659-3e2f-4c94-82e8-0355ad4c7a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250370817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3250370817
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1621632115
Short name T868
Test name
Test status
Simulation time 16473261266 ps
CPU time 17.08 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:02:35 PM PDT 24
Peak memory 216244 kb
Host smart-5dae30b3-96ec-419d-8bb8-115320688582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621632115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1621632115
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2806423955
Short name T157
Test name
Test status
Simulation time 12358977504 ps
CPU time 9.1 seconds
Started May 12 01:02:18 PM PDT 24
Finished May 12 01:02:28 PM PDT 24
Peak memory 216012 kb
Host smart-c0866e13-8b41-497e-b622-bda4aa360a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806423955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2806423955
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2572298983
Short name T593
Test name
Test status
Simulation time 38944972 ps
CPU time 0.83 seconds
Started May 12 01:02:19 PM PDT 24
Finished May 12 01:02:20 PM PDT 24
Peak memory 205592 kb
Host smart-0077df0b-837f-4631-9c2f-5a3552d11008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572298983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2572298983
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2710259253
Short name T691
Test name
Test status
Simulation time 275757759 ps
CPU time 0.95 seconds
Started May 12 01:02:18 PM PDT 24
Finished May 12 01:02:19 PM PDT 24
Peak memory 205860 kb
Host smart-2cf152db-a3b0-408a-b142-fc850daaa45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710259253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2710259253
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1418234769
Short name T501
Test name
Test status
Simulation time 8094160734 ps
CPU time 9.61 seconds
Started May 12 01:02:17 PM PDT 24
Finished May 12 01:02:27 PM PDT 24
Peak memory 228832 kb
Host smart-34c51286-cd9a-485a-9331-fe2c609d9a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418234769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1418234769
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1080168312
Short name T947
Test name
Test status
Simulation time 26299368 ps
CPU time 0.76 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 205452 kb
Host smart-4dc815a9-1199-4c12-a861-a959d8c20f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080168312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1080168312
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3366417444
Short name T756
Test name
Test status
Simulation time 418542973 ps
CPU time 7.23 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:02:31 PM PDT 24
Peak memory 219184 kb
Host smart-da8babfc-a401-42f0-a38e-06cb0fab1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366417444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3366417444
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3829082706
Short name T396
Test name
Test status
Simulation time 34285878 ps
CPU time 0.82 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 206632 kb
Host smart-dc5d4e8c-0455-44f6-9f7b-cd783c2c43ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829082706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3829082706
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1784167896
Short name T723
Test name
Test status
Simulation time 1950806068 ps
CPU time 23.69 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 233580 kb
Host smart-ae781ca0-a74c-4a95-86d7-3582dcff6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784167896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1784167896
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.897780548
Short name T425
Test name
Test status
Simulation time 271720239184 ps
CPU time 475.73 seconds
Started May 12 01:02:26 PM PDT 24
Finished May 12 01:10:22 PM PDT 24
Peak memory 265260 kb
Host smart-7b7670ae-4107-4d0a-91bf-3d4adfd5fed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897780548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.897780548
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2589787355
Short name T229
Test name
Test status
Simulation time 1067695324 ps
CPU time 28.24 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 239260 kb
Host smart-d03d2a5c-4240-48f6-be8e-a78c20766b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589787355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2589787355
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.171841015
Short name T301
Test name
Test status
Simulation time 646565124 ps
CPU time 10.12 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:02:33 PM PDT 24
Peak memory 248836 kb
Host smart-a4103a1c-6c4c-4051-82a8-c6c8479f8111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171841015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.171841015
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.941387378
Short name T279
Test name
Test status
Simulation time 2424521774 ps
CPU time 18.98 seconds
Started May 12 01:02:21 PM PDT 24
Finished May 12 01:02:41 PM PDT 24
Peak memory 219868 kb
Host smart-295f84f8-19bd-4651-ba2d-8a0284c07ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941387378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.941387378
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1321798693
Short name T185
Test name
Test status
Simulation time 72173172204 ps
CPU time 74.37 seconds
Started May 12 01:02:26 PM PDT 24
Finished May 12 01:03:40 PM PDT 24
Peak memory 249464 kb
Host smart-db03b43a-e008-41c3-948f-b516e50ebb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321798693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1321798693
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1873934731
Short name T189
Test name
Test status
Simulation time 6178418104 ps
CPU time 19.27 seconds
Started May 12 01:02:24 PM PDT 24
Finished May 12 01:02:44 PM PDT 24
Peak memory 218184 kb
Host smart-e35f8aff-a13a-40b5-a7f7-446f0d521ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873934731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1873934731
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1540453149
Short name T821
Test name
Test status
Simulation time 12495474939 ps
CPU time 8.18 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:02:36 PM PDT 24
Peak memory 220912 kb
Host smart-92707bad-a21c-4654-8215-540a0570104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540453149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1540453149
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3412166811
Short name T684
Test name
Test status
Simulation time 1920863336 ps
CPU time 6.72 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:31 PM PDT 24
Peak memory 218576 kb
Host smart-7a35229b-01ea-4f49-9427-1d0b1b658dbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3412166811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3412166811
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3855355225
Short name T147
Test name
Test status
Simulation time 8611759975 ps
CPU time 56.6 seconds
Started May 12 01:02:24 PM PDT 24
Finished May 12 01:03:21 PM PDT 24
Peak memory 254368 kb
Host smart-8be4df45-be3c-4d88-9ebd-d4e83397d73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855355225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3855355225
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.291954935
Short name T479
Test name
Test status
Simulation time 2416867440 ps
CPU time 24.49 seconds
Started May 12 01:02:21 PM PDT 24
Finished May 12 01:02:46 PM PDT 24
Peak memory 216028 kb
Host smart-d7660756-9b96-4da9-82c5-937f2e35ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291954935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.291954935
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2032000
Short name T472
Test name
Test status
Simulation time 6014144982 ps
CPU time 10.1 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 216008 kb
Host smart-562c8f53-4253-42db-9d18-131d5b120b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2032000
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2024766532
Short name T940
Test name
Test status
Simulation time 111097094 ps
CPU time 1.69 seconds
Started May 12 01:02:21 PM PDT 24
Finished May 12 01:02:23 PM PDT 24
Peak memory 216064 kb
Host smart-738ec60a-392f-4b94-b119-00b1c740c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024766532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2024766532
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3051410784
Short name T854
Test name
Test status
Simulation time 74819560 ps
CPU time 0.84 seconds
Started May 12 01:02:22 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 205668 kb
Host smart-b5a3b199-7c1c-4dc2-a82c-088ee85c3823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051410784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3051410784
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1847357069
Short name T266
Test name
Test status
Simulation time 124488061 ps
CPU time 3.05 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:27 PM PDT 24
Peak memory 233836 kb
Host smart-450c78e0-c0d3-48c9-807d-9ef449921111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847357069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1847357069
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3052422133
Short name T916
Test name
Test status
Simulation time 45897515 ps
CPU time 0.78 seconds
Started May 12 01:02:29 PM PDT 24
Finished May 12 01:02:30 PM PDT 24
Peak memory 204716 kb
Host smart-f8d529d2-fc35-4be1-b33d-e384116362b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052422133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3052422133
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1412384648
Short name T953
Test name
Test status
Simulation time 776489181 ps
CPU time 4.78 seconds
Started May 12 01:02:28 PM PDT 24
Finished May 12 01:02:33 PM PDT 24
Peak memory 219504 kb
Host smart-f7f47e74-1d01-4a37-99e7-008bf18b41b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412384648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1412384648
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2914816872
Short name T492
Test name
Test status
Simulation time 121556243 ps
CPU time 0.74 seconds
Started May 12 01:02:23 PM PDT 24
Finished May 12 01:02:25 PM PDT 24
Peak memory 206664 kb
Host smart-dc186f4b-a98d-4cbe-8a4e-cace00485200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914816872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2914816872
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.425736498
Short name T165
Test name
Test status
Simulation time 31287956121 ps
CPU time 226.83 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:06:18 PM PDT 24
Peak memory 248988 kb
Host smart-4b6e5c8b-34fd-4c81-92a9-0e45771e7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425736498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.425736498
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1102561663
Short name T664
Test name
Test status
Simulation time 13255484272 ps
CPU time 44.99 seconds
Started May 12 01:02:30 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 240808 kb
Host smart-eb4f1a2c-51c5-438a-bd8a-892ca7e7e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102561663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1102561663
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3347726255
Short name T39
Test name
Test status
Simulation time 3152437001 ps
CPU time 47.27 seconds
Started May 12 01:02:26 PM PDT 24
Finished May 12 01:03:14 PM PDT 24
Peak memory 248964 kb
Host smart-c59277aa-6c97-42f3-a96b-4581184c4499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347726255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3347726255
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3191276652
Short name T355
Test name
Test status
Simulation time 374327873 ps
CPU time 3.64 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:02:35 PM PDT 24
Peak memory 232568 kb
Host smart-6bc5219f-0b15-42d3-a397-eb5c42a2b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191276652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3191276652
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1252259227
Short name T168
Test name
Test status
Simulation time 2263771357 ps
CPU time 17.17 seconds
Started May 12 01:02:28 PM PDT 24
Finished May 12 01:02:46 PM PDT 24
Peak memory 219280 kb
Host smart-32c12b08-649d-4f2b-b40d-0aef137ee77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252259227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1252259227
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1449672906
Short name T213
Test name
Test status
Simulation time 3249980329 ps
CPU time 32.61 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 233800 kb
Host smart-e3f085ee-044c-4b99-9513-0ddee8b1bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449672906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1449672906
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3738734030
Short name T583
Test name
Test status
Simulation time 129180701 ps
CPU time 2.64 seconds
Started May 12 01:02:28 PM PDT 24
Finished May 12 01:02:31 PM PDT 24
Peak memory 221200 kb
Host smart-a5bb4733-37ca-4204-b16b-0ea7f4773f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738734030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3738734030
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4080632339
Short name T378
Test name
Test status
Simulation time 21564449704 ps
CPU time 20.54 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:02:49 PM PDT 24
Peak memory 249160 kb
Host smart-587fb8a0-5ba2-45d2-8b7a-11488756de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080632339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4080632339
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1702730040
Short name T13
Test name
Test status
Simulation time 2244184769 ps
CPU time 5.72 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:02:37 PM PDT 24
Peak memory 218896 kb
Host smart-3b850ce7-3a85-415d-b87c-0477dba43a4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1702730040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1702730040
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1949055870
Short name T249
Test name
Test status
Simulation time 15532151292 ps
CPU time 151.89 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:05:00 PM PDT 24
Peak memory 236432 kb
Host smart-e72d75b2-b1e5-464d-8416-82f9c45ab7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949055870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1949055870
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1946512497
Short name T17
Test name
Test status
Simulation time 3326980996 ps
CPU time 21.64 seconds
Started May 12 01:02:30 PM PDT 24
Finished May 12 01:02:52 PM PDT 24
Peak memory 216136 kb
Host smart-af06be44-97c6-41a8-9613-e0afef219318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946512497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1946512497
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3937036321
Short name T366
Test name
Test status
Simulation time 3988974476 ps
CPU time 4.61 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:02:33 PM PDT 24
Peak memory 216020 kb
Host smart-7b674f5d-6010-4f1e-890e-51b7015599c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937036321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3937036321
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.621311339
Short name T569
Test name
Test status
Simulation time 119082752 ps
CPU time 0.76 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:02:28 PM PDT 24
Peak memory 205756 kb
Host smart-27bf4307-a3e7-4579-bc31-f48ecdfc52ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621311339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.621311339
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2897997673
Short name T387
Test name
Test status
Simulation time 51149167 ps
CPU time 0.89 seconds
Started May 12 01:02:29 PM PDT 24
Finished May 12 01:02:30 PM PDT 24
Peak memory 205692 kb
Host smart-d9e13167-4d87-46f5-817f-c6e585ca3a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897997673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2897997673
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1551358345
Short name T924
Test name
Test status
Simulation time 1803669784 ps
CPU time 9.6 seconds
Started May 12 01:02:27 PM PDT 24
Finished May 12 01:02:37 PM PDT 24
Peak memory 234784 kb
Host smart-a991e9f9-f4b0-4302-9878-eddd19b75ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551358345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1551358345
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1568225645
Short name T59
Test name
Test status
Simulation time 13635051 ps
CPU time 0.72 seconds
Started May 12 01:02:34 PM PDT 24
Finished May 12 01:02:35 PM PDT 24
Peak memory 204736 kb
Host smart-eb9fd5f0-ec24-43e1-8f5b-54a51590b2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568225645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1568225645
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.237756839
Short name T606
Test name
Test status
Simulation time 657220518 ps
CPU time 3.37 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:36 PM PDT 24
Peak memory 219576 kb
Host smart-9e21fc19-f26c-4e08-9d29-56e6163b7da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237756839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.237756839
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1448257923
Short name T855
Test name
Test status
Simulation time 19385082 ps
CPU time 0.82 seconds
Started May 12 01:02:30 PM PDT 24
Finished May 12 01:02:31 PM PDT 24
Peak memory 206308 kb
Host smart-4fabe6f9-0b6d-47f3-8dc3-e624298b83b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448257923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1448257923
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.344508206
Short name T155
Test name
Test status
Simulation time 1100005518 ps
CPU time 10.97 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:02:42 PM PDT 24
Peak memory 234560 kb
Host smart-d4c20e9a-996d-436e-9e4e-49626a18c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344508206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.344508206
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.446508259
Short name T218
Test name
Test status
Simulation time 126180965694 ps
CPU time 232.93 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:06:25 PM PDT 24
Peak memory 252096 kb
Host smart-db5e334a-7c4f-41e6-8c79-8b7c048167de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446508259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.446508259
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2140490205
Short name T127
Test name
Test status
Simulation time 1572886710 ps
CPU time 39.4 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:03:12 PM PDT 24
Peak memory 240128 kb
Host smart-31c5e0c2-16f1-4176-a3bf-7509e6970f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140490205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2140490205
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1878053089
Short name T194
Test name
Test status
Simulation time 554749172 ps
CPU time 4.07 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:36 PM PDT 24
Peak memory 233380 kb
Host smart-515362f6-e45e-49d9-a352-b39b614348e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878053089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1878053089
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2198489831
Short name T162
Test name
Test status
Simulation time 19332476532 ps
CPU time 17.96 seconds
Started May 12 01:02:36 PM PDT 24
Finished May 12 01:02:54 PM PDT 24
Peak memory 240532 kb
Host smart-a0d54a57-c7d8-4727-bf7a-b80a9c4c6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198489831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2198489831
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2756625476
Short name T85
Test name
Test status
Simulation time 117917444 ps
CPU time 2.23 seconds
Started May 12 01:02:31 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 218140 kb
Host smart-9ef0d9f4-b7f7-4ac5-8857-252dc538da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756625476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2756625476
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3840701382
Short name T509
Test name
Test status
Simulation time 1208176803 ps
CPU time 4.51 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:37 PM PDT 24
Peak memory 218476 kb
Host smart-fafb627c-81e1-4b55-9f19-f53602d2e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840701382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3840701382
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3658121753
Short name T467
Test name
Test status
Simulation time 1360433814 ps
CPU time 10.79 seconds
Started May 12 01:02:33 PM PDT 24
Finished May 12 01:02:44 PM PDT 24
Peak memory 220152 kb
Host smart-8804020a-ad9c-4e8e-afe2-2a5efcfb669e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658121753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3658121753
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.565725171
Short name T149
Test name
Test status
Simulation time 11965385268 ps
CPU time 43.98 seconds
Started May 12 01:02:34 PM PDT 24
Finished May 12 01:03:18 PM PDT 24
Peak memory 248964 kb
Host smart-09cacc7d-ae74-4ab5-a13d-05c8711e47ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565725171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.565725171
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.659895742
Short name T660
Test name
Test status
Simulation time 4223823838 ps
CPU time 26.31 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:59 PM PDT 24
Peak memory 219344 kb
Host smart-a4019ac2-1471-44ad-8907-34b3fd21284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659895742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.659895742
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3453991039
Short name T321
Test name
Test status
Simulation time 40564130 ps
CPU time 0.73 seconds
Started May 12 01:02:34 PM PDT 24
Finished May 12 01:02:35 PM PDT 24
Peak memory 205376 kb
Host smart-dc9db486-9a84-455c-ad5e-a1598e0df2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453991039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3453991039
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1456347617
Short name T47
Test name
Test status
Simulation time 41424113 ps
CPU time 0.73 seconds
Started May 12 01:02:34 PM PDT 24
Finished May 12 01:02:35 PM PDT 24
Peak memory 205404 kb
Host smart-02cc0fd9-3d45-46ed-afda-a090d42b86bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456347617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1456347617
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3500715511
Short name T634
Test name
Test status
Simulation time 32005010 ps
CPU time 0.75 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 205336 kb
Host smart-7f512886-9712-4786-a34e-26d3a4dd07a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500715511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3500715511
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.800195728
Short name T771
Test name
Test status
Simulation time 500195987 ps
CPU time 5.93 seconds
Started May 12 01:02:33 PM PDT 24
Finished May 12 01:02:40 PM PDT 24
Peak memory 224168 kb
Host smart-c1edf388-9576-467e-b535-89ca12e6cc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800195728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.800195728
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3081734283
Short name T448
Test name
Test status
Simulation time 39647247 ps
CPU time 0.72 seconds
Started May 12 01:02:38 PM PDT 24
Finished May 12 01:02:39 PM PDT 24
Peak memory 204608 kb
Host smart-fdcb5bbc-0c5f-42c7-b87a-972aceb45ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081734283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3081734283
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3350724243
Short name T30
Test name
Test status
Simulation time 30498877 ps
CPU time 2.1 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:46 PM PDT 24
Peak memory 215976 kb
Host smart-80a38320-9c24-4103-b503-e340c94d6b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350724243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3350724243
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2114649936
Short name T405
Test name
Test status
Simulation time 19641633 ps
CPU time 0.83 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 206352 kb
Host smart-caf8cd61-eaf9-454d-93f0-4a1c94fa665e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114649936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2114649936
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4223548049
Short name T410
Test name
Test status
Simulation time 19750205811 ps
CPU time 128.36 seconds
Started May 12 01:02:37 PM PDT 24
Finished May 12 01:04:46 PM PDT 24
Peak memory 250832 kb
Host smart-5d131475-466d-44fd-9ab6-cc07be269cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223548049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4223548049
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3682133428
Short name T197
Test name
Test status
Simulation time 31208957107 ps
CPU time 351.87 seconds
Started May 12 01:02:37 PM PDT 24
Finished May 12 01:08:29 PM PDT 24
Peak memory 265388 kb
Host smart-9ec43a20-84b4-4bdb-a6d7-2bb983208775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682133428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3682133428
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2055110229
Short name T840
Test name
Test status
Simulation time 41984975677 ps
CPU time 105.32 seconds
Started May 12 01:02:40 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 250884 kb
Host smart-c188b826-39d9-498a-bc5c-28178a6bf26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055110229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2055110229
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3567750737
Short name T669
Test name
Test status
Simulation time 2191608136 ps
CPU time 29.54 seconds
Started May 12 01:02:38 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 224256 kb
Host smart-62843dd8-79ef-414f-a6c2-31d691f2ef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567750737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3567750737
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.687307052
Short name T671
Test name
Test status
Simulation time 1402668295 ps
CPU time 12.44 seconds
Started May 12 01:02:35 PM PDT 24
Finished May 12 01:02:48 PM PDT 24
Peak memory 235848 kb
Host smart-7fdf0a65-463e-41eb-a963-bf2cf94f7282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687307052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.687307052
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.329193546
Short name T477
Test name
Test status
Simulation time 30807527711 ps
CPU time 66.92 seconds
Started May 12 01:02:38 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 233476 kb
Host smart-c9918b44-043a-4c16-b201-b4dab4ee4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329193546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.329193546
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2428189839
Short name T831
Test name
Test status
Simulation time 765572014 ps
CPU time 2.76 seconds
Started May 12 01:02:32 PM PDT 24
Finished May 12 01:02:35 PM PDT 24
Peak memory 216440 kb
Host smart-62c018f5-025a-4b8f-ad59-113884337997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428189839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2428189839
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3804692295
Short name T611
Test name
Test status
Simulation time 8319991399 ps
CPU time 8.98 seconds
Started May 12 01:02:33 PM PDT 24
Finished May 12 01:02:43 PM PDT 24
Peak memory 218684 kb
Host smart-a2e4957b-baa7-4e7f-90a7-51dcd0bafafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804692295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3804692295
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2000121008
Short name T763
Test name
Test status
Simulation time 1236631662 ps
CPU time 5.88 seconds
Started May 12 01:02:37 PM PDT 24
Finished May 12 01:02:44 PM PDT 24
Peak memory 222656 kb
Host smart-e2cf6873-443f-4a6b-8c58-6b34e8dcc4ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2000121008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2000121008
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2229821979
Short name T277
Test name
Test status
Simulation time 15216510799 ps
CPU time 78.47 seconds
Started May 12 01:02:40 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 248932 kb
Host smart-3df9b1f0-148d-4be1-843b-82960a103214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229821979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2229821979
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3990904550
Short name T833
Test name
Test status
Simulation time 3229464055 ps
CPU time 13.77 seconds
Started May 12 01:02:33 PM PDT 24
Finished May 12 01:02:47 PM PDT 24
Peak memory 219748 kb
Host smart-42e569fe-b839-48e1-91b0-4d8bc8bf84d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990904550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3990904550
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2763166982
Short name T336
Test name
Test status
Simulation time 2566790089 ps
CPU time 6.67 seconds
Started May 12 01:02:33 PM PDT 24
Finished May 12 01:02:41 PM PDT 24
Peak memory 216140 kb
Host smart-75ff5365-f5b7-48bb-aba2-a2cbabddae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763166982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2763166982
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3460531210
Short name T580
Test name
Test status
Simulation time 78291618 ps
CPU time 1 seconds
Started May 12 01:02:35 PM PDT 24
Finished May 12 01:02:37 PM PDT 24
Peak memory 206680 kb
Host smart-c42df39c-8f95-40fc-a117-b672c77a0da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460531210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3460531210
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4231581931
Short name T549
Test name
Test status
Simulation time 390736347 ps
CPU time 0.97 seconds
Started May 12 01:02:33 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 206624 kb
Host smart-3b88ab90-d405-4809-b7ac-b70fd45d5132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231581931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4231581931
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1411912077
Short name T510
Test name
Test status
Simulation time 320671790 ps
CPU time 4.35 seconds
Started May 12 01:02:37 PM PDT 24
Finished May 12 01:02:42 PM PDT 24
Peak memory 235960 kb
Host smart-fddf6992-3649-42ae-b27d-2fcd0b25c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411912077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1411912077
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1496672685
Short name T807
Test name
Test status
Simulation time 36282449 ps
CPU time 0.71 seconds
Started May 12 01:02:43 PM PDT 24
Finished May 12 01:02:44 PM PDT 24
Peak memory 204528 kb
Host smart-beb0f0f6-058d-4db5-99ad-615423e12a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496672685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1496672685
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.989453835
Short name T170
Test name
Test status
Simulation time 252512431 ps
CPU time 3 seconds
Started May 12 01:02:37 PM PDT 24
Finished May 12 01:02:40 PM PDT 24
Peak memory 218288 kb
Host smart-d74e1e54-36c2-4ab1-aa2d-bdea86a5ea11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989453835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.989453835
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2589859508
Short name T622
Test name
Test status
Simulation time 37777802 ps
CPU time 0.78 seconds
Started May 12 01:02:39 PM PDT 24
Finished May 12 01:02:40 PM PDT 24
Peak memory 205404 kb
Host smart-56bc576f-d642-4671-b78b-6363853cf50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589859508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2589859508
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2000225194
Short name T235
Test name
Test status
Simulation time 35531156773 ps
CPU time 183.58 seconds
Started May 12 01:02:40 PM PDT 24
Finished May 12 01:05:44 PM PDT 24
Peak memory 240748 kb
Host smart-9379bef8-30a6-44ed-a9b8-33ba8d71bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000225194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2000225194
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.597176422
Short name T443
Test name
Test status
Simulation time 9171219497 ps
CPU time 65.38 seconds
Started May 12 01:02:42 PM PDT 24
Finished May 12 01:03:48 PM PDT 24
Peak memory 236944 kb
Host smart-ffac89b1-884d-49a7-8f72-50cc8caed0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597176422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.597176422
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2420384411
Short name T243
Test name
Test status
Simulation time 72469377276 ps
CPU time 589.3 seconds
Started May 12 01:02:43 PM PDT 24
Finished May 12 01:12:33 PM PDT 24
Peak memory 256416 kb
Host smart-de226513-7840-4a23-9edb-379e439f847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420384411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2420384411
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.127801302
Short name T537
Test name
Test status
Simulation time 8560095052 ps
CPU time 22.86 seconds
Started May 12 01:02:41 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 238308 kb
Host smart-498ba99b-c3f2-4d80-b3bb-4f54f3788768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127801302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.127801302
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1243493113
Short name T188
Test name
Test status
Simulation time 4154866245 ps
CPU time 17.97 seconds
Started May 12 01:02:37 PM PDT 24
Finished May 12 01:02:56 PM PDT 24
Peak memory 232436 kb
Host smart-5b2cd68d-5327-422d-a84a-b3348f254ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243493113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1243493113
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1727174080
Short name T920
Test name
Test status
Simulation time 2976867989 ps
CPU time 14.09 seconds
Started May 12 01:02:40 PM PDT 24
Finished May 12 01:02:55 PM PDT 24
Peak memory 237644 kb
Host smart-db2daeb6-8e09-4219-843a-8e3803168a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727174080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1727174080
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2848472235
Short name T753
Test name
Test status
Simulation time 249380521 ps
CPU time 4.18 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:49 PM PDT 24
Peak memory 218728 kb
Host smart-cc4613b5-4787-464a-a118-21201e0284cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848472235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2848472235
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2903976908
Short name T414
Test name
Test status
Simulation time 8070865292 ps
CPU time 23.84 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:03:09 PM PDT 24
Peak memory 236356 kb
Host smart-b697e367-1d05-4a6f-b730-d172f22e5fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903976908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2903976908
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3366684920
Short name T470
Test name
Test status
Simulation time 2145890246 ps
CPU time 6.66 seconds
Started May 12 01:02:39 PM PDT 24
Finished May 12 01:02:46 PM PDT 24
Peak memory 218588 kb
Host smart-f341d972-98dc-496a-9b34-e75400438a61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366684920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3366684920
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1564839691
Short name T227
Test name
Test status
Simulation time 372461709124 ps
CPU time 966.6 seconds
Started May 12 01:02:42 PM PDT 24
Finished May 12 01:18:50 PM PDT 24
Peak memory 289428 kb
Host smart-4e681ec8-d018-4f86-a01d-a25bf2066f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564839691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1564839691
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3381754310
Short name T328
Test name
Test status
Simulation time 2032890143 ps
CPU time 3.88 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:48 PM PDT 24
Peak memory 216072 kb
Host smart-d09622a5-090a-4d0c-b083-bb0b832b372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381754310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3381754310
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.900150230
Short name T772
Test name
Test status
Simulation time 127194766 ps
CPU time 6.47 seconds
Started May 12 01:02:39 PM PDT 24
Finished May 12 01:02:46 PM PDT 24
Peak memory 216016 kb
Host smart-1d27cbea-0e20-4a02-8660-5167a7c82564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900150230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.900150230
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4091263566
Short name T400
Test name
Test status
Simulation time 459441443 ps
CPU time 1.01 seconds
Started May 12 01:02:36 PM PDT 24
Finished May 12 01:02:38 PM PDT 24
Peak memory 206568 kb
Host smart-77bc519a-cebc-49ea-8add-bb862168b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091263566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4091263566
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3751694967
Short name T923
Test name
Test status
Simulation time 221737882 ps
CPU time 2.78 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:48 PM PDT 24
Peak memory 232540 kb
Host smart-5a775eae-6e23-4d2d-a8cc-0fc5432ed278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751694967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3751694967
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1608459819
Short name T58
Test name
Test status
Simulation time 97495333 ps
CPU time 0.76 seconds
Started May 12 01:02:53 PM PDT 24
Finished May 12 01:02:54 PM PDT 24
Peak memory 204636 kb
Host smart-f86b18d8-faa5-485a-8740-6c4af4dbd944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608459819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1608459819
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3586300680
Short name T927
Test name
Test status
Simulation time 2136661385 ps
CPU time 7.54 seconds
Started May 12 01:02:43 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 234316 kb
Host smart-1bbf36b7-939a-4bc5-9b99-80d0acc98e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586300680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3586300680
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3064016072
Short name T411
Test name
Test status
Simulation time 53883383 ps
CPU time 0.81 seconds
Started May 12 01:02:42 PM PDT 24
Finished May 12 01:02:44 PM PDT 24
Peak memory 206472 kb
Host smart-29719556-c5a4-4987-9232-383f32a1d6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064016072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3064016072
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.629535197
Short name T544
Test name
Test status
Simulation time 85288218092 ps
CPU time 150.07 seconds
Started May 12 01:02:43 PM PDT 24
Finished May 12 01:05:14 PM PDT 24
Peak memory 249012 kb
Host smart-4f2d1201-d5d0-409c-97be-3475a0066156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629535197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.629535197
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1002543944
Short name T282
Test name
Test status
Simulation time 33300138165 ps
CPU time 339.9 seconds
Started May 12 01:02:53 PM PDT 24
Finished May 12 01:08:33 PM PDT 24
Peak memory 256548 kb
Host smart-f58df51a-8615-4c7b-83db-66c5893a0cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002543944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1002543944
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3887694313
Short name T730
Test name
Test status
Simulation time 9996347460 ps
CPU time 78.86 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 252580 kb
Host smart-e181e4bc-cd2c-4c7c-898e-f91abdc37b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887694313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3887694313
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1164533482
Short name T632
Test name
Test status
Simulation time 8122112654 ps
CPU time 13.86 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:59 PM PDT 24
Peak memory 235404 kb
Host smart-d8bac194-10e5-4d26-8510-533667f1bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164533482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1164533482
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3012603033
Short name T184
Test name
Test status
Simulation time 77863823611 ps
CPU time 58.8 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 236180 kb
Host smart-af7ec9c1-883b-465e-a94b-ad252b4ba1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012603033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3012603033
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2390173671
Short name T219
Test name
Test status
Simulation time 1995152435 ps
CPU time 6.29 seconds
Started May 12 01:02:45 PM PDT 24
Finished May 12 01:02:52 PM PDT 24
Peak memory 236692 kb
Host smart-b6e63488-9237-43cc-919c-20619bb80eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390173671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2390173671
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1472612518
Short name T898
Test name
Test status
Simulation time 458156173 ps
CPU time 6.58 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 249232 kb
Host smart-103b8790-a06d-4a8f-b227-7251f127146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472612518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1472612518
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3784052366
Short name T139
Test name
Test status
Simulation time 1274885855 ps
CPU time 7.65 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:52 PM PDT 24
Peak memory 222256 kb
Host smart-098eff70-e880-4a08-98f8-d5e38dc32368
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3784052366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3784052366
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2417811312
Short name T230
Test name
Test status
Simulation time 22610444744 ps
CPU time 143.3 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:05:12 PM PDT 24
Peak memory 254648 kb
Host smart-7116e68e-18f0-40ef-9bd4-2b8cce435e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417811312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2417811312
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1235309477
Short name T732
Test name
Test status
Simulation time 1146790196 ps
CPU time 6.77 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 216264 kb
Host smart-0d6e060c-f0cb-47f5-b7b9-ce6e597f65aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235309477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1235309477
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.720331507
Short name T737
Test name
Test status
Simulation time 15035606331 ps
CPU time 21.05 seconds
Started May 12 01:02:42 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 216092 kb
Host smart-5e1c710d-2349-4e9c-a1b7-52238f5243fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720331507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.720331507
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1579044970
Short name T416
Test name
Test status
Simulation time 67141024 ps
CPU time 0.86 seconds
Started May 12 01:02:42 PM PDT 24
Finished May 12 01:02:43 PM PDT 24
Peak memory 205680 kb
Host smart-4190d46a-8484-4781-b7da-7b7318901017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579044970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1579044970
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2878135968
Short name T651
Test name
Test status
Simulation time 145817678 ps
CPU time 0.88 seconds
Started May 12 01:02:42 PM PDT 24
Finished May 12 01:02:43 PM PDT 24
Peak memory 205560 kb
Host smart-ed78b540-d0ee-4555-a3b4-9c47da53c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878135968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2878135968
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2668943585
Short name T293
Test name
Test status
Simulation time 1352009407 ps
CPU time 5.66 seconds
Started May 12 01:02:44 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 233272 kb
Host smart-a7ecbc9d-26da-4701-be98-5efbbe755914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668943585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2668943585
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1719462715
Short name T774
Test name
Test status
Simulation time 18106934 ps
CPU time 0.74 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:02:50 PM PDT 24
Peak memory 204692 kb
Host smart-40fe9ef8-eccc-4d93-95de-15319ae4ee49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719462715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1719462715
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.888626097
Short name T181
Test name
Test status
Simulation time 176296631 ps
CPU time 4.47 seconds
Started May 12 01:02:49 PM PDT 24
Finished May 12 01:02:54 PM PDT 24
Peak memory 234484 kb
Host smart-7c632e77-c460-4fa3-90bf-558a346c4c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888626097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.888626097
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.424605557
Short name T929
Test name
Test status
Simulation time 15498608 ps
CPU time 0.75 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:02:50 PM PDT 24
Peak memory 205612 kb
Host smart-f8f949f4-a8df-4507-a1b2-0d43f12b41be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424605557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.424605557
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1698357089
Short name T232
Test name
Test status
Simulation time 6038860530 ps
CPU time 46.32 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 240668 kb
Host smart-806e1696-2357-4d1d-8c36-f928122c6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698357089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1698357089
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3790292545
Short name T447
Test name
Test status
Simulation time 6094116488 ps
CPU time 81.73 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:04:11 PM PDT 24
Peak memory 252364 kb
Host smart-ab487a48-bc9f-4ec3-9e7b-c9d78c9ce0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790292545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3790292545
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1523472683
Short name T704
Test name
Test status
Simulation time 108183402022 ps
CPU time 262.28 seconds
Started May 12 01:02:49 PM PDT 24
Finished May 12 01:07:12 PM PDT 24
Peak memory 254996 kb
Host smart-360ba358-9c12-4c08-bfa0-1769510b64e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523472683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1523472683
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3930235874
Short name T274
Test name
Test status
Simulation time 4082151928 ps
CPU time 66.48 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:03:57 PM PDT 24
Peak memory 249000 kb
Host smart-3a451613-2e9e-4aa9-a7c2-d2beb4c437f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930235874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3930235874
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2813251359
Short name T532
Test name
Test status
Simulation time 3020290969 ps
CPU time 6.43 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:02:55 PM PDT 24
Peak memory 224292 kb
Host smart-51990635-b3d2-45bb-a77c-505e9e7af474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813251359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2813251359
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1846770960
Short name T781
Test name
Test status
Simulation time 13453660048 ps
CPU time 23.23 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:03:11 PM PDT 24
Peak memory 226848 kb
Host smart-bfff7a50-f7d8-4eb5-8225-7fb1f6ac29c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846770960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1846770960
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3690734214
Short name T766
Test name
Test status
Simulation time 7719794841 ps
CPU time 15.37 seconds
Started May 12 01:02:48 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 233112 kb
Host smart-55596904-1c91-46c7-9a43-e5efe6ef08fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690734214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3690734214
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3784997355
Short name T668
Test name
Test status
Simulation time 5559838362 ps
CPU time 10.17 seconds
Started May 12 01:02:49 PM PDT 24
Finished May 12 01:03:00 PM PDT 24
Peak memory 240028 kb
Host smart-cb4c34cb-ebc9-4e48-8394-352f93a6c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784997355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3784997355
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.971116249
Short name T503
Test name
Test status
Simulation time 119816983 ps
CPU time 4.46 seconds
Started May 12 01:02:49 PM PDT 24
Finished May 12 01:02:54 PM PDT 24
Peak memory 222676 kb
Host smart-ba2638f0-aa21-4b02-abf8-e03c95cc0621
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=971116249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.971116249
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1154743005
Short name T893
Test name
Test status
Simulation time 48308036704 ps
CPU time 34.13 seconds
Started May 12 01:02:49 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 216116 kb
Host smart-39f99611-b2ae-4d66-b15c-47ca091e58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154743005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1154743005
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.329992881
Short name T434
Test name
Test status
Simulation time 1269390690 ps
CPU time 4 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:02:54 PM PDT 24
Peak memory 215868 kb
Host smart-cb8bf078-63fe-4664-8c01-4a806d385ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329992881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.329992881
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1323921961
Short name T329
Test name
Test status
Simulation time 29058290 ps
CPU time 0.86 seconds
Started May 12 01:02:49 PM PDT 24
Finished May 12 01:02:50 PM PDT 24
Peak memory 206284 kb
Host smart-bc31a7e8-6f86-400d-9c5a-9355a71b3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323921961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1323921961
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4286957119
Short name T867
Test name
Test status
Simulation time 123346495 ps
CPU time 0.86 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 206564 kb
Host smart-46343428-7e7f-4b0d-a56c-51a6353b6f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286957119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4286957119
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3398518371
Short name T478
Test name
Test status
Simulation time 4008551567 ps
CPU time 9.44 seconds
Started May 12 01:02:50 PM PDT 24
Finished May 12 01:03:00 PM PDT 24
Peak memory 217080 kb
Host smart-a9c77fe2-fbd4-4ddd-a005-4878c484cb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398518371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3398518371
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3919785158
Short name T390
Test name
Test status
Simulation time 14517357 ps
CPU time 0.78 seconds
Started May 12 01:01:34 PM PDT 24
Finished May 12 01:01:35 PM PDT 24
Peak memory 204680 kb
Host smart-24eed2f1-cb00-4709-9a95-1a5ab1a8158d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919785158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
919785158
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2510669664
Short name T499
Test name
Test status
Simulation time 246153023 ps
CPU time 5.01 seconds
Started May 12 01:01:33 PM PDT 24
Finished May 12 01:01:39 PM PDT 24
Peak memory 234468 kb
Host smart-4bf337f5-e880-41db-b7df-5f7f7b6f3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510669664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2510669664
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4170384821
Short name T813
Test name
Test status
Simulation time 19972617 ps
CPU time 0.81 seconds
Started May 12 01:01:32 PM PDT 24
Finished May 12 01:01:34 PM PDT 24
Peak memory 206644 kb
Host smart-c458ea70-217b-480c-8a5b-f45b40c00a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170384821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4170384821
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.245781205
Short name T673
Test name
Test status
Simulation time 23732202375 ps
CPU time 169.14 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 248092 kb
Host smart-c498ac5c-bd78-480f-b004-2c943643ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245781205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.245781205
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.959448829
Short name T220
Test name
Test status
Simulation time 73952594025 ps
CPU time 568.53 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:11:05 PM PDT 24
Peak memory 266192 kb
Host smart-4509331c-926d-471f-aa7d-6c5c7aa27e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959448829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.959448829
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1830535708
Short name T22
Test name
Test status
Simulation time 2010499061 ps
CPU time 46.08 seconds
Started May 12 01:01:33 PM PDT 24
Finished May 12 01:02:19 PM PDT 24
Peak memory 240676 kb
Host smart-38017a59-31b2-4f24-9e44-3f363182588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830535708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1830535708
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3495124973
Short name T674
Test name
Test status
Simulation time 340131323 ps
CPU time 3.38 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:01:40 PM PDT 24
Peak memory 216504 kb
Host smart-4bd21528-6b29-4388-bbc5-7f2765dbdc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495124973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3495124973
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3265798359
Short name T614
Test name
Test status
Simulation time 1233219951 ps
CPU time 19.68 seconds
Started May 12 01:01:34 PM PDT 24
Finished May 12 01:01:54 PM PDT 24
Peak memory 232328 kb
Host smart-2f8ea097-eb4e-49ad-8500-ed020b191730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265798359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3265798359
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.847930454
Short name T720
Test name
Test status
Simulation time 28360155 ps
CPU time 2.01 seconds
Started May 12 01:01:32 PM PDT 24
Finished May 12 01:01:35 PM PDT 24
Peak memory 215852 kb
Host smart-53d9daa0-aed5-4e3b-a3d2-1c82d259bf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847930454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
847930454
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.769380665
Short name T761
Test name
Test status
Simulation time 1414834901 ps
CPU time 6.7 seconds
Started May 12 01:01:32 PM PDT 24
Finished May 12 01:01:40 PM PDT 24
Peak memory 219552 kb
Host smart-bb6abaf7-feb7-41a9-a8d1-1a136133554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769380665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.769380665
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2859186901
Short name T381
Test name
Test status
Simulation time 1865109874 ps
CPU time 10.29 seconds
Started May 12 01:01:32 PM PDT 24
Finished May 12 01:01:43 PM PDT 24
Peak memory 221580 kb
Host smart-45a74443-3ef3-49da-8bc3-891faeae850f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859186901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2859186901
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1398076410
Short name T68
Test name
Test status
Simulation time 614769588 ps
CPU time 1.24 seconds
Started May 12 01:01:33 PM PDT 24
Finished May 12 01:01:34 PM PDT 24
Peak memory 236176 kb
Host smart-57cb63bd-9f7a-4a19-bd50-aed35ea43b12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398076410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1398076410
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4172029490
Short name T124
Test name
Test status
Simulation time 3923404625 ps
CPU time 23.95 seconds
Started May 12 01:01:35 PM PDT 24
Finished May 12 01:01:59 PM PDT 24
Peak memory 240696 kb
Host smart-dcc70549-5193-41bd-bfe0-765ef076c755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172029490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4172029490
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3061737556
Short name T309
Test name
Test status
Simulation time 15317125330 ps
CPU time 15.37 seconds
Started May 12 01:01:35 PM PDT 24
Finished May 12 01:01:50 PM PDT 24
Peak memory 216116 kb
Host smart-2a1c1441-fe9f-4f69-a494-0a236e4ea9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061737556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3061737556
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2787854931
Short name T507
Test name
Test status
Simulation time 2317339036 ps
CPU time 7.88 seconds
Started May 12 01:01:32 PM PDT 24
Finished May 12 01:01:40 PM PDT 24
Peak memory 216084 kb
Host smart-feedae08-b82f-4ef7-88d7-b10ce675f5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787854931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2787854931
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1456563185
Short name T429
Test name
Test status
Simulation time 1122195682 ps
CPU time 2.71 seconds
Started May 12 01:01:33 PM PDT 24
Finished May 12 01:01:36 PM PDT 24
Peak memory 216052 kb
Host smart-54e4d37b-cfe4-4853-9244-0c582ee60b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456563185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1456563185
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2099328314
Short name T380
Test name
Test status
Simulation time 88831950 ps
CPU time 1.08 seconds
Started May 12 01:01:35 PM PDT 24
Finished May 12 01:01:36 PM PDT 24
Peak memory 206720 kb
Host smart-d0538913-c0aa-40bc-9b8a-73230e1f658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099328314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2099328314
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1879385915
Short name T193
Test name
Test status
Simulation time 265326108 ps
CPU time 2.84 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:01:39 PM PDT 24
Peak memory 234124 kb
Host smart-082f50f8-5133-4eae-bcdd-054f72f8f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879385915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1879385915
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3803219234
Short name T765
Test name
Test status
Simulation time 26169561 ps
CPU time 0.74 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:02:56 PM PDT 24
Peak memory 205168 kb
Host smart-5dcd1ca1-ddd7-47c9-92b0-1d9d02b2db30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803219234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3803219234
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3228496017
Short name T663
Test name
Test status
Simulation time 293639973 ps
CPU time 2.88 seconds
Started May 12 01:02:55 PM PDT 24
Finished May 12 01:02:58 PM PDT 24
Peak memory 233984 kb
Host smart-c8a022b7-5c45-4011-a440-dc0fe94bab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228496017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3228496017
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1010479352
Short name T376
Test name
Test status
Simulation time 15660639 ps
CPU time 0.77 seconds
Started May 12 01:02:53 PM PDT 24
Finished May 12 01:02:54 PM PDT 24
Peak memory 205116 kb
Host smart-4f15f273-e7c6-4b7f-9f48-9a004c072a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010479352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1010479352
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.179469615
Short name T695
Test name
Test status
Simulation time 2345771880 ps
CPU time 23.13 seconds
Started May 12 01:03:04 PM PDT 24
Finished May 12 01:03:27 PM PDT 24
Peak memory 239140 kb
Host smart-2ad4aa94-d377-4991-a193-0954c55ea00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179469615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.179469615
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2389254532
Short name T888
Test name
Test status
Simulation time 5046239483 ps
CPU time 61.75 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 249336 kb
Host smart-8edb970e-0210-485b-aac1-3ebb1997992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389254532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2389254532
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2624388204
Short name T828
Test name
Test status
Simulation time 543688346 ps
CPU time 15.1 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:03:11 PM PDT 24
Peak memory 249956 kb
Host smart-daf9a57f-2ca9-4557-a539-67d26c2d313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624388204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2624388204
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2076029913
Short name T354
Test name
Test status
Simulation time 14655710249 ps
CPU time 32.4 seconds
Started May 12 01:02:57 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 232392 kb
Host smart-3458f9ef-14dc-4fcb-b42d-03d1333a8dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076029913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2076029913
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2400723931
Short name T494
Test name
Test status
Simulation time 58972485 ps
CPU time 2.41 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:02:58 PM PDT 24
Peak memory 221052 kb
Host smart-2ce27584-942e-46f1-abdf-4ee3ca560220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400723931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2400723931
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2198425135
Short name T826
Test name
Test status
Simulation time 1656033388 ps
CPU time 6.29 seconds
Started May 12 01:02:55 PM PDT 24
Finished May 12 01:03:02 PM PDT 24
Peak memory 238812 kb
Host smart-b996bada-6945-49a8-8395-acf8254b6322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198425135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2198425135
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1730385835
Short name T748
Test name
Test status
Simulation time 489606456 ps
CPU time 3.94 seconds
Started May 12 01:02:55 PM PDT 24
Finished May 12 01:02:59 PM PDT 24
Peak memory 222912 kb
Host smart-b513f5f7-ca70-42fd-82ed-83761f7794d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1730385835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1730385835
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4122894952
Short name T316
Test name
Test status
Simulation time 1756550457 ps
CPU time 27.68 seconds
Started May 12 01:02:47 PM PDT 24
Finished May 12 01:03:16 PM PDT 24
Peak memory 216352 kb
Host smart-a5e84061-0129-4654-a476-3a67631ba1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122894952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4122894952
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3542668157
Short name T435
Test name
Test status
Simulation time 223647310 ps
CPU time 1.92 seconds
Started May 12 01:02:51 PM PDT 24
Finished May 12 01:02:53 PM PDT 24
Peak memory 207608 kb
Host smart-07315649-70d9-425d-a380-426632b55cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542668157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3542668157
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3819580187
Short name T858
Test name
Test status
Simulation time 12912691 ps
CPU time 0.71 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:02:56 PM PDT 24
Peak memory 205444 kb
Host smart-95a3f833-b746-4e0c-bdcc-ae6904ec1f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819580187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3819580187
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.267606443
Short name T595
Test name
Test status
Simulation time 91808341 ps
CPU time 0.86 seconds
Started May 12 01:02:51 PM PDT 24
Finished May 12 01:02:52 PM PDT 24
Peak memory 205580 kb
Host smart-86a74fd4-7aa1-45a8-9889-2e8afd48d8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267606443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.267606443
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1601265153
Short name T775
Test name
Test status
Simulation time 3621844033 ps
CPU time 15.9 seconds
Started May 12 01:03:03 PM PDT 24
Finished May 12 01:03:19 PM PDT 24
Peak memory 238636 kb
Host smart-0438d7cb-ebb7-4432-ab7c-77a44371a8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601265153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1601265153
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2565861487
Short name T846
Test name
Test status
Simulation time 17136551 ps
CPU time 0.76 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:03:01 PM PDT 24
Peak memory 204552 kb
Host smart-90d7cc47-36ae-461b-a0d6-c266d57bdfdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565861487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2565861487
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.241459668
Short name T647
Test name
Test status
Simulation time 169695352 ps
CPU time 3.67 seconds
Started May 12 01:02:55 PM PDT 24
Finished May 12 01:02:59 PM PDT 24
Peak memory 218396 kb
Host smart-d8ee19cf-3c00-4d0e-849f-0396b433a209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241459668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.241459668
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1546921562
Short name T423
Test name
Test status
Simulation time 43672766 ps
CPU time 0.76 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:02:55 PM PDT 24
Peak memory 206608 kb
Host smart-5594f518-352f-4d92-a32e-2a7b06487e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546921562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1546921562
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3643922593
Short name T561
Test name
Test status
Simulation time 9912012761 ps
CPU time 43.12 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 217408 kb
Host smart-9b210c6e-4dbd-4e72-bae2-b848d96f94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643922593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3643922593
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.487995093
Short name T176
Test name
Test status
Simulation time 6667962752 ps
CPU time 42.94 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:03:44 PM PDT 24
Peak memory 240772 kb
Host smart-fa17b7ac-659f-4bc8-ae6b-c809dd2513d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487995093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.487995093
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2892233124
Short name T283
Test name
Test status
Simulation time 358097844 ps
CPU time 3.49 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:03:00 PM PDT 24
Peak memory 224256 kb
Host smart-5600fdae-ee91-40a2-ab11-6232f60829cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892233124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2892233124
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1338027332
Short name T212
Test name
Test status
Simulation time 15146520497 ps
CPU time 15.13 seconds
Started May 12 01:03:02 PM PDT 24
Finished May 12 01:03:18 PM PDT 24
Peak memory 219524 kb
Host smart-f2bb1a39-ae1e-42e7-8fa9-9256b748bef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338027332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1338027332
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3422108877
Short name T48
Test name
Test status
Simulation time 2484263633 ps
CPU time 19.75 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 231480 kb
Host smart-5e91d8c8-4333-401a-819c-78d265bfed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422108877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3422108877
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1782886325
Short name T566
Test name
Test status
Simulation time 594145864 ps
CPU time 2.91 seconds
Started May 12 01:02:54 PM PDT 24
Finished May 12 01:02:57 PM PDT 24
Peak memory 218464 kb
Host smart-1a66b343-3d7b-4be2-9c67-4619d8edbcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782886325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1782886325
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2758488658
Short name T521
Test name
Test status
Simulation time 12861798275 ps
CPU time 12.45 seconds
Started May 12 01:02:57 PM PDT 24
Finished May 12 01:03:10 PM PDT 24
Peak memory 234712 kb
Host smart-8eeb1180-b4d7-4d42-91cd-ff66e5d80ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758488658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2758488658
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1122652561
Short name T365
Test name
Test status
Simulation time 360998539 ps
CPU time 4.73 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:03:02 PM PDT 24
Peak memory 218552 kb
Host smart-50610fb8-eefa-4226-a04e-8087d18cf33c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122652561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1122652561
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2520084463
Short name T930
Test name
Test status
Simulation time 17000985944 ps
CPU time 100.72 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:04:42 PM PDT 24
Peak memory 249320 kb
Host smart-4ee20dfa-ebf6-45e6-8b0f-37deb63664ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520084463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2520084463
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.938644567
Short name T871
Test name
Test status
Simulation time 17877365405 ps
CPU time 54.84 seconds
Started May 12 01:02:55 PM PDT 24
Finished May 12 01:03:50 PM PDT 24
Peak memory 216052 kb
Host smart-497e4df5-e096-45ea-8f70-911d64182354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938644567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.938644567
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.609920617
Short name T688
Test name
Test status
Simulation time 12269519317 ps
CPU time 8.06 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:03:05 PM PDT 24
Peak memory 217260 kb
Host smart-e9379904-a73c-48f1-9caf-d74933486877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609920617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.609920617
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.508232715
Short name T551
Test name
Test status
Simulation time 58533500 ps
CPU time 1.89 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:02:59 PM PDT 24
Peak memory 216336 kb
Host smart-62fa2de1-b974-4d99-bf14-354a0599819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508232715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.508232715
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3776057903
Short name T158
Test name
Test status
Simulation time 57468439 ps
CPU time 0.68 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:02:57 PM PDT 24
Peak memory 205692 kb
Host smart-0996b2ba-1330-4a99-afc4-7e21d8a41f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776057903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3776057903
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1098919972
Short name T589
Test name
Test status
Simulation time 688130533 ps
CPU time 6.86 seconds
Started May 12 01:02:56 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 218568 kb
Host smart-d346d42c-b41a-4461-90cc-812bdca94ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098919972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1098919972
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4129659460
Short name T777
Test name
Test status
Simulation time 25623030 ps
CPU time 0.73 seconds
Started May 12 01:02:59 PM PDT 24
Finished May 12 01:03:00 PM PDT 24
Peak memory 205180 kb
Host smart-e76b075a-f436-48ef-93b3-77cfb93eacfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129659460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4129659460
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1139855686
Short name T174
Test name
Test status
Simulation time 276360495 ps
CPU time 5.01 seconds
Started May 12 01:03:04 PM PDT 24
Finished May 12 01:03:10 PM PDT 24
Peak memory 235360 kb
Host smart-b4fd2bd2-61f9-47c7-bb7f-195ed12ccb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139855686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1139855686
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1178423615
Short name T450
Test name
Test status
Simulation time 129842424 ps
CPU time 0.75 seconds
Started May 12 01:03:02 PM PDT 24
Finished May 12 01:03:04 PM PDT 24
Peak memory 205332 kb
Host smart-810625b0-2beb-4778-be79-63c4d4b6b144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178423615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1178423615
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3373674895
Short name T598
Test name
Test status
Simulation time 10003955956 ps
CPU time 76.32 seconds
Started May 12 01:03:01 PM PDT 24
Finished May 12 01:04:17 PM PDT 24
Peak memory 240672 kb
Host smart-817664be-ee69-40fd-a2f4-aa6411c948a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373674895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3373674895
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1994748450
Short name T269
Test name
Test status
Simulation time 7556489948 ps
CPU time 97.44 seconds
Started May 12 01:03:04 PM PDT 24
Finished May 12 01:04:42 PM PDT 24
Peak memory 248984 kb
Host smart-d6d83e68-4d16-4211-a3aa-5c5c0b59c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994748450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1994748450
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.636911309
Short name T427
Test name
Test status
Simulation time 6936810749 ps
CPU time 103.28 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 254884 kb
Host smart-1fe8d5a0-47dc-4ab0-af13-d9dd6dcdf350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636911309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.636911309
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3001686648
Short name T304
Test name
Test status
Simulation time 231740039 ps
CPU time 6.04 seconds
Started May 12 01:03:03 PM PDT 24
Finished May 12 01:03:09 PM PDT 24
Peak memory 232932 kb
Host smart-38021304-199f-41a2-8bb4-ae2492be44a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001686648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3001686648
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.164632320
Short name T712
Test name
Test status
Simulation time 5963896150 ps
CPU time 15.55 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:03:16 PM PDT 24
Peak memory 234328 kb
Host smart-36f85077-8683-48e3-a707-acf81a2934a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164632320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.164632320
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2014749730
Short name T790
Test name
Test status
Simulation time 770670779 ps
CPU time 10.87 seconds
Started May 12 01:03:03 PM PDT 24
Finished May 12 01:03:14 PM PDT 24
Peak memory 235756 kb
Host smart-421c2abc-fdf4-487d-bb6d-92ee2923b353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014749730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2014749730
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4244026490
Short name T786
Test name
Test status
Simulation time 5426554335 ps
CPU time 15.72 seconds
Started May 12 01:02:59 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 240752 kb
Host smart-299c7d58-1c9c-4486-8f15-4673ebf98856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244026490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4244026490
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3077698303
Short name T454
Test name
Test status
Simulation time 1442520368 ps
CPU time 7.87 seconds
Started May 12 01:02:59 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 234984 kb
Host smart-866bc82f-0756-4dda-a3d6-a9698fa21d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077698303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3077698303
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3314910126
Short name T802
Test name
Test status
Simulation time 1287151736 ps
CPU time 10.62 seconds
Started May 12 01:03:01 PM PDT 24
Finished May 12 01:03:12 PM PDT 24
Peak memory 221772 kb
Host smart-0d128d44-88d8-4538-850f-ae1050a352c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3314910126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3314910126
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1990195706
Short name T644
Test name
Test status
Simulation time 23358209935 ps
CPU time 286.44 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:07:47 PM PDT 24
Peak memory 272924 kb
Host smart-b7388b15-1e2a-4617-aa31-7934d74acb68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990195706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1990195706
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.869440887
Short name T864
Test name
Test status
Simulation time 14360358292 ps
CPU time 24.62 seconds
Started May 12 01:02:59 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 216208 kb
Host smart-8250e909-669a-4b94-a533-41527c2ebaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869440887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.869440887
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.138872410
Short name T508
Test name
Test status
Simulation time 388353777 ps
CPU time 2.75 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:03:03 PM PDT 24
Peak memory 216032 kb
Host smart-258ffe9b-7e8c-4a3b-8229-1be122885fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138872410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.138872410
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2446821054
Short name T943
Test name
Test status
Simulation time 53057731 ps
CPU time 0.93 seconds
Started May 12 01:03:02 PM PDT 24
Finished May 12 01:03:03 PM PDT 24
Peak memory 206680 kb
Host smart-3138a268-2a6d-423f-b188-67c3efe74cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446821054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2446821054
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_upload.1905352628
Short name T173
Test name
Test status
Simulation time 2768345015 ps
CPU time 4.65 seconds
Started May 12 01:02:59 PM PDT 24
Finished May 12 01:03:05 PM PDT 24
Peak memory 224348 kb
Host smart-84f87548-c589-4174-8581-2742bd57534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905352628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1905352628
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1806922823
Short name T341
Test name
Test status
Simulation time 41852320 ps
CPU time 0.76 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 205240 kb
Host smart-96469cd1-d4ee-46f3-a12c-2980c1f68505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806922823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1806922823
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4174441107
Short name T563
Test name
Test status
Simulation time 342966233 ps
CPU time 4.07 seconds
Started May 12 01:03:09 PM PDT 24
Finished May 12 01:03:13 PM PDT 24
Peak memory 219476 kb
Host smart-e3448979-3a81-462e-afe1-44880e4afb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174441107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4174441107
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1495273857
Short name T344
Test name
Test status
Simulation time 16398021 ps
CPU time 0.77 seconds
Started May 12 01:02:58 PM PDT 24
Finished May 12 01:03:00 PM PDT 24
Peak memory 206384 kb
Host smart-56743eb2-82ec-40dd-9279-3d50ff76ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495273857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1495273857
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1612844105
Short name T708
Test name
Test status
Simulation time 14889327818 ps
CPU time 56.61 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:04:04 PM PDT 24
Peak memory 239748 kb
Host smart-5ca0dbc4-fc6f-4da5-949b-7843e326c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612844105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1612844105
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1327505172
Short name T313
Test name
Test status
Simulation time 86918727639 ps
CPU time 144.27 seconds
Started May 12 01:03:10 PM PDT 24
Finished May 12 01:05:34 PM PDT 24
Peak memory 248896 kb
Host smart-7fd3801f-2123-4442-b67d-300ca92a8c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327505172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1327505172
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3959556215
Short name T936
Test name
Test status
Simulation time 608438308 ps
CPU time 2.73 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:03:10 PM PDT 24
Peak memory 224208 kb
Host smart-2a00de18-8f7a-4f8b-ad99-73f0297b0286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959556215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3959556215
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.368010143
Short name T811
Test name
Test status
Simulation time 100500950 ps
CPU time 3.68 seconds
Started May 12 01:03:06 PM PDT 24
Finished May 12 01:03:11 PM PDT 24
Peak memory 233440 kb
Host smart-a831e808-f96b-4f65-b487-e75a937bc556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368010143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.368010143
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3919157119
Short name T949
Test name
Test status
Simulation time 15262938555 ps
CPU time 15.75 seconds
Started May 12 01:03:06 PM PDT 24
Finished May 12 01:03:22 PM PDT 24
Peak memory 222624 kb
Host smart-09cc1c85-791c-4be4-86ad-f0fc01a0837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919157119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3919157119
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2878557025
Short name T462
Test name
Test status
Simulation time 1964038253 ps
CPU time 8.43 seconds
Started May 12 01:02:58 PM PDT 24
Finished May 12 01:03:07 PM PDT 24
Peak memory 218956 kb
Host smart-0dc60744-5a8d-4295-ab25-c18fad680b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878557025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2878557025
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.680331983
Short name T910
Test name
Test status
Simulation time 30139769663 ps
CPU time 39.56 seconds
Started May 12 01:03:03 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 246332 kb
Host smart-74e237c5-f868-48f6-b20d-d58dacdda814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680331983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.680331983
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2651714583
Short name T955
Test name
Test status
Simulation time 2168522338 ps
CPU time 11.47 seconds
Started May 12 01:03:05 PM PDT 24
Finished May 12 01:03:17 PM PDT 24
Peak memory 219840 kb
Host smart-80793506-73a5-4582-94e7-5ffba89f52c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2651714583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2651714583
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3970265446
Short name T296
Test name
Test status
Simulation time 26920585813 ps
CPU time 176.42 seconds
Started May 12 01:03:05 PM PDT 24
Finished May 12 01:06:02 PM PDT 24
Peak memory 252080 kb
Host smart-d29c915c-4a8a-4d5f-a686-de826df32676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970265446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3970265446
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3205065693
Short name T705
Test name
Test status
Simulation time 3689796291 ps
CPU time 25.28 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 216064 kb
Host smart-28ff76e9-c4c3-4c39-a5a3-9a05d9d3a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205065693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3205065693
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3612463206
Short name T514
Test name
Test status
Simulation time 22527296 ps
CPU time 0.74 seconds
Started May 12 01:03:02 PM PDT 24
Finished May 12 01:03:03 PM PDT 24
Peak memory 205716 kb
Host smart-53572832-a70c-43ba-8b6a-65d7e69d32f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612463206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3612463206
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2280036214
Short name T816
Test name
Test status
Simulation time 278365353 ps
CPU time 6.33 seconds
Started May 12 01:03:00 PM PDT 24
Finished May 12 01:03:07 PM PDT 24
Peak memory 215936 kb
Host smart-7f7c4df7-7e41-4bf8-b5e0-f060a17bb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280036214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2280036214
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1791932366
Short name T779
Test name
Test status
Simulation time 54677149 ps
CPU time 0.84 seconds
Started May 12 01:02:58 PM PDT 24
Finished May 12 01:02:59 PM PDT 24
Peak memory 205552 kb
Host smart-aa51923a-0292-4c1d-b977-118c454005d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791932366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1791932366
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3889098055
Short name T286
Test name
Test status
Simulation time 1008450121 ps
CPU time 5.66 seconds
Started May 12 01:03:05 PM PDT 24
Finished May 12 01:03:12 PM PDT 24
Peak memory 233484 kb
Host smart-ee2f7a74-5197-4e33-bb09-d7b57e69a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889098055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3889098055
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1370075185
Short name T800
Test name
Test status
Simulation time 15632345 ps
CPU time 0.74 seconds
Started May 12 01:03:14 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 205196 kb
Host smart-951c0e09-2fd3-429f-a307-6c7326ffbaad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370075185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1370075185
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2172102059
Short name T496
Test name
Test status
Simulation time 117220753 ps
CPU time 3.62 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 218440 kb
Host smart-2e2ccac3-0067-4e1a-af54-486c85bf95c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172102059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2172102059
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.19813868
Short name T715
Test name
Test status
Simulation time 107016912 ps
CPU time 0.74 seconds
Started May 12 01:03:06 PM PDT 24
Finished May 12 01:03:07 PM PDT 24
Peak memory 205424 kb
Host smart-d60ddcd4-9caf-40d6-8e1b-27ecf6066605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19813868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.19813868
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.997719666
Short name T298
Test name
Test status
Simulation time 368271585442 ps
CPU time 239.37 seconds
Started May 12 01:03:12 PM PDT 24
Finished May 12 01:07:12 PM PDT 24
Peak memory 238732 kb
Host smart-4c46b2bd-4bcc-4db0-9b3a-9ff847ccfa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997719666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.997719666
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4233931942
Short name T721
Test name
Test status
Simulation time 19193038299 ps
CPU time 182.5 seconds
Started May 12 01:03:10 PM PDT 24
Finished May 12 01:06:13 PM PDT 24
Peak memory 253112 kb
Host smart-2b393af7-c9ae-425c-a30f-548cf16c90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233931942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4233931942
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2304243175
Short name T696
Test name
Test status
Simulation time 4972100759 ps
CPU time 72.45 seconds
Started May 12 01:03:13 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 252552 kb
Host smart-e97af748-9a45-4bb1-9485-2d27d48a70fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304243175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2304243175
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2137669714
Short name T353
Test name
Test status
Simulation time 2520835191 ps
CPU time 10.7 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:23 PM PDT 24
Peak memory 224460 kb
Host smart-18f46f7c-0518-40ba-85f9-59f2dd7b489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137669714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2137669714
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4112875422
Short name T872
Test name
Test status
Simulation time 106274222 ps
CPU time 2.27 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:03:09 PM PDT 24
Peak memory 215812 kb
Host smart-71faa3ff-5ae8-44ac-bae3-ebdf56b2a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112875422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4112875422
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3218895471
Short name T368
Test name
Test status
Simulation time 54105821 ps
CPU time 2.25 seconds
Started May 12 01:03:05 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 221060 kb
Host smart-f0be22ed-c462-41ef-b9b1-12718d348bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218895471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3218895471
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3871739700
Short name T809
Test name
Test status
Simulation time 16300305591 ps
CPU time 13.01 seconds
Started May 12 01:03:09 PM PDT 24
Finished May 12 01:03:22 PM PDT 24
Peak memory 233424 kb
Host smart-3e261465-09fb-4feb-8d74-395630c01e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871739700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3871739700
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3995231095
Short name T497
Test name
Test status
Simulation time 165775231 ps
CPU time 3.45 seconds
Started May 12 01:03:05 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 217156 kb
Host smart-67f6e78e-cb3f-4d67-ab8d-99ff59bbeeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995231095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3995231095
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1789154570
Short name T491
Test name
Test status
Simulation time 261840988 ps
CPU time 4.8 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:17 PM PDT 24
Peak memory 218392 kb
Host smart-f10e4d68-e0e8-47eb-8d88-85abe1c77fcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1789154570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1789154570
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.531887297
Short name T746
Test name
Test status
Simulation time 55252574062 ps
CPU time 497.04 seconds
Started May 12 01:03:12 PM PDT 24
Finished May 12 01:11:30 PM PDT 24
Peak memory 265368 kb
Host smart-e2d1f976-f9f6-49b7-90ea-7052d657136e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531887297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.531887297
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2886596619
Short name T788
Test name
Test status
Simulation time 25249658 ps
CPU time 0.72 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 205496 kb
Host smart-9ee7f9e4-03bc-485c-b30f-4806b0a93b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886596619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2886596619
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3004491440
Short name T654
Test name
Test status
Simulation time 3426676976 ps
CPU time 6.49 seconds
Started May 12 01:03:06 PM PDT 24
Finished May 12 01:03:13 PM PDT 24
Peak memory 216372 kb
Host smart-a7d7ca15-319d-400b-82be-9b8a9adaa057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004491440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3004491440
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.829173346
Short name T808
Test name
Test status
Simulation time 206153667 ps
CPU time 0.99 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 207108 kb
Host smart-c7df0b1e-4b7e-4790-8e51-edf0c7a241b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829173346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.829173346
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2736302290
Short name T7
Test name
Test status
Simulation time 143006992 ps
CPU time 0.88 seconds
Started May 12 01:03:07 PM PDT 24
Finished May 12 01:03:08 PM PDT 24
Peak memory 205588 kb
Host smart-d0d105c5-c40b-4b96-ad84-1c48243a4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736302290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2736302290
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4088083681
Short name T412
Test name
Test status
Simulation time 1735896086 ps
CPU time 5.36 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:17 PM PDT 24
Peak memory 224240 kb
Host smart-acb8607f-8387-4534-9fdd-968b05fbf76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088083681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4088083681
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1942651701
Short name T635
Test name
Test status
Simulation time 31917035 ps
CPU time 0.72 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:03:18 PM PDT 24
Peak memory 205152 kb
Host smart-6c933cd0-273b-4dd1-a8e3-3802a30d84cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942651701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1942651701
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3274619907
Short name T458
Test name
Test status
Simulation time 1073614773 ps
CPU time 3.48 seconds
Started May 12 01:03:12 PM PDT 24
Finished May 12 01:03:16 PM PDT 24
Peak memory 234024 kb
Host smart-6626403b-fa39-47ff-ab7b-32ad96e1a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274619907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3274619907
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.141274342
Short name T156
Test name
Test status
Simulation time 28440302 ps
CPU time 0.76 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:12 PM PDT 24
Peak memory 205404 kb
Host smart-17592a7e-744d-4b19-bbec-7ac273d55b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141274342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.141274342
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.429688902
Short name T946
Test name
Test status
Simulation time 4367107869 ps
CPU time 48.81 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:04:00 PM PDT 24
Peak memory 250764 kb
Host smart-f83ffab0-0ed5-4e5e-8f65-d56533d01165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429688902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.429688902
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.211929553
Short name T830
Test name
Test status
Simulation time 36959918479 ps
CPU time 99.97 seconds
Started May 12 01:03:15 PM PDT 24
Finished May 12 01:04:55 PM PDT 24
Peak memory 268360 kb
Host smart-1f96960b-54ae-4d3b-88c4-f686ed014ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211929553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.211929553
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2240718976
Short name T502
Test name
Test status
Simulation time 7448421081 ps
CPU time 52.2 seconds
Started May 12 01:03:10 PM PDT 24
Finished May 12 01:04:03 PM PDT 24
Peak memory 249284 kb
Host smart-480f71d9-560b-4efb-9d36-7d34dda44e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240718976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2240718976
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3538637519
Short name T302
Test name
Test status
Simulation time 1600363365 ps
CPU time 11.77 seconds
Started May 12 01:03:15 PM PDT 24
Finished May 12 01:03:27 PM PDT 24
Peak memory 247912 kb
Host smart-4fb6d80c-5a13-4bf9-ad82-432bdd9ab205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538637519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3538637519
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2977094973
Short name T204
Test name
Test status
Simulation time 1686045948 ps
CPU time 4.23 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:16 PM PDT 24
Peak memory 218316 kb
Host smart-f9ed84ee-ae7e-4612-a88a-ded49c7bdcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977094973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2977094973
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.477565461
Short name T792
Test name
Test status
Simulation time 4172938106 ps
CPU time 14.28 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 218532 kb
Host smart-db27a433-6545-451a-874e-89efc72f18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477565461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.477565461
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3244648457
Short name T716
Test name
Test status
Simulation time 492744074 ps
CPU time 5.99 seconds
Started May 12 01:03:12 PM PDT 24
Finished May 12 01:03:18 PM PDT 24
Peak memory 218188 kb
Host smart-81d8d595-d49d-49d1-97b3-a1f61c2dc041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244648457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3244648457
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1528129762
Short name T208
Test name
Test status
Simulation time 2209356165 ps
CPU time 8.78 seconds
Started May 12 01:03:10 PM PDT 24
Finished May 12 01:03:19 PM PDT 24
Peak memory 233468 kb
Host smart-7d6e5350-36e4-4223-bee5-ba448bfc6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528129762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1528129762
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1601645939
Short name T594
Test name
Test status
Simulation time 66753754 ps
CPU time 3.51 seconds
Started May 12 01:03:10 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 222432 kb
Host smart-9a033b27-e3e1-4d37-a00d-082c2900dc78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1601645939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1601645939
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2354936546
Short name T901
Test name
Test status
Simulation time 18558558857 ps
CPU time 107.65 seconds
Started May 12 01:03:16 PM PDT 24
Finished May 12 01:05:04 PM PDT 24
Peak memory 252504 kb
Host smart-e5e82c20-f53c-435d-ab17-a39d816b1e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354936546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2354936546
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.486867691
Short name T844
Test name
Test status
Simulation time 8021169755 ps
CPU time 11.86 seconds
Started May 12 01:03:11 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 216132 kb
Host smart-60fa193b-c46d-4fe8-b635-ca4df12f51f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486867691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.486867691
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.965794649
Short name T646
Test name
Test status
Simulation time 326563565 ps
CPU time 1.27 seconds
Started May 12 01:03:13 PM PDT 24
Finished May 12 01:03:15 PM PDT 24
Peak memory 206640 kb
Host smart-ad987b6d-9a63-4d55-ac72-853b73cb4a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965794649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.965794649
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3216289028
Short name T919
Test name
Test status
Simulation time 11578508 ps
CPU time 0.71 seconds
Started May 12 01:03:10 PM PDT 24
Finished May 12 01:03:12 PM PDT 24
Peak memory 205320 kb
Host smart-e99f8a89-ed70-48ba-9e7d-55373b893075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216289028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3216289028
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1610234242
Short name T639
Test name
Test status
Simulation time 94928547 ps
CPU time 0.79 seconds
Started May 12 01:03:14 PM PDT 24
Finished May 12 01:03:16 PM PDT 24
Peak memory 205712 kb
Host smart-6ebbd494-3b11-4057-91c5-06f5a38e402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610234242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1610234242
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3810075296
Short name T190
Test name
Test status
Simulation time 2229455655 ps
CPU time 4.81 seconds
Started May 12 01:03:12 PM PDT 24
Finished May 12 01:03:17 PM PDT 24
Peak memory 232628 kb
Host smart-15c1a959-2e59-41e5-a88a-9436e54c4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810075296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3810075296
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1977565441
Short name T600
Test name
Test status
Simulation time 41318163 ps
CPU time 0.73 seconds
Started May 12 01:03:24 PM PDT 24
Finished May 12 01:03:25 PM PDT 24
Peak memory 205624 kb
Host smart-341ba197-b77e-4e46-b5b5-3301b3012869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977565441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1977565441
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1852058815
Short name T806
Test name
Test status
Simulation time 199363162 ps
CPU time 5.26 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:31 PM PDT 24
Peak memory 234360 kb
Host smart-734bc69f-0270-4940-8c7f-790a73fa93da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852058815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1852058815
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2956492137
Short name T670
Test name
Test status
Simulation time 23272348 ps
CPU time 0.76 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:03:18 PM PDT 24
Peak memory 206328 kb
Host smart-59397bc0-c6cf-4ea5-8148-3a85d79b3e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956492137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2956492137
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1556492843
Short name T9
Test name
Test status
Simulation time 49668504140 ps
CPU time 361.61 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:09:28 PM PDT 24
Peak memory 256284 kb
Host smart-ab75108c-deda-4149-b792-8b8a14d8076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556492843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1556492843
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2791257922
Short name T206
Test name
Test status
Simulation time 723367843664 ps
CPU time 764.64 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:16:02 PM PDT 24
Peak memory 252580 kb
Host smart-a9a8f058-74dd-403d-a004-73484631074c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791257922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2791257922
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4137357609
Short name T246
Test name
Test status
Simulation time 5053282079 ps
CPU time 66.2 seconds
Started May 12 01:03:18 PM PDT 24
Finished May 12 01:04:24 PM PDT 24
Peak memory 239480 kb
Host smart-03d7eb36-5676-46b0-94b6-780a09a16c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137357609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4137357609
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3270273586
Short name T272
Test name
Test status
Simulation time 4065689487 ps
CPU time 11.6 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:38 PM PDT 24
Peak memory 224476 kb
Host smart-0ce53b7e-c2b6-4c4a-8f13-2a0c197462b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270273586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3270273586
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4049283215
Short name T729
Test name
Test status
Simulation time 4631484319 ps
CPU time 15.75 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 233812 kb
Host smart-bc60cec9-c793-43fd-bd4a-4b4b794a2312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049283215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4049283215
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3818743145
Short name T848
Test name
Test status
Simulation time 1015226476 ps
CPU time 8.4 seconds
Started May 12 01:03:15 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 240436 kb
Host smart-469ded69-e414-4868-9d6b-a74785f569e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818743145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3818743145
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1547324255
Short name T954
Test name
Test status
Simulation time 6791156814 ps
CPU time 18.02 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:03:36 PM PDT 24
Peak memory 226548 kb
Host smart-73c1a994-88d7-4203-b3c4-d3d31071968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547324255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1547324255
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3749303090
Short name T754
Test name
Test status
Simulation time 10131974786 ps
CPU time 8.45 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 232520 kb
Host smart-8428029a-0993-4149-9178-43e8a663afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749303090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3749303090
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3224106432
Short name T769
Test name
Test status
Simulation time 786950027 ps
CPU time 11.29 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:38 PM PDT 24
Peak memory 220212 kb
Host smart-8bdb12e6-620f-43f7-a3c7-9f6eb8ab8297
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3224106432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3224106432
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2713278857
Short name T616
Test name
Test status
Simulation time 2781502561 ps
CPU time 15.06 seconds
Started May 12 01:03:17 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 216152 kb
Host smart-ce097fb7-28b6-4128-b55f-7018b05e276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713278857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2713278857
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2307295902
Short name T913
Test name
Test status
Simulation time 9634669664 ps
CPU time 26.71 seconds
Started May 12 01:03:16 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 216004 kb
Host smart-cb956aa3-07d3-4079-8677-170d10401b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307295902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2307295902
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3910478610
Short name T490
Test name
Test status
Simulation time 688721156 ps
CPU time 2.05 seconds
Started May 12 01:03:15 PM PDT 24
Finished May 12 01:03:18 PM PDT 24
Peak memory 215976 kb
Host smart-3418bbbf-c272-4a3e-a4fe-63687514f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910478610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3910478610
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2655290779
Short name T687
Test name
Test status
Simulation time 136721387 ps
CPU time 0.8 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:28 PM PDT 24
Peak memory 205716 kb
Host smart-291a812a-7a0b-4645-a084-12ea6f96309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655290779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2655290779
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2497848514
Short name T577
Test name
Test status
Simulation time 18576014775 ps
CPU time 28.97 seconds
Started May 12 01:03:16 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 234452 kb
Host smart-c2e37bcf-3752-4ae0-b6a1-8fe656fca77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497848514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2497848514
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1908781521
Short name T326
Test name
Test status
Simulation time 48651342 ps
CPU time 0.71 seconds
Started May 12 01:03:21 PM PDT 24
Finished May 12 01:03:22 PM PDT 24
Peak memory 205116 kb
Host smart-ee6cdbd5-4920-48aa-81a7-b2b27cf32156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908781521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1908781521
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1770331684
Short name T386
Test name
Test status
Simulation time 1168975666 ps
CPU time 4.08 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 219704 kb
Host smart-c0feef52-141b-4523-95e4-a0e5bc21ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770331684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1770331684
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1586549557
Short name T612
Test name
Test status
Simulation time 19378652 ps
CPU time 0.8 seconds
Started May 12 01:03:23 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 206304 kb
Host smart-291bc751-abe6-4b3d-832b-99f0d26ff09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586549557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1586549557
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3177508358
Short name T172
Test name
Test status
Simulation time 34500629405 ps
CPU time 135.39 seconds
Started May 12 01:03:22 PM PDT 24
Finished May 12 01:05:38 PM PDT 24
Peak memory 265228 kb
Host smart-9a5956bd-fa48-43a2-b8ec-e9f82543939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177508358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3177508358
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1239655895
Short name T154
Test name
Test status
Simulation time 2713268581 ps
CPU time 32.24 seconds
Started May 12 01:03:22 PM PDT 24
Finished May 12 01:03:55 PM PDT 24
Peak memory 239748 kb
Host smart-6396fce1-e8a3-4cca-af38-0b63ae9f5de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239655895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1239655895
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2971120956
Short name T656
Test name
Test status
Simulation time 2735040326 ps
CPU time 17.51 seconds
Started May 12 01:03:25 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 224324 kb
Host smart-ba15dfe8-607c-40b5-aa61-695c156e136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971120956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2971120956
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.666961337
Short name T166
Test name
Test status
Simulation time 1567832077 ps
CPU time 13.28 seconds
Started May 12 01:03:25 PM PDT 24
Finished May 12 01:03:39 PM PDT 24
Peak memory 219388 kb
Host smart-12ec64c5-457e-4312-9920-501780813cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666961337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.666961337
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3698612961
Short name T500
Test name
Test status
Simulation time 4626480644 ps
CPU time 54.59 seconds
Started May 12 01:03:21 PM PDT 24
Finished May 12 01:04:16 PM PDT 24
Peak memory 240332 kb
Host smart-aa8abba2-7dd4-43f7-a5a2-41776f347e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698612961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3698612961
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3835998483
Short name T894
Test name
Test status
Simulation time 74055180 ps
CPU time 2.2 seconds
Started May 12 01:03:24 PM PDT 24
Finished May 12 01:03:27 PM PDT 24
Peak memory 216576 kb
Host smart-5083d2de-662a-4b86-ae39-ed53d734bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835998483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3835998483
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4245729852
Short name T655
Test name
Test status
Simulation time 5281909829 ps
CPU time 14.01 seconds
Started May 12 01:03:24 PM PDT 24
Finished May 12 01:03:39 PM PDT 24
Peak memory 218356 kb
Host smart-bab03cbf-54f9-4d31-b890-e3e1a4a93145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245729852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4245729852
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2217814935
Short name T676
Test name
Test status
Simulation time 219056085 ps
CPU time 3.58 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:31 PM PDT 24
Peak memory 222712 kb
Host smart-2adf22d4-8cea-4afc-a731-e4e3d57843c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2217814935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2217814935
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2619299481
Short name T455
Test name
Test status
Simulation time 1041877538 ps
CPU time 6.67 seconds
Started May 12 01:03:25 PM PDT 24
Finished May 12 01:03:32 PM PDT 24
Peak memory 218708 kb
Host smart-c3dabf39-8894-4a67-ba9b-062d419290a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619299481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2619299481
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.296148434
Short name T459
Test name
Test status
Simulation time 599054018 ps
CPU time 3.2 seconds
Started May 12 01:03:25 PM PDT 24
Finished May 12 01:03:28 PM PDT 24
Peak memory 215964 kb
Host smart-243db660-9fbf-41f5-bbe3-757e20a8bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296148434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.296148434
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3284045723
Short name T393
Test name
Test status
Simulation time 63641749 ps
CPU time 1.28 seconds
Started May 12 01:03:22 PM PDT 24
Finished May 12 01:03:24 PM PDT 24
Peak memory 215908 kb
Host smart-3bd1fb7d-eb6f-4c74-9ea7-18e32875f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284045723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3284045723
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3875089353
Short name T742
Test name
Test status
Simulation time 60209134 ps
CPU time 0.83 seconds
Started May 12 01:03:25 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 205656 kb
Host smart-c35e8e92-b9b1-403b-affb-863d118c5d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875089353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3875089353
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2265338469
Short name T739
Test name
Test status
Simulation time 2399779990 ps
CPU time 4.74 seconds
Started May 12 01:03:24 PM PDT 24
Finished May 12 01:03:29 PM PDT 24
Peak memory 232600 kb
Host smart-1cd76947-6ff0-41e4-aac2-1d797e8df65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265338469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2265338469
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3858843964
Short name T486
Test name
Test status
Simulation time 15937530 ps
CPU time 0.76 seconds
Started May 12 01:03:29 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 205192 kb
Host smart-12cae42f-f71d-42f9-a24a-394b27a2fe58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858843964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3858843964
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2350539132
Short name T186
Test name
Test status
Simulation time 391040262 ps
CPU time 3.02 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:29 PM PDT 24
Peak memory 233732 kb
Host smart-ea0f8122-6e80-4083-a68f-a05511322db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350539132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2350539132
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2740180995
Short name T648
Test name
Test status
Simulation time 17042935 ps
CPU time 0.81 seconds
Started May 12 01:03:22 PM PDT 24
Finished May 12 01:03:23 PM PDT 24
Peak memory 206044 kb
Host smart-bc874a74-6b33-490d-868b-d23ec96288aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740180995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2740180995
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2485581750
Short name T659
Test name
Test status
Simulation time 5022385567 ps
CPU time 45.21 seconds
Started May 12 01:03:28 PM PDT 24
Finished May 12 01:04:14 PM PDT 24
Peak memory 240664 kb
Host smart-a6186ea1-c172-471c-9df4-114b07ec2853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485581750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2485581750
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1474659602
Short name T834
Test name
Test status
Simulation time 5331903229 ps
CPU time 96.96 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:05:05 PM PDT 24
Peak memory 248972 kb
Host smart-2d01d8b5-a8b9-497b-b1b5-1865d93ab4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474659602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1474659602
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4255882405
Short name T16
Test name
Test status
Simulation time 51976331247 ps
CPU time 80.77 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:04:48 PM PDT 24
Peak memory 251244 kb
Host smart-90b596f0-011e-4e7c-bc64-1f14ee8c752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255882405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4255882405
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2123542997
Short name T285
Test name
Test status
Simulation time 115176637 ps
CPU time 2.67 seconds
Started May 12 01:03:28 PM PDT 24
Finished May 12 01:03:31 PM PDT 24
Peak memory 224180 kb
Host smart-d4da6c8a-8863-4a58-aec5-d98f6d2e8fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123542997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2123542997
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.271667880
Short name T281
Test name
Test status
Simulation time 1652284239 ps
CPU time 13.52 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:41 PM PDT 24
Peak memory 219448 kb
Host smart-ef9f0b76-c43c-4a7d-b6c2-3b3ed93015fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271667880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.271667880
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3978681449
Short name T884
Test name
Test status
Simulation time 122369382 ps
CPU time 4.96 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:32 PM PDT 24
Peak memory 234392 kb
Host smart-fc4348df-97c0-42a9-838e-a5dfeccdd944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978681449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3978681449
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4243972718
Short name T918
Test name
Test status
Simulation time 117076113895 ps
CPU time 26.01 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:53 PM PDT 24
Peak memory 232884 kb
Host smart-2238bc64-20ca-4956-a61a-7a152844cd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243972718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4243972718
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.471251846
Short name T678
Test name
Test status
Simulation time 7161209698 ps
CPU time 22.62 seconds
Started May 12 01:03:30 PM PDT 24
Finished May 12 01:03:53 PM PDT 24
Peak memory 220812 kb
Host smart-72fdfd8e-92cc-4524-9ad6-4f69c3fd374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471251846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.471251846
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.677834083
Short name T679
Test name
Test status
Simulation time 272168419 ps
CPU time 5.09 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 222212 kb
Host smart-286efdf7-e86c-453b-92d3-87cede17605a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=677834083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.677834083
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3750438480
Short name T683
Test name
Test status
Simulation time 74389050 ps
CPU time 1.2 seconds
Started May 12 01:03:28 PM PDT 24
Finished May 12 01:03:29 PM PDT 24
Peak memory 207004 kb
Host smart-a1f997d9-b090-47cd-bebd-f993e4dbf6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750438480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3750438480
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2820767836
Short name T702
Test name
Test status
Simulation time 5553850577 ps
CPU time 23.32 seconds
Started May 12 01:03:23 PM PDT 24
Finished May 12 01:03:46 PM PDT 24
Peak memory 216004 kb
Host smart-51ae0a58-86a9-4874-821e-5b3bd0dca6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820767836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2820767836
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2729548717
Short name T824
Test name
Test status
Simulation time 4038208651 ps
CPU time 5.49 seconds
Started May 12 01:03:24 PM PDT 24
Finished May 12 01:03:31 PM PDT 24
Peak memory 216092 kb
Host smart-ef4c0812-0182-42dd-a431-7abe9ab3407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729548717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2729548717
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2410782244
Short name T932
Test name
Test status
Simulation time 263089561 ps
CPU time 1.63 seconds
Started May 12 01:03:21 PM PDT 24
Finished May 12 01:03:23 PM PDT 24
Peak memory 216096 kb
Host smart-7a580882-8833-49f1-9edb-89ae6306e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410782244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2410782244
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3249748393
Short name T891
Test name
Test status
Simulation time 137977180 ps
CPU time 1.02 seconds
Started May 12 01:03:24 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 205636 kb
Host smart-f9ad914b-4bad-4e3f-a3ee-33736f535dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249748393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3249748393
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2614583027
Short name T294
Test name
Test status
Simulation time 734710060 ps
CPU time 6.29 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 237064 kb
Host smart-89b0c268-59de-4a87-b663-641b1ee29652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614583027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2614583027
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2320138176
Short name T812
Test name
Test status
Simulation time 41128198 ps
CPU time 0.71 seconds
Started May 12 01:03:33 PM PDT 24
Finished May 12 01:03:34 PM PDT 24
Peak memory 204680 kb
Host smart-dfa50670-7f70-4342-8993-92dc8efa69af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320138176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2320138176
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3156191557
Short name T744
Test name
Test status
Simulation time 125503342 ps
CPU time 3.42 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:31 PM PDT 24
Peak memory 234312 kb
Host smart-216f950e-6ff5-4c6d-bf83-6559a7de1921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156191557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3156191557
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3934435473
Short name T343
Test name
Test status
Simulation time 15416452 ps
CPU time 0.74 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:28 PM PDT 24
Peak memory 205288 kb
Host smart-0d904b8b-74e5-4ae8-96b6-5533a16c60dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934435473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3934435473
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3719066049
Short name T878
Test name
Test status
Simulation time 19465813123 ps
CPU time 162.5 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:06:15 PM PDT 24
Peak memory 250628 kb
Host smart-167bf6ee-2fde-4dcf-b9f7-da6d4c6b81be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719066049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3719066049
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.351896086
Short name T437
Test name
Test status
Simulation time 116879666954 ps
CPU time 254.16 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:07:47 PM PDT 24
Peak memory 249016 kb
Host smart-2eafb568-3060-4086-b063-3386177c31cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351896086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.351896086
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1491087496
Short name T175
Test name
Test status
Simulation time 45946679182 ps
CPU time 208.39 seconds
Started May 12 01:03:31 PM PDT 24
Finished May 12 01:07:00 PM PDT 24
Peak memory 248896 kb
Host smart-9aba8d78-85b6-49d2-a8bb-d65edd903976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491087496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1491087496
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3995838003
Short name T303
Test name
Test status
Simulation time 54114121 ps
CPU time 3.58 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 224248 kb
Host smart-94a4b763-2336-4648-9846-e18c9a91fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995838003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3995838003
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1611079424
Short name T140
Test name
Test status
Simulation time 1699917706 ps
CPU time 4.9 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 218368 kb
Host smart-f893afac-0246-45b1-872a-6228241b823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611079424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1611079424
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3466993220
Short name T733
Test name
Test status
Simulation time 4987271863 ps
CPU time 18 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:03:50 PM PDT 24
Peak memory 240444 kb
Host smart-8d9bfb69-0424-400f-a4e2-080ead356ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466993220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3466993220
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4263535242
Short name T215
Test name
Test status
Simulation time 7018896632 ps
CPU time 9.27 seconds
Started May 12 01:03:30 PM PDT 24
Finished May 12 01:03:39 PM PDT 24
Peak memory 224280 kb
Host smart-cceca121-a91f-4b42-a444-0e7ff21c56ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263535242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4263535242
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3928935306
Short name T718
Test name
Test status
Simulation time 111485855 ps
CPU time 2.39 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 216524 kb
Host smart-c65ee255-fa8c-4d9b-9340-7f0482a97f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928935306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3928935306
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1385192250
Short name T822
Test name
Test status
Simulation time 4588251211 ps
CPU time 10.25 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 219780 kb
Host smart-9773df1c-e086-4ea9-8f94-dcfa9402da56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1385192250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1385192250
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4158850997
Short name T917
Test name
Test status
Simulation time 16860433890 ps
CPU time 30.97 seconds
Started May 12 01:03:30 PM PDT 24
Finished May 12 01:04:01 PM PDT 24
Peak memory 216104 kb
Host smart-1a672cfc-a948-4ecd-aba9-fc866ef67c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158850997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4158850997
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2921925153
Short name T399
Test name
Test status
Simulation time 2849915069 ps
CPU time 12.43 seconds
Started May 12 01:03:27 PM PDT 24
Finished May 12 01:03:40 PM PDT 24
Peak memory 215968 kb
Host smart-56bc183a-a6d7-4aaf-84de-d302e50a225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921925153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2921925153
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2394659880
Short name T409
Test name
Test status
Simulation time 134853057 ps
CPU time 1.82 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:29 PM PDT 24
Peak memory 216132 kb
Host smart-e5d089e8-7a55-4009-a471-30b6aec1fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394659880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2394659880
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2778614957
Short name T768
Test name
Test status
Simulation time 23283774 ps
CPU time 0.74 seconds
Started May 12 01:03:28 PM PDT 24
Finished May 12 01:03:29 PM PDT 24
Peak memory 205596 kb
Host smart-a62003ce-845c-4ae8-9a27-3a420b8496d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778614957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2778614957
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.715852842
Short name T958
Test name
Test status
Simulation time 322277619 ps
CPU time 2.63 seconds
Started May 12 01:03:26 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 224292 kb
Host smart-2784ec35-151c-4e6e-8032-c20a4d177ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715852842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.715852842
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1112114239
Short name T370
Test name
Test status
Simulation time 29801462 ps
CPU time 0.76 seconds
Started May 12 01:01:37 PM PDT 24
Finished May 12 01:01:38 PM PDT 24
Peak memory 205180 kb
Host smart-62342916-2ec2-46f4-afbe-1911765e6468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112114239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
112114239
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1586531563
Short name T825
Test name
Test status
Simulation time 943453250 ps
CPU time 4.16 seconds
Started May 12 01:01:38 PM PDT 24
Finished May 12 01:01:43 PM PDT 24
Peak memory 218884 kb
Host smart-1f8850c5-bef0-4726-a54e-58f42f31898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586531563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1586531563
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1552306109
Short name T527
Test name
Test status
Simulation time 28460404 ps
CPU time 0.74 seconds
Started May 12 01:01:34 PM PDT 24
Finished May 12 01:01:36 PM PDT 24
Peak memory 205744 kb
Host smart-29ba1b9c-c9e2-4c1a-b7d0-0a4d0b75ea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552306109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1552306109
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.870517131
Short name T226
Test name
Test status
Simulation time 2013761102 ps
CPU time 25.58 seconds
Started May 12 01:01:39 PM PDT 24
Finished May 12 01:02:05 PM PDT 24
Peak memory 239056 kb
Host smart-32f13e8e-7e2e-489b-bba5-38abcff31f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870517131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.870517131
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.478483550
Short name T523
Test name
Test status
Simulation time 22821233394 ps
CPU time 209.7 seconds
Started May 12 01:01:38 PM PDT 24
Finished May 12 01:05:08 PM PDT 24
Peak memory 255664 kb
Host smart-a4ce72f4-e4b6-419d-9353-5688b416159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478483550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.478483550
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.326622182
Short name T505
Test name
Test status
Simulation time 18646754159 ps
CPU time 42.25 seconds
Started May 12 01:01:41 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 224284 kb
Host smart-9dcaa69b-6514-4ffd-a465-fcfcd29db562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326622182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
326622182
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2187647432
Short name T132
Test name
Test status
Simulation time 2293119680 ps
CPU time 34.48 seconds
Started May 12 01:01:41 PM PDT 24
Finished May 12 01:02:16 PM PDT 24
Peak memory 240664 kb
Host smart-0c76a75a-56a0-4340-a112-08d1cb6cd2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187647432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2187647432
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.903019509
Short name T895
Test name
Test status
Simulation time 2277867878 ps
CPU time 7.88 seconds
Started May 12 01:01:37 PM PDT 24
Finished May 12 01:01:45 PM PDT 24
Peak memory 218416 kb
Host smart-2c938db2-a59e-472a-b73d-6d688c458673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903019509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.903019509
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2083488659
Short name T419
Test name
Test status
Simulation time 143759378 ps
CPU time 2.97 seconds
Started May 12 01:01:41 PM PDT 24
Finished May 12 01:01:44 PM PDT 24
Peak memory 224228 kb
Host smart-fca8332d-7f6f-4cdb-9c55-2516ae212644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083488659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2083488659
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.530163039
Short name T843
Test name
Test status
Simulation time 3385124458 ps
CPU time 7.03 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:01:43 PM PDT 24
Peak memory 224288 kb
Host smart-dada1953-2270-4a76-953d-1e1ab70c50d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530163039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
530163039
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2427953333
Short name T276
Test name
Test status
Simulation time 721231160 ps
CPU time 4.86 seconds
Started May 12 01:01:34 PM PDT 24
Finished May 12 01:01:39 PM PDT 24
Peak memory 233772 kb
Host smart-b397eb57-d61c-4aab-a6dd-e45fb51f4d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427953333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2427953333
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.356236386
Short name T909
Test name
Test status
Simulation time 16379711522 ps
CPU time 12.55 seconds
Started May 12 01:01:38 PM PDT 24
Finished May 12 01:01:51 PM PDT 24
Peak memory 222596 kb
Host smart-6bf2ead1-2e5b-4d67-93ea-cd9e62712c7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=356236386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.356236386
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3751739033
Short name T67
Test name
Test status
Simulation time 137421215 ps
CPU time 0.97 seconds
Started May 12 01:01:40 PM PDT 24
Finished May 12 01:01:41 PM PDT 24
Peak memory 234676 kb
Host smart-5760a166-3134-4199-9705-0e100e0625e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751739033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3751739033
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2364164145
Short name T46
Test name
Test status
Simulation time 9207182243 ps
CPU time 124.81 seconds
Started May 12 01:01:40 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 253960 kb
Host smart-3c1545ed-0232-440d-be7c-ae01169f6448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364164145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2364164145
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1397701965
Short name T312
Test name
Test status
Simulation time 1078597013 ps
CPU time 13.62 seconds
Started May 12 01:01:35 PM PDT 24
Finished May 12 01:01:49 PM PDT 24
Peak memory 216160 kb
Host smart-89b685ec-d70a-4a65-8fdf-6cf813cbf37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397701965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1397701965
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.375768420
Short name T465
Test name
Test status
Simulation time 34156913 ps
CPU time 0.74 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:01:37 PM PDT 24
Peak memory 205412 kb
Host smart-7945a974-397a-4a01-93f0-d6808ccacea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375768420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.375768420
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1533633167
Short name T783
Test name
Test status
Simulation time 692151978 ps
CPU time 6.3 seconds
Started May 12 01:01:34 PM PDT 24
Finished May 12 01:01:41 PM PDT 24
Peak memory 216060 kb
Host smart-f0568cc9-549b-4bf7-9dbf-689387b5bff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533633167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1533633167
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3843229280
Short name T325
Test name
Test status
Simulation time 19873538 ps
CPU time 0.79 seconds
Started May 12 01:01:36 PM PDT 24
Finished May 12 01:01:37 PM PDT 24
Peak memory 205608 kb
Host smart-dcb59146-db17-4f95-9b2a-56bef27e6b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843229280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3843229280
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2226204443
Short name T483
Test name
Test status
Simulation time 594599370 ps
CPU time 4.38 seconds
Started May 12 01:01:39 PM PDT 24
Finished May 12 01:01:44 PM PDT 24
Peak memory 218916 kb
Host smart-e0ff3928-9053-4a15-ad37-257d8fed51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226204443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2226204443
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.5693336
Short name T394
Test name
Test status
Simulation time 25909988 ps
CPU time 0.7 seconds
Started May 12 01:03:42 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 205124 kb
Host smart-b5d17c3e-3bc5-4192-a0ea-028100c8d294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5693336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.5693336
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3016179434
Short name T727
Test name
Test status
Simulation time 872243944 ps
CPU time 6.27 seconds
Started May 12 01:03:30 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 218508 kb
Host smart-99e45691-a5cf-4c8d-b095-f5333e7fab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016179434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3016179434
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2998071476
Short name T749
Test name
Test status
Simulation time 19738875 ps
CPU time 0.81 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 206340 kb
Host smart-7d0205a0-10f6-46a7-8090-520d8886254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998071476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2998071476
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.699580689
Short name T468
Test name
Test status
Simulation time 20580151683 ps
CPU time 57.19 seconds
Started May 12 01:03:31 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 249164 kb
Host smart-3dd4a56a-cc28-4395-b011-76dec7566b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699580689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.699580689
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3969191317
Short name T129
Test name
Test status
Simulation time 9084658788 ps
CPU time 90.82 seconds
Started May 12 01:03:33 PM PDT 24
Finished May 12 01:05:04 PM PDT 24
Peak memory 233580 kb
Host smart-8644de62-80ed-4b18-bd83-85e5b6b2f323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969191317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3969191317
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1247762730
Short name T237
Test name
Test status
Simulation time 21468539293 ps
CPU time 172.35 seconds
Started May 12 01:03:33 PM PDT 24
Finished May 12 01:06:25 PM PDT 24
Peak memory 249448 kb
Host smart-8f46314c-67c3-42dc-98a0-9be5cdddb889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247762730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1247762730
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3458314982
Short name T842
Test name
Test status
Simulation time 1547911638 ps
CPU time 24.38 seconds
Started May 12 01:03:33 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 240648 kb
Host smart-6d4ef967-b2cc-46d4-ae8b-96c65213c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458314982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3458314982
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.657579207
Short name T451
Test name
Test status
Simulation time 205758353 ps
CPU time 4.36 seconds
Started May 12 01:03:31 PM PDT 24
Finished May 12 01:03:36 PM PDT 24
Peak memory 218468 kb
Host smart-0f54e545-d5e9-4b71-b4e5-ab7703dd4823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657579207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.657579207
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.334144890
Short name T805
Test name
Test status
Simulation time 191822513 ps
CPU time 2.27 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:03:38 PM PDT 24
Peak memory 218328 kb
Host smart-c12e5781-3ac9-4d94-8674-7c5ff86d3c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334144890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.334144890
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1959867647
Short name T245
Test name
Test status
Simulation time 666911811 ps
CPU time 4.44 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 218368 kb
Host smart-4e85bb84-8d3d-43c2-91f7-ed33b7eaee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959867647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1959867647
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3909868950
Short name T280
Test name
Test status
Simulation time 1056335884 ps
CPU time 5.71 seconds
Started May 12 01:03:34 PM PDT 24
Finished May 12 01:03:40 PM PDT 24
Peak memory 218432 kb
Host smart-1ed4aa48-7a17-44ee-aec6-dc72864f0f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909868950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3909868950
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3845473384
Short name T136
Test name
Test status
Simulation time 1347892505 ps
CPU time 12.66 seconds
Started May 12 01:03:31 PM PDT 24
Finished May 12 01:03:44 PM PDT 24
Peak memory 222688 kb
Host smart-16688ebf-249b-4540-88f0-bec43d7146e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3845473384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3845473384
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3430375285
Short name T629
Test name
Test status
Simulation time 12186547116 ps
CPU time 87.56 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:05:00 PM PDT 24
Peak memory 248948 kb
Host smart-2b6550ce-31ae-49cf-8a0c-8ded4a050e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430375285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3430375285
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2980107070
Short name T362
Test name
Test status
Simulation time 1877731913 ps
CPU time 3.82 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 216000 kb
Host smart-3f90ab79-c45a-4736-9f38-6cdb0fb870de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980107070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2980107070
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.397737860
Short name T743
Test name
Test status
Simulation time 11421601473 ps
CPU time 3.77 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:03:39 PM PDT 24
Peak memory 215968 kb
Host smart-37380b56-55d2-4e0b-8595-780200509795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397737860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.397737860
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.70911631
Short name T630
Test name
Test status
Simulation time 38896816 ps
CPU time 1.67 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 216028 kb
Host smart-80037bcb-50ba-43ba-ba5c-90012a588456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70911631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.70911631
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1170658431
Short name T902
Test name
Test status
Simulation time 282666396 ps
CPU time 0.83 seconds
Started May 12 01:03:32 PM PDT 24
Finished May 12 01:03:33 PM PDT 24
Peak memory 205532 kb
Host smart-646bf850-9edf-433c-89b3-a7d3cd2373d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170658431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1170658431
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2730199480
Short name T724
Test name
Test status
Simulation time 505904049 ps
CPU time 8.86 seconds
Started May 12 01:03:33 PM PDT 24
Finished May 12 01:03:42 PM PDT 24
Peak memory 246744 kb
Host smart-09497cb4-65f0-4056-86b4-06390ac6f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730199480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2730199480
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3291727659
Short name T552
Test name
Test status
Simulation time 33981986 ps
CPU time 0.72 seconds
Started May 12 01:03:42 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 204576 kb
Host smart-9c403d37-1b18-4fb7-aaa3-c9327065be17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291727659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3291727659
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.749072465
Short name T205
Test name
Test status
Simulation time 4560141127 ps
CPU time 10.92 seconds
Started May 12 01:03:37 PM PDT 24
Finished May 12 01:03:48 PM PDT 24
Peak memory 233972 kb
Host smart-dab16400-66c3-40f2-bdf0-05e53754942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749072465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.749072465
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.593207915
Short name T599
Test name
Test status
Simulation time 71663703 ps
CPU time 0.83 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:03:37 PM PDT 24
Peak memory 206360 kb
Host smart-bb013a91-2e47-401c-a6fd-98d6d08a6f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593207915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.593207915
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.500707385
Short name T33
Test name
Test status
Simulation time 45625835064 ps
CPU time 338.74 seconds
Started May 12 01:03:37 PM PDT 24
Finished May 12 01:09:16 PM PDT 24
Peak memory 255880 kb
Host smart-7b2f77c6-cfa3-4a3e-82f8-937e6abb1583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500707385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.500707385
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1412686357
Short name T799
Test name
Test status
Simulation time 4745273127 ps
CPU time 29.04 seconds
Started May 12 01:03:36 PM PDT 24
Finished May 12 01:04:05 PM PDT 24
Peak memory 237012 kb
Host smart-9ef24e16-bc68-4ed8-884b-35ab08e82ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412686357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1412686357
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.78135719
Short name T657
Test name
Test status
Simulation time 145270761 ps
CPU time 0.82 seconds
Started May 12 01:03:36 PM PDT 24
Finished May 12 01:03:38 PM PDT 24
Peak memory 217860 kb
Host smart-3cbf0d05-9305-4f5f-a2aa-e65469423608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78135719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.78135719
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3082886942
Short name T307
Test name
Test status
Simulation time 2406940806 ps
CPU time 33.26 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 240644 kb
Host smart-358576d5-9e00-46c2-959c-eb090e41087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082886942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3082886942
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4205224150
Short name T433
Test name
Test status
Simulation time 957918983 ps
CPU time 11.92 seconds
Started May 12 01:03:42 PM PDT 24
Finished May 12 01:03:54 PM PDT 24
Peak memory 233760 kb
Host smart-5710ebe9-f641-4812-8a70-769a5c671b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205224150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4205224150
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.375025921
Short name T199
Test name
Test status
Simulation time 10227335521 ps
CPU time 13.56 seconds
Started May 12 01:03:40 PM PDT 24
Finished May 12 01:03:54 PM PDT 24
Peak memory 234060 kb
Host smart-101851f4-c12f-4770-9db9-5371ece25615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375025921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.375025921
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.185068987
Short name T169
Test name
Test status
Simulation time 12745159359 ps
CPU time 12.09 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:03:47 PM PDT 24
Peak memory 219008 kb
Host smart-deccc8bb-0a4f-4965-bfc7-7fa1484b6f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185068987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.185068987
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3621095811
Short name T533
Test name
Test status
Simulation time 5259708622 ps
CPU time 7.85 seconds
Started May 12 01:03:39 PM PDT 24
Finished May 12 01:03:47 PM PDT 24
Peak memory 218804 kb
Host smart-2e78c117-1d00-45d4-9173-b0c5de2c3168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621095811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3621095811
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3981811304
Short name T424
Test name
Test status
Simulation time 761378776 ps
CPU time 6.03 seconds
Started May 12 01:03:36 PM PDT 24
Finished May 12 01:03:42 PM PDT 24
Peak memory 218648 kb
Host smart-753e34b0-fa94-4ebb-976a-e861415c52ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981811304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3981811304
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1540306883
Short name T125
Test name
Test status
Simulation time 14041903121 ps
CPU time 123.51 seconds
Started May 12 01:03:42 PM PDT 24
Finished May 12 01:05:46 PM PDT 24
Peak memory 256096 kb
Host smart-431d3436-29ab-4287-99ff-698207bab160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540306883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1540306883
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2672518988
Short name T315
Test name
Test status
Simulation time 783154095 ps
CPU time 7.67 seconds
Started May 12 01:03:37 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 216092 kb
Host smart-801c432b-f23d-4905-9a90-a77600e68984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672518988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2672518988
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3885592658
Short name T747
Test name
Test status
Simulation time 876752245 ps
CPU time 4.08 seconds
Started May 12 01:03:36 PM PDT 24
Finished May 12 01:03:41 PM PDT 24
Peak memory 215924 kb
Host smart-3f5e92a1-7651-4e34-90d0-417e75f85fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885592658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3885592658
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2276688930
Short name T392
Test name
Test status
Simulation time 363051913 ps
CPU time 2.96 seconds
Started May 12 01:03:35 PM PDT 24
Finished May 12 01:03:38 PM PDT 24
Peak memory 216024 kb
Host smart-02c45a48-7f5e-4e7b-8238-f020b91c0a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276688930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2276688930
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3884801360
Short name T796
Test name
Test status
Simulation time 57519579 ps
CPU time 0.87 seconds
Started May 12 01:03:38 PM PDT 24
Finished May 12 01:03:39 PM PDT 24
Peak memory 206548 kb
Host smart-f4369c82-d474-41a0-802a-3f65da058111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884801360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3884801360
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2665490645
Short name T862
Test name
Test status
Simulation time 80532805 ps
CPU time 2.92 seconds
Started May 12 01:03:34 PM PDT 24
Finished May 12 01:03:38 PM PDT 24
Peak memory 232692 kb
Host smart-8fe0467e-0238-4dd4-89fd-38486877fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665490645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2665490645
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2634688543
Short name T952
Test name
Test status
Simulation time 50024571 ps
CPU time 0.72 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 204728 kb
Host smart-d5f745a8-7680-4951-92dd-51efc58ede47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634688543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2634688543
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1751072557
Short name T446
Test name
Test status
Simulation time 1812009980 ps
CPU time 9.22 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:51 PM PDT 24
Peak memory 234336 kb
Host smart-01c4c74b-41da-481d-8c04-ca4500b238d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751072557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1751072557
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3527981025
Short name T881
Test name
Test status
Simulation time 49337517 ps
CPU time 0.78 seconds
Started May 12 01:03:40 PM PDT 24
Finished May 12 01:03:41 PM PDT 24
Peak memory 206452 kb
Host smart-59704955-aed1-401a-9914-401fa24ae811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527981025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3527981025
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3341410736
Short name T214
Test name
Test status
Simulation time 9739266229 ps
CPU time 60.47 seconds
Started May 12 01:03:48 PM PDT 24
Finished May 12 01:04:49 PM PDT 24
Peak memory 249204 kb
Host smart-72c1f747-6e17-467a-a833-057db15802fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341410736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3341410736
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.783897706
Short name T567
Test name
Test status
Simulation time 6472017358 ps
CPU time 58.79 seconds
Started May 12 01:03:43 PM PDT 24
Finished May 12 01:04:42 PM PDT 24
Peak memory 251580 kb
Host smart-6e66f146-bf1c-42d1-9fbb-8badfc1f320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783897706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.783897706
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2274489970
Short name T590
Test name
Test status
Simulation time 21147477814 ps
CPU time 100.91 seconds
Started May 12 01:03:43 PM PDT 24
Finished May 12 01:05:25 PM PDT 24
Peak memory 250120 kb
Host smart-e3a96dbd-3d32-40ff-a9df-8d0dac868d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274489970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2274489970
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1996642954
Short name T935
Test name
Test status
Simulation time 140548910 ps
CPU time 6.1 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:48 PM PDT 24
Peak memory 234416 kb
Host smart-78134d41-19a3-4953-af50-56251013b0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996642954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1996642954
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2956398145
Short name T529
Test name
Test status
Simulation time 107631738 ps
CPU time 2.61 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:44 PM PDT 24
Peak memory 233008 kb
Host smart-e9285b61-2f5a-4fa9-bbc9-4b45fc8ad222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956398145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2956398145
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3575447815
Short name T903
Test name
Test status
Simulation time 62730253492 ps
CPU time 88.37 seconds
Started May 12 01:03:47 PM PDT 24
Finished May 12 01:05:16 PM PDT 24
Peak memory 240852 kb
Host smart-a658ab55-8578-4024-9abb-6780283519d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575447815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3575447815
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4003766378
Short name T253
Test name
Test status
Simulation time 27569614539 ps
CPU time 16.46 seconds
Started May 12 01:03:47 PM PDT 24
Finished May 12 01:04:04 PM PDT 24
Peak memory 233712 kb
Host smart-72d91f05-bc3f-4ef2-8d27-e00a8bc85629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003766378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4003766378
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1904537826
Short name T163
Test name
Test status
Simulation time 318824580 ps
CPU time 3.69 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 233596 kb
Host smart-59096203-c7d7-439e-aa94-48d96369187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904537826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1904537826
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4251244900
Short name T938
Test name
Test status
Simulation time 3841442190 ps
CPU time 6.92 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:48 PM PDT 24
Peak memory 222176 kb
Host smart-402404a7-a482-4e6f-a118-a0900ca997b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251244900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4251244900
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.330818568
Short name T908
Test name
Test status
Simulation time 41547467 ps
CPU time 0.9 seconds
Started May 12 01:03:44 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 206384 kb
Host smart-dccbc690-4506-47a0-9b58-b5857643b50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330818568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.330818568
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2092648265
Short name T372
Test name
Test status
Simulation time 3717170336 ps
CPU time 5.15 seconds
Started May 12 01:03:37 PM PDT 24
Finished May 12 01:03:42 PM PDT 24
Peak memory 216064 kb
Host smart-a65786d3-193b-4d9d-b5a5-1f5639c49a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092648265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2092648265
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.994628382
Short name T360
Test name
Test status
Simulation time 3731842841 ps
CPU time 12.82 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:55 PM PDT 24
Peak memory 215976 kb
Host smart-339526f6-4739-4a61-bbdc-1b036596c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994628382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.994628382
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1964917270
Short name T751
Test name
Test status
Simulation time 59597319 ps
CPU time 0.76 seconds
Started May 12 01:03:45 PM PDT 24
Finished May 12 01:03:46 PM PDT 24
Peak memory 205660 kb
Host smart-c83361bd-9781-4377-8ce8-6313097c9bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964917270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1964917270
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1071313151
Short name T791
Test name
Test status
Simulation time 22448824 ps
CPU time 0.78 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 205576 kb
Host smart-bdab67ec-4623-4d6b-9342-18a02c8f19d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071313151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1071313151
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3139167355
Short name T50
Test name
Test status
Simulation time 28662089555 ps
CPU time 9.92 seconds
Started May 12 01:03:43 PM PDT 24
Finished May 12 01:03:54 PM PDT 24
Peak memory 219272 kb
Host smart-15e8d9e8-4fa3-45ff-aea2-79964016bf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139167355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3139167355
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2492094898
Short name T628
Test name
Test status
Simulation time 41720857 ps
CPU time 0.74 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:03:47 PM PDT 24
Peak memory 205568 kb
Host smart-01f22b46-3242-4741-9346-ed1b3bd67c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492094898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2492094898
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.131718593
Short name T886
Test name
Test status
Simulation time 1696524040 ps
CPU time 10.2 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:04:04 PM PDT 24
Peak memory 218332 kb
Host smart-b43fd374-56ec-4bc4-a359-3e6bc02fc309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131718593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.131718593
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1557822135
Short name T506
Test name
Test status
Simulation time 39494771 ps
CPU time 0.73 seconds
Started May 12 01:03:43 PM PDT 24
Finished May 12 01:03:45 PM PDT 24
Peak memory 205620 kb
Host smart-07c0f92c-1136-4563-b6ea-943b1c029281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557822135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1557822135
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1139318137
Short name T897
Test name
Test status
Simulation time 14885444573 ps
CPU time 22.17 seconds
Started May 12 01:03:52 PM PDT 24
Finished May 12 01:04:16 PM PDT 24
Peak memory 250808 kb
Host smart-4ed951fb-8e5e-4557-b844-6695767d6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139318137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1139318137
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3201635137
Short name T5
Test name
Test status
Simulation time 12266922079 ps
CPU time 64.38 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:04:51 PM PDT 24
Peak memory 252432 kb
Host smart-0b50e9c7-d3c0-434e-a7db-62dd06f63b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201635137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3201635137
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.549781115
Short name T911
Test name
Test status
Simulation time 3531671791 ps
CPU time 57.77 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:04:52 PM PDT 24
Peak memory 224320 kb
Host smart-532d1a9b-2658-4c35-bb5c-30df74458df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549781115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.549781115
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2106360668
Short name T773
Test name
Test status
Simulation time 4087725083 ps
CPU time 8.09 seconds
Started May 12 01:03:48 PM PDT 24
Finished May 12 01:03:56 PM PDT 24
Peak memory 218592 kb
Host smart-2ff5b31b-6f95-4575-a497-4520fa540cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106360668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2106360668
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4152113122
Short name T680
Test name
Test status
Simulation time 20090788055 ps
CPU time 15.5 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:04:02 PM PDT 24
Peak memory 223476 kb
Host smart-771630eb-b6f3-4ddf-82bd-f8f2ce8b69cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152113122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4152113122
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.800846750
Short name T937
Test name
Test status
Simulation time 16163269137 ps
CPU time 16.48 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:04:03 PM PDT 24
Peak memory 220624 kb
Host smart-0df39f14-a537-4a6a-9610-4b03a19a3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800846750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.800846750
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.811102359
Short name T171
Test name
Test status
Simulation time 156765971 ps
CPU time 3.19 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:03:50 PM PDT 24
Peak memory 233512 kb
Host smart-0f0f952c-2b94-43b7-a031-7176e8938160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811102359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.811102359
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1059269130
Short name T388
Test name
Test status
Simulation time 1180908051 ps
CPU time 17.97 seconds
Started May 12 01:03:52 PM PDT 24
Finished May 12 01:04:11 PM PDT 24
Peak memory 219964 kb
Host smart-91f10191-57f2-42d4-9493-44a27690578b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1059269130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1059269130
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2153831196
Short name T469
Test name
Test status
Simulation time 3374890141 ps
CPU time 42.89 seconds
Started May 12 01:03:47 PM PDT 24
Finished May 12 01:04:31 PM PDT 24
Peak memory 248980 kb
Host smart-65b179a3-036e-4055-9208-adc95a2fbfbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153831196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2153831196
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1767196958
Short name T564
Test name
Test status
Simulation time 3499854138 ps
CPU time 27.06 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 216128 kb
Host smart-52930f17-f15d-435c-ab4b-5040b0f3cd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767196958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1767196958
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2910627558
Short name T915
Test name
Test status
Simulation time 27253874359 ps
CPU time 17.78 seconds
Started May 12 01:03:41 PM PDT 24
Finished May 12 01:03:59 PM PDT 24
Peak memory 216120 kb
Host smart-29cd80bb-8e89-4d35-8805-970b48c18864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910627558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2910627558
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.19668827
Short name T553
Test name
Test status
Simulation time 62913515 ps
CPU time 0.94 seconds
Started May 12 01:03:45 PM PDT 24
Finished May 12 01:03:47 PM PDT 24
Peak memory 207052 kb
Host smart-c3f35581-5170-4716-893e-739e18918c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19668827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.19668827
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1490377854
Short name T543
Test name
Test status
Simulation time 104347259 ps
CPU time 0.78 seconds
Started May 12 01:03:42 PM PDT 24
Finished May 12 01:03:43 PM PDT 24
Peak memory 205608 kb
Host smart-3dfceb19-2d5d-4e72-8025-7bea63ca078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490377854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1490377854
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3857503219
Short name T752
Test name
Test status
Simulation time 29332718 ps
CPU time 0.7 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:03:55 PM PDT 24
Peak memory 204600 kb
Host smart-c4ef1c40-775c-4851-8b5a-6e587e48744d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857503219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3857503219
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2336698683
Short name T795
Test name
Test status
Simulation time 82997109 ps
CPU time 2.74 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:03:59 PM PDT 24
Peak memory 217568 kb
Host smart-251d3c07-960e-48b7-a0ae-ffd0a92afc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336698683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2336698683
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2767629169
Short name T397
Test name
Test status
Simulation time 15826249 ps
CPU time 0.79 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:03:54 PM PDT 24
Peak memory 205304 kb
Host smart-0b21a541-77bc-44f3-9503-8028933176bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767629169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2767629169
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.945291307
Short name T956
Test name
Test status
Simulation time 95170681670 ps
CPU time 192.39 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:07:07 PM PDT 24
Peak memory 249012 kb
Host smart-9db5886b-4fec-48b1-9dbc-75d0fb8f047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945291307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.945291307
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3847095163
Short name T71
Test name
Test status
Simulation time 342210863864 ps
CPU time 285.04 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:08:39 PM PDT 24
Peak memory 257168 kb
Host smart-8ee6a48c-d6db-4f99-bfa6-c7a85bef841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847095163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3847095163
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1628344588
Short name T535
Test name
Test status
Simulation time 100881012 ps
CPU time 0.85 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:03:57 PM PDT 24
Peak memory 216608 kb
Host smart-b685fb1a-9cd4-451f-a14e-cf35ea76dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628344588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1628344588
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3742606763
Short name T440
Test name
Test status
Simulation time 381151139 ps
CPU time 2.44 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:03:57 PM PDT 24
Peak memory 218708 kb
Host smart-cb00dbef-054c-4fdc-bac3-207424162273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742606763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3742606763
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3497601764
Short name T780
Test name
Test status
Simulation time 204373013 ps
CPU time 4.5 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:03:51 PM PDT 24
Peak memory 233036 kb
Host smart-ab321c16-7238-4857-9f3c-bc032a0c08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497601764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3497601764
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3320060807
Short name T84
Test name
Test status
Simulation time 3654695783 ps
CPU time 33.45 seconds
Started May 12 01:03:45 PM PDT 24
Finished May 12 01:04:19 PM PDT 24
Peak memory 227096 kb
Host smart-99385e17-5369-413b-a28a-c4bab8bc37f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320060807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3320060807
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.767937772
Short name T121
Test name
Test status
Simulation time 333782361 ps
CPU time 2.52 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:03:57 PM PDT 24
Peak memory 216508 kb
Host smart-d7b75228-ee06-422a-ae80-131dfe4f0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767937772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.767937772
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3486426478
Short name T707
Test name
Test status
Simulation time 2508873207 ps
CPU time 7.85 seconds
Started May 12 01:03:48 PM PDT 24
Finished May 12 01:03:56 PM PDT 24
Peak memory 236516 kb
Host smart-9313ff52-f88c-43c5-9bfc-ad7319e51fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486426478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3486426478
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.13133294
Short name T540
Test name
Test status
Simulation time 456874722 ps
CPU time 3.69 seconds
Started May 12 01:03:51 PM PDT 24
Finished May 12 01:03:55 PM PDT 24
Peak memory 222880 kb
Host smart-f7bd638a-aabb-43ce-bb8b-d7b621440f91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13133294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.13133294
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.323688805
Short name T311
Test name
Test status
Simulation time 9732437786 ps
CPU time 24.56 seconds
Started May 12 01:03:52 PM PDT 24
Finished May 12 01:04:18 PM PDT 24
Peak memory 217212 kb
Host smart-55555101-9154-4a1d-acd3-2a5b3f518f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323688805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.323688805
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.65993509
Short name T42
Test name
Test status
Simulation time 10367062819 ps
CPU time 4.42 seconds
Started May 12 01:03:47 PM PDT 24
Finished May 12 01:03:52 PM PDT 24
Peak memory 216024 kb
Host smart-5526c2f4-ec91-437f-aa4b-b0f1473fd719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65993509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.65993509
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3091719142
Short name T728
Test name
Test status
Simulation time 201825391 ps
CPU time 1.56 seconds
Started May 12 01:03:47 PM PDT 24
Finished May 12 01:03:49 PM PDT 24
Peak memory 207804 kb
Host smart-80b1e16c-3bea-4078-bad7-49d9926be2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091719142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3091719142
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3593801324
Short name T352
Test name
Test status
Simulation time 146743965 ps
CPU time 0.87 seconds
Started May 12 01:03:46 PM PDT 24
Finished May 12 01:03:48 PM PDT 24
Peak memory 205560 kb
Host smart-42992dc5-c25c-445a-8385-140f0150cc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593801324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3593801324
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1771691206
Short name T586
Test name
Test status
Simulation time 4707714310 ps
CPU time 21.25 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:04:15 PM PDT 24
Peak memory 240656 kb
Host smart-305eb46b-8fee-493b-a310-3fa1df82017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771691206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1771691206
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3043277105
Short name T536
Test name
Test status
Simulation time 13124646 ps
CPU time 0.71 seconds
Started May 12 01:03:59 PM PDT 24
Finished May 12 01:04:00 PM PDT 24
Peak memory 204680 kb
Host smart-0a98c643-67ea-4b1d-9f02-0ef3ed841fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043277105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3043277105
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2371513725
Short name T851
Test name
Test status
Simulation time 147074370 ps
CPU time 2.57 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 218288 kb
Host smart-b310afd8-f3d5-4659-b0bd-cbd6d3f7dc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371513725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2371513725
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1600830395
Short name T331
Test name
Test status
Simulation time 57292240 ps
CPU time 0.77 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 206340 kb
Host smart-1801d954-7b4f-41b0-bf9c-fc01a90ff845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600830395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1600830395
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4079907650
Short name T778
Test name
Test status
Simulation time 11210822021 ps
CPU time 78.47 seconds
Started May 12 01:03:54 PM PDT 24
Finished May 12 01:05:14 PM PDT 24
Peak memory 233056 kb
Host smart-71accf57-0159-494c-a791-2fede0753134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079907650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4079907650
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.52492866
Short name T649
Test name
Test status
Simulation time 7082582365 ps
CPU time 42.3 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:04:38 PM PDT 24
Peak memory 252280 kb
Host smart-4b81c48f-8c42-4521-bc6e-a21900d82b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52492866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.52492866
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1545423180
Short name T770
Test name
Test status
Simulation time 13807017332 ps
CPU time 48.95 seconds
Started May 12 01:03:58 PM PDT 24
Finished May 12 01:04:47 PM PDT 24
Peak memory 249024 kb
Host smart-c8cf1b59-3c81-4647-b89e-0ff6937c2a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545423180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1545423180
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3079939448
Short name T672
Test name
Test status
Simulation time 3858288602 ps
CPU time 62.9 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:04:59 PM PDT 24
Peak memory 232456 kb
Host smart-85a9e88b-9e1b-44ef-9950-091d715b4939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079939448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3079939448
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3165382940
Short name T690
Test name
Test status
Simulation time 1231506126 ps
CPU time 5.26 seconds
Started May 12 01:03:52 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 235896 kb
Host smart-8d3ddef6-c827-4ebc-a62d-2ef7a4ecbeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165382940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3165382940
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3269834088
Short name T879
Test name
Test status
Simulation time 6902195333 ps
CPU time 73.57 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:05:11 PM PDT 24
Peak memory 228600 kb
Host smart-a9a2dba1-bc75-41f1-b112-12b7419bd9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269834088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3269834088
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3678371828
Short name T922
Test name
Test status
Simulation time 2451094404 ps
CPU time 10.42 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:04:07 PM PDT 24
Peak memory 225520 kb
Host smart-0c193831-81c3-4725-add8-fdbf80ad68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678371828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3678371828
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3308973245
Short name T323
Test name
Test status
Simulation time 31833948 ps
CPU time 2.2 seconds
Started May 12 01:03:54 PM PDT 24
Finished May 12 01:03:57 PM PDT 24
Peak memory 221440 kb
Host smart-3a5a8668-c2bc-475d-a1b1-c89fc74d8ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308973245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3308973245
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.134833378
Short name T817
Test name
Test status
Simulation time 143190798 ps
CPU time 3.91 seconds
Started May 12 01:03:54 PM PDT 24
Finished May 12 01:03:59 PM PDT 24
Peak memory 222620 kb
Host smart-5042a315-37e9-4c85-9b71-cde2b1904624
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=134833378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.134833378
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2734208368
Short name T948
Test name
Test status
Simulation time 67398471924 ps
CPU time 630.04 seconds
Started May 12 01:04:03 PM PDT 24
Finished May 12 01:14:34 PM PDT 24
Peak memory 265468 kb
Host smart-551f5719-2481-4ec0-a916-aa4bb91b58ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734208368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2734208368
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3964972721
Short name T815
Test name
Test status
Simulation time 28423916 ps
CPU time 0.73 seconds
Started May 12 01:03:54 PM PDT 24
Finished May 12 01:03:56 PM PDT 24
Peak memory 205424 kb
Host smart-a2ef5f73-315d-4bc2-b609-752c6ef047b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964972721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3964972721
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3127509542
Short name T379
Test name
Test status
Simulation time 96175716 ps
CPU time 0.73 seconds
Started May 12 01:03:51 PM PDT 24
Finished May 12 01:03:52 PM PDT 24
Peak memory 205432 kb
Host smart-224c2254-a410-4720-be01-abdd470088a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127509542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3127509542
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.54574768
Short name T351
Test name
Test status
Simulation time 65801051 ps
CPU time 2.94 seconds
Started May 12 01:03:53 PM PDT 24
Finished May 12 01:03:57 PM PDT 24
Peak memory 216120 kb
Host smart-efa6a903-f1f7-4b1d-8f42-faf9f2bdd203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54574768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.54574768
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2609881754
Short name T444
Test name
Test status
Simulation time 31381754 ps
CPU time 0.84 seconds
Started May 12 01:03:52 PM PDT 24
Finished May 12 01:03:54 PM PDT 24
Peak memory 205544 kb
Host smart-3f3beb12-b806-4e85-b817-5f0be32370d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609881754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2609881754
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.293135518
Short name T415
Test name
Test status
Simulation time 192633815 ps
CPU time 3.2 seconds
Started May 12 01:03:54 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 224228 kb
Host smart-d056c2cb-158e-4bca-862b-aaf0414e1e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293135518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.293135518
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2510477843
Short name T395
Test name
Test status
Simulation time 55088009 ps
CPU time 0.74 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:04:01 PM PDT 24
Peak memory 205188 kb
Host smart-3d4ca435-46b1-4706-a6b5-396d295c1ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510477843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2510477843
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2295126024
Short name T106
Test name
Test status
Simulation time 637040762 ps
CPU time 4.48 seconds
Started May 12 01:04:03 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 233856 kb
Host smart-edca3c5d-8cd1-41f6-8a1d-53785f0bfaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295126024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2295126024
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3363610939
Short name T546
Test name
Test status
Simulation time 28700416 ps
CPU time 0.79 seconds
Started May 12 01:03:57 PM PDT 24
Finished May 12 01:03:59 PM PDT 24
Peak memory 206608 kb
Host smart-a9c3d0ec-1d48-47bb-aca0-f90d711e9916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363610939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3363610939
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3063951268
Short name T874
Test name
Test status
Simulation time 31573929509 ps
CPU time 52.45 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:04:50 PM PDT 24
Peak memory 235792 kb
Host smart-a1ad80b9-7714-46c8-9fc3-d033b75b8a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063951268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3063951268
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1229798967
Short name T183
Test name
Test status
Simulation time 7251487681 ps
CPU time 146.65 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:06:28 PM PDT 24
Peak memory 249108 kb
Host smart-694b311c-2539-4fdc-bdb6-098ae372f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229798967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1229798967
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3109335403
Short name T223
Test name
Test status
Simulation time 37661319347 ps
CPU time 377.18 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:10:19 PM PDT 24
Peak memory 240872 kb
Host smart-80423250-0376-44c9-a109-2d46d66fc3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109335403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3109335403
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3439687971
Short name T53
Test name
Test status
Simulation time 524581909 ps
CPU time 4.85 seconds
Started May 12 01:03:57 PM PDT 24
Finished May 12 01:04:02 PM PDT 24
Peak memory 240588 kb
Host smart-19b1db7a-1203-4326-b189-6e1e96e37001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439687971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3439687971
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.568844198
Short name T198
Test name
Test status
Simulation time 2856581406 ps
CPU time 4.9 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:04:02 PM PDT 24
Peak memory 219216 kb
Host smart-fcc0020f-c7a1-4e6f-a2b5-36d88a245e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568844198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.568844198
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2727581203
Short name T613
Test name
Test status
Simulation time 3719160206 ps
CPU time 9.62 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:04:06 PM PDT 24
Peak memory 233144 kb
Host smart-cf2c1c8a-0e8e-4c77-82b6-685f450646c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727581203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2727581203
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1050733440
Short name T760
Test name
Test status
Simulation time 22931687111 ps
CPU time 25.46 seconds
Started May 12 01:03:57 PM PDT 24
Finished May 12 01:04:23 PM PDT 24
Peak memory 230528 kb
Host smart-039f673d-56f7-48b7-86a4-dde58d0bf25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050733440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1050733440
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1180418109
Short name T547
Test name
Test status
Simulation time 89114893566 ps
CPU time 14.28 seconds
Started May 12 01:03:59 PM PDT 24
Finished May 12 01:04:13 PM PDT 24
Peak memory 240756 kb
Host smart-24ead885-c3f2-42d3-ad7d-29d75d3fd06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180418109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1180418109
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1084768735
Short name T548
Test name
Test status
Simulation time 166545136 ps
CPU time 4.17 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:04:01 PM PDT 24
Peak memory 222276 kb
Host smart-53e31604-8f89-4581-a384-8df358228fc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1084768735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1084768735
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3380762773
Short name T421
Test name
Test status
Simulation time 90952983 ps
CPU time 1.1 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:03 PM PDT 24
Peak memory 206636 kb
Host smart-906a97a7-defb-4f14-a7ec-401c4603276f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380762773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3380762773
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3905485587
Short name T866
Test name
Test status
Simulation time 35042401 ps
CPU time 0.7 seconds
Started May 12 01:03:57 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 205408 kb
Host smart-fa419e02-2328-4dd2-b46a-812db5c293b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905485587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3905485587
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3813675849
Short name T725
Test name
Test status
Simulation time 2759004843 ps
CPU time 6.16 seconds
Started May 12 01:03:55 PM PDT 24
Finished May 12 01:04:02 PM PDT 24
Peak memory 216068 kb
Host smart-f6da4561-6a83-4fb4-b4ce-a2a1f14f69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813675849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3813675849
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2439419332
Short name T338
Test name
Test status
Simulation time 112966582 ps
CPU time 1.3 seconds
Started May 12 01:04:03 PM PDT 24
Finished May 12 01:04:05 PM PDT 24
Peak memory 207804 kb
Host smart-46ad5486-99a4-49ba-ae5a-f92b4bd6dbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439419332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2439419332
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1724744310
Short name T6
Test name
Test status
Simulation time 18850999 ps
CPU time 0.71 seconds
Started May 12 01:03:56 PM PDT 24
Finished May 12 01:03:58 PM PDT 24
Peak memory 205524 kb
Host smart-b8630ad1-59d2-4ebc-a9bd-fc69326de405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724744310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1724744310
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1738335038
Short name T284
Test name
Test status
Simulation time 2903964854 ps
CPU time 12.33 seconds
Started May 12 01:03:57 PM PDT 24
Finished May 12 01:04:10 PM PDT 24
Peak memory 220772 kb
Host smart-be5f3f12-1be2-4a14-ac6a-c90cd24e40e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738335038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1738335038
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4045552446
Short name T603
Test name
Test status
Simulation time 13825151 ps
CPU time 0.82 seconds
Started May 12 01:04:04 PM PDT 24
Finished May 12 01:04:05 PM PDT 24
Peak memory 205452 kb
Host smart-849fbb16-d2c5-48de-91af-eaa87969fd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045552446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4045552446
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.902010029
Short name T292
Test name
Test status
Simulation time 35981849 ps
CPU time 2.34 seconds
Started May 12 01:04:02 PM PDT 24
Finished May 12 01:04:05 PM PDT 24
Peak memory 232712 kb
Host smart-47af3c6f-5f95-4656-b151-667f2c2693e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902010029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.902010029
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1592514667
Short name T10
Test name
Test status
Simulation time 28630940 ps
CPU time 0.78 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:02 PM PDT 24
Peak memory 205384 kb
Host smart-c0967b7b-f9cd-465b-a20d-90be36548a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592514667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1592514667
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.860023059
Short name T850
Test name
Test status
Simulation time 25055897193 ps
CPU time 57.1 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:59 PM PDT 24
Peak memory 248908 kb
Host smart-70229387-6be3-47cf-9116-7020fceda28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860023059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.860023059
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4193938590
Short name T231
Test name
Test status
Simulation time 38673509068 ps
CPU time 325.85 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:09:27 PM PDT 24
Peak memory 248992 kb
Host smart-64a8d1b2-e739-46b2-acd3-559c2a286c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193938590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4193938590
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.60143287
Short name T267
Test name
Test status
Simulation time 12391411892 ps
CPU time 129.36 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:06:11 PM PDT 24
Peak memory 249008 kb
Host smart-537d6d12-d8ce-4ec2-8100-007d7699934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60143287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.60143287
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2308961721
Short name T575
Test name
Test status
Simulation time 772659474 ps
CPU time 16.02 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:17 PM PDT 24
Peak memory 248896 kb
Host smart-b78728e5-9883-4253-a5cd-dd6267503992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308961721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2308961721
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3934962932
Short name T271
Test name
Test status
Simulation time 18229322717 ps
CPU time 24.15 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 238016 kb
Host smart-1ac43b8b-8d8a-408c-848a-3d3d02b15227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934962932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3934962932
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.256061974
Short name T179
Test name
Test status
Simulation time 1920140446 ps
CPU time 5.87 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:04:07 PM PDT 24
Peak memory 218616 kb
Host smart-ae7dff4d-5d6e-4f33-95fc-6aa24cc7f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256061974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.256061974
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4055087417
Short name T861
Test name
Test status
Simulation time 9083459611 ps
CPU time 24.21 seconds
Started May 12 01:04:02 PM PDT 24
Finished May 12 01:04:27 PM PDT 24
Peak memory 233552 kb
Host smart-cbc5fc2a-cee0-4e46-9a98-6d4e1c2582e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055087417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4055087417
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3759197818
Short name T697
Test name
Test status
Simulation time 205566870 ps
CPU time 2.16 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:04:03 PM PDT 24
Peak memory 215864 kb
Host smart-5f85d818-9424-421c-a0a6-8e74e47f8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759197818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3759197818
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1865581240
Short name T776
Test name
Test status
Simulation time 1787529996 ps
CPU time 18.56 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:04:20 PM PDT 24
Peak memory 221992 kb
Host smart-33b3404e-3b81-4f88-af40-c6d506a3f1d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1865581240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1865581240
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4113327698
Short name T64
Test name
Test status
Simulation time 4482451273 ps
CPU time 18.09 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:20 PM PDT 24
Peak memory 224416 kb
Host smart-1d5fb025-cc61-4366-9dff-0bf8281eb72c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113327698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4113327698
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3719316361
Short name T942
Test name
Test status
Simulation time 10217483516 ps
CPU time 12.4 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:15 PM PDT 24
Peak memory 216108 kb
Host smart-e7c822d6-7897-4fc6-9db1-1431aa6c7fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719316361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3719316361
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.371547825
Short name T755
Test name
Test status
Simulation time 19131030323 ps
CPU time 5.29 seconds
Started May 12 01:04:02 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 216324 kb
Host smart-f3f9ce76-e159-4afa-890e-c16a773f625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371547825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.371547825
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.306498998
Short name T653
Test name
Test status
Simulation time 573330077 ps
CPU time 4.13 seconds
Started May 12 01:04:01 PM PDT 24
Finished May 12 01:04:06 PM PDT 24
Peak memory 215988 kb
Host smart-b9d02784-9e8d-47d0-9db0-e1e3be349296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306498998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.306498998
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2101946289
Short name T453
Test name
Test status
Simulation time 94554244 ps
CPU time 0.98 seconds
Started May 12 01:04:00 PM PDT 24
Finished May 12 01:04:02 PM PDT 24
Peak memory 205576 kb
Host smart-a55da0ef-d67d-40b2-9d96-7d4a482390d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101946289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2101946289
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.122378225
Short name T49
Test name
Test status
Simulation time 3775183851 ps
CPU time 10.33 seconds
Started May 12 01:03:58 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 224352 kb
Host smart-2a8945e3-5c2c-4147-9afb-90ff085482a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122378225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.122378225
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.65350317
Short name T759
Test name
Test status
Simulation time 39975099 ps
CPU time 0.76 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 204644 kb
Host smart-0dd486ef-9a49-4997-afad-097a1c4ad520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65350317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.65350317
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.391425140
Short name T442
Test name
Test status
Simulation time 326402102 ps
CPU time 3.13 seconds
Started May 12 01:04:08 PM PDT 24
Finished May 12 01:04:12 PM PDT 24
Peak memory 219320 kb
Host smart-dc56376b-271a-4bfa-be08-f6d274f7f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391425140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.391425140
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.463978816
Short name T339
Test name
Test status
Simulation time 54498764 ps
CPU time 0.78 seconds
Started May 12 01:04:09 PM PDT 24
Finished May 12 01:04:10 PM PDT 24
Peak memory 206336 kb
Host smart-d0fe197e-1ac0-4941-a9f9-baf7ba8235d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463978816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.463978816
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.471717834
Short name T361
Test name
Test status
Simulation time 583515865 ps
CPU time 11.99 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:20 PM PDT 24
Peak memory 232492 kb
Host smart-6e496cda-7a40-4ec4-abae-9fa764e648ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471717834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.471717834
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4075268228
Short name T456
Test name
Test status
Simulation time 1516433977 ps
CPU time 15.26 seconds
Started May 12 01:04:08 PM PDT 24
Finished May 12 01:04:24 PM PDT 24
Peak memory 218324 kb
Host smart-402075d6-d456-4d04-a0a2-d7293f247380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075268228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4075268228
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1801952963
Short name T767
Test name
Test status
Simulation time 5623208906 ps
CPU time 24.42 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:32 PM PDT 24
Peak memory 222700 kb
Host smart-95d57a6d-2d69-4449-b6fe-ee85cfd2c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801952963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1801952963
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1762424091
Short name T829
Test name
Test status
Simulation time 752068731 ps
CPU time 4.16 seconds
Started May 12 01:04:04 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 234936 kb
Host smart-c2429ee8-11d9-4d71-90af-b85f6a1e8f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762424091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1762424091
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2834163064
Short name T288
Test name
Test status
Simulation time 125177411 ps
CPU time 2.54 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 233464 kb
Host smart-5ef29a61-9f72-4e7b-a907-069d4e2cd930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834163064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2834163064
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3899316826
Short name T845
Test name
Test status
Simulation time 74447974 ps
CPU time 3.64 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 221852 kb
Host smart-1761c61a-0466-4874-b235-fa702d099dfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899316826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3899316826
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.501036941
Short name T160
Test name
Test status
Simulation time 58360226 ps
CPU time 0.92 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 206728 kb
Host smart-901c36d8-8a02-4747-a887-e57d07f527be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501036941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.501036941
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2859736658
Short name T474
Test name
Test status
Simulation time 4606141465 ps
CPU time 21.74 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 216244 kb
Host smart-6f271bff-0c8b-4679-a9af-a5de7fab2a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859736658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2859736658
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.901446496
Short name T420
Test name
Test status
Simulation time 2464279987 ps
CPU time 3.65 seconds
Started May 12 01:04:04 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 216100 kb
Host smart-69e2fc03-c372-4fe8-b1bd-8f68e74ec38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901446496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.901446496
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2361483474
Short name T794
Test name
Test status
Simulation time 28734620 ps
CPU time 0.78 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:04:06 PM PDT 24
Peak memory 205756 kb
Host smart-2e633fc5-2647-41d6-a054-77dce765abcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361483474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2361483474
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2616478543
Short name T933
Test name
Test status
Simulation time 35803641 ps
CPU time 0.77 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 205644 kb
Host smart-4045ffe1-622d-49f7-9e45-ef20bae9ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616478543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2616478543
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2073850671
Short name T559
Test name
Test status
Simulation time 4851539910 ps
CPU time 10.23 seconds
Started May 12 01:04:04 PM PDT 24
Finished May 12 01:04:15 PM PDT 24
Peak memory 233756 kb
Host smart-ac8186c8-5e13-4694-8247-0ad9dada6045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073850671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2073850671
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2166036956
Short name T522
Test name
Test status
Simulation time 22845659 ps
CPU time 0.74 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:22 PM PDT 24
Peak memory 205068 kb
Host smart-0c5afd97-204d-490f-9388-a51247e2c11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166036956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2166036956
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1371864602
Short name T123
Test name
Test status
Simulation time 543980727 ps
CPU time 4.3 seconds
Started May 12 01:04:10 PM PDT 24
Finished May 12 01:04:15 PM PDT 24
Peak memory 233536 kb
Host smart-58e53d15-27db-4364-8897-0d2f426091a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371864602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1371864602
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1533467021
Short name T407
Test name
Test status
Simulation time 41618173 ps
CPU time 0.79 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 205252 kb
Host smart-7d86264e-5a39-4bd5-89f2-a7f36f0b6978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533467021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1533467021
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.974298635
Short name T278
Test name
Test status
Simulation time 17863070814 ps
CPU time 140.31 seconds
Started May 12 01:04:11 PM PDT 24
Finished May 12 01:06:32 PM PDT 24
Peak memory 248872 kb
Host smart-a72d36a8-51ba-4596-a40a-bf9185d13d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974298635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.974298635
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4082438240
Short name T608
Test name
Test status
Simulation time 11167311350 ps
CPU time 93.57 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:05:55 PM PDT 24
Peak memory 232968 kb
Host smart-c9c269fd-1d82-493b-9781-9ff5008059e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082438240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4082438240
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3962268447
Short name T250
Test name
Test status
Simulation time 42877839198 ps
CPU time 131.19 seconds
Started May 12 01:04:09 PM PDT 24
Finished May 12 01:06:21 PM PDT 24
Peak memory 256312 kb
Host smart-67640901-b3f0-41da-bb70-29933be31e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962268447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3962268447
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2040462832
Short name T398
Test name
Test status
Simulation time 4123418835 ps
CPU time 56.23 seconds
Started May 12 01:04:11 PM PDT 24
Finished May 12 01:05:08 PM PDT 24
Peak memory 242064 kb
Host smart-00b0f661-fcb6-4f07-9311-3773dc018f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040462832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2040462832
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1931534874
Short name T856
Test name
Test status
Simulation time 109789353 ps
CPU time 4.2 seconds
Started May 12 01:04:06 PM PDT 24
Finished May 12 01:04:11 PM PDT 24
Peak memory 233312 kb
Host smart-4783c389-55ff-4681-a454-d98163a14170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931534874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1931534874
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3455742783
Short name T682
Test name
Test status
Simulation time 1054924062 ps
CPU time 13.96 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:21 PM PDT 24
Peak memory 234832 kb
Host smart-2b25c5a8-63df-4afb-90e6-3f72765c7ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455742783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3455742783
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.675785427
Short name T3
Test name
Test status
Simulation time 103403890 ps
CPU time 2.81 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 233740 kb
Host smart-154b840a-4d4d-4220-984c-007cc38863dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675785427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.675785427
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.587485356
Short name T422
Test name
Test status
Simulation time 650002269 ps
CPU time 6.99 seconds
Started May 12 01:04:09 PM PDT 24
Finished May 12 01:04:16 PM PDT 24
Peak memory 234144 kb
Host smart-6514a66a-29f7-4a78-9c0f-87b75e42cf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587485356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.587485356
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3091031831
Short name T876
Test name
Test status
Simulation time 405936021 ps
CPU time 5.26 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:25 PM PDT 24
Peak memory 222332 kb
Host smart-331421db-f9d5-4077-836c-6c3814862fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091031831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3091031831
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1766367554
Short name T928
Test name
Test status
Simulation time 43534551758 ps
CPU time 153.77 seconds
Started May 12 01:04:12 PM PDT 24
Finished May 12 01:06:46 PM PDT 24
Peak memory 256420 kb
Host smart-c0ee041d-30c3-4925-b565-fc5d06986ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766367554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1766367554
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4030136042
Short name T389
Test name
Test status
Simulation time 1914546041 ps
CPU time 11.6 seconds
Started May 12 01:04:06 PM PDT 24
Finished May 12 01:04:18 PM PDT 24
Peak memory 216052 kb
Host smart-8c3fae1b-b4f8-43e7-8408-506279233fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030136042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4030136042
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2510333792
Short name T585
Test name
Test status
Simulation time 16664952515 ps
CPU time 6.15 seconds
Started May 12 01:04:05 PM PDT 24
Finished May 12 01:04:12 PM PDT 24
Peak memory 216016 kb
Host smart-135c69a5-1081-4c2f-832f-95a362c56845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510333792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2510333792
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.585450536
Short name T439
Test name
Test status
Simulation time 1565999856 ps
CPU time 3.39 seconds
Started May 12 01:04:07 PM PDT 24
Finished May 12 01:04:11 PM PDT 24
Peak memory 216008 kb
Host smart-c49f3144-124a-4739-a70c-1a3921fffb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585450536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.585450536
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3900278228
Short name T677
Test name
Test status
Simulation time 67686156 ps
CPU time 0.92 seconds
Started May 12 01:04:06 PM PDT 24
Finished May 12 01:04:08 PM PDT 24
Peak memory 205544 kb
Host smart-c919abb9-0f27-4083-9363-e47d5215142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900278228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3900278228
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3042235165
Short name T637
Test name
Test status
Simulation time 6924075920 ps
CPU time 8.64 seconds
Started May 12 01:04:04 PM PDT 24
Finished May 12 01:04:14 PM PDT 24
Peak memory 219452 kb
Host smart-935e5b13-2bad-45e8-9997-0da40ec892e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042235165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3042235165
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2361911957
Short name T518
Test name
Test status
Simulation time 11354406 ps
CPU time 0.71 seconds
Started May 12 01:01:43 PM PDT 24
Finished May 12 01:01:44 PM PDT 24
Peak memory 204576 kb
Host smart-33a2dec6-e574-464d-be82-4a8750bd44b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361911957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
361911957
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.572360054
Short name T513
Test name
Test status
Simulation time 127759307 ps
CPU time 2.31 seconds
Started May 12 01:01:41 PM PDT 24
Finished May 12 01:01:44 PM PDT 24
Peak memory 232944 kb
Host smart-e486e75c-2072-4ba3-acab-d0c87fb6d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572360054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.572360054
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.868969046
Short name T643
Test name
Test status
Simulation time 13299147 ps
CPU time 0.75 seconds
Started May 12 01:01:40 PM PDT 24
Finished May 12 01:01:41 PM PDT 24
Peak memory 206740 kb
Host smart-ff5c4978-637a-403a-905a-713acdec77af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868969046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.868969046
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1377174045
Short name T545
Test name
Test status
Simulation time 7210416653 ps
CPU time 66.92 seconds
Started May 12 01:01:42 PM PDT 24
Finished May 12 01:02:49 PM PDT 24
Peak memory 256116 kb
Host smart-64531584-2bb2-4349-b31f-03462adccaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377174045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1377174045
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2271404468
Short name T225
Test name
Test status
Simulation time 321987937282 ps
CPU time 590.59 seconds
Started May 12 01:01:44 PM PDT 24
Finished May 12 01:11:35 PM PDT 24
Peak memory 269396 kb
Host smart-869995e9-571c-4288-9e3f-7bfb02896415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271404468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2271404468
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2258954923
Short name T516
Test name
Test status
Simulation time 929565625 ps
CPU time 7.46 seconds
Started May 12 01:01:43 PM PDT 24
Finished May 12 01:01:51 PM PDT 24
Peak memory 224216 kb
Host smart-50b18392-bfd9-4cbe-899e-d87a4e77c0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258954923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2258954923
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3182745204
Short name T265
Test name
Test status
Simulation time 734997197 ps
CPU time 9.11 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:01:55 PM PDT 24
Peak memory 218336 kb
Host smart-016afc95-68bc-455a-8680-4cbbe657697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182745204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3182745204
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3801854978
Short name T264
Test name
Test status
Simulation time 9287288098 ps
CPU time 32.78 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:02:19 PM PDT 24
Peak memory 248840 kb
Host smart-10b5af25-28c1-44ef-90bf-4da6b5307877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801854978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3801854978
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3042873442
Short name T714
Test name
Test status
Simulation time 16983345231 ps
CPU time 14.07 seconds
Started May 12 01:01:46 PM PDT 24
Finished May 12 01:02:00 PM PDT 24
Peak memory 236768 kb
Host smart-15c48194-c8d7-4227-ac78-b0363fa45865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042873442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3042873442
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2788930127
Short name T576
Test name
Test status
Simulation time 3648474034 ps
CPU time 16.93 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:02:03 PM PDT 24
Peak memory 230836 kb
Host smart-e9e54914-a5dd-484d-8ee2-b672f5a34c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788930127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2788930127
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.466183385
Short name T515
Test name
Test status
Simulation time 1175034131 ps
CPU time 17.33 seconds
Started May 12 01:01:46 PM PDT 24
Finished May 12 01:02:04 PM PDT 24
Peak memory 218660 kb
Host smart-a2c6a60b-9666-42f2-925d-7abb0c3ead2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=466183385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.466183385
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3844005376
Short name T69
Test name
Test status
Simulation time 110195275 ps
CPU time 1.09 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:01:47 PM PDT 24
Peak memory 234652 kb
Host smart-76200ff5-57f8-4bda-8273-560aba5adff5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844005376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3844005376
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4209545462
Short name T151
Test name
Test status
Simulation time 44128141 ps
CPU time 0.96 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:01:46 PM PDT 24
Peak memory 205472 kb
Host smart-e5a4b341-e69c-407f-a7fd-76134f728407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209545462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4209545462
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1644700610
Short name T314
Test name
Test status
Simulation time 924050444 ps
CPU time 2.62 seconds
Started May 12 01:01:43 PM PDT 24
Finished May 12 01:01:47 PM PDT 24
Peak memory 216284 kb
Host smart-c85ea3db-7ce9-4899-b54b-304d1b7e6366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644700610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1644700610
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3105320245
Short name T482
Test name
Test status
Simulation time 721189382 ps
CPU time 3.27 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:01:49 PM PDT 24
Peak memory 215952 kb
Host smart-d73bccc6-3d5a-482a-8f30-5ce8db7c0244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105320245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3105320245
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2157250475
Short name T689
Test name
Test status
Simulation time 160053006 ps
CPU time 0.97 seconds
Started May 12 01:01:46 PM PDT 24
Finished May 12 01:01:48 PM PDT 24
Peak memory 206792 kb
Host smart-e977dc2b-0121-428d-8ae2-29143f9d1c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157250475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2157250475
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2054955047
Short name T15
Test name
Test status
Simulation time 80495216 ps
CPU time 0.86 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:01:46 PM PDT 24
Peak memory 205652 kb
Host smart-ec1331bc-f4a9-4f70-8bbb-eaf605922e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054955047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2054955047
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1604103497
Short name T289
Test name
Test status
Simulation time 2461378510 ps
CPU time 11.51 seconds
Started May 12 01:01:45 PM PDT 24
Finished May 12 01:01:58 PM PDT 24
Peak memory 234272 kb
Host smart-b5b91360-cc42-42e1-bfc4-ebe50e509323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604103497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1604103497
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.556719547
Short name T838
Test name
Test status
Simulation time 46419227 ps
CPU time 0.7 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:18 PM PDT 24
Peak memory 205140 kb
Host smart-894cce3f-5f5c-40c1-9884-3c95d8aed2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556719547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.556719547
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.273386680
Short name T550
Test name
Test status
Simulation time 827235702 ps
CPU time 9.22 seconds
Started May 12 01:04:17 PM PDT 24
Finished May 12 01:04:27 PM PDT 24
Peak memory 233952 kb
Host smart-a377301a-71f4-4eb5-b186-5c8a8f80734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273386680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.273386680
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.104630811
Short name T592
Test name
Test status
Simulation time 55913383 ps
CPU time 0.79 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:22 PM PDT 24
Peak memory 205388 kb
Host smart-360548bc-c236-42e3-ba1b-4c399c66375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104630811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.104630811
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3767226874
Short name T36
Test name
Test status
Simulation time 34042037172 ps
CPU time 186.04 seconds
Started May 12 01:04:15 PM PDT 24
Finished May 12 01:07:21 PM PDT 24
Peak memory 248836 kb
Host smart-3d4ee8f4-f19a-47d7-8110-d5a00a446694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767226874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3767226874
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3894705751
Short name T273
Test name
Test status
Simulation time 15331922374 ps
CPU time 137.6 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:06:34 PM PDT 24
Peak memory 252116 kb
Host smart-c1eb4f50-999f-48ad-8d10-c01c28a13d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894705751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3894705751
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1411404866
Short name T217
Test name
Test status
Simulation time 36825380152 ps
CPU time 319.65 seconds
Started May 12 01:04:14 PM PDT 24
Finished May 12 01:09:34 PM PDT 24
Peak memory 264524 kb
Host smart-ba5c0d9a-0df6-4c6d-b436-993e195e49e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411404866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1411404866
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2936529442
Short name T619
Test name
Test status
Simulation time 2929595320 ps
CPU time 44.77 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:05:01 PM PDT 24
Peak memory 248928 kb
Host smart-89d6a134-80e9-43ce-995e-4c69adf79f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936529442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2936529442
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.461392930
Short name T890
Test name
Test status
Simulation time 1197612069 ps
CPU time 12.6 seconds
Started May 12 01:04:14 PM PDT 24
Finished May 12 01:04:27 PM PDT 24
Peak memory 233160 kb
Host smart-49849afe-0d88-48cf-95b2-8c9e7a2a45eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461392930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.461392930
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1079093653
Short name T431
Test name
Test status
Simulation time 8329520316 ps
CPU time 26.02 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:43 PM PDT 24
Peak memory 232544 kb
Host smart-0f96e7dd-bfc3-4328-97bf-f6a6d69472a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079093653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1079093653
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3952731272
Short name T384
Test name
Test status
Simulation time 32733268 ps
CPU time 2.32 seconds
Started May 12 01:04:11 PM PDT 24
Finished May 12 01:04:14 PM PDT 24
Peak memory 220704 kb
Host smart-311e9cbf-4588-4d6b-83ba-2fa3c24673bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952731272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3952731272
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2611123587
Short name T798
Test name
Test status
Simulation time 1474930068 ps
CPU time 6.86 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:27 PM PDT 24
Peak memory 234812 kb
Host smart-792385e7-2b77-4f02-b662-616657930e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611123587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2611123587
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2559283115
Short name T134
Test name
Test status
Simulation time 2961868977 ps
CPU time 11.94 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 222776 kb
Host smart-bfe4cebd-ef2c-4355-90e0-d2368d566bc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2559283115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2559283115
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2438230755
Short name T873
Test name
Test status
Simulation time 5884710685 ps
CPU time 120.37 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:06:17 PM PDT 24
Peak memory 262852 kb
Host smart-975d5b93-6121-4334-8b19-24970d8fe256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438230755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2438230755
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.856174304
Short name T318
Test name
Test status
Simulation time 1294932078 ps
CPU time 3.81 seconds
Started May 12 01:04:13 PM PDT 24
Finished May 12 01:04:17 PM PDT 24
Peak memory 217592 kb
Host smart-cbc91173-fc0a-4b55-8a97-ea184f96e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856174304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.856174304
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.126980183
Short name T711
Test name
Test status
Simulation time 1662193070 ps
CPU time 1.95 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:23 PM PDT 24
Peak memory 206728 kb
Host smart-a2a9f95b-0999-400c-ba0c-defd0c1ac7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126980183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.126980183
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2964629237
Short name T153
Test name
Test status
Simulation time 10516101 ps
CPU time 0.7 seconds
Started May 12 01:04:11 PM PDT 24
Finished May 12 01:04:12 PM PDT 24
Peak memory 205404 kb
Host smart-bb1852ae-26d3-49c4-8ed5-d07eea38b1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964629237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2964629237
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.294220407
Short name T369
Test name
Test status
Simulation time 40119489 ps
CPU time 0.77 seconds
Started May 12 01:04:08 PM PDT 24
Finished May 12 01:04:09 PM PDT 24
Peak memory 205644 kb
Host smart-e3628ef7-8ca6-4bf2-b1af-269db863a1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294220407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.294220407
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3735059165
Short name T530
Test name
Test status
Simulation time 143167402 ps
CPU time 2.33 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:23 PM PDT 24
Peak memory 221120 kb
Host smart-49d4eb97-92da-4175-b659-134263389bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735059165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3735059165
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1731177138
Short name T480
Test name
Test status
Simulation time 16896794 ps
CPU time 0.67 seconds
Started May 12 01:04:22 PM PDT 24
Finished May 12 01:04:24 PM PDT 24
Peak memory 205408 kb
Host smart-c5262688-b9e1-422c-a5b2-4678e86235e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731177138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1731177138
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4065391708
Short name T83
Test name
Test status
Simulation time 354085066 ps
CPU time 3.58 seconds
Started May 12 01:04:14 PM PDT 24
Finished May 12 01:04:18 PM PDT 24
Peak memory 233736 kb
Host smart-87690dc3-8d52-4dd5-98c6-569e9dda9ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065391708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4065391708
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3447183342
Short name T512
Test name
Test status
Simulation time 21100093 ps
CPU time 0.83 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:17 PM PDT 24
Peak memory 206464 kb
Host smart-ac9cc2cd-6e9b-4359-9db7-84ae6568e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447183342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3447183342
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3305261396
Short name T869
Test name
Test status
Simulation time 34717372029 ps
CPU time 75.43 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:05:37 PM PDT 24
Peak memory 249004 kb
Host smart-c793956b-a04f-4027-a876-773ebfd25483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305261396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3305261396
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3552470585
Short name T43
Test name
Test status
Simulation time 26003187619 ps
CPU time 87.87 seconds
Started May 12 01:04:17 PM PDT 24
Finished May 12 01:05:45 PM PDT 24
Peak memory 238168 kb
Host smart-6d7ca9df-948d-4216-af18-d9058eca4f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552470585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3552470585
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2154042026
Short name T899
Test name
Test status
Simulation time 5599371233 ps
CPU time 100.15 seconds
Started May 12 01:04:17 PM PDT 24
Finished May 12 01:05:58 PM PDT 24
Peak memory 255260 kb
Host smart-6471cddf-e063-48b5-b8f7-3e1eaf965967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154042026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2154042026
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3253875732
Short name T631
Test name
Test status
Simulation time 10775119260 ps
CPU time 19.13 seconds
Started May 12 01:04:18 PM PDT 24
Finished May 12 01:04:38 PM PDT 24
Peak memory 248892 kb
Host smart-a60e179a-19d9-40d6-a6ef-e47a2248e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253875732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3253875732
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2420520715
Short name T620
Test name
Test status
Simulation time 392623338 ps
CPU time 7.73 seconds
Started May 12 01:04:17 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 233540 kb
Host smart-47fc4cb6-803f-44d3-8f53-590fd1df07fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420520715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2420520715
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1127435829
Short name T601
Test name
Test status
Simulation time 453936314 ps
CPU time 2.33 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:20 PM PDT 24
Peak memory 215804 kb
Host smart-d834a51c-9577-46ab-ac13-acbd212163ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127435829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1127435829
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4027693334
Short name T473
Test name
Test status
Simulation time 457747138 ps
CPU time 8.32 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 240696 kb
Host smart-8a78112a-ab40-4b30-a574-39cbf15c76fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027693334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4027693334
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.431823315
Short name T605
Test name
Test status
Simulation time 16079719259 ps
CPU time 12.98 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:33 PM PDT 24
Peak memory 240428 kb
Host smart-fe4a68e1-28bf-4402-9a16-04fb20773e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431823315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.431823315
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1293198971
Short name T133
Test name
Test status
Simulation time 671912289 ps
CPU time 9.61 seconds
Started May 12 01:04:18 PM PDT 24
Finished May 12 01:04:28 PM PDT 24
Peak memory 222260 kb
Host smart-e5c7d613-d07e-4b1c-bd91-ce0a41e86cbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1293198971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1293198971
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3233318433
Short name T578
Test name
Test status
Simulation time 22028818471 ps
CPU time 205.82 seconds
Started May 12 01:04:21 PM PDT 24
Finished May 12 01:07:48 PM PDT 24
Peak memory 253248 kb
Host smart-f108af8c-7f18-4fb8-b20f-25fc59093478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233318433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3233318433
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2539331051
Short name T852
Test name
Test status
Simulation time 12946565651 ps
CPU time 24.13 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 216236 kb
Host smart-62c0abba-896c-4950-a5c3-c122abdc1330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539331051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2539331051
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2744182481
Short name T330
Test name
Test status
Simulation time 1016838963 ps
CPU time 6.01 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 215880 kb
Host smart-640adb76-6534-4b44-a4e3-a3a94208d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744182481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2744182481
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2745806787
Short name T359
Test name
Test status
Simulation time 47227697 ps
CPU time 1.13 seconds
Started May 12 01:04:16 PM PDT 24
Finished May 12 01:04:18 PM PDT 24
Peak memory 207352 kb
Host smart-c392b480-b77f-4053-9c6a-286e9e50b0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745806787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2745806787
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2809164964
Short name T596
Test name
Test status
Simulation time 51767292 ps
CPU time 0.81 seconds
Started May 12 01:04:15 PM PDT 24
Finished May 12 01:04:17 PM PDT 24
Peak memory 205548 kb
Host smart-0b3a07a0-ccf3-48f5-b5f8-80f1278c43c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809164964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2809164964
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3058395693
Short name T926
Test name
Test status
Simulation time 25156032703 ps
CPU time 20.77 seconds
Started May 12 01:04:13 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 235004 kb
Host smart-0470a265-b936-4f40-8254-9ee8bec367c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058395693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3058395693
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.853772990
Short name T885
Test name
Test status
Simulation time 75124254 ps
CPU time 0.7 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:21 PM PDT 24
Peak memory 204680 kb
Host smart-86d764e3-00a1-490d-83fc-b295a5de8227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853772990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.853772990
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2724180224
Short name T633
Test name
Test status
Simulation time 947763457 ps
CPU time 9.77 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:31 PM PDT 24
Peak memory 219748 kb
Host smart-c621391e-db76-4f93-a10c-c232328ae41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724180224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2724180224
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1820755785
Short name T476
Test name
Test status
Simulation time 15215071 ps
CPU time 0.79 seconds
Started May 12 01:04:24 PM PDT 24
Finished May 12 01:04:25 PM PDT 24
Peak memory 205608 kb
Host smart-8a354f21-dd55-4e7d-a341-bebbf767cdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820755785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1820755785
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2298175372
Short name T233
Test name
Test status
Simulation time 154113460045 ps
CPU time 370.79 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:10:32 PM PDT 24
Peak memory 248980 kb
Host smart-cae62667-67c8-4fb4-bd34-1ec0c5b07a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298175372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2298175372
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4259864100
Short name T675
Test name
Test status
Simulation time 20493678274 ps
CPU time 164.02 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:07:06 PM PDT 24
Peak memory 240692 kb
Host smart-bd6c3ee3-63fe-41b5-83ae-79738c0e917f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259864100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4259864100
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3982876248
Short name T1
Test name
Test status
Simulation time 1808589920 ps
CPU time 19.64 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:40 PM PDT 24
Peak memory 251596 kb
Host smart-22a573ab-7aaf-4588-8bab-88084ebd0ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982876248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3982876248
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3718701508
Short name T457
Test name
Test status
Simulation time 1534500493 ps
CPU time 6.72 seconds
Started May 12 01:04:21 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 219460 kb
Host smart-225be8aa-fcf6-4127-9301-f7b15939428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718701508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3718701508
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2350168498
Short name T827
Test name
Test status
Simulation time 1626784211 ps
CPU time 6.74 seconds
Started May 12 01:04:18 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 218448 kb
Host smart-6bdea77f-e44a-469b-bb8e-03e148098887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350168498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2350168498
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3432138116
Short name T12
Test name
Test status
Simulation time 1223182436 ps
CPU time 6.15 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:28 PM PDT 24
Peak memory 233380 kb
Host smart-28b3933e-53ae-48aa-bc76-c0cac64fef75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432138116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3432138116
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1256385999
Short name T750
Test name
Test status
Simulation time 70644000 ps
CPU time 2.43 seconds
Started May 12 01:04:23 PM PDT 24
Finished May 12 01:04:26 PM PDT 24
Peak memory 233332 kb
Host smart-1103e92a-95ef-4504-b2b1-1dac1fb6965e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256385999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1256385999
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4121864492
Short name T931
Test name
Test status
Simulation time 236508999 ps
CPU time 3.28 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:25 PM PDT 24
Peak memory 222224 kb
Host smart-a8dd74b4-1747-4777-9f54-0340106bb28e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4121864492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4121864492
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1736807435
Short name T784
Test name
Test status
Simulation time 369573521 ps
CPU time 1.04 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:23 PM PDT 24
Peak memory 207036 kb
Host smart-786b662e-6947-4b14-8586-74f51dbf12ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736807435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1736807435
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.208034963
Short name T317
Test name
Test status
Simulation time 864509360 ps
CPU time 4.94 seconds
Started May 12 01:04:22 PM PDT 24
Finished May 12 01:04:27 PM PDT 24
Peak memory 216180 kb
Host smart-91dda914-9999-41a7-8df4-f72d0877a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208034963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.208034963
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2752640412
Short name T641
Test name
Test status
Simulation time 2770781170 ps
CPU time 6.97 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:28 PM PDT 24
Peak memory 216048 kb
Host smart-c41ec1ce-4116-4d54-8296-2473be8fcefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752640412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2752640412
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3013052542
Short name T485
Test name
Test status
Simulation time 91375420 ps
CPU time 1.01 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:21 PM PDT 24
Peak memory 207740 kb
Host smart-fa2632b5-2006-4227-9199-5176a11b7c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013052542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3013052542
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.358416871
Short name T406
Test name
Test status
Simulation time 15904599 ps
CPU time 0.68 seconds
Started May 12 01:04:18 PM PDT 24
Finished May 12 01:04:20 PM PDT 24
Peak memory 205376 kb
Host smart-13b7f85f-4d2d-4846-ab2f-350f27c685a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358416871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.358416871
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2301731497
Short name T498
Test name
Test status
Simulation time 24412762381 ps
CPU time 42.59 seconds
Started May 12 01:04:21 PM PDT 24
Finished May 12 01:05:05 PM PDT 24
Peak memory 238752 kb
Host smart-d1763d2a-b99d-410d-813c-3316f2063f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301731497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2301731497
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2438837829
Short name T413
Test name
Test status
Simulation time 11064407 ps
CPU time 0.73 seconds
Started May 12 01:04:22 PM PDT 24
Finished May 12 01:04:24 PM PDT 24
Peak memory 205468 kb
Host smart-a834a627-fa1d-4a7f-bc2c-4568512589df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438837829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2438837829
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4270998479
Short name T484
Test name
Test status
Simulation time 1102919203 ps
CPU time 3.67 seconds
Started May 12 01:04:25 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 218568 kb
Host smart-50d0ee44-d5b7-4727-8136-1d015fcd4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270998479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4270998479
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4022130606
Short name T332
Test name
Test status
Simulation time 35767281 ps
CPU time 0.75 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:21 PM PDT 24
Peak memory 205424 kb
Host smart-b0c8d7e4-a88c-47c0-8663-e48f5202d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022130606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4022130606
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1081208838
Short name T441
Test name
Test status
Simulation time 4506824840 ps
CPU time 44.39 seconds
Started May 12 01:04:27 PM PDT 24
Finished May 12 01:05:12 PM PDT 24
Peak memory 245544 kb
Host smart-b98a9a91-8796-4768-ad59-b9be4e85fd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081208838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1081208838
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.300745958
Short name T26
Test name
Test status
Simulation time 2118275854 ps
CPU time 32.38 seconds
Started May 12 01:04:26 PM PDT 24
Finished May 12 01:04:59 PM PDT 24
Peak memory 239000 kb
Host smart-ef514bff-8228-4e7f-b638-1a74b9302f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300745958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.300745958
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3597646853
Short name T402
Test name
Test status
Simulation time 3311353506 ps
CPU time 25.31 seconds
Started May 12 01:04:24 PM PDT 24
Finished May 12 01:04:50 PM PDT 24
Peak memory 217224 kb
Host smart-77d63f02-2466-4fcd-b77e-5438cf4f1dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597646853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3597646853
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1474527055
Short name T348
Test name
Test status
Simulation time 1114200600 ps
CPU time 4 seconds
Started May 12 01:04:24 PM PDT 24
Finished May 12 01:04:28 PM PDT 24
Peak memory 233696 kb
Host smart-c9b3b928-e959-4697-8570-d9dc287f0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474527055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1474527055
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1656966915
Short name T880
Test name
Test status
Simulation time 348766473 ps
CPU time 5.79 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:25 PM PDT 24
Peak memory 219376 kb
Host smart-e0ac38a0-a8f1-44cc-b8d4-dc237810ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656966915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1656966915
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1856095613
Short name T839
Test name
Test status
Simulation time 27391060957 ps
CPU time 99.04 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:05:59 PM PDT 24
Peak memory 253832 kb
Host smart-f01a8cce-4031-4298-bae5-434d182d7cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856095613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1856095613
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2646208071
Short name T159
Test name
Test status
Simulation time 1373736086 ps
CPU time 3.73 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:24 PM PDT 24
Peak memory 218532 kb
Host smart-c447d89c-feed-40b1-b78a-9892fdc3e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646208071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2646208071
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3562195054
Short name T21
Test name
Test status
Simulation time 998469938 ps
CPU time 8.35 seconds
Started May 12 01:04:19 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 233788 kb
Host smart-cbf39523-5c32-44ac-aea2-a14e125c05f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562195054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3562195054
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2953320164
Short name T837
Test name
Test status
Simulation time 775135107 ps
CPU time 4.28 seconds
Started May 12 01:04:23 PM PDT 24
Finished May 12 01:04:28 PM PDT 24
Peak memory 219404 kb
Host smart-922da4fc-630e-446b-856e-be94ffb18b50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953320164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2953320164
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2760868878
Short name T44
Test name
Test status
Simulation time 60272448343 ps
CPU time 561.14 seconds
Started May 12 01:04:27 PM PDT 24
Finished May 12 01:13:49 PM PDT 24
Peak memory 250520 kb
Host smart-5bc49036-179f-4c3c-b8a7-8e2020af7ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760868878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2760868878
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3621979221
Short name T534
Test name
Test status
Simulation time 20956140287 ps
CPU time 23.75 seconds
Started May 12 01:04:21 PM PDT 24
Finished May 12 01:04:46 PM PDT 24
Peak memory 216320 kb
Host smart-e263a469-7f6e-45ad-954c-dee36d8f48b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621979221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3621979221
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2452568473
Short name T914
Test name
Test status
Simulation time 13672188501 ps
CPU time 21.46 seconds
Started May 12 01:04:21 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 216024 kb
Host smart-81f65869-fb96-46c3-80f5-fb5e35eadd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452568473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2452568473
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1750559108
Short name T19
Test name
Test status
Simulation time 1038123163 ps
CPU time 5.82 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:27 PM PDT 24
Peak memory 216124 kb
Host smart-b76c8da4-cc2c-4ddf-8f2f-dfeaf71d03ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750559108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1750559108
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3380503945
Short name T324
Test name
Test status
Simulation time 156087675 ps
CPU time 0.78 seconds
Started May 12 01:04:20 PM PDT 24
Finished May 12 01:04:23 PM PDT 24
Peak memory 205676 kb
Host smart-9e2d0760-bf33-4511-b4cf-0ba54574f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380503945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3380503945
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3162040194
Short name T519
Test name
Test status
Simulation time 317493719 ps
CPU time 6.71 seconds
Started May 12 01:04:22 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 239600 kb
Host smart-4cd73d07-169a-4ab0-b3e2-6fe0e7611196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162040194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3162040194
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.850643866
Short name T661
Test name
Test status
Simulation time 41318733 ps
CPU time 0.71 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 205160 kb
Host smart-a3afc19b-3e4e-4e83-b214-48a023b130ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850643866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.850643866
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3456651727
Short name T430
Test name
Test status
Simulation time 670075108 ps
CPU time 3.42 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:04:33 PM PDT 24
Peak memory 218560 kb
Host smart-aabda150-55c0-40f8-83ae-b8457bcc4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456651727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3456651727
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1997149723
Short name T699
Test name
Test status
Simulation time 40357945 ps
CPU time 0.76 seconds
Started May 12 01:04:24 PM PDT 24
Finished May 12 01:04:25 PM PDT 24
Peak memory 205632 kb
Host smart-de94a26a-dc72-48de-ae45-42b4cfde8e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997149723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1997149723
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.201391198
Short name T710
Test name
Test status
Simulation time 2860389482 ps
CPU time 61.71 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:05:31 PM PDT 24
Peak memory 254924 kb
Host smart-c75fbea4-cb8a-4e3e-a3df-ece744eb05b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201391198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.201391198
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1855516228
Short name T182
Test name
Test status
Simulation time 60924727827 ps
CPU time 609.46 seconds
Started May 12 01:04:32 PM PDT 24
Finished May 12 01:14:42 PM PDT 24
Peak memory 256036 kb
Host smart-6d21f678-701a-488b-9de1-be7aa1a3e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855516228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1855516228
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2946983926
Short name T588
Test name
Test status
Simulation time 206954290 ps
CPU time 3.53 seconds
Started May 12 01:04:31 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 224204 kb
Host smart-3fa4132e-b3e3-438a-a69b-f224862d0e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946983926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2946983926
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.593409726
Short name T209
Test name
Test status
Simulation time 369941593 ps
CPU time 6.72 seconds
Started May 12 01:04:24 PM PDT 24
Finished May 12 01:04:31 PM PDT 24
Peak memory 234056 kb
Host smart-86c4ced3-9e72-46c4-9528-444c92fb90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593409726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.593409726
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1081575610
Short name T524
Test name
Test status
Simulation time 1880360931 ps
CPU time 7.38 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:04:37 PM PDT 24
Peak memory 237392 kb
Host smart-752ccc67-d500-4c30-939e-19d83a4e49a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081575610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1081575610
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.346462703
Short name T238
Test name
Test status
Simulation time 1712236139 ps
CPU time 5.18 seconds
Started May 12 01:04:23 PM PDT 24
Finished May 12 01:04:29 PM PDT 24
Peak memory 233652 kb
Host smart-072af583-ed19-4286-bf84-f812abd229eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346462703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.346462703
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2275713881
Short name T582
Test name
Test status
Simulation time 7208700733 ps
CPU time 20.7 seconds
Started May 12 01:04:24 PM PDT 24
Finished May 12 01:04:45 PM PDT 24
Peak memory 233452 kb
Host smart-8bc95fb6-7ec8-42ae-903e-e2108531aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275713881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2275713881
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3508892146
Short name T466
Test name
Test status
Simulation time 487818717 ps
CPU time 6.01 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 218564 kb
Host smart-c84ad3fa-aa9e-4944-9f31-c4dfaa1c01c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3508892146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3508892146
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2506098447
Short name T148
Test name
Test status
Simulation time 49626606014 ps
CPU time 177.25 seconds
Started May 12 01:04:30 PM PDT 24
Finished May 12 01:07:27 PM PDT 24
Peak memory 248884 kb
Host smart-9370f11b-a62a-46e5-a149-6e0bd7fe23fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506098447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2506098447
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2386163861
Short name T310
Test name
Test status
Simulation time 1135434167 ps
CPU time 5.64 seconds
Started May 12 01:04:26 PM PDT 24
Finished May 12 01:04:32 PM PDT 24
Peak memory 216460 kb
Host smart-ad39d268-c6bb-452d-a9c5-668b8f8b5ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386163861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2386163861
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.341691125
Short name T865
Test name
Test status
Simulation time 9922085171 ps
CPU time 15.91 seconds
Started May 12 01:04:25 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 216136 kb
Host smart-52217b2f-3bb8-4cb2-a852-c834c4877168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341691125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.341691125
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.267957189
Short name T904
Test name
Test status
Simulation time 110173762 ps
CPU time 2.14 seconds
Started May 12 01:04:22 PM PDT 24
Finished May 12 01:04:25 PM PDT 24
Peak memory 216132 kb
Host smart-bc4fc335-7999-485b-8570-5051ca400867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267957189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.267957189
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3226238864
Short name T757
Test name
Test status
Simulation time 100554845 ps
CPU time 0.87 seconds
Started May 12 01:04:23 PM PDT 24
Finished May 12 01:04:24 PM PDT 24
Peak memory 205492 kb
Host smart-9690756e-ed59-4a62-8e63-3e4c2985c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226238864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3226238864
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2041396904
Short name T681
Test name
Test status
Simulation time 446600072 ps
CPU time 7.57 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:04:37 PM PDT 24
Peak memory 246700 kb
Host smart-a2db2063-30e5-4f05-b8c4-7d5ad6de8024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041396904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2041396904
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2822834586
Short name T857
Test name
Test status
Simulation time 16667821 ps
CPU time 0.74 seconds
Started May 12 01:04:30 PM PDT 24
Finished May 12 01:04:31 PM PDT 24
Peak memory 205196 kb
Host smart-4ad44e60-bbf5-4499-8d55-715be1f528a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822834586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2822834586
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.286362277
Short name T787
Test name
Test status
Simulation time 723964269 ps
CPU time 3.14 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:04:32 PM PDT 24
Peak memory 233064 kb
Host smart-8d223d9e-eeb1-4a0a-a8f7-d16380558a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286362277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.286362277
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3516262797
Short name T703
Test name
Test status
Simulation time 45831829 ps
CPU time 0.75 seconds
Started May 12 01:04:30 PM PDT 24
Finished May 12 01:04:31 PM PDT 24
Peak memory 205672 kb
Host smart-23170b11-7df6-483f-b896-359dafd006bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516262797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3516262797
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3306969328
Short name T242
Test name
Test status
Simulation time 238618943781 ps
CPU time 440.1 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:11:49 PM PDT 24
Peak memory 251872 kb
Host smart-cca583b3-87b0-4344-a7e9-b5d666b00791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306969328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3306969328
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2513206390
Short name T489
Test name
Test status
Simulation time 10696370102 ps
CPU time 85.44 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:05:54 PM PDT 24
Peak memory 248960 kb
Host smart-7790be04-6b8f-48be-a9e7-df9bc9b9f2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513206390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2513206390
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1436286977
Short name T925
Test name
Test status
Simulation time 150028596 ps
CPU time 2.45 seconds
Started May 12 01:04:31 PM PDT 24
Finished May 12 01:04:34 PM PDT 24
Peak memory 217208 kb
Host smart-26581e65-104d-43e2-9be3-21ddeaf38994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436286977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1436286977
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3179861395
Short name T573
Test name
Test status
Simulation time 557397582 ps
CPU time 8.8 seconds
Started May 12 01:04:31 PM PDT 24
Finished May 12 01:04:40 PM PDT 24
Peak memory 233876 kb
Host smart-fcbb59f8-5f9c-41d5-a59c-3d1dc777717c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179861395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3179861395
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.608326566
Short name T203
Test name
Test status
Simulation time 1852341071 ps
CPU time 9.64 seconds
Started May 12 01:04:30 PM PDT 24
Finished May 12 01:04:40 PM PDT 24
Peak memory 220140 kb
Host smart-181dea74-de7e-4ace-9d88-1759a3201129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608326566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.608326566
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2427454184
Short name T295
Test name
Test status
Simulation time 6385090805 ps
CPU time 67.47 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:05:37 PM PDT 24
Peak memory 245432 kb
Host smart-fc7669e7-ea92-4c97-84b6-683aed073deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427454184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2427454184
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1462590415
Short name T572
Test name
Test status
Simulation time 7753403503 ps
CPU time 10.95 seconds
Started May 12 01:04:30 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 232976 kb
Host smart-d2df95c9-4e5d-4e1a-bb89-e6c189c59b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462590415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1462590415
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.748409748
Short name T785
Test name
Test status
Simulation time 1220582889 ps
CPU time 2.17 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:04:32 PM PDT 24
Peak memory 218736 kb
Host smart-80309e6d-581d-496c-a943-f83358817a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748409748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.748409748
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.90937794
Short name T356
Test name
Test status
Simulation time 1034175019 ps
CPU time 8.96 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:04:38 PM PDT 24
Peak memory 218952 kb
Host smart-c4dc70e9-626c-4567-aaf0-ab7f3b65c237
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90937794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direc
t.90937794
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3450073440
Short name T216
Test name
Test status
Simulation time 21793338076 ps
CPU time 187.83 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:07:38 PM PDT 24
Peak memory 251204 kb
Host smart-6d995f1b-815c-4082-bb84-e09e0302d882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450073440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3450073440
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2272853220
Short name T525
Test name
Test status
Simulation time 5066834478 ps
CPU time 34.3 seconds
Started May 12 01:04:31 PM PDT 24
Finished May 12 01:05:06 PM PDT 24
Peak memory 216176 kb
Host smart-1e92742a-6f5c-467c-9f12-e8a1fabf9e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272853220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2272853220
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1559123691
Short name T54
Test name
Test status
Simulation time 46973720183 ps
CPU time 17.07 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:04:47 PM PDT 24
Peak memory 216176 kb
Host smart-2afec810-6af2-4a07-88a8-a23eb5a601bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559123691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1559123691
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1842548154
Short name T740
Test name
Test status
Simulation time 263184777 ps
CPU time 2.5 seconds
Started May 12 01:04:29 PM PDT 24
Finished May 12 01:04:33 PM PDT 24
Peak memory 216008 kb
Host smart-9ca543b0-2bd9-41b2-bccc-eb69650aa529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842548154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1842548154
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2281217506
Short name T579
Test name
Test status
Simulation time 80977725 ps
CPU time 0.76 seconds
Started May 12 01:04:30 PM PDT 24
Finished May 12 01:04:31 PM PDT 24
Peak memory 205640 kb
Host smart-7c1c3397-d5a6-42c7-b561-8a7d0f77f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281217506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2281217506
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3739559779
Short name T555
Test name
Test status
Simulation time 2596779911 ps
CPU time 9.98 seconds
Started May 12 01:04:28 PM PDT 24
Finished May 12 01:04:39 PM PDT 24
Peak memory 234728 kb
Host smart-4e6d0cc4-dc8e-4208-a31c-d1822e7a26a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739559779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3739559779
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.716781430
Short name T557
Test name
Test status
Simulation time 33771944 ps
CPU time 0.71 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 205224 kb
Host smart-35dd5f0a-2077-4f3c-8d0d-b956f86490c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716781430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.716781430
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.916446722
Short name T849
Test name
Test status
Simulation time 172025598 ps
CPU time 2.36 seconds
Started May 12 01:04:32 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 232508 kb
Host smart-9421a639-67e7-4fb9-9ff8-dffb56143ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916446722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.916446722
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.207241985
Short name T706
Test name
Test status
Simulation time 47725872 ps
CPU time 0.76 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:34 PM PDT 24
Peak memory 205320 kb
Host smart-e6dbb17e-90bb-4f1b-888a-6ff613a14ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207241985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.207241985
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2756211931
Short name T222
Test name
Test status
Simulation time 24292103097 ps
CPU time 82.46 seconds
Started May 12 01:04:32 PM PDT 24
Finished May 12 01:05:55 PM PDT 24
Peak memory 248936 kb
Host smart-28004f8a-a32f-49bb-ab52-f5d2d0c7e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756211931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2756211931
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.192956178
Short name T191
Test name
Test status
Simulation time 92911928897 ps
CPU time 183.25 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:07:38 PM PDT 24
Peak memory 252524 kb
Host smart-be1caecb-0fcd-4f77-90dc-4eff1d760f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192956178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.192956178
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1019712314
Short name T488
Test name
Test status
Simulation time 77621860410 ps
CPU time 405.06 seconds
Started May 12 01:04:35 PM PDT 24
Finished May 12 01:11:20 PM PDT 24
Peak memory 257484 kb
Host smart-6e845fcf-f1fb-40fb-a868-74956744a3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019712314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1019712314
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.946040579
Short name T860
Test name
Test status
Simulation time 568753682 ps
CPU time 5.77 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:04:40 PM PDT 24
Peak memory 248808 kb
Host smart-a0b19d72-cbc5-432d-896e-3f45de18a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946040579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.946040579
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3934616193
Short name T37
Test name
Test status
Simulation time 828242238 ps
CPU time 10.46 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 233576 kb
Host smart-735ba2b7-782a-40a0-92a5-ff3311a9bc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934616193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3934616193
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1917304896
Short name T554
Test name
Test status
Simulation time 2819169078 ps
CPU time 14.83 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:48 PM PDT 24
Peak memory 233920 kb
Host smart-5ee8c548-4b32-43f1-b686-f0024c0bac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917304896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1917304896
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.31175429
Short name T86
Test name
Test status
Simulation time 2054174712 ps
CPU time 5.66 seconds
Started May 12 01:04:32 PM PDT 24
Finished May 12 01:04:38 PM PDT 24
Peak memory 233652 kb
Host smart-ffcced1a-348a-4e32-a5e5-d6838f156ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31175429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.31175429
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3567195370
Short name T627
Test name
Test status
Simulation time 1177133199 ps
CPU time 3.51 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:37 PM PDT 24
Peak memory 219572 kb
Host smart-3fd1c93f-ba0b-4e97-aea4-4b5c6ba475cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567195370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3567195370
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3965660410
Short name T364
Test name
Test status
Simulation time 151541223 ps
CPU time 3.97 seconds
Started May 12 01:04:37 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 220044 kb
Host smart-998646e0-866b-49b1-a391-229fe33200d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3965660410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3965660410
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1414907345
Short name T130
Test name
Test status
Simulation time 572984818139 ps
CPU time 1414.35 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:28:09 PM PDT 24
Peak memory 281812 kb
Host smart-4bae19b4-e64f-4997-be9b-2e2f68c1357c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414907345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1414907345
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1339389299
Short name T719
Test name
Test status
Simulation time 31513358 ps
CPU time 0.73 seconds
Started May 12 01:04:35 PM PDT 24
Finished May 12 01:04:36 PM PDT 24
Peak memory 205432 kb
Host smart-d47dec28-bf46-4984-8419-e9fa0e48d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339389299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1339389299
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4257697343
Short name T667
Test name
Test status
Simulation time 32665779916 ps
CPU time 21.35 seconds
Started May 12 01:04:36 PM PDT 24
Finished May 12 01:04:58 PM PDT 24
Peak memory 216060 kb
Host smart-6eed4629-c8a3-444e-b925-d195f65a312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257697343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4257697343
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1320909397
Short name T374
Test name
Test status
Simulation time 13261264 ps
CPU time 0.7 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 205368 kb
Host smart-3ffcafa7-447f-4dc9-ab31-f8d7f44830a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320909397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1320909397
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2570191129
Short name T345
Test name
Test status
Simulation time 37591473 ps
CPU time 0.73 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:34 PM PDT 24
Peak memory 205596 kb
Host smart-d920f8b6-fd13-41ba-8078-6f4362c9088d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570191129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2570191129
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4035233515
Short name T426
Test name
Test status
Simulation time 1962982058 ps
CPU time 3.44 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:04:38 PM PDT 24
Peak memory 224324 kb
Host smart-16bf5cfa-bab7-448a-9f95-d07f0deb5f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035233515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4035233515
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.960017183
Short name T383
Test name
Test status
Simulation time 52775845 ps
CPU time 0.74 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:04:39 PM PDT 24
Peak memory 205172 kb
Host smart-84353510-06aa-44e4-8a11-53e21ea7a17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960017183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.960017183
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1433574122
Short name T758
Test name
Test status
Simulation time 1211611919 ps
CPU time 14.26 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:55 PM PDT 24
Peak memory 234092 kb
Host smart-6b047248-5e07-4def-8147-30d28cc86a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433574122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1433574122
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2235699438
Short name T327
Test name
Test status
Simulation time 38446654 ps
CPU time 0.74 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:34 PM PDT 24
Peak memory 206776 kb
Host smart-d005c723-cddb-417c-bb7c-c9350b0adf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235699438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2235699438
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2304787804
Short name T726
Test name
Test status
Simulation time 58694967259 ps
CPU time 111.33 seconds
Started May 12 01:04:41 PM PDT 24
Finished May 12 01:06:33 PM PDT 24
Peak memory 237780 kb
Host smart-cfc3353f-76d1-4561-acf3-d31d27880808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304787804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2304787804
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1993984706
Short name T251
Test name
Test status
Simulation time 217549397069 ps
CPU time 608.74 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:14:49 PM PDT 24
Peak memory 265312 kb
Host smart-0d719046-f79e-4bea-948d-33e0e01cd365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993984706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1993984706
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4198688235
Short name T196
Test name
Test status
Simulation time 10877782898 ps
CPU time 76.3 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:05:55 PM PDT 24
Peak memory 255312 kb
Host smart-b1a09cae-8fae-4b80-8dea-9e3e9db5d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198688235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4198688235
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2192850596
Short name T305
Test name
Test status
Simulation time 2214739430 ps
CPU time 11.32 seconds
Started May 12 01:04:41 PM PDT 24
Finished May 12 01:04:53 PM PDT 24
Peak memory 238092 kb
Host smart-42d5623d-f8aa-4308-85db-d75d1bb546cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192850596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2192850596
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2405881405
Short name T859
Test name
Test status
Simulation time 304188325 ps
CPU time 3.05 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:43 PM PDT 24
Peak memory 232524 kb
Host smart-77976c22-81b5-4e81-ae16-12d0679ba09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405881405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2405881405
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3270788958
Short name T665
Test name
Test status
Simulation time 449105664 ps
CPU time 3.34 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:04:42 PM PDT 24
Peak memory 232464 kb
Host smart-4db060b6-8a99-4386-a3bb-562611dee24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270788958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3270788958
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3331294607
Short name T560
Test name
Test status
Simulation time 188421409 ps
CPU time 2.74 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 218712 kb
Host smart-d67bd4ea-f1ce-4973-a390-7751cacac14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331294607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3331294607
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3481614677
Short name T764
Test name
Test status
Simulation time 29312221171 ps
CPU time 20.1 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:53 PM PDT 24
Peak memory 233052 kb
Host smart-4d73e4f7-e21a-407f-8d79-8a9508b31834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481614677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3481614677
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.875147758
Short name T438
Test name
Test status
Simulation time 1027081742 ps
CPU time 12.56 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:53 PM PDT 24
Peak memory 218880 kb
Host smart-8a1a742e-87f5-47b1-af62-4644a376a369
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=875147758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.875147758
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3931059172
Short name T882
Test name
Test status
Simulation time 15428490404 ps
CPU time 159.24 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:07:18 PM PDT 24
Peak memory 251608 kb
Host smart-8962db69-311f-40a2-8a14-32b2dd85c35c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931059172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3931059172
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.804449431
Short name T810
Test name
Test status
Simulation time 15063174670 ps
CPU time 27.57 seconds
Started May 12 01:04:32 PM PDT 24
Finished May 12 01:05:00 PM PDT 24
Peak memory 216364 kb
Host smart-b295bd56-7da8-446d-82a8-a34737d883bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804449431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.804449431
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.451377999
Short name T542
Test name
Test status
Simulation time 5301714963 ps
CPU time 9 seconds
Started May 12 01:04:34 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 216132 kb
Host smart-65a396bb-2e1a-4098-8703-f1231f4b3bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451377999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.451377999
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1760329666
Short name T375
Test name
Test status
Simulation time 51692808 ps
CPU time 1.02 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:35 PM PDT 24
Peak memory 207672 kb
Host smart-2642dbfa-d77d-4262-a764-64fcb3606847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760329666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1760329666
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1207604957
Short name T449
Test name
Test status
Simulation time 44234532 ps
CPU time 0.78 seconds
Started May 12 01:04:33 PM PDT 24
Finished May 12 01:04:34 PM PDT 24
Peak memory 205620 kb
Host smart-1c2a4b39-d017-492e-9dce-ce99ec05f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207604957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1207604957
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1780006454
Short name T350
Test name
Test status
Simulation time 453218173 ps
CPU time 2.94 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:04:42 PM PDT 24
Peak memory 232420 kb
Host smart-76d55464-8554-4d68-9ed0-b7bee29d592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780006454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1780006454
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1148389361
Short name T892
Test name
Test status
Simulation time 31845141 ps
CPU time 0.72 seconds
Started May 12 01:04:48 PM PDT 24
Finished May 12 01:04:49 PM PDT 24
Peak memory 205236 kb
Host smart-d61c5411-02e2-4d43-9878-011aa042fd8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148389361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1148389361
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1253070684
Short name T921
Test name
Test status
Simulation time 31870557 ps
CPU time 2.37 seconds
Started May 12 01:04:41 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 220936 kb
Host smart-9d7e390f-3436-46be-999e-f6319200c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253070684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1253070684
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3500445651
Short name T887
Test name
Test status
Simulation time 81066165 ps
CPU time 0.8 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 206400 kb
Host smart-a64ac0d1-e203-4297-8ea7-87427720b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500445651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3500445651
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2138447240
Short name T686
Test name
Test status
Simulation time 5931493238 ps
CPU time 52.32 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:05:36 PM PDT 24
Peak memory 251980 kb
Host smart-41f8dcea-604d-4a96-a605-d2f0f392fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138447240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2138447240
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3598011241
Short name T201
Test name
Test status
Simulation time 5255790127 ps
CPU time 47.49 seconds
Started May 12 01:04:45 PM PDT 24
Finished May 12 01:05:33 PM PDT 24
Peak memory 239292 kb
Host smart-fa6cf3e0-daea-4f4a-b96e-ec6ada710ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598011241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3598011241
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.413866747
Short name T618
Test name
Test status
Simulation time 5783881775 ps
CPU time 57.11 seconds
Started May 12 01:04:46 PM PDT 24
Finished May 12 01:05:44 PM PDT 24
Peak memory 252844 kb
Host smart-bf798e5d-7dd3-4e18-ab9f-ae339bcc7dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413866747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.413866747
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2019098604
Short name T853
Test name
Test status
Simulation time 970436926 ps
CPU time 12.4 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:04:55 PM PDT 24
Peak memory 232416 kb
Host smart-0bd8ac70-a94a-46d0-9fc6-b80c2360db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019098604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2019098604
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1076296022
Short name T889
Test name
Test status
Simulation time 3784040851 ps
CPU time 9.83 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:50 PM PDT 24
Peak memory 224332 kb
Host smart-5c18c786-ad48-4944-affe-a92084388a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076296022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1076296022
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2176140680
Short name T835
Test name
Test status
Simulation time 209334597 ps
CPU time 2.33 seconds
Started May 12 01:04:41 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 215872 kb
Host smart-773413e4-df1c-4c86-b4b0-3061314e8728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176140680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2176140680
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2742009196
Short name T604
Test name
Test status
Simulation time 24027869232 ps
CPU time 11.86 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:04:50 PM PDT 24
Peak memory 234724 kb
Host smart-62008383-b797-4e77-ace7-2140277bb927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742009196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2742009196
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1082445223
Short name T565
Test name
Test status
Simulation time 1784027343 ps
CPU time 7.06 seconds
Started May 12 01:04:38 PM PDT 24
Finished May 12 01:04:46 PM PDT 24
Peak memory 232440 kb
Host smart-17b3c156-eec6-4711-8a25-20225d717ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082445223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1082445223
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1784469759
Short name T709
Test name
Test status
Simulation time 949765512 ps
CPU time 5.39 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:04:49 PM PDT 24
Peak memory 221580 kb
Host smart-fd49e834-203e-47e7-a2b2-778ef61aa34e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1784469759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1784469759
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2276396271
Short name T63
Test name
Test status
Simulation time 1884135365 ps
CPU time 31.55 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:05:16 PM PDT 24
Peak memory 232736 kb
Host smart-a40911e4-0d6c-48ce-8ac9-20bda37b2406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276396271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2276396271
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.177781688
Short name T587
Test name
Test status
Simulation time 20042621241 ps
CPU time 27.29 seconds
Started May 12 01:04:42 PM PDT 24
Finished May 12 01:05:10 PM PDT 24
Peak memory 216392 kb
Host smart-d01492de-c15d-4c68-b516-0720533a15ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177781688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.177781688
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3816622558
Short name T734
Test name
Test status
Simulation time 1874278004 ps
CPU time 5.98 seconds
Started May 12 01:04:41 PM PDT 24
Finished May 12 01:04:47 PM PDT 24
Peak memory 215892 kb
Host smart-a49ca25b-b338-4f42-afa5-0e123dce0db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816622558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3816622558
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2818450758
Short name T346
Test name
Test status
Simulation time 19267530 ps
CPU time 0.71 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 205372 kb
Host smart-f59c9f3f-7d42-4f25-84e3-e158f90d6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818450758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2818450758
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.322254384
Short name T481
Test name
Test status
Simulation time 71769450 ps
CPU time 0.78 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 205668 kb
Host smart-694946fc-8531-4a75-9ed0-e03c02f1311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322254384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.322254384
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1157686353
Short name T202
Test name
Test status
Simulation time 11932040695 ps
CPU time 11.98 seconds
Started May 12 01:04:40 PM PDT 24
Finished May 12 01:04:53 PM PDT 24
Peak memory 232408 kb
Host smart-ef4d079a-3f93-47a6-a068-356152fa2430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157686353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1157686353
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3556663992
Short name T333
Test name
Test status
Simulation time 12299036 ps
CPU time 0.72 seconds
Started May 12 01:04:42 PM PDT 24
Finished May 12 01:04:43 PM PDT 24
Peak memory 205288 kb
Host smart-1f2e8890-442a-460f-a43f-cb427e9da8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556663992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3556663992
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1430360407
Short name T692
Test name
Test status
Simulation time 11412708984 ps
CPU time 9.19 seconds
Started May 12 01:04:46 PM PDT 24
Finished May 12 01:04:55 PM PDT 24
Peak memory 234288 kb
Host smart-291536f3-a63f-4df4-aa68-941c1a81e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430360407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1430360407
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.622903923
Short name T570
Test name
Test status
Simulation time 17077953 ps
CPU time 0.77 seconds
Started May 12 01:04:44 PM PDT 24
Finished May 12 01:04:46 PM PDT 24
Peak memory 206332 kb
Host smart-eea9b3cc-674f-4ca3-9eec-944d03022bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622903923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.622903923
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3097027355
Short name T180
Test name
Test status
Simulation time 5399711844 ps
CPU time 38.92 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:05:23 PM PDT 24
Peak memory 251860 kb
Host smart-2882795f-d308-41b9-a232-7e27c8cf8bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097027355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3097027355
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1532359906
Short name T685
Test name
Test status
Simulation time 4800192270 ps
CPU time 87.02 seconds
Started May 12 01:04:44 PM PDT 24
Finished May 12 01:06:11 PM PDT 24
Peak memory 248972 kb
Host smart-6020c9f5-4af5-4ec4-bdc5-1782cd710988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532359906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1532359906
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2550952412
Short name T452
Test name
Test status
Simulation time 3550038632 ps
CPU time 56.84 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:05:41 PM PDT 24
Peak memory 249200 kb
Host smart-7d739d12-2b0b-4159-a848-7d9009b9cc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550952412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2550952412
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2944513807
Short name T300
Test name
Test status
Simulation time 3026906609 ps
CPU time 27.66 seconds
Started May 12 01:04:45 PM PDT 24
Finished May 12 01:05:13 PM PDT 24
Peak memory 240700 kb
Host smart-0e7f6ccf-9021-4c31-92ca-b9108106fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944513807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2944513807
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1977771198
Short name T291
Test name
Test status
Simulation time 361264894 ps
CPU time 3.99 seconds
Started May 12 01:04:46 PM PDT 24
Finished May 12 01:04:50 PM PDT 24
Peak memory 218312 kb
Host smart-69cd8da6-fc8d-4119-a9a3-e819e16140ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977771198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1977771198
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1078009117
Short name T195
Test name
Test status
Simulation time 7848209495 ps
CPU time 24.76 seconds
Started May 12 01:04:48 PM PDT 24
Finished May 12 01:05:14 PM PDT 24
Peak memory 227304 kb
Host smart-c46aa351-8e38-4d8b-8731-8e7684557825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078009117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1078009117
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2448672415
Short name T950
Test name
Test status
Simulation time 1242548535 ps
CPU time 6.36 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:04:50 PM PDT 24
Peak memory 218512 kb
Host smart-5d5815d1-7c55-4922-bf75-1f572e9c3120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448672415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2448672415
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3138839278
Short name T722
Test name
Test status
Simulation time 15890249701 ps
CPU time 9.93 seconds
Started May 12 01:04:42 PM PDT 24
Finished May 12 01:04:52 PM PDT 24
Peak memory 233444 kb
Host smart-9742ade2-8d8d-4f6d-bca6-cb2bbc6af276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138839278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3138839278
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1151375319
Short name T137
Test name
Test status
Simulation time 6488291304 ps
CPU time 17.84 seconds
Started May 12 01:04:44 PM PDT 24
Finished May 12 01:05:02 PM PDT 24
Peak memory 222788 kb
Host smart-235b4cbc-439a-4d48-94bd-9ebee9caa723
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1151375319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1151375319
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4211246987
Short name T793
Test name
Test status
Simulation time 159944999 ps
CPU time 1.1 seconds
Started May 12 01:04:48 PM PDT 24
Finished May 12 01:04:49 PM PDT 24
Peak memory 206584 kb
Host smart-ec8f172e-3cc6-4dee-921c-2b02409f1652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211246987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4211246987
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2986627996
Short name T626
Test name
Test status
Simulation time 1645649114 ps
CPU time 3.22 seconds
Started May 12 01:04:45 PM PDT 24
Finished May 12 01:04:48 PM PDT 24
Peak memory 216088 kb
Host smart-c701383a-618c-4164-80c3-7870da9cbd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986627996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2986627996
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1021204820
Short name T877
Test name
Test status
Simulation time 83320782 ps
CPU time 1.55 seconds
Started May 12 01:04:45 PM PDT 24
Finished May 12 01:04:47 PM PDT 24
Peak memory 216144 kb
Host smart-619afa44-22d9-4194-8055-90703ebf7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021204820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1021204820
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.990533075
Short name T322
Test name
Test status
Simulation time 41393203 ps
CPU time 0.72 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:04:44 PM PDT 24
Peak memory 205644 kb
Host smart-ba0a995b-bdaa-49c0-9f7d-e2f20dd096ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990533075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.990533075
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3751969592
Short name T55
Test name
Test status
Simulation time 4516223231 ps
CPU time 10.27 seconds
Started May 12 01:04:43 PM PDT 24
Finished May 12 01:04:54 PM PDT 24
Peak memory 234560 kb
Host smart-b781a338-798b-44eb-83b5-cfc840f716dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751969592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3751969592
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2315056247
Short name T906
Test name
Test status
Simulation time 15031824 ps
CPU time 0.74 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:01:50 PM PDT 24
Peak memory 205288 kb
Host smart-f72af3ba-e67f-4b3b-80c5-570f2302ac89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315056247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
315056247
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3132013026
Short name T650
Test name
Test status
Simulation time 107774112 ps
CPU time 2.5 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:01:52 PM PDT 24
Peak memory 220788 kb
Host smart-47439501-8d3e-4d1d-b433-54a71a80fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132013026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3132013026
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3786725818
Short name T701
Test name
Test status
Simulation time 61565437 ps
CPU time 0.74 seconds
Started May 12 01:01:43 PM PDT 24
Finished May 12 01:01:45 PM PDT 24
Peak memory 206368 kb
Host smart-719c335e-23e9-48e5-a12f-b44d0b252bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786725818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3786725818
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4105894663
Short name T713
Test name
Test status
Simulation time 19519563504 ps
CPU time 151.41 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:04:21 PM PDT 24
Peak memory 240876 kb
Host smart-99a2866d-434b-4216-abcf-c6f71d6fbb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105894663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4105894663
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3121780682
Short name T738
Test name
Test status
Simulation time 3409504750 ps
CPU time 47.28 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:02:36 PM PDT 24
Peak memory 249084 kb
Host smart-86d122cd-cd74-490a-afce-8ba35375c72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121780682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3121780682
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1572260479
Short name T52
Test name
Test status
Simulation time 8898323975 ps
CPU time 44.5 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 248912 kb
Host smart-e0cef091-4418-4e24-9b93-3cb274a81fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572260479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1572260479
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1509689711
Short name T700
Test name
Test status
Simulation time 429151256 ps
CPU time 4.87 seconds
Started May 12 01:01:47 PM PDT 24
Finished May 12 01:01:53 PM PDT 24
Peak memory 224184 kb
Host smart-cfa6360b-35b7-4597-a19a-15f6229ddd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509689711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1509689711
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1995157100
Short name T290
Test name
Test status
Simulation time 248914381 ps
CPU time 5.24 seconds
Started May 12 01:01:47 PM PDT 24
Finished May 12 01:01:53 PM PDT 24
Peak memory 232452 kb
Host smart-98ae7026-93ec-4557-8462-18e4a5bf90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995157100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1995157100
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4149666082
Short name T951
Test name
Test status
Simulation time 4359127870 ps
CPU time 24.98 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:02:14 PM PDT 24
Peak memory 237712 kb
Host smart-180f3773-4825-44f1-9aca-fd50fd097176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149666082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4149666082
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.723873694
Short name T252
Test name
Test status
Simulation time 2980378787 ps
CPU time 7.58 seconds
Started May 12 01:01:49 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 219412 kb
Host smart-0f79f33d-a986-4e29-8af1-cedc5e31eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723873694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
723873694
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2152819203
Short name T92
Test name
Test status
Simulation time 4679331569 ps
CPU time 15.12 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:02:03 PM PDT 24
Peak memory 219500 kb
Host smart-efdacc7c-5c34-4002-83c8-398a3771f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152819203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2152819203
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3370735699
Short name T574
Test name
Test status
Simulation time 794435681 ps
CPU time 5.34 seconds
Started May 12 01:01:49 PM PDT 24
Finished May 12 01:01:55 PM PDT 24
Peak memory 222360 kb
Host smart-27c19cfd-386a-4806-9c78-d719f3eca41a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3370735699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3370735699
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.962458968
Short name T487
Test name
Test status
Simulation time 5767012207 ps
CPU time 19.26 seconds
Started May 12 01:01:50 PM PDT 24
Finished May 12 01:02:09 PM PDT 24
Peak memory 216228 kb
Host smart-0a3b2537-21af-4042-88a1-65a7cbef2c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962458968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.962458968
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2296485093
Short name T609
Test name
Test status
Simulation time 10183034295 ps
CPU time 8.3 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 215912 kb
Host smart-99902611-1377-4b11-924e-a350f7303d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296485093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2296485093
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.836451065
Short name T528
Test name
Test status
Simulation time 22989793 ps
CPU time 0.92 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:01:50 PM PDT 24
Peak memory 206300 kb
Host smart-c7efbc79-4dd1-451a-89ee-3ba9ba4c113a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836451065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.836451065
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4249552640
Short name T623
Test name
Test status
Simulation time 49806779 ps
CPU time 0.75 seconds
Started May 12 01:01:48 PM PDT 24
Finished May 12 01:01:49 PM PDT 24
Peak memory 205572 kb
Host smart-d156f4ba-384e-402a-a301-ccbc7d11daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249552640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4249552640
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3597671259
Short name T91
Test name
Test status
Simulation time 974677299 ps
CPU time 4.92 seconds
Started May 12 01:01:51 PM PDT 24
Finished May 12 01:01:56 PM PDT 24
Peak memory 235136 kb
Host smart-3b5b85cb-4866-4673-8f23-09cff5332c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597671259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3597671259
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3396812347
Short name T337
Test name
Test status
Simulation time 32862569 ps
CPU time 0.7 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:03 PM PDT 24
Peak memory 205260 kb
Host smart-867ff6fd-bfd9-4668-9f80-3b04e8ac19f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396812347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
396812347
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1843335312
Short name T819
Test name
Test status
Simulation time 3296821800 ps
CPU time 4.64 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:07 PM PDT 24
Peak memory 233464 kb
Host smart-7fcd6035-4319-4f84-9a1f-84d04f80dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843335312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1843335312
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1442344323
Short name T495
Test name
Test status
Simulation time 22058552 ps
CPU time 0.76 seconds
Started May 12 01:01:51 PM PDT 24
Finished May 12 01:01:53 PM PDT 24
Peak memory 206340 kb
Host smart-e38782b6-482e-49b8-a42a-cef083099b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442344323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1442344323
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3294677928
Short name T299
Test name
Test status
Simulation time 367192791 ps
CPU time 9.18 seconds
Started May 12 01:01:55 PM PDT 24
Finished May 12 01:02:05 PM PDT 24
Peak memory 224552 kb
Host smart-dc6ec192-5ea0-4f44-b8fb-c7ff8899c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294677928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3294677928
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3936151703
Short name T698
Test name
Test status
Simulation time 9809135721 ps
CPU time 77.91 seconds
Started May 12 01:02:01 PM PDT 24
Finished May 12 01:03:20 PM PDT 24
Peak memory 249052 kb
Host smart-c395e260-f193-4d1a-8b85-f37c42a54c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936151703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3936151703
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4147503762
Short name T539
Test name
Test status
Simulation time 21365872425 ps
CPU time 182.75 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:05:05 PM PDT 24
Peak memory 249024 kb
Host smart-2aecb0fe-95b8-424a-ae66-95492c5fa12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147503762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4147503762
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2836611181
Short name T863
Test name
Test status
Simulation time 142206751 ps
CPU time 2.94 seconds
Started May 12 01:01:53 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 224192 kb
Host smart-ec3a2336-ea1f-4b53-ad96-98c922de9d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836611181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2836611181
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.188439473
Short name T504
Test name
Test status
Simulation time 127460725 ps
CPU time 3.13 seconds
Started May 12 01:01:54 PM PDT 24
Finished May 12 01:01:58 PM PDT 24
Peak memory 233940 kb
Host smart-480c694d-8143-40eb-b11a-2f333195a358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188439473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.188439473
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1703436552
Short name T907
Test name
Test status
Simulation time 7048912905 ps
CPU time 62.11 seconds
Started May 12 01:01:53 PM PDT 24
Finished May 12 01:02:57 PM PDT 24
Peak memory 245884 kb
Host smart-0bd5edbe-4587-4cef-af2d-d068c40b5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703436552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1703436552
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2965900057
Short name T870
Test name
Test status
Simulation time 485130211 ps
CPU time 3.56 seconds
Started May 12 01:01:52 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 233772 kb
Host smart-fc2d7613-f37b-4859-a8e6-249ba34e11b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965900057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2965900057
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4083638438
Short name T335
Test name
Test status
Simulation time 104269007 ps
CPU time 2.38 seconds
Started May 12 01:01:54 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 221148 kb
Host smart-243eba52-bef4-4ac5-b96e-a812af793d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083638438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4083638438
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2077872167
Short name T135
Test name
Test status
Simulation time 867659737 ps
CPU time 11.72 seconds
Started May 12 01:01:55 PM PDT 24
Finished May 12 01:02:07 PM PDT 24
Peak memory 220160 kb
Host smart-3c9f2680-4093-4655-9a5a-03401ef31ba7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077872167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2077872167
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3602804667
Short name T20
Test name
Test status
Simulation time 162012427 ps
CPU time 1.03 seconds
Started May 12 01:01:54 PM PDT 24
Finished May 12 01:01:56 PM PDT 24
Peak memory 206932 kb
Host smart-106a31be-9fd5-4912-adfd-e7a22b6f01a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602804667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3602804667
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1132792250
Short name T464
Test name
Test status
Simulation time 30080378311 ps
CPU time 44.83 seconds
Started May 12 01:01:49 PM PDT 24
Finished May 12 01:02:34 PM PDT 24
Peak memory 216300 kb
Host smart-dce705d4-fe79-403b-a664-0417a6eb3faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132792250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1132792250
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.795648610
Short name T625
Test name
Test status
Simulation time 29640339098 ps
CPU time 17.79 seconds
Started May 12 01:01:47 PM PDT 24
Finished May 12 01:02:06 PM PDT 24
Peak memory 216056 kb
Host smart-d0a97826-1a0d-4a28-979f-d5ffcaf33c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795648610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.795648610
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3216460568
Short name T896
Test name
Test status
Simulation time 451832330 ps
CPU time 1.5 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:04 PM PDT 24
Peak memory 207880 kb
Host smart-17fde14f-d494-4951-b00f-e44b8dcb8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216460568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3216460568
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1090178026
Short name T621
Test name
Test status
Simulation time 16999267 ps
CPU time 0.72 seconds
Started May 12 01:01:52 PM PDT 24
Finished May 12 01:01:54 PM PDT 24
Peak memory 205548 kb
Host smart-99a88cc1-4b6f-4db2-a5f7-b0b1e66819de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090178026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1090178026
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2341568166
Short name T31
Test name
Test status
Simulation time 5330433864 ps
CPU time 10.05 seconds
Started May 12 01:02:01 PM PDT 24
Finished May 12 01:02:12 PM PDT 24
Peak memory 234220 kb
Host smart-ca65b3a3-d694-4e44-9091-ed935479f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341568166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2341568166
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.923795181
Short name T607
Test name
Test status
Simulation time 40608579 ps
CPU time 0.69 seconds
Started May 12 01:02:04 PM PDT 24
Finished May 12 01:02:05 PM PDT 24
Peak memory 205536 kb
Host smart-b13dfc7c-7357-4849-bad1-37493f90cd27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923795181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.923795181
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3458030245
Short name T320
Test name
Test status
Simulation time 57032319 ps
CPU time 2.46 seconds
Started May 12 01:01:59 PM PDT 24
Finished May 12 01:02:02 PM PDT 24
Peak memory 220840 kb
Host smart-d6b972e5-4382-48cf-8b0f-dfc3f86dab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458030245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3458030245
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.44430468
Short name T56
Test name
Test status
Simulation time 42465572 ps
CPU time 0.83 seconds
Started May 12 01:01:56 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 206724 kb
Host smart-6608db74-6df2-4145-a9a9-ab16c57082d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44430468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.44430468
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3175310669
Short name T27
Test name
Test status
Simulation time 13108229582 ps
CPU time 62.93 seconds
Started May 12 01:01:58 PM PDT 24
Finished May 12 01:03:01 PM PDT 24
Peak memory 264912 kb
Host smart-e927c038-e68e-41e5-a2ce-9ac9ece96b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175310669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3175310669
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.684614028
Short name T161
Test name
Test status
Simulation time 125535582210 ps
CPU time 103.95 seconds
Started May 12 01:01:58 PM PDT 24
Finished May 12 01:03:42 PM PDT 24
Peak memory 251048 kb
Host smart-b4f3b3f6-7948-4fcb-910e-3d198f048f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684614028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.684614028
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1098157936
Short name T240
Test name
Test status
Simulation time 24617785730 ps
CPU time 228.94 seconds
Started May 12 01:01:58 PM PDT 24
Finished May 12 01:05:47 PM PDT 24
Peak memory 264804 kb
Host smart-d8f231b4-4e68-4b57-92cb-ae3514f0ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098157936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1098157936
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1687169058
Short name T475
Test name
Test status
Simulation time 4886866287 ps
CPU time 69.72 seconds
Started May 12 01:01:57 PM PDT 24
Finished May 12 01:03:07 PM PDT 24
Peak memory 232468 kb
Host smart-033b1865-8148-42c4-ac68-6a11b0dc47fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687169058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1687169058
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4160742063
Short name T373
Test name
Test status
Simulation time 1201502304 ps
CPU time 7.42 seconds
Started May 12 01:02:05 PM PDT 24
Finished May 12 01:02:13 PM PDT 24
Peak memory 234792 kb
Host smart-abd23151-934e-41b2-b164-6f868d6395c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160742063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4160742063
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1150006861
Short name T823
Test name
Test status
Simulation time 23803805018 ps
CPU time 20.14 seconds
Started May 12 01:01:59 PM PDT 24
Finished May 12 01:02:20 PM PDT 24
Peak memory 240512 kb
Host smart-d4340f65-0860-410e-86b3-90508464c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150006861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1150006861
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3554413937
Short name T875
Test name
Test status
Simulation time 306190365 ps
CPU time 5.02 seconds
Started May 12 01:01:53 PM PDT 24
Finished May 12 01:01:59 PM PDT 24
Peak memory 234744 kb
Host smart-3bd702aa-536c-461c-80e1-038d280eef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554413937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3554413937
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3537233042
Short name T287
Test name
Test status
Simulation time 15486713786 ps
CPU time 12.59 seconds
Started May 12 01:01:54 PM PDT 24
Finished May 12 01:02:07 PM PDT 24
Peak memory 223612 kb
Host smart-f4097edd-1604-46ae-93fa-b06db0f6921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537233042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3537233042
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.728467656
Short name T404
Test name
Test status
Simulation time 572064256 ps
CPU time 9.58 seconds
Started May 12 01:02:00 PM PDT 24
Finished May 12 01:02:10 PM PDT 24
Peak memory 221856 kb
Host smart-b334c186-756f-4ad9-a3d9-a1a13265ddc0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=728467656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.728467656
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2287826724
Short name T382
Test name
Test status
Simulation time 247331423 ps
CPU time 4.67 seconds
Started May 12 01:01:52 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 216396 kb
Host smart-e1479dee-c1a6-4462-aeeb-35895667a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287826724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2287826724
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3472106018
Short name T801
Test name
Test status
Simulation time 35141354 ps
CPU time 0.7 seconds
Started May 12 01:01:53 PM PDT 24
Finished May 12 01:01:54 PM PDT 24
Peak memory 205488 kb
Host smart-233d4d0c-a70e-49b2-87b3-5fffedb93c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472106018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3472106018
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1867142630
Short name T385
Test name
Test status
Simulation time 668778307 ps
CPU time 2.24 seconds
Started May 12 01:01:53 PM PDT 24
Finished May 12 01:01:56 PM PDT 24
Peak memory 216096 kb
Host smart-519c9448-037e-4044-8e98-0b641b587a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867142630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1867142630
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2101643156
Short name T70
Test name
Test status
Simulation time 45259445 ps
CPU time 0.7 seconds
Started May 12 01:01:53 PM PDT 24
Finished May 12 01:01:55 PM PDT 24
Peak memory 205332 kb
Host smart-8d9d2cef-85c6-44b6-bac4-55dbb8d7c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101643156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2101643156
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1767730339
Short name T538
Test name
Test status
Simulation time 3854601655 ps
CPU time 8.96 seconds
Started May 12 01:01:58 PM PDT 24
Finished May 12 01:02:08 PM PDT 24
Peak memory 234464 kb
Host smart-74204df0-f3b3-41a6-b08c-f0c5432247b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767730339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1767730339
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4029615885
Short name T568
Test name
Test status
Simulation time 10857060 ps
CPU time 0.79 seconds
Started May 12 01:02:04 PM PDT 24
Finished May 12 01:02:05 PM PDT 24
Peak memory 205160 kb
Host smart-07068480-3c12-4e82-8315-43cb9a9acb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029615885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
029615885
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4252331171
Short name T602
Test name
Test status
Simulation time 36103573 ps
CPU time 2.43 seconds
Started May 12 01:02:03 PM PDT 24
Finished May 12 01:02:06 PM PDT 24
Peak memory 232460 kb
Host smart-bb39befc-145c-4498-a6d7-10a6f3cf3591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252331171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4252331171
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1294796025
Short name T694
Test name
Test status
Simulation time 16569635 ps
CPU time 0.78 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:04 PM PDT 24
Peak memory 206408 kb
Host smart-30e79559-2c83-4dab-979d-6d5191c74dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294796025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1294796025
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1661261198
Short name T297
Test name
Test status
Simulation time 49416260245 ps
CPU time 81.91 seconds
Started May 12 01:02:03 PM PDT 24
Finished May 12 01:03:26 PM PDT 24
Peak memory 232524 kb
Host smart-a88bc422-1fe7-4246-8ae0-aa4c2ea32691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661261198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1661261198
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.570887867
Short name T818
Test name
Test status
Simulation time 10152712612 ps
CPU time 48.83 seconds
Started May 12 01:02:01 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 239436 kb
Host smart-b6a7dd10-6ff8-4f82-85b6-83dfe785bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570887867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.570887867
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.867394970
Short name T247
Test name
Test status
Simulation time 1737282337 ps
CPU time 20.27 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:30 PM PDT 24
Peak memory 221940 kb
Host smart-27c8be95-d9ee-466c-9328-ab3afd706273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867394970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
867394970
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1597143294
Short name T597
Test name
Test status
Simulation time 439220952 ps
CPU time 3.01 seconds
Started May 12 01:02:05 PM PDT 24
Finished May 12 01:02:08 PM PDT 24
Peak memory 224192 kb
Host smart-9ed82043-05a0-4d6f-93ba-97d079f24c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597143294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1597143294
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.872224060
Short name T814
Test name
Test status
Simulation time 985818640 ps
CPU time 13.65 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:17 PM PDT 24
Peak memory 220928 kb
Host smart-b1def013-828f-4e75-989c-b05a24705001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872224060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.872224060
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.416806238
Short name T428
Test name
Test status
Simulation time 295276294 ps
CPU time 4.62 seconds
Started May 12 01:02:03 PM PDT 24
Finished May 12 01:02:08 PM PDT 24
Peak memory 235144 kb
Host smart-cf3768d9-e712-465b-bc12-47ddabd1b6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416806238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.416806238
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2418581912
Short name T741
Test name
Test status
Simulation time 274054358 ps
CPU time 3.98 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:07 PM PDT 24
Peak memory 224392 kb
Host smart-62928038-e780-4faf-9df0-d4fa4cb38f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418581912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2418581912
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3814957718
Short name T531
Test name
Test status
Simulation time 1301658502 ps
CPU time 9.23 seconds
Started May 12 01:02:01 PM PDT 24
Finished May 12 01:02:11 PM PDT 24
Peak memory 235828 kb
Host smart-f58de6f1-c90c-4903-8fa6-a3378a560f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814957718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3814957718
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2114611937
Short name T40
Test name
Test status
Simulation time 91204339 ps
CPU time 4.14 seconds
Started May 12 01:02:03 PM PDT 24
Finished May 12 01:02:08 PM PDT 24
Peak memory 218600 kb
Host smart-0840bea1-d511-4cc1-b985-41faf6ba7ee5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2114611937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2114611937
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.820168537
Short name T584
Test name
Test status
Simulation time 201941592 ps
CPU time 1.2 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:04 PM PDT 24
Peak memory 206948 kb
Host smart-90dc44ab-f9ae-41ba-9470-37bfbc34865d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820168537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.820168537
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.775827372
Short name T517
Test name
Test status
Simulation time 5024982172 ps
CPU time 27.81 seconds
Started May 12 01:01:58 PM PDT 24
Finished May 12 01:02:26 PM PDT 24
Peak memory 216440 kb
Host smart-a76404ca-0de5-412f-8338-2a1a2370f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775827372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.775827372
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.160967525
Short name T77
Test name
Test status
Simulation time 4478795413 ps
CPU time 15.39 seconds
Started May 12 01:01:57 PM PDT 24
Finished May 12 01:02:13 PM PDT 24
Peak memory 216064 kb
Host smart-3fe7300a-8b1b-46fa-b000-e796df07e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160967525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.160967525
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2547877417
Short name T347
Test name
Test status
Simulation time 76503031 ps
CPU time 1.12 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:04 PM PDT 24
Peak memory 207796 kb
Host smart-394d5225-705c-42ce-b554-8cc03202316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547877417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2547877417
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1809677349
Short name T912
Test name
Test status
Simulation time 102582794 ps
CPU time 1.02 seconds
Started May 12 01:01:58 PM PDT 24
Finished May 12 01:01:59 PM PDT 24
Peak memory 205684 kb
Host smart-4ec018dd-be12-40b9-998c-dc6d1ef44c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809677349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1809677349
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2287179314
Short name T541
Test name
Test status
Simulation time 23120681538 ps
CPU time 20.45 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:30 PM PDT 24
Peak memory 230204 kb
Host smart-d396cb7d-4577-4c90-a512-540703a667e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287179314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2287179314
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3133536290
Short name T934
Test name
Test status
Simulation time 52429892 ps
CPU time 0.74 seconds
Started May 12 01:02:10 PM PDT 24
Finished May 12 01:02:11 PM PDT 24
Peak memory 205852 kb
Host smart-95508886-f50a-4cab-8ef3-994c3198ffe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133536290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
133536290
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3387968942
Short name T463
Test name
Test status
Simulation time 219574399 ps
CPU time 3.97 seconds
Started May 12 01:02:10 PM PDT 24
Finished May 12 01:02:14 PM PDT 24
Peak memory 218144 kb
Host smart-f9346c01-1e5c-4a98-81d7-a45a404b2d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387968942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3387968942
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2306282566
Short name T638
Test name
Test status
Simulation time 15170467 ps
CPU time 0.78 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:10 PM PDT 24
Peak memory 206672 kb
Host smart-befe2218-43c8-4d2f-b496-3512501b35cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306282566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2306282566
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1268337343
Short name T905
Test name
Test status
Simulation time 118186651682 ps
CPU time 406.95 seconds
Started May 12 01:02:13 PM PDT 24
Finished May 12 01:09:01 PM PDT 24
Peak memory 240796 kb
Host smart-1cde967d-353a-460b-8ad0-4ba3ca166d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268337343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1268337343
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2756912612
Short name T636
Test name
Test status
Simulation time 3706769553 ps
CPU time 40.55 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:51 PM PDT 24
Peak memory 232536 kb
Host smart-fedc4c61-09ce-40c4-8a22-378c45fa6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756912612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2756912612
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3505538453
Short name T23
Test name
Test status
Simulation time 130751814693 ps
CPU time 314.54 seconds
Started May 12 01:02:07 PM PDT 24
Finished May 12 01:07:22 PM PDT 24
Peak memory 261620 kb
Host smart-bd13e3e9-5b19-4090-80db-86b6964911ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505538453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3505538453
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4196228277
Short name T944
Test name
Test status
Simulation time 2957182333 ps
CPU time 12.93 seconds
Started May 12 01:02:11 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 240672 kb
Host smart-f260bb15-3219-407c-b884-616fe43130db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196228277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4196228277
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2017636702
Short name T645
Test name
Test status
Simulation time 205097888 ps
CPU time 4.68 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:15 PM PDT 24
Peak memory 218204 kb
Host smart-21200d36-6379-424f-8f66-cd0677ab48d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017636702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2017636702
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.634780414
Short name T207
Test name
Test status
Simulation time 917068216 ps
CPU time 15.85 seconds
Started May 12 01:02:08 PM PDT 24
Finished May 12 01:02:25 PM PDT 24
Peak memory 232452 kb
Host smart-3709e327-b76e-4089-abe0-161bf44eb85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634780414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.634780414
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.72223090
Short name T520
Test name
Test status
Simulation time 1360967388 ps
CPU time 6.13 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:16 PM PDT 24
Peak memory 238120 kb
Host smart-cc4291a3-e413-471b-9128-2674a1e22cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72223090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.72223090
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2764922355
Short name T652
Test name
Test status
Simulation time 322217012 ps
CPU time 5.6 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:15 PM PDT 24
Peak memory 224232 kb
Host smart-4fa957ac-6c6c-4693-a17a-e19fb82a0579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764922355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2764922355
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1875794167
Short name T642
Test name
Test status
Simulation time 731931969 ps
CPU time 10.33 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:02:21 PM PDT 24
Peak memory 219548 kb
Host smart-41279717-2879-4b4f-a4a9-92ae64559cca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1875794167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1875794167
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.281316567
Short name T150
Test name
Test status
Simulation time 253651164262 ps
CPU time 373.25 seconds
Started May 12 01:02:09 PM PDT 24
Finished May 12 01:08:23 PM PDT 24
Peak memory 265388 kb
Host smart-6995a376-9915-4f3c-8ded-9929b71493f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281316567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.281316567
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1522379445
Short name T745
Test name
Test status
Simulation time 13632880788 ps
CPU time 18.41 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:21 PM PDT 24
Peak memory 216124 kb
Host smart-12aefb18-96af-4250-b4f4-161a8355374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522379445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1522379445
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2732397828
Short name T391
Test name
Test status
Simulation time 10842706013 ps
CPU time 9.13 seconds
Started May 12 01:02:03 PM PDT 24
Finished May 12 01:02:13 PM PDT 24
Peak memory 216024 kb
Host smart-584cb9a3-1004-4034-bfca-bd18daa33df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732397828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2732397828
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2569967307
Short name T358
Test name
Test status
Simulation time 31998362 ps
CPU time 0.98 seconds
Started May 12 01:02:05 PM PDT 24
Finished May 12 01:02:06 PM PDT 24
Peak memory 206712 kb
Host smart-53488fbb-3c16-4160-86aa-bf18b76c5d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569967307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2569967307
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.290903020
Short name T836
Test name
Test status
Simulation time 122140240 ps
CPU time 0.82 seconds
Started May 12 01:02:02 PM PDT 24
Finished May 12 01:02:04 PM PDT 24
Peak memory 205688 kb
Host smart-5fe4def6-df77-4258-856c-bfe0e87846ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290903020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.290903020
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.558081487
Short name T558
Test name
Test status
Simulation time 19798938886 ps
CPU time 17.74 seconds
Started May 12 01:02:05 PM PDT 24
Finished May 12 01:02:24 PM PDT 24
Peak memory 233836 kb
Host smart-6848d267-0000-4192-ab67-9d4ddc08fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558081487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.558081487
Directory /workspace/9.spi_device_upload/latest
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