Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3682229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3849427

1

T1

1177

T3

1383

T4

4700

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4293526	1			T1	84		T2	1		T3	992
values[0x0]	1617980	1			T1	586		T3	454		T4	446
values[0x1]	1620150	1			T1	551		T3	436		T4	460

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2604455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4927201

1

T1

1189

T2

1

T3

1485

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	38668	1			T4	52		T5	30		T6	1
valid_sources[0x01]	29886	1			T4	25		T5	32		T11	3
valid_sources[0x02]	26483	1			T4	23		T5	29		T6	6
valid_sources[0x03]	27818	1			T4	30		T5	29		T6	6
valid_sources[0x04]	27962	1			T4	25		T5	41		T6	4
valid_sources[0x05]	28860	1			T4	24		T5	41		T6	3
valid_sources[0x06]	31884	1			T4	40		T5	23		T6	2
valid_sources[0x07]	27923	1			T4	24		T5	19		T11	6
valid_sources[0x08]	26435	1			T4	27		T5	29		T11	5
valid_sources[0x09]	28855	1			T4	33		T5	39		T6	1
valid_sources[0x0a]	31265	1			T4	39		T5	35		T6	5
valid_sources[0x0b]	31529	1			T4	31		T5	24		T6	1
valid_sources[0x0c]	31550	1			T4	41		T5	27		T6	1
valid_sources[0x0d]	44697	1			T4	23		T5	27		T6	4
valid_sources[0x0e]	28260	1			T4	34		T5	25		T6	4
valid_sources[0x0f]	28245	1			T4	30		T5	29		T6	4
valid_sources[0x10]	27654	1			T4	24		T5	30		T6	6
valid_sources[0x11]	28245	1			T4	35		T5	32		T6	6
valid_sources[0x12]	28064	1			T4	45		T5	27		T6	5
valid_sources[0x13]	29666	1			T4	37		T5	33		T6	8
valid_sources[0x14]	28659	1			T4	63		T5	39		T6	4
valid_sources[0x15]	29222	1			T4	52		T5	22		T6	2
valid_sources[0x16]	28074	1			T4	40		T5	27		T6	5
valid_sources[0x17]	28535	1			T4	34		T5	23		T6	4
valid_sources[0x18]	27527	1			T4	36		T5	34		T6	4
valid_sources[0x19]	28252	1			T4	29		T5	21		T6	7
valid_sources[0x1a]	30434	1			T4	44		T5	40		T6	2
valid_sources[0x1b]	28323	1			T4	42		T5	29		T6	4
valid_sources[0x1c]	28397	1			T4	31		T5	28		T6	7
valid_sources[0x1d]	27617	1			T4	31		T5	33		T6	2
valid_sources[0x1e]	29543	1			T4	30		T5	36		T6	2
valid_sources[0x1f]	33806	1			T4	26		T5	30		T6	4
valid_sources[0x20]	27613	1			T4	36		T5	26		T6	4
valid_sources[0x21]	27402	1			T4	29		T5	33		T6	7
valid_sources[0x22]	27019	1			T4	35		T5	46		T6	5
valid_sources[0x23]	28616	1			T4	34		T5	36		T6	11
valid_sources[0x24]	29522	1			T4	28		T5	33		T6	4
valid_sources[0x25]	27848	1			T4	29		T5	31		T6	2
valid_sources[0x26]	34892	1			T4	39		T5	25		T6	6
valid_sources[0x27]	31258	1			T4	34		T5	29		T11	3
valid_sources[0x28]	27743	1			T4	30		T5	27		T6	4
valid_sources[0x29]	28317	1			T4	41		T5	32		T6	2
valid_sources[0x2a]	31350	1			T4	27		T5	33		T6	1
valid_sources[0x2b]	29421	1			T4	28		T5	34		T6	4
valid_sources[0x2c]	30392	1			T4	38		T5	24		T6	4
valid_sources[0x2d]	32011	1			T4	40		T5	47		T6	6
valid_sources[0x2e]	26711	1			T4	36		T5	35		T6	2
valid_sources[0x2f]	26459	1			T4	45		T5	26		T6	6
valid_sources[0x30]	26496	1			T4	44		T5	34		T6	2
valid_sources[0x31]	29246	1			T4	30		T5	35		T6	5
valid_sources[0x32]	31433	1			T4	18		T5	27		T6	3
valid_sources[0x33]	29871	1			T4	22		T5	31		T6	5
valid_sources[0x34]	27892	1			T4	34		T5	45		T6	2
valid_sources[0x35]	26221	1			T4	43		T5	40		T6	6
valid_sources[0x36]	27068	1			T1	451		T4	43		T5	26
valid_sources[0x37]	28572	1			T4	17		T5	23		T6	4
valid_sources[0x38]	27788	1			T4	45		T5	23		T6	3
valid_sources[0x39]	27845	1			T4	29		T5	19		T6	6
valid_sources[0x3a]	27457	1			T4	23		T5	28		T6	6
valid_sources[0x3b]	28229	1			T4	26		T5	32		T6	1
valid_sources[0x3c]	27302	1			T3	8		T4	29		T5	33
valid_sources[0x3d]	27288	1			T4	40		T5	24		T6	3
valid_sources[0x3e]	27354	1			T4	32		T5	29		T6	6
valid_sources[0x3f]	28239	1			T4	49		T5	23		T6	6
valid_sources[0x40]	28907	1			T4	36		T5	19		T6	5
valid_sources[0x41]	26037	1			T4	44		T5	19		T6	5
valid_sources[0x42]	30523	1			T3	103		T4	52		T5	34
valid_sources[0x43]	31677	1			T4	43		T5	50		T6	3
valid_sources[0x44]	27209	1			T4	31		T5	31		T6	8
valid_sources[0x45]	27175	1			T4	31		T5	31		T6	2
valid_sources[0x46]	28383	1			T4	42		T5	27		T6	5
valid_sources[0x47]	30500	1			T4	33		T5	33		T11	4
valid_sources[0x48]	28545	1			T4	46		T5	33		T6	4
valid_sources[0x49]	27058	1			T4	38		T5	33		T6	4
valid_sources[0x4a]	27750	1			T4	39		T5	36		T6	2
valid_sources[0x4b]	35368	1			T4	22		T5	28		T6	1
valid_sources[0x4c]	29631	1			T4	35		T5	26		T6	2
valid_sources[0x4d]	28005	1			T4	57		T5	39		T6	4
valid_sources[0x4e]	29580	1			T4	23		T5	30		T6	6
valid_sources[0x4f]	29391	1			T4	42		T5	30		T6	7
valid_sources[0x50]	26049	1			T4	40		T5	31		T6	5
valid_sources[0x51]	28668	1			T4	33		T5	25		T6	6
valid_sources[0x52]	27876	1			T4	23		T5	35		T6	3
valid_sources[0x53]	33261	1			T4	35		T5	46		T6	4
valid_sources[0x54]	27971	1			T4	31		T5	21		T6	3
valid_sources[0x55]	26017	1			T4	36		T5	26		T6	2
valid_sources[0x56]	29130	1			T4	47		T5	39		T6	7
valid_sources[0x57]	31704	1			T4	29		T5	30		T6	1
valid_sources[0x58]	28470	1			T4	45		T5	35		T6	3
valid_sources[0x59]	29862	1			T4	19		T5	25		T6	3
valid_sources[0x5a]	27701	1			T4	32		T5	28		T6	3
valid_sources[0x5b]	29569	1			T4	36		T5	34		T6	3
valid_sources[0x5c]	28009	1			T4	38		T5	35		T6	9
valid_sources[0x5d]	28237	1			T4	27		T5	27		T6	1
valid_sources[0x5e]	28775	1			T2	1		T4	38		T5	35
valid_sources[0x5f]	27235	1			T1	455		T4	24		T5	40
valid_sources[0x60]	29271	1			T4	36		T5	33		T6	4
valid_sources[0x61]	28495	1			T4	36		T5	28		T11	6
valid_sources[0x62]	29077	1			T4	38		T5	39		T6	4
valid_sources[0x63]	28830	1			T4	33		T5	39		T6	2
valid_sources[0x64]	50885	1			T4	49		T5	34		T6	4
valid_sources[0x65]	27227	1			T4	17		T5	43		T6	3
valid_sources[0x66]	35610	1			T4	24		T5	32		T6	2
valid_sources[0x67]	29507	1			T4	31		T5	29		T6	1
valid_sources[0x68]	29163	1			T4	29		T5	40		T6	4
valid_sources[0x69]	29522	1			T4	30		T5	34		T6	6
valid_sources[0x6a]	26372	1			T4	20		T5	29		T6	3
valid_sources[0x6b]	28772	1			T4	30		T5	17		T6	1
valid_sources[0x6c]	31545	1			T4	27		T5	25		T6	2
valid_sources[0x6d]	29030	1			T4	35		T5	33		T6	11
valid_sources[0x6e]	28536	1			T4	44		T5	25		T6	2
valid_sources[0x6f]	28477	1			T4	24		T5	26		T6	4
valid_sources[0x70]	27767	1			T4	25		T5	21		T6	2
valid_sources[0x71]	28442	1			T4	38		T5	29		T6	3
valid_sources[0x72]	30919	1			T1	179		T4	41		T5	17
valid_sources[0x73]	29330	1			T4	38		T5	27		T6	3
valid_sources[0x74]	32325	1			T4	24		T5	27		T6	3
valid_sources[0x75]	30226	1			T4	27		T5	38		T6	8
valid_sources[0x76]	27674	1			T4	30		T5	19		T6	3
valid_sources[0x77]	28633	1			T4	36		T5	39		T6	7
valid_sources[0x78]	30010	1			T4	24		T5	34		T6	1
valid_sources[0x79]	30990	1			T4	33		T5	27		T6	6
valid_sources[0x7a]	35870	1			T4	29		T5	22		T6	1
valid_sources[0x7b]	28826	1			T4	25		T5	35		T6	3
valid_sources[0x7c]	31887	1			T4	28		T5	28		T6	4
valid_sources[0x7d]	26438	1			T4	37		T5	33		T6	3
valid_sources[0x7e]	30089	1			T4	39		T5	30		T6	1
valid_sources[0x7f]	33118	1			T4	29		T5	26		T6	5
valid_sources[0x80]	27904	1			T4	35		T5	37		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

966118

1

T1

46

T3

504

T4

3799

values[0x0]

all_enables

biggest_size

1454034

1

T1

584

T3

450

T4

446

values[0x1]

all_enables

biggest_size

1429275

1

T1

547

T3

429

T4

455