Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3704367

1

T1

44

T2

1

T3

499

full_word

3850602

1

T1

1177

T3

1383

T4

4700

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7554569	1			T1	1221		T2	1		T3	1882
auto[TlIntgErrCmd]	146	1			T70	7		T96	6		T97	16
auto[TlIntgErrData]	117	1			T70	7		T96	6		T97	5
auto[TlIntgErrBoth]	137	1			T70	16		T96	8		T97	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4296779

1

T1

84

T2

1

T3

992

auto[1]

3258190

1

T1

1137

T3

890

T4

906

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3330256	1			T1	38		T2	1		T3	488
auto[TlIntgErrNone]	partial	auto[1]	373745	1			T1	6		T3	11		T4	5
auto[TlIntgErrNone]	full_word	auto[0]	966359	1			T1	46		T3	504		T4	3799
auto[TlIntgErrNone]	full_word	auto[1]	2884209	1			T1	1131		T3	879		T4	901
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T70	2		T96	4		T97	7
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T70	5		T96	2		T97	8
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T146	1		T275	1		T276	3
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T97	1		T146	2		T277	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T70	3		T96	2		T97	2
auto[TlIntgErrData]	partial	auto[1]	61	1			T70	3		T96	2		T97	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T70	1		T97	1		T278	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T96	2		T146	1		T279	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T70	5		T96	2		T97	5
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T70	10		T96	5		T97	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T70	1		T96	1		T275	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T280	1		T281	2		-	-