Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.04	94.37	69.17			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	129152066	17994551	0	0
DepthKnown_A	129152066	95646406	0	0
RvalidKnown_A	129152066	95646406	0	0
WreadyKnown_A	129152066	95646406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	129152066	17994551	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	17994551	0	0
T1	9396	6937	0	0
T3	21324	19739	0	0
T4	173585	0	0	0
T5	180880	0	0	0
T6	153657	7712	0	0
T7	4392	0	0	0
T9	28084	0	0	0
T11	19520	9636	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	0	65319	0	0
T24	0	70548	0	0
T31	0	10506	0	0
T32	0	14689	0	0
T33	0	96132	0	0
T48	0	20836	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	17994551	0	0
T1	9396	6937	0	0
T3	21324	19739	0	0
T4	173585	0	0	0
T5	180880	0	0	0
T6	153657	7712	0	0
T7	4392	0	0	0
T9	28084	0	0	0
T11	19520	9636	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	0	65319	0	0
T24	0	70548	0	0
T31	0	10506	0	0
T32	0	14689	0	0
T33	0	96132	0	0
T48	0	20836	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	129152066	18921771	0	0
DepthKnown_A	129152066	95646406	0	0
RvalidKnown_A	129152066	95646406	0	0
WreadyKnown_A	129152066	95646406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	129152066	18921771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	18921771	0	0
T1	9396	7220	0	0
T3	21324	20626	0	0
T4	173585	0	0	0
T5	180880	0	0	0
T6	153657	8214	0	0
T7	4392	0	0	0
T9	28084	0	0	0
T11	19520	11004	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	0	67834	0	0
T24	0	73896	0	0
T31	0	12000	0	0
T32	0	15592	0	0
T33	0	99782	0	0
T48	0	21756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	18921771	0	0
T1	9396	7220	0	0
T3	21324	20626	0	0
T4	173585	0	0	0
T5	180880	0	0	0
T6	153657	8214	0	0
T7	4392	0	0	0
T9	28084	0	0	0
T11	19520	11004	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	0	67834	0	0
T24	0	73896	0	0
T31	0	12000	0	0
T32	0	15592	0	0
T33	0	99782	0	0
T48	0	21756	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	129152066	0	0	0
DepthKnown_A	129152066	95646406	0	0
RvalidKnown_A	129152066	95646406	0	0
WreadyKnown_A	129152066	95646406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	129152066	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T17

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T17
1	0	Not Covered
1	1	Covered	T7,T15,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T15,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T15,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T15,T19
1	0	1	Covered	T7,T15,T19
1	1	0	Not Covered
1	1	1	Covered	T7,T15,T19

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T19

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T19

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T19
1	0	Covered	T7,T15,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T15,T17
0	0	Covered	T7,T15,T17

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T19
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	129152066	6452890	0	0
DepthKnown_A	129152066	32203293	0	0
RvalidKnown_A	129152066	32203293	0	0
WreadyKnown_A	129152066	32203293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	129152066	6452890	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	6452890	0	0
T7	4392	1136	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	72180	0	0
T17	1051	0	0	0
T19	0	27116	0	0
T20	0	9937	0	0
T22	0	41790	0	0
T28	0	35140	0	0
T29	0	23970	0	0
T30	0	57950	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	611	0	0
T51	0	24848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	6452890	0	0
T7	4392	1136	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	72180	0	0
T17	1051	0	0	0
T19	0	27116	0	0
T20	0	9937	0	0
T22	0	41790	0	0
T28	0	35140	0	0
T29	0	23970	0	0
T30	0	57950	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	611	0	0
T51	0	24848	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T17

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T17
1	0	Not Covered
1	1	Covered	T7,T15,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T15,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T15,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T15,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T15,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T15,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T15,T17
0	0	Covered	T7,T15,T17

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T19
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	129152066	207318	0	0
DepthKnown_A	129152066	32203293	0	0
RvalidKnown_A	129152066	32203293	0	0
WreadyKnown_A	129152066	32203293	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	129152066	207318	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	207318	0	0
T7	4392	38	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	2325	0	0
T17	1051	0	0	0
T19	0	874	0	0
T20	0	321	0	0
T22	0	1342	0	0
T28	0	1128	0	0
T29	0	762	0	0
T30	0	1865	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	20	0	0
T51	0	795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	207318	0	0
T7	4392	38	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	2325	0	0
T17	1051	0	0	0
T19	0	874	0	0
T20	0	321	0	0
T22	0	1342	0	0
T28	0	1128	0	0
T29	0	762	0	0
T30	0	1865	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	20	0	0
T51	0	795	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400930895	2411198	0	0
DepthKnown_A	400930895	400848440	0	0
RvalidKnown_A	400930895	400848440	0	0
WreadyKnown_A	400930895	400848440	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	400930895	2411198	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	2411198	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	2690	0	0
T4	177261	837	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	0	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	2610	0	0
T13	0	832	0	0
T14	0	20412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	2411198	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	2690	0	0
T4	177261	837	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	0	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	2610	0	0
T13	0	832	0	0
T14	0	20412	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400930895	0	0	0
DepthKnown_A	400930895	400848440	0	0
RvalidKnown_A	400930895	400848440	0	0
WreadyKnown_A	400930895	400848440	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	400930895	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400930895	0	0	0
DepthKnown_A	400930895	400848440	0	0
RvalidKnown_A	400930895	400848440	0	0
WreadyKnown_A	400930895	400848440	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	400930895	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T14,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T24,T19
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T14,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T14,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400930895	362052	0	0
DepthKnown_A	400930895	400848440	0	0
RvalidKnown_A	400930895	400848440	0	0
WreadyKnown_A	400930895	400848440	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	400930895	362052	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	362052	0	0
T7	2941	36	0	0
T8	1757	0	0	0
T9	86908	0	0	0
T10	1088	0	0	0
T11	22991	0	0	0
T12	84780	0	0	0
T13	176013	0	0	0
T14	292297	1609	0	0
T15	0	1052	0	0
T19	0	615	0	0
T20	0	237	0	0
T22	0	3971	0	0
T24	0	322	0	0
T28	0	512	0	0
T29	0	723	0	0
T30	0	4691	0	0
T31	45396	0	0	0
T32	27439	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	362052	0	0
T7	2941	36	0	0
T8	1757	0	0	0
T9	86908	0	0	0
T10	1088	0	0	0
T11	22991	0	0	0
T12	84780	0	0	0
T13	176013	0	0	0
T14	292297	1609	0	0
T15	0	1052	0	0
T19	0	615	0	0
T20	0	237	0	0
T22	0	3971	0	0
T24	0	322	0	0
T28	0	512	0	0
T29	0	723	0	0
T30	0	4691	0	0
T31	45396	0	0	0
T32	27439	0	0	0