Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T15,T19
1	0	Covered	T7,T15,T19

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T17
1	0	Unreachable
1	1	Covered	T7,T15,T19

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T24,T19

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T24,T19
1	0	Covered	T14,T24,T19

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T14,T24,T19

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T14,T15
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	659235027	528698139	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	659235027	3056434	0	0
GntImpliesValid_A	659235027	3056434	0	0
GrantKnown_A	659235027	528698139	0	0
IdxKnown_A	659235027	528698139	0	0
IndexIsCorrect_A	659235027	3056434	0	0
LockArbDecision_A	659235027	0	0	0
NoReadyValidNoGrant_A	659235027	0	0	0
ReadyAndValidImplyGrant_A	659235027	3056434	0	0
ReqAndReadyImplyGrant_A	659235027	3056434	0	0
ReqImpliesValid_A	659235027	3056434	0	0
ReqStaysHighUntilGranted0_M	659235027	0	0	0
RoundRobin_A	659235027	5	0	906
ValidKnown_A	659235027	528698139	0	0
gen_data_port_assertion.DataFlow_A	659235027	3056434	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	528698139	0	0
T1	15131	15068	0	0
T2	5666	4008	0	0
T3	199239	198783	0	0
T4	350846	350648	0	0
T5	364992	364910	0	0
T6	617239	616766	0	0
T7	11725	7277	0	0
T8	1757	1682	0	0
T9	143076	114931	0	0
T10	1088	1011	0	0
T11	39040	19520	0	0
T12	49796	24608	0	0
T13	115200	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	528698139	0	0
T1	15131	15068	0	0
T2	5666	4008	0	0
T3	199239	198783	0	0
T4	350846	350648	0	0
T5	364992	364910	0	0
T6	617239	616766	0	0
T7	11725	7277	0	0
T8	1757	1682	0	0
T9	143076	114931	0	0
T10	1088	1011	0	0
T11	39040	19520	0	0
T12	49796	24608	0	0
T13	115200	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	528698139	0	0
T1	15131	15068	0	0
T2	5666	4008	0	0
T3	199239	198783	0	0
T4	350846	350648	0	0
T5	364992	364910	0	0
T6	617239	616766	0	0
T7	11725	7277	0	0
T8	1757	1682	0	0
T9	143076	114931	0	0
T10	1088	1011	0	0
T11	39040	19520	0	0
T12	49796	24608	0	0
T13	115200	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	5	0	906
T53	104222	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	78597	0	0	1
T59	8041	0	0	1
T60	301915	0	0	1
T61	1150	0	0	1
T62	1388	0	0	1
T63	34499	0	0	1
T64	935878	0	0	1
T65	1375	0	0	1
T66	4270	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	528698139	0	0
T1	15131	15068	0	0
T2	5666	4008	0	0
T3	199239	198783	0	0
T4	350846	350648	0	0
T5	364992	364910	0	0
T6	617239	616766	0	0
T7	11725	7277	0	0
T8	1757	1682	0	0
T9	143076	114931	0	0
T10	1088	1011	0	0
T11	39040	19520	0	0
T12	49796	24608	0	0
T13	115200	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659235027	3056434	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	7333	251	0	0
T8	1757	0	0	0
T9	114992	832	0	0
T10	1088	0	0	0
T11	19520	832	0	0
T12	24898	832	0	0
T13	57600	832	0	0
T14	956258	1984	0	0
T15	301506	6584	0	0
T17	2102	0	0	0
T19	0	3361	0	0
T20	0	1253	0	0
T22	0	6435	0	0
T24	304059	648	0	0
T28	0	3226	0	0
T29	0	3662	0	0
T30	0	5954	0	0
T31	331348	0	0	0
T32	32204	0	0	0
T33	170734	0	0	0
T48	22076	0	0	0
T50	0	196	0	0
T51	0	2721	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T15,T19
1	0	Covered	T7,T15,T19

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T17
1	0	Unreachable
1	1	Covered	T7,T15,T19

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T15,T19
0	0	1	Unreachable
0	0	0	Covered	T7,T15,T17

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129152066	32203293	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	129152066	700128	0	0
GntImpliesValid_A	129152066	700128	0	0
GrantKnown_A	129152066	32203293	0	0
IdxKnown_A	129152066	32203293	0	0
IndexIsCorrect_A	129152066	700128	0	0
LockArbDecision_A	129152066	0	0	0
NoReadyValidNoGrant_A	129152066	0	0	0
ReadyAndValidImplyGrant_A	129152066	700128	0	0
ReqAndReadyImplyGrant_A	129152066	700128	0	0
ReqImpliesValid_A	129152066	700128	0	0
ReqStaysHighUntilGranted0_M	129152066	0	0	0
RoundRobin_A	129152066	0	0	0
ValidKnown_A	129152066	32203293	0	0
gen_data_port_assertion.DataFlow_A	129152066	700128	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	32203293	0	0
T7	4392	4392	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	143784	0	0
T17	1051	1008	0	0
T18	0	216	0	0
T19	0	124296	0	0
T20	0	64856	0	0
T22	0	150216	0	0
T28	0	355232	0	0
T29	0	127656	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T52	0	108184	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	700128	0	0
T7	4392	177	0	0
T9	28084	0	0	0
T11	19520	0	0	0
T12	24898	0	0	0
T13	57600	0	0	0
T14	478129	0	0	0
T15	150753	6584	0	0
T17	1051	0	0	0
T19	0	2964	0	0
T20	0	1251	0	0
T22	0	6027	0	0
T28	0	3205	0	0
T29	0	3662	0	0
T30	0	5646	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T50	0	196	0	0
T51	0	2199	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T24,T19

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T24,T19
1	0	Covered	T14,T24,T19

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T14,T24,T19

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T24,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T14,T24,T19
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T24,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T24,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129152066	95646406	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	129152066	453744	0	0
GntImpliesValid_A	129152066	453744	0	0
GrantKnown_A	129152066	95646406	0	0
IdxKnown_A	129152066	95646406	0	0
IndexIsCorrect_A	129152066	453744	0	0
LockArbDecision_A	129152066	0	0	0
NoReadyValidNoGrant_A	129152066	0	0	0
ReadyAndValidImplyGrant_A	129152066	453744	0	0
ReqAndReadyImplyGrant_A	129152066	453744	0	0
ReqImpliesValid_A	129152066	453744	0	0
ReqStaysHighUntilGranted0_M	129152066	0	0	0
RoundRobin_A	129152066	0	0	0
ValidKnown_A	129152066	95646406	0	0
gen_data_port_assertion.DataFlow_A	129152066	453744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	95646406	0	0
T1	9396	9396	0	0
T3	21324	20922	0	0
T4	173585	173472	0	0
T5	180880	180880	0	0
T6	153657	153262	0	0
T7	4392	0	0	0
T9	28084	28084	0	0
T11	19520	19520	0	0
T12	24898	24608	0	0
T13	57600	57600	0	0
T14	0	473272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129152066	453744	0	0
T14	478129	1984	0	0
T15	150753	0	0	0
T17	1051	0	0	0
T18	251	0	0	0
T19	289651	397	0	0
T20	0	2	0	0
T22	0	408	0	0
T24	304059	648	0	0
T28	0	21	0	0
T30	0	308	0	0
T31	165674	0	0	0
T32	16102	0	0	0
T33	170734	0	0	0
T34	0	7	0	0
T48	22076	0	0	0
T51	0	522	0	0
T67	0	524	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T14,T15
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400930895	400848440	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	400930895	1902562	0	0
GntImpliesValid_A	400930895	1902562	0	0
GrantKnown_A	400930895	400848440	0	0
IdxKnown_A	400930895	400848440	0	0
IndexIsCorrect_A	400930895	1902562	0	0
LockArbDecision_A	400930895	0	0	0
NoReadyValidNoGrant_A	400930895	0	0	0
ReadyAndValidImplyGrant_A	400930895	1902562	0	0
ReqAndReadyImplyGrant_A	400930895	1902562	0	0
ReqImpliesValid_A	400930895	1902562	0	0
ReqStaysHighUntilGranted0_M	400930895	0	0	0
RoundRobin_A	400930895	5	0	906
ValidKnown_A	400930895	400848440	0	0
gen_data_port_assertion.DataFlow_A	400930895	1902562	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	5	0	906
T53	104222	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	78597	0	0	1
T59	8041	0	0	1
T60	301915	0	0	1
T61	1150	0	0	1
T62	1388	0	0	1
T63	34499	0	0	1
T64	935878	0	0	1
T65	1375	0	0	1
T66	4270	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	400848440	0	0
T1	5735	5672	0	0
T2	5666	4008	0	0
T3	177915	177861	0	0
T4	177261	177176	0	0
T5	184112	184030	0	0
T6	463582	463504	0	0
T7	2941	2885	0	0
T8	1757	1682	0	0
T9	86908	86847	0	0
T10	1088	1011	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400930895	1902562	0	0
T1	5735	1088	0	0
T2	5666	0	0	0
T3	177915	832	0	0
T4	177261	832	0	0
T5	184112	832	0	0
T6	463582	832	0	0
T7	2941	74	0	0
T8	1757	0	0	0
T9	86908	832	0	0
T10	1088	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0