Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
3729 |
0 |
0 |
T69 |
11151 |
3 |
0 |
0 |
T70 |
29060 |
2 |
0 |
0 |
T71 |
4505 |
99 |
0 |
0 |
T95 |
4268 |
177 |
0 |
0 |
T96 |
18852 |
3 |
0 |
0 |
T98 |
13850 |
125 |
0 |
0 |
T101 |
13874 |
201 |
0 |
0 |
T102 |
15241 |
204 |
0 |
0 |
T103 |
14979 |
274 |
0 |
0 |
T107 |
12507 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1665 |
0 |
0 |
T69 |
11151 |
18 |
0 |
0 |
T97 |
94087 |
47 |
0 |
0 |
T106 |
5826 |
4 |
0 |
0 |
T111 |
7264 |
13 |
0 |
0 |
T142 |
156728 |
249 |
0 |
0 |
T143 |
15183 |
8 |
0 |
0 |
T144 |
9659 |
10 |
0 |
0 |
T145 |
38094 |
18 |
0 |
0 |
T146 |
99705 |
114 |
0 |
0 |
T147 |
5489 |
8 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1707 |
0 |
0 |
T69 |
11151 |
23 |
0 |
0 |
T82 |
3480 |
5 |
0 |
0 |
T97 |
94087 |
57 |
0 |
0 |
T106 |
5826 |
1 |
0 |
0 |
T111 |
7264 |
4 |
0 |
0 |
T142 |
156728 |
297 |
0 |
0 |
T143 |
15183 |
23 |
0 |
0 |
T144 |
9659 |
19 |
0 |
0 |
T145 |
38094 |
48 |
0 |
0 |
T146 |
99705 |
122 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
2048 |
0 |
0 |
T69 |
11151 |
26 |
0 |
0 |
T97 |
94087 |
150 |
0 |
0 |
T106 |
5826 |
17 |
0 |
0 |
T111 |
7264 |
14 |
0 |
0 |
T142 |
156728 |
266 |
0 |
0 |
T143 |
15183 |
17 |
0 |
0 |
T145 |
38094 |
76 |
0 |
0 |
T146 |
99705 |
197 |
0 |
0 |
T147 |
5489 |
15 |
0 |
0 |
T148 |
20143 |
41 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
8847 |
0 |
0 |
T69 |
11151 |
122 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
1051 |
0 |
0 |
T106 |
5826 |
8 |
0 |
0 |
T111 |
7264 |
273 |
0 |
0 |
T142 |
156728 |
234 |
0 |
0 |
T143 |
15183 |
135 |
0 |
0 |
T144 |
9659 |
62 |
0 |
0 |
T145 |
38094 |
685 |
0 |
0 |
T146 |
99705 |
1285 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
8828 |
0 |
0 |
T69 |
11151 |
20 |
0 |
0 |
T97 |
94087 |
1258 |
0 |
0 |
T106 |
5826 |
125 |
0 |
0 |
T111 |
7264 |
241 |
0 |
0 |
T142 |
156728 |
278 |
0 |
0 |
T143 |
15183 |
254 |
0 |
0 |
T144 |
9659 |
29 |
0 |
0 |
T145 |
38094 |
525 |
0 |
0 |
T146 |
99705 |
1517 |
0 |
0 |
T147 |
5489 |
117 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
9172 |
0 |
0 |
T69 |
11151 |
106 |
0 |
0 |
T97 |
94087 |
1246 |
0 |
0 |
T106 |
5826 |
125 |
0 |
0 |
T111 |
7264 |
1 |
0 |
0 |
T142 |
156728 |
269 |
0 |
0 |
T143 |
15183 |
11 |
0 |
0 |
T144 |
9659 |
76 |
0 |
0 |
T145 |
38094 |
663 |
0 |
0 |
T146 |
99705 |
1946 |
0 |
0 |
T147 |
5489 |
9 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
8782 |
0 |
0 |
T69 |
11151 |
18 |
0 |
0 |
T82 |
3480 |
9 |
0 |
0 |
T97 |
94087 |
1233 |
0 |
0 |
T106 |
5826 |
130 |
0 |
0 |
T111 |
7264 |
123 |
0 |
0 |
T142 |
156728 |
283 |
0 |
0 |
T143 |
15183 |
94 |
0 |
0 |
T144 |
9659 |
136 |
0 |
0 |
T145 |
38094 |
446 |
0 |
0 |
T146 |
99705 |
2540 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
10180 |
0 |
0 |
T69 |
11151 |
116 |
0 |
0 |
T97 |
94087 |
1372 |
0 |
0 |
T106 |
5826 |
8 |
0 |
0 |
T111 |
7264 |
96 |
0 |
0 |
T142 |
156728 |
235 |
0 |
0 |
T143 |
15183 |
345 |
0 |
0 |
T144 |
9659 |
92 |
0 |
0 |
T145 |
38094 |
875 |
0 |
0 |
T146 |
99705 |
2245 |
0 |
0 |
T147 |
5489 |
156 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
9130 |
0 |
0 |
T69 |
11151 |
205 |
0 |
0 |
T82 |
3480 |
5 |
0 |
0 |
T97 |
94087 |
1011 |
0 |
0 |
T106 |
5826 |
146 |
0 |
0 |
T111 |
7264 |
126 |
0 |
0 |
T142 |
156728 |
279 |
0 |
0 |
T143 |
15183 |
372 |
0 |
0 |
T144 |
9659 |
125 |
0 |
0 |
T145 |
38094 |
606 |
0 |
0 |
T146 |
99705 |
1499 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
8466 |
0 |
0 |
T69 |
11151 |
14 |
0 |
0 |
T82 |
3480 |
5 |
0 |
0 |
T97 |
94087 |
1229 |
0 |
0 |
T106 |
5826 |
8 |
0 |
0 |
T111 |
7264 |
13 |
0 |
0 |
T142 |
156728 |
260 |
0 |
0 |
T143 |
15183 |
116 |
0 |
0 |
T144 |
9659 |
51 |
0 |
0 |
T145 |
38094 |
1093 |
0 |
0 |
T146 |
99705 |
1837 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
9226 |
0 |
0 |
T69 |
11151 |
266 |
0 |
0 |
T82 |
3480 |
7 |
0 |
0 |
T97 |
94087 |
876 |
0 |
0 |
T100 |
10187 |
7 |
0 |
0 |
T106 |
5826 |
135 |
0 |
0 |
T111 |
7264 |
5 |
0 |
0 |
T142 |
156728 |
264 |
0 |
0 |
T143 |
15183 |
216 |
0 |
0 |
T144 |
9659 |
83 |
0 |
0 |
T145 |
38094 |
870 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4329 |
0 |
0 |
T69 |
11151 |
54 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
383 |
0 |
0 |
T106 |
5826 |
3 |
0 |
0 |
T111 |
7264 |
42 |
0 |
0 |
T142 |
156728 |
251 |
0 |
0 |
T143 |
15183 |
44 |
0 |
0 |
T144 |
9659 |
9 |
0 |
0 |
T145 |
38094 |
239 |
0 |
0 |
T146 |
99705 |
823 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4148 |
0 |
0 |
T69 |
11151 |
112 |
0 |
0 |
T97 |
94087 |
278 |
0 |
0 |
T106 |
5826 |
5 |
0 |
0 |
T111 |
7264 |
97 |
0 |
0 |
T142 |
156728 |
285 |
0 |
0 |
T143 |
15183 |
48 |
0 |
0 |
T144 |
9659 |
14 |
0 |
0 |
T145 |
38094 |
57 |
0 |
0 |
T146 |
99705 |
799 |
0 |
0 |
T147 |
5489 |
8 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4713 |
0 |
0 |
T69 |
11151 |
112 |
0 |
0 |
T97 |
94087 |
503 |
0 |
0 |
T101 |
13874 |
1 |
0 |
0 |
T106 |
5826 |
46 |
0 |
0 |
T111 |
7264 |
110 |
0 |
0 |
T142 |
156728 |
280 |
0 |
0 |
T143 |
15183 |
97 |
0 |
0 |
T144 |
9659 |
48 |
0 |
0 |
T145 |
38094 |
155 |
0 |
0 |
T146 |
99705 |
846 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4552 |
0 |
0 |
T69 |
11151 |
94 |
0 |
0 |
T97 |
94087 |
346 |
0 |
0 |
T106 |
5826 |
8 |
0 |
0 |
T111 |
7264 |
58 |
0 |
0 |
T142 |
156728 |
280 |
0 |
0 |
T143 |
15183 |
22 |
0 |
0 |
T144 |
9659 |
29 |
0 |
0 |
T145 |
38094 |
350 |
0 |
0 |
T146 |
99705 |
874 |
0 |
0 |
T147 |
5489 |
55 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4353 |
0 |
0 |
T69 |
11151 |
48 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
430 |
0 |
0 |
T106 |
5826 |
47 |
0 |
0 |
T111 |
7264 |
103 |
0 |
0 |
T142 |
156728 |
259 |
0 |
0 |
T143 |
15183 |
66 |
0 |
0 |
T144 |
9659 |
27 |
0 |
0 |
T145 |
38094 |
192 |
0 |
0 |
T146 |
99705 |
685 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4691 |
0 |
0 |
T69 |
11151 |
123 |
0 |
0 |
T97 |
94087 |
524 |
0 |
0 |
T106 |
5826 |
61 |
0 |
0 |
T111 |
7264 |
92 |
0 |
0 |
T142 |
156728 |
277 |
0 |
0 |
T143 |
15183 |
94 |
0 |
0 |
T144 |
9659 |
3 |
0 |
0 |
T145 |
38094 |
367 |
0 |
0 |
T146 |
99705 |
878 |
0 |
0 |
T147 |
5489 |
5 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4195 |
0 |
0 |
T69 |
11151 |
112 |
0 |
0 |
T82 |
3480 |
13 |
0 |
0 |
T97 |
94087 |
449 |
0 |
0 |
T103 |
14979 |
7 |
0 |
0 |
T106 |
5826 |
36 |
0 |
0 |
T111 |
7264 |
8 |
0 |
0 |
T142 |
156728 |
285 |
0 |
0 |
T143 |
15183 |
113 |
0 |
0 |
T144 |
9659 |
58 |
0 |
0 |
T145 |
38094 |
196 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4881 |
0 |
0 |
T69 |
11151 |
74 |
0 |
0 |
T82 |
3480 |
9 |
0 |
0 |
T97 |
94087 |
532 |
0 |
0 |
T103 |
14979 |
1 |
0 |
0 |
T106 |
5826 |
58 |
0 |
0 |
T111 |
7264 |
7 |
0 |
0 |
T142 |
156728 |
260 |
0 |
0 |
T143 |
15183 |
68 |
0 |
0 |
T144 |
9659 |
73 |
0 |
0 |
T145 |
38094 |
298 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4301 |
0 |
0 |
T69 |
11151 |
62 |
0 |
0 |
T82 |
3480 |
3 |
0 |
0 |
T97 |
94087 |
410 |
0 |
0 |
T106 |
5826 |
9 |
0 |
0 |
T111 |
7264 |
10 |
0 |
0 |
T142 |
156728 |
312 |
0 |
0 |
T143 |
15183 |
77 |
0 |
0 |
T144 |
9659 |
23 |
0 |
0 |
T145 |
38094 |
258 |
0 |
0 |
T146 |
99705 |
784 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
3882 |
0 |
0 |
T69 |
11151 |
56 |
0 |
0 |
T97 |
94087 |
318 |
0 |
0 |
T106 |
5826 |
3 |
0 |
0 |
T111 |
7264 |
115 |
0 |
0 |
T142 |
156728 |
276 |
0 |
0 |
T143 |
15183 |
56 |
0 |
0 |
T144 |
9659 |
39 |
0 |
0 |
T145 |
38094 |
224 |
0 |
0 |
T146 |
99705 |
697 |
0 |
0 |
T147 |
5489 |
57 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4416 |
0 |
0 |
T69 |
11151 |
82 |
0 |
0 |
T82 |
3480 |
3 |
0 |
0 |
T97 |
94087 |
228 |
0 |
0 |
T98 |
13850 |
5 |
0 |
0 |
T106 |
5826 |
6 |
0 |
0 |
T111 |
7264 |
61 |
0 |
0 |
T142 |
156728 |
309 |
0 |
0 |
T143 |
15183 |
20 |
0 |
0 |
T144 |
9659 |
46 |
0 |
0 |
T145 |
38094 |
259 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4412 |
0 |
0 |
T69 |
11151 |
53 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
542 |
0 |
0 |
T106 |
5826 |
6 |
0 |
0 |
T111 |
7264 |
43 |
0 |
0 |
T142 |
156728 |
226 |
0 |
0 |
T143 |
15183 |
48 |
0 |
0 |
T144 |
9659 |
56 |
0 |
0 |
T145 |
38094 |
298 |
0 |
0 |
T146 |
99705 |
802 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4860 |
0 |
0 |
T69 |
11151 |
75 |
0 |
0 |
T97 |
94087 |
535 |
0 |
0 |
T106 |
5826 |
60 |
0 |
0 |
T111 |
7264 |
11 |
0 |
0 |
T142 |
156728 |
279 |
0 |
0 |
T143 |
15183 |
177 |
0 |
0 |
T144 |
9659 |
54 |
0 |
0 |
T145 |
38094 |
232 |
0 |
0 |
T146 |
99705 |
913 |
0 |
0 |
T147 |
5489 |
7 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4689 |
0 |
0 |
T69 |
11151 |
43 |
0 |
0 |
T82 |
3480 |
13 |
0 |
0 |
T97 |
94087 |
351 |
0 |
0 |
T106 |
5826 |
57 |
0 |
0 |
T111 |
7264 |
53 |
0 |
0 |
T142 |
156728 |
298 |
0 |
0 |
T143 |
15183 |
146 |
0 |
0 |
T144 |
9659 |
48 |
0 |
0 |
T145 |
38094 |
346 |
0 |
0 |
T146 |
99705 |
906 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
5144 |
0 |
0 |
T69 |
11151 |
59 |
0 |
0 |
T82 |
3480 |
5 |
0 |
0 |
T97 |
94087 |
474 |
0 |
0 |
T98 |
13850 |
4 |
0 |
0 |
T106 |
5826 |
57 |
0 |
0 |
T111 |
7264 |
53 |
0 |
0 |
T142 |
156728 |
263 |
0 |
0 |
T143 |
15183 |
74 |
0 |
0 |
T144 |
9659 |
54 |
0 |
0 |
T145 |
38094 |
342 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4818 |
0 |
0 |
T69 |
11151 |
64 |
0 |
0 |
T82 |
3480 |
3 |
0 |
0 |
T97 |
94087 |
634 |
0 |
0 |
T103 |
14979 |
1 |
0 |
0 |
T106 |
5826 |
82 |
0 |
0 |
T111 |
7264 |
31 |
0 |
0 |
T142 |
156728 |
230 |
0 |
0 |
T143 |
15183 |
105 |
0 |
0 |
T145 |
38094 |
295 |
0 |
0 |
T146 |
99705 |
840 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4905 |
0 |
0 |
T69 |
11151 |
12 |
0 |
0 |
T82 |
3480 |
9 |
0 |
0 |
T97 |
94087 |
273 |
0 |
0 |
T106 |
5826 |
70 |
0 |
0 |
T111 |
7264 |
56 |
0 |
0 |
T142 |
156728 |
311 |
0 |
0 |
T143 |
15183 |
126 |
0 |
0 |
T144 |
9659 |
28 |
0 |
0 |
T145 |
38094 |
379 |
0 |
0 |
T146 |
99705 |
824 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4318 |
0 |
0 |
T69 |
11151 |
106 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
449 |
0 |
0 |
T106 |
5826 |
43 |
0 |
0 |
T111 |
7264 |
13 |
0 |
0 |
T142 |
156728 |
252 |
0 |
0 |
T143 |
15183 |
59 |
0 |
0 |
T144 |
9659 |
14 |
0 |
0 |
T145 |
38094 |
341 |
0 |
0 |
T146 |
99705 |
952 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4338 |
0 |
0 |
T69 |
11151 |
54 |
0 |
0 |
T97 |
94087 |
453 |
0 |
0 |
T106 |
5826 |
46 |
0 |
0 |
T111 |
7264 |
64 |
0 |
0 |
T142 |
156728 |
263 |
0 |
0 |
T143 |
15183 |
132 |
0 |
0 |
T144 |
9659 |
41 |
0 |
0 |
T145 |
38094 |
299 |
0 |
0 |
T146 |
99705 |
723 |
0 |
0 |
T147 |
5489 |
58 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4557 |
0 |
0 |
T69 |
11151 |
84 |
0 |
0 |
T82 |
3480 |
5 |
0 |
0 |
T97 |
94087 |
387 |
0 |
0 |
T106 |
5826 |
2 |
0 |
0 |
T111 |
7264 |
39 |
0 |
0 |
T142 |
156728 |
262 |
0 |
0 |
T143 |
15183 |
161 |
0 |
0 |
T144 |
9659 |
31 |
0 |
0 |
T145 |
38094 |
305 |
0 |
0 |
T146 |
99705 |
618 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4038 |
0 |
0 |
T69 |
11151 |
61 |
0 |
0 |
T82 |
3480 |
10 |
0 |
0 |
T97 |
94087 |
440 |
0 |
0 |
T106 |
5826 |
60 |
0 |
0 |
T111 |
7264 |
60 |
0 |
0 |
T142 |
156728 |
274 |
0 |
0 |
T143 |
15183 |
20 |
0 |
0 |
T144 |
9659 |
2 |
0 |
0 |
T145 |
38094 |
189 |
0 |
0 |
T146 |
99705 |
389 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4575 |
0 |
0 |
T69 |
11151 |
22 |
0 |
0 |
T82 |
3480 |
4 |
0 |
0 |
T97 |
94087 |
534 |
0 |
0 |
T103 |
14979 |
5 |
0 |
0 |
T106 |
5826 |
5 |
0 |
0 |
T111 |
7264 |
42 |
0 |
0 |
T142 |
156728 |
222 |
0 |
0 |
T143 |
15183 |
75 |
0 |
0 |
T144 |
9659 |
71 |
0 |
0 |
T145 |
38094 |
232 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4509 |
0 |
0 |
T69 |
11151 |
81 |
0 |
0 |
T82 |
3480 |
1 |
0 |
0 |
T97 |
94087 |
548 |
0 |
0 |
T98 |
13850 |
1 |
0 |
0 |
T106 |
5826 |
54 |
0 |
0 |
T111 |
7264 |
83 |
0 |
0 |
T142 |
156728 |
293 |
0 |
0 |
T143 |
15183 |
55 |
0 |
0 |
T144 |
9659 |
13 |
0 |
0 |
T145 |
38094 |
270 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
4291 |
0 |
0 |
T69 |
11151 |
17 |
0 |
0 |
T82 |
3480 |
7 |
0 |
0 |
T97 |
94087 |
455 |
0 |
0 |
T106 |
5826 |
10 |
0 |
0 |
T111 |
7264 |
14 |
0 |
0 |
T142 |
156728 |
243 |
0 |
0 |
T143 |
15183 |
28 |
0 |
0 |
T144 |
9659 |
57 |
0 |
0 |
T145 |
38094 |
317 |
0 |
0 |
T146 |
99705 |
735 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1919 |
0 |
0 |
T69 |
11151 |
20 |
0 |
0 |
T82 |
3480 |
8 |
0 |
0 |
T97 |
94087 |
99 |
0 |
0 |
T106 |
5826 |
8 |
0 |
0 |
T111 |
7264 |
16 |
0 |
0 |
T142 |
156728 |
284 |
0 |
0 |
T143 |
15183 |
32 |
0 |
0 |
T144 |
9659 |
4 |
0 |
0 |
T145 |
38094 |
44 |
0 |
0 |
T146 |
99705 |
161 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1914 |
0 |
0 |
T69 |
11151 |
7 |
0 |
0 |
T97 |
94087 |
88 |
0 |
0 |
T98 |
13850 |
8 |
0 |
0 |
T104 |
21723 |
9 |
0 |
0 |
T106 |
5826 |
10 |
0 |
0 |
T111 |
7264 |
13 |
0 |
0 |
T142 |
156728 |
281 |
0 |
0 |
T143 |
15183 |
33 |
0 |
0 |
T144 |
9659 |
8 |
0 |
0 |
T145 |
38094 |
52 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1874 |
0 |
0 |
T69 |
11151 |
20 |
0 |
0 |
T82 |
3480 |
4 |
0 |
0 |
T97 |
94087 |
128 |
0 |
0 |
T106 |
5826 |
18 |
0 |
0 |
T111 |
7264 |
11 |
0 |
0 |
T142 |
156728 |
229 |
0 |
0 |
T143 |
15183 |
29 |
0 |
0 |
T144 |
9659 |
10 |
0 |
0 |
T145 |
38094 |
64 |
0 |
0 |
T146 |
99705 |
184 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1838 |
0 |
0 |
T69 |
11151 |
11 |
0 |
0 |
T82 |
3480 |
4 |
0 |
0 |
T97 |
94087 |
77 |
0 |
0 |
T106 |
5826 |
4 |
0 |
0 |
T111 |
7264 |
17 |
0 |
0 |
T142 |
156728 |
271 |
0 |
0 |
T143 |
15183 |
28 |
0 |
0 |
T144 |
9659 |
13 |
0 |
0 |
T145 |
38094 |
55 |
0 |
0 |
T146 |
99705 |
155 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
2288 |
0 |
0 |
T69 |
11151 |
17 |
0 |
0 |
T82 |
3480 |
1 |
0 |
0 |
T97 |
94087 |
117 |
0 |
0 |
T106 |
5826 |
21 |
0 |
0 |
T111 |
7264 |
5 |
0 |
0 |
T142 |
156728 |
283 |
0 |
0 |
T143 |
15183 |
54 |
0 |
0 |
T144 |
9659 |
12 |
0 |
0 |
T145 |
38094 |
102 |
0 |
0 |
T146 |
99705 |
296 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
3534 |
0 |
0 |
T30 |
383667 |
20 |
0 |
0 |
T42 |
0 |
22 |
0 |
0 |
T47 |
0 |
16 |
0 |
0 |
T50 |
3827 |
0 |
0 |
0 |
T73 |
0 |
41 |
0 |
0 |
T88 |
0 |
40 |
0 |
0 |
T149 |
0 |
33 |
0 |
0 |
T150 |
0 |
16 |
0 |
0 |
T151 |
0 |
11 |
0 |
0 |
T152 |
0 |
6 |
0 |
0 |
T153 |
0 |
21 |
0 |
0 |
T154 |
29090 |
0 |
0 |
0 |
T155 |
15570 |
0 |
0 |
0 |
T156 |
3976 |
0 |
0 |
0 |
T157 |
3289 |
0 |
0 |
0 |
T158 |
9914 |
0 |
0 |
0 |
T159 |
8591 |
0 |
0 |
0 |
T160 |
1799 |
0 |
0 |
0 |
T161 |
832 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1945 |
0 |
0 |
T69 |
11151 |
21 |
0 |
0 |
T82 |
3480 |
4 |
0 |
0 |
T97 |
94087 |
77 |
0 |
0 |
T104 |
21723 |
7 |
0 |
0 |
T106 |
5826 |
4 |
0 |
0 |
T111 |
7264 |
21 |
0 |
0 |
T142 |
156728 |
284 |
0 |
0 |
T143 |
15183 |
29 |
0 |
0 |
T144 |
9659 |
13 |
0 |
0 |
T145 |
38094 |
56 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1913 |
0 |
0 |
T69 |
11151 |
18 |
0 |
0 |
T97 |
94087 |
97 |
0 |
0 |
T106 |
5826 |
3 |
0 |
0 |
T111 |
7264 |
1 |
0 |
0 |
T142 |
156728 |
286 |
0 |
0 |
T143 |
15183 |
35 |
0 |
0 |
T144 |
9659 |
14 |
0 |
0 |
T145 |
38094 |
38 |
0 |
0 |
T146 |
99705 |
164 |
0 |
0 |
T147 |
5489 |
7 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1723 |
0 |
0 |
T69 |
11151 |
19 |
0 |
0 |
T82 |
3480 |
7 |
0 |
0 |
T97 |
94087 |
77 |
0 |
0 |
T106 |
5826 |
17 |
0 |
0 |
T111 |
7264 |
8 |
0 |
0 |
T142 |
156728 |
240 |
0 |
0 |
T143 |
15183 |
23 |
0 |
0 |
T144 |
9659 |
5 |
0 |
0 |
T145 |
38094 |
36 |
0 |
0 |
T146 |
99705 |
94 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1657 |
0 |
0 |
T69 |
11151 |
20 |
0 |
0 |
T82 |
3480 |
5 |
0 |
0 |
T97 |
94087 |
71 |
0 |
0 |
T103 |
14979 |
7 |
0 |
0 |
T106 |
5826 |
5 |
0 |
0 |
T111 |
7264 |
10 |
0 |
0 |
T142 |
156728 |
268 |
0 |
0 |
T143 |
15183 |
19 |
0 |
0 |
T144 |
9659 |
7 |
0 |
0 |
T145 |
38094 |
28 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1612 |
0 |
0 |
T69 |
11151 |
11 |
0 |
0 |
T82 |
3480 |
4 |
0 |
0 |
T97 |
94087 |
81 |
0 |
0 |
T106 |
5826 |
10 |
0 |
0 |
T111 |
7264 |
6 |
0 |
0 |
T142 |
156728 |
218 |
0 |
0 |
T143 |
15183 |
21 |
0 |
0 |
T144 |
9659 |
7 |
0 |
0 |
T145 |
38094 |
43 |
0 |
0 |
T146 |
99705 |
106 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1694 |
0 |
0 |
T69 |
11151 |
19 |
0 |
0 |
T97 |
94087 |
60 |
0 |
0 |
T106 |
5826 |
11 |
0 |
0 |
T111 |
7264 |
5 |
0 |
0 |
T142 |
156728 |
228 |
0 |
0 |
T143 |
15183 |
34 |
0 |
0 |
T144 |
9659 |
9 |
0 |
0 |
T145 |
38094 |
47 |
0 |
0 |
T146 |
99705 |
125 |
0 |
0 |
T147 |
5489 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
2266 |
0 |
0 |
T69 |
11151 |
27 |
0 |
0 |
T82 |
3480 |
1 |
0 |
0 |
T97 |
94087 |
129 |
0 |
0 |
T104 |
21723 |
2 |
0 |
0 |
T106 |
5826 |
1 |
0 |
0 |
T111 |
7264 |
13 |
0 |
0 |
T142 |
156728 |
263 |
0 |
0 |
T143 |
15183 |
37 |
0 |
0 |
T144 |
9659 |
9 |
0 |
0 |
T145 |
38094 |
91 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1688 |
0 |
0 |
T69 |
11151 |
14 |
0 |
0 |
T97 |
94087 |
71 |
0 |
0 |
T101 |
13874 |
1 |
0 |
0 |
T106 |
5826 |
11 |
0 |
0 |
T111 |
7264 |
13 |
0 |
0 |
T142 |
156728 |
269 |
0 |
0 |
T143 |
15183 |
25 |
0 |
0 |
T144 |
9659 |
20 |
0 |
0 |
T145 |
38094 |
45 |
0 |
0 |
T146 |
99705 |
131 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
2459 |
0 |
0 |
T69 |
11151 |
32 |
0 |
0 |
T97 |
94087 |
180 |
0 |
0 |
T106 |
5826 |
11 |
0 |
0 |
T111 |
7264 |
32 |
0 |
0 |
T142 |
156728 |
243 |
0 |
0 |
T143 |
15183 |
70 |
0 |
0 |
T144 |
9659 |
29 |
0 |
0 |
T145 |
38094 |
91 |
0 |
0 |
T146 |
99705 |
333 |
0 |
0 |
T147 |
5489 |
8 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1945 |
0 |
0 |
T69 |
11151 |
19 |
0 |
0 |
T82 |
3480 |
9 |
0 |
0 |
T97 |
94087 |
102 |
0 |
0 |
T106 |
5826 |
1 |
0 |
0 |
T111 |
7264 |
14 |
0 |
0 |
T142 |
156728 |
317 |
0 |
0 |
T143 |
15183 |
17 |
0 |
0 |
T144 |
9659 |
10 |
0 |
0 |
T145 |
38094 |
47 |
0 |
0 |
T146 |
99705 |
191 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1734 |
0 |
0 |
T69 |
11151 |
16 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
63 |
0 |
0 |
T100 |
10187 |
10 |
0 |
0 |
T102 |
15241 |
5 |
0 |
0 |
T106 |
5826 |
12 |
0 |
0 |
T111 |
7264 |
11 |
0 |
0 |
T142 |
156728 |
329 |
0 |
0 |
T143 |
15183 |
20 |
0 |
0 |
T144 |
9659 |
10 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1690 |
0 |
0 |
T69 |
11151 |
5 |
0 |
0 |
T82 |
3480 |
6 |
0 |
0 |
T97 |
94087 |
49 |
0 |
0 |
T106 |
5826 |
15 |
0 |
0 |
T111 |
7264 |
8 |
0 |
0 |
T142 |
156728 |
304 |
0 |
0 |
T143 |
15183 |
18 |
0 |
0 |
T145 |
38094 |
33 |
0 |
0 |
T146 |
99705 |
147 |
0 |
0 |
T147 |
5489 |
9 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1610 |
0 |
0 |
T69 |
11151 |
13 |
0 |
0 |
T97 |
94087 |
96 |
0 |
0 |
T106 |
5826 |
3 |
0 |
0 |
T111 |
7264 |
5 |
0 |
0 |
T142 |
156728 |
278 |
0 |
0 |
T143 |
15183 |
27 |
0 |
0 |
T144 |
9659 |
6 |
0 |
0 |
T145 |
38094 |
27 |
0 |
0 |
T146 |
99705 |
122 |
0 |
0 |
T147 |
5489 |
6 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1653 |
0 |
0 |
T69 |
11151 |
16 |
0 |
0 |
T82 |
3480 |
2 |
0 |
0 |
T97 |
94087 |
73 |
0 |
0 |
T103 |
14979 |
3 |
0 |
0 |
T106 |
5826 |
3 |
0 |
0 |
T111 |
7264 |
5 |
0 |
0 |
T142 |
156728 |
267 |
0 |
0 |
T143 |
15183 |
14 |
0 |
0 |
T144 |
9659 |
18 |
0 |
0 |
T145 |
38094 |
25 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1795 |
0 |
0 |
T69 |
11151 |
26 |
0 |
0 |
T82 |
3480 |
6 |
0 |
0 |
T97 |
94087 |
73 |
0 |
0 |
T104 |
21723 |
6 |
0 |
0 |
T106 |
5826 |
13 |
0 |
0 |
T111 |
7264 |
2 |
0 |
0 |
T142 |
156728 |
345 |
0 |
0 |
T143 |
15183 |
36 |
0 |
0 |
T145 |
38094 |
44 |
0 |
0 |
T146 |
99705 |
90 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403024826 |
1712 |
0 |
0 |
T69 |
11151 |
18 |
0 |
0 |
T82 |
3480 |
4 |
0 |
0 |
T97 |
94087 |
39 |
0 |
0 |
T106 |
5826 |
14 |
0 |
0 |
T111 |
7264 |
7 |
0 |
0 |
T142 |
156728 |
315 |
0 |
0 |
T143 |
15183 |
20 |
0 |
0 |
T144 |
9659 |
15 |
0 |
0 |
T145 |
38094 |
43 |
0 |
0 |
T146 |
99705 |
120 |
0 |
0 |