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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.90 98.30 94.11 98.61 89.36 97.06 95.83 98.07


Total test records in report: 1081
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T820 /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.782451887 May 14 01:27:31 PM PDT 24 May 14 01:27:38 PM PDT 24 519954083 ps
T821 /workspace/coverage/default/41.spi_device_csb_read.931131397 May 14 01:29:22 PM PDT 24 May 14 01:29:26 PM PDT 24 45435766 ps
T248 /workspace/coverage/default/9.spi_device_stress_all.945766341 May 14 01:27:54 PM PDT 24 May 14 01:31:33 PM PDT 24 93369703496 ps
T822 /workspace/coverage/default/45.spi_device_tpm_sts_read.3281043176 May 14 01:29:31 PM PDT 24 May 14 01:29:33 PM PDT 24 117877867 ps
T823 /workspace/coverage/default/17.spi_device_cfg_cmd.3419275609 May 14 01:28:19 PM PDT 24 May 14 01:28:26 PM PDT 24 109775313 ps
T223 /workspace/coverage/default/14.spi_device_flash_and_tpm.3429783849 May 14 01:28:10 PM PDT 24 May 14 01:30:48 PM PDT 24 9727110387 ps
T824 /workspace/coverage/default/28.spi_device_mailbox.1080989728 May 14 01:28:47 PM PDT 24 May 14 01:29:26 PM PDT 24 2459625145 ps
T825 /workspace/coverage/default/3.spi_device_csb_read.1379417257 May 14 01:27:29 PM PDT 24 May 14 01:27:30 PM PDT 24 34445198 ps
T826 /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1254897411 May 14 01:28:19 PM PDT 24 May 14 01:28:51 PM PDT 24 15765548661 ps
T827 /workspace/coverage/default/6.spi_device_read_buffer_direct.3001224793 May 14 01:27:47 PM PDT 24 May 14 01:27:54 PM PDT 24 934474614 ps
T828 /workspace/coverage/default/43.spi_device_read_buffer_direct.700512519 May 14 01:29:33 PM PDT 24 May 14 01:29:42 PM PDT 24 1089498510 ps
T829 /workspace/coverage/default/45.spi_device_flash_and_tpm.1170752502 May 14 01:29:32 PM PDT 24 May 14 01:29:58 PM PDT 24 6028154970 ps
T830 /workspace/coverage/default/7.spi_device_tpm_sts_read.2392660317 May 14 01:27:46 PM PDT 24 May 14 01:27:49 PM PDT 24 201062727 ps
T831 /workspace/coverage/default/23.spi_device_cfg_cmd.252708246 May 14 01:28:32 PM PDT 24 May 14 01:28:42 PM PDT 24 208840925 ps
T832 /workspace/coverage/default/17.spi_device_intercept.3416697800 May 14 01:28:07 PM PDT 24 May 14 01:28:16 PM PDT 24 865353525 ps
T833 /workspace/coverage/default/41.spi_device_tpm_all.2962845746 May 14 01:29:25 PM PDT 24 May 14 01:29:32 PM PDT 24 598626815 ps
T834 /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3781487412 May 14 01:27:36 PM PDT 24 May 14 01:27:39 PM PDT 24 12069134 ps
T835 /workspace/coverage/default/40.spi_device_read_buffer_direct.3478877222 May 14 01:29:18 PM PDT 24 May 14 01:29:26 PM PDT 24 420869748 ps
T836 /workspace/coverage/default/32.spi_device_mailbox.953154867 May 14 01:28:59 PM PDT 24 May 14 01:29:28 PM PDT 24 8664790386 ps
T837 /workspace/coverage/default/5.spi_device_upload.194431250 May 14 01:27:34 PM PDT 24 May 14 01:27:46 PM PDT 24 1089292847 ps
T838 /workspace/coverage/default/37.spi_device_read_buffer_direct.1661490108 May 14 01:29:14 PM PDT 24 May 14 01:29:37 PM PDT 24 3820331603 ps
T839 /workspace/coverage/default/45.spi_device_alert_test.1442519380 May 14 01:29:38 PM PDT 24 May 14 01:29:41 PM PDT 24 35218051 ps
T840 /workspace/coverage/default/23.spi_device_csb_read.3574407070 May 14 01:28:31 PM PDT 24 May 14 01:28:38 PM PDT 24 22033765 ps
T841 /workspace/coverage/default/15.spi_device_csb_read.1508128507 May 14 01:28:15 PM PDT 24 May 14 01:28:18 PM PDT 24 48936312 ps
T842 /workspace/coverage/default/30.spi_device_tpm_sts_read.780694460 May 14 01:28:46 PM PDT 24 May 14 01:28:49 PM PDT 24 47090626 ps
T843 /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1907381796 May 14 01:28:40 PM PDT 24 May 14 01:39:43 PM PDT 24 187635080651 ps
T844 /workspace/coverage/default/24.spi_device_tpm_rw.444510168 May 14 01:28:33 PM PDT 24 May 14 01:28:40 PM PDT 24 74927234 ps
T249 /workspace/coverage/default/2.spi_device_flash_all.2379910718 May 14 01:27:30 PM PDT 24 May 14 01:33:45 PM PDT 24 109809500511 ps
T845 /workspace/coverage/default/44.spi_device_flash_and_tpm.4213200298 May 14 01:29:31 PM PDT 24 May 14 01:30:10 PM PDT 24 12709201269 ps
T295 /workspace/coverage/default/41.spi_device_intercept.3329201447 May 14 01:29:24 PM PDT 24 May 14 01:29:36 PM PDT 24 419240154 ps
T846 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2987790996 May 14 01:28:01 PM PDT 24 May 14 01:33:51 PM PDT 24 37241112354 ps
T847 /workspace/coverage/default/29.spi_device_tpm_sts_read.845416155 May 14 01:28:47 PM PDT 24 May 14 01:28:49 PM PDT 24 99869242 ps
T848 /workspace/coverage/default/40.spi_device_tpm_sts_read.1469874947 May 14 01:29:19 PM PDT 24 May 14 01:29:23 PM PDT 24 75936672 ps
T849 /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2334885866 May 14 01:28:39 PM PDT 24 May 14 01:28:46 PM PDT 24 977459446 ps
T850 /workspace/coverage/default/10.spi_device_upload.908091182 May 14 01:27:56 PM PDT 24 May 14 01:27:59 PM PDT 24 106790803 ps
T851 /workspace/coverage/default/22.spi_device_tpm_all.1999530414 May 14 01:28:29 PM PDT 24 May 14 01:28:43 PM PDT 24 4251723159 ps
T852 /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.304154640 May 14 01:29:01 PM PDT 24 May 14 01:29:05 PM PDT 24 67759140 ps
T853 /workspace/coverage/default/18.spi_device_flash_mode.1980851594 May 14 01:28:19 PM PDT 24 May 14 01:28:29 PM PDT 24 140167672 ps
T854 /workspace/coverage/default/32.spi_device_upload.4155472851 May 14 01:28:58 PM PDT 24 May 14 01:29:02 PM PDT 24 94588979 ps
T855 /workspace/coverage/default/20.spi_device_tpm_all.4184557109 May 14 01:28:17 PM PDT 24 May 14 01:28:53 PM PDT 24 2174522306 ps
T856 /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3631198364 May 14 01:27:33 PM PDT 24 May 14 01:28:00 PM PDT 24 7536925970 ps
T857 /workspace/coverage/default/12.spi_device_mailbox.266464111 May 14 01:27:59 PM PDT 24 May 14 01:28:04 PM PDT 24 105647866 ps
T858 /workspace/coverage/default/40.spi_device_flash_all.1356992627 May 14 01:29:20 PM PDT 24 May 14 01:33:38 PM PDT 24 33332739796 ps
T859 /workspace/coverage/default/3.spi_device_flash_mode.2088874094 May 14 01:27:34 PM PDT 24 May 14 01:27:40 PM PDT 24 215879686 ps
T860 /workspace/coverage/default/28.spi_device_alert_test.2709904326 May 14 01:28:48 PM PDT 24 May 14 01:28:51 PM PDT 24 36520764 ps
T861 /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3469635748 May 14 01:27:50 PM PDT 24 May 14 01:27:57 PM PDT 24 4097190001 ps
T862 /workspace/coverage/default/44.spi_device_flash_mode.2823461380 May 14 01:29:33 PM PDT 24 May 14 01:29:46 PM PDT 24 557504942 ps
T257 /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.813330781 May 14 01:29:37 PM PDT 24 May 14 01:29:49 PM PDT 24 9156216501 ps
T863 /workspace/coverage/default/7.spi_device_alert_test.1439432801 May 14 01:27:38 PM PDT 24 May 14 01:27:40 PM PDT 24 14401208 ps
T864 /workspace/coverage/default/4.spi_device_tpm_sts_read.1220453261 May 14 01:27:31 PM PDT 24 May 14 01:27:35 PM PDT 24 23276087 ps
T865 /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1663437901 May 14 01:27:56 PM PDT 24 May 14 01:28:02 PM PDT 24 1566152514 ps
T866 /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1059858489 May 14 01:29:42 PM PDT 24 May 14 01:30:13 PM PDT 24 64989812334 ps
T867 /workspace/coverage/default/32.spi_device_tpm_rw.2725964586 May 14 01:28:55 PM PDT 24 May 14 01:28:57 PM PDT 24 20630955 ps
T868 /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2496821535 May 14 01:28:01 PM PDT 24 May 14 01:28:08 PM PDT 24 305820325 ps
T869 /workspace/coverage/default/13.spi_device_cfg_cmd.3323067570 May 14 01:28:10 PM PDT 24 May 14 01:28:16 PM PDT 24 454601139 ps
T870 /workspace/coverage/default/7.spi_device_mailbox.2505597262 May 14 01:27:47 PM PDT 24 May 14 01:27:53 PM PDT 24 150315161 ps
T871 /workspace/coverage/default/26.spi_device_csb_read.1608673999 May 14 01:28:42 PM PDT 24 May 14 01:28:45 PM PDT 24 32695615 ps
T872 /workspace/coverage/default/48.spi_device_alert_test.1561971570 May 14 01:29:54 PM PDT 24 May 14 01:29:56 PM PDT 24 45407366 ps
T873 /workspace/coverage/default/1.spi_device_mailbox.3509594838 May 14 01:27:19 PM PDT 24 May 14 01:27:38 PM PDT 24 10117253110 ps
T254 /workspace/coverage/default/7.spi_device_stress_all.2652959853 May 14 01:27:44 PM PDT 24 May 14 01:29:09 PM PDT 24 7181806295 ps
T874 /workspace/coverage/default/27.spi_device_tpm_rw.744191891 May 14 01:28:38 PM PDT 24 May 14 01:28:44 PM PDT 24 167265934 ps
T229 /workspace/coverage/default/36.spi_device_stress_all.3022806156 May 14 01:29:13 PM PDT 24 May 14 01:40:40 PM PDT 24 155489701279 ps
T259 /workspace/coverage/default/41.spi_device_stress_all.2100196018 May 14 01:29:24 PM PDT 24 May 14 01:33:02 PM PDT 24 158820672087 ps
T875 /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3991812974 May 14 01:28:28 PM PDT 24 May 14 01:28:37 PM PDT 24 1281106863 ps
T876 /workspace/coverage/default/2.spi_device_stress_all.1568662120 May 14 01:27:30 PM PDT 24 May 14 01:27:32 PM PDT 24 90013662 ps
T877 /workspace/coverage/default/48.spi_device_tpm_rw.3827972617 May 14 01:29:39 PM PDT 24 May 14 01:29:43 PM PDT 24 1760669762 ps
T878 /workspace/coverage/default/12.spi_device_cfg_cmd.2908533097 May 14 01:27:57 PM PDT 24 May 14 01:28:01 PM PDT 24 104389524 ps
T879 /workspace/coverage/default/41.spi_device_flash_mode.3626289543 May 14 01:29:24 PM PDT 24 May 14 01:29:35 PM PDT 24 884907633 ps
T880 /workspace/coverage/default/37.spi_device_intercept.248572587 May 14 01:29:11 PM PDT 24 May 14 01:29:16 PM PDT 24 119620617 ps
T881 /workspace/coverage/default/22.spi_device_tpm_rw.1739863755 May 14 01:28:28 PM PDT 24 May 14 01:28:34 PM PDT 24 156879045 ps
T882 /workspace/coverage/default/31.spi_device_flash_and_tpm.3376121909 May 14 01:28:56 PM PDT 24 May 14 01:29:28 PM PDT 24 6733256034 ps
T883 /workspace/coverage/default/12.spi_device_tpm_sts_read.618098038 May 14 01:27:59 PM PDT 24 May 14 01:28:02 PM PDT 24 41940200 ps
T884 /workspace/coverage/default/14.spi_device_flash_mode.927164230 May 14 01:28:03 PM PDT 24 May 14 01:28:30 PM PDT 24 1605199531 ps
T885 /workspace/coverage/default/49.spi_device_tpm_sts_read.1746532454 May 14 01:29:50 PM PDT 24 May 14 01:29:52 PM PDT 24 41784679 ps
T886 /workspace/coverage/default/9.spi_device_flash_and_tpm.1028282331 May 14 01:27:54 PM PDT 24 May 14 01:28:28 PM PDT 24 2421104342 ps
T887 /workspace/coverage/default/38.spi_device_cfg_cmd.3969519429 May 14 01:29:20 PM PDT 24 May 14 01:29:30 PM PDT 24 456981458 ps
T888 /workspace/coverage/default/28.spi_device_upload.2302962993 May 14 01:28:48 PM PDT 24 May 14 01:29:24 PM PDT 24 8817735834 ps
T889 /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3536078374 May 14 01:28:24 PM PDT 24 May 14 01:29:50 PM PDT 24 7179775221 ps
T890 /workspace/coverage/default/11.spi_device_intercept.839100895 May 14 01:27:48 PM PDT 24 May 14 01:27:55 PM PDT 24 458316701 ps
T891 /workspace/coverage/default/30.spi_device_csb_read.3009304788 May 14 01:28:50 PM PDT 24 May 14 01:28:53 PM PDT 24 32451735 ps
T892 /workspace/coverage/default/8.spi_device_upload.1451998992 May 14 01:27:47 PM PDT 24 May 14 01:28:05 PM PDT 24 2140715816 ps
T893 /workspace/coverage/default/24.spi_device_alert_test.1919843860 May 14 01:28:31 PM PDT 24 May 14 01:28:38 PM PDT 24 12711316 ps
T894 /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4085668915 May 14 01:28:48 PM PDT 24 May 14 01:29:03 PM PDT 24 3528853216 ps
T895 /workspace/coverage/default/20.spi_device_cfg_cmd.3135522000 May 14 01:28:18 PM PDT 24 May 14 01:28:26 PM PDT 24 47796497 ps
T133 /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.581235234 May 14 01:28:56 PM PDT 24 May 14 01:37:58 PM PDT 24 52677534192 ps
T896 /workspace/coverage/default/17.spi_device_tpm_all.3626200622 May 14 01:28:14 PM PDT 24 May 14 01:28:33 PM PDT 24 4374916388 ps
T897 /workspace/coverage/default/8.spi_device_flash_and_tpm.2082473218 May 14 01:27:50 PM PDT 24 May 14 01:31:21 PM PDT 24 94128608123 ps
T898 /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3911034589 May 14 01:29:50 PM PDT 24 May 14 01:41:22 PM PDT 24 74953744321 ps
T899 /workspace/coverage/default/5.spi_device_mailbox.4037111557 May 14 01:27:32 PM PDT 24 May 14 01:28:22 PM PDT 24 15336039017 ps
T900 /workspace/coverage/default/16.spi_device_mailbox.920796631 May 14 01:28:10 PM PDT 24 May 14 01:28:51 PM PDT 24 3905086982 ps
T901 /workspace/coverage/default/38.spi_device_mailbox.1024680183 May 14 01:29:18 PM PDT 24 May 14 01:30:00 PM PDT 24 3932046792 ps
T902 /workspace/coverage/default/40.spi_device_flash_and_tpm.3730556987 May 14 01:29:21 PM PDT 24 May 14 01:30:59 PM PDT 24 69511061409 ps
T903 /workspace/coverage/default/9.spi_device_flash_mode.3699302541 May 14 01:27:53 PM PDT 24 May 14 01:27:58 PM PDT 24 788351243 ps
T904 /workspace/coverage/default/43.spi_device_pass_cmd_filtering.670558817 May 14 01:29:37 PM PDT 24 May 14 01:29:46 PM PDT 24 2345028022 ps
T905 /workspace/coverage/default/1.spi_device_stress_all.4282725859 May 14 01:27:19 PM PDT 24 May 14 01:28:07 PM PDT 24 3205398454 ps
T906 /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.500734540 May 14 01:29:31 PM PDT 24 May 14 01:29:59 PM PDT 24 6383902070 ps
T907 /workspace/coverage/default/17.spi_device_tpm_rw.1187051746 May 14 01:28:16 PM PDT 24 May 14 01:28:22 PM PDT 24 366077908 ps
T57 /workspace/coverage/default/2.spi_device_flash_and_tpm.1594407940 May 14 01:27:32 PM PDT 24 May 14 01:28:34 PM PDT 24 14029825915 ps
T908 /workspace/coverage/default/46.spi_device_cfg_cmd.2341542158 May 14 01:29:41 PM PDT 24 May 14 01:29:49 PM PDT 24 729053340 ps
T909 /workspace/coverage/default/7.spi_device_flash_mode.2774645450 May 14 01:27:46 PM PDT 24 May 14 01:27:51 PM PDT 24 773269285 ps
T910 /workspace/coverage/default/25.spi_device_alert_test.3464042103 May 14 01:28:37 PM PDT 24 May 14 01:28:41 PM PDT 24 183934835 ps
T250 /workspace/coverage/default/3.spi_device_stress_all.665990384 May 14 01:27:29 PM PDT 24 May 14 01:45:59 PM PDT 24 577466293972 ps
T911 /workspace/coverage/default/8.spi_device_tpm_all.3178490024 May 14 01:27:51 PM PDT 24 May 14 01:28:17 PM PDT 24 5844225894 ps
T912 /workspace/coverage/default/42.spi_device_mailbox.3386085839 May 14 01:29:27 PM PDT 24 May 14 01:29:37 PM PDT 24 600110332 ps
T913 /workspace/coverage/default/9.spi_device_upload.1153772590 May 14 01:27:54 PM PDT 24 May 14 01:27:59 PM PDT 24 211892183 ps
T914 /workspace/coverage/default/35.spi_device_tpm_sts_read.3473811313 May 14 01:29:07 PM PDT 24 May 14 01:29:09 PM PDT 24 54352825 ps
T915 /workspace/coverage/default/33.spi_device_flash_mode.1262017424 May 14 01:29:09 PM PDT 24 May 14 01:29:17 PM PDT 24 747828105 ps
T916 /workspace/coverage/default/29.spi_device_tpm_rw.1693256674 May 14 01:28:47 PM PDT 24 May 14 01:28:51 PM PDT 24 346240787 ps
T917 /workspace/coverage/default/26.spi_device_tpm_sts_read.539918789 May 14 01:28:39 PM PDT 24 May 14 01:28:43 PM PDT 24 113103154 ps
T918 /workspace/coverage/default/20.spi_device_tpm_sts_read.608791816 May 14 01:28:16 PM PDT 24 May 14 01:28:21 PM PDT 24 198694198 ps
T919 /workspace/coverage/default/38.spi_device_read_buffer_direct.2052994869 May 14 01:29:20 PM PDT 24 May 14 01:29:29 PM PDT 24 1407028813 ps
T920 /workspace/coverage/default/15.spi_device_flash_and_tpm.1250316131 May 14 01:28:15 PM PDT 24 May 14 01:28:24 PM PDT 24 290692090 ps
T921 /workspace/coverage/default/47.spi_device_read_buffer_direct.3637545167 May 14 01:29:39 PM PDT 24 May 14 01:29:47 PM PDT 24 1029569875 ps
T922 /workspace/coverage/default/17.spi_device_alert_test.2708592416 May 14 01:28:19 PM PDT 24 May 14 01:28:25 PM PDT 24 13662196 ps
T923 /workspace/coverage/default/21.spi_device_intercept.598078428 May 14 01:28:25 PM PDT 24 May 14 01:28:53 PM PDT 24 10009791250 ps
T924 /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2715920791 May 14 01:28:20 PM PDT 24 May 14 01:28:34 PM PDT 24 4661296616 ps
T925 /workspace/coverage/default/46.spi_device_alert_test.3462429011 May 14 01:29:41 PM PDT 24 May 14 01:29:44 PM PDT 24 11030003 ps
T926 /workspace/coverage/default/42.spi_device_intercept.2558924958 May 14 01:29:26 PM PDT 24 May 14 01:29:34 PM PDT 24 384249454 ps
T927 /workspace/coverage/default/19.spi_device_upload.3877609393 May 14 01:28:16 PM PDT 24 May 14 01:28:29 PM PDT 24 701211178 ps
T928 /workspace/coverage/default/23.spi_device_alert_test.3343173596 May 14 01:28:38 PM PDT 24 May 14 01:28:42 PM PDT 24 19866867 ps
T26 /workspace/coverage/default/4.spi_device_stress_all.593840286 May 14 01:27:34 PM PDT 24 May 14 01:36:36 PM PDT 24 329232665138 ps
T929 /workspace/coverage/default/1.spi_device_alert_test.2568405317 May 14 01:27:20 PM PDT 24 May 14 01:27:24 PM PDT 24 15336293 ps
T230 /workspace/coverage/default/29.spi_device_flash_and_tpm.309097230 May 14 01:28:47 PM PDT 24 May 14 01:30:13 PM PDT 24 7016360451 ps
T930 /workspace/coverage/default/24.spi_device_mailbox.3059631200 May 14 01:28:33 PM PDT 24 May 14 01:29:23 PM PDT 24 3137859995 ps
T931 /workspace/coverage/default/6.spi_device_tpm_rw.266273510 May 14 01:27:32 PM PDT 24 May 14 01:27:37 PM PDT 24 142539445 ps
T932 /workspace/coverage/default/19.spi_device_csb_read.315320912 May 14 01:28:16 PM PDT 24 May 14 01:28:20 PM PDT 24 38537215 ps
T933 /workspace/coverage/default/12.spi_device_flash_mode.4268783428 May 14 01:28:07 PM PDT 24 May 14 01:29:14 PM PDT 24 5434205007 ps
T934 /workspace/coverage/default/20.spi_device_read_buffer_direct.4015060480 May 14 01:28:29 PM PDT 24 May 14 01:28:48 PM PDT 24 986937920 ps
T935 /workspace/coverage/default/24.spi_device_tpm_sts_read.938261005 May 14 01:28:33 PM PDT 24 May 14 01:28:39 PM PDT 24 36792079 ps
T936 /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.243565110 May 14 01:28:08 PM PDT 24 May 14 01:28:17 PM PDT 24 3082133964 ps
T937 /workspace/coverage/default/34.spi_device_upload.3492335681 May 14 01:29:06 PM PDT 24 May 14 01:29:11 PM PDT 24 254338730 ps
T938 /workspace/coverage/default/36.spi_device_tpm_rw.4160747762 May 14 01:29:15 PM PDT 24 May 14 01:29:18 PM PDT 24 152230115 ps
T939 /workspace/coverage/default/41.spi_device_tpm_sts_read.365416336 May 14 01:29:23 PM PDT 24 May 14 01:29:27 PM PDT 24 143967091 ps
T940 /workspace/coverage/default/29.spi_device_mailbox.4262540201 May 14 01:28:48 PM PDT 24 May 14 01:29:13 PM PDT 24 28902900749 ps
T941 /workspace/coverage/default/46.spi_device_stress_all.1916455388 May 14 01:29:39 PM PDT 24 May 14 01:29:50 PM PDT 24 2978994137 ps
T942 /workspace/coverage/default/48.spi_device_intercept.1133214249 May 14 01:29:40 PM PDT 24 May 14 01:29:50 PM PDT 24 13093565604 ps
T943 /workspace/coverage/default/22.spi_device_flash_mode.1576873075 May 14 01:28:29 PM PDT 24 May 14 01:29:53 PM PDT 24 26249487439 ps
T944 /workspace/coverage/default/16.spi_device_csb_read.2865358461 May 14 01:28:08 PM PDT 24 May 14 01:28:11 PM PDT 24 109717084 ps
T945 /workspace/coverage/default/5.spi_device_tpm_all.1207402482 May 14 01:27:31 PM PDT 24 May 14 01:27:34 PM PDT 24 13708642 ps
T946 /workspace/coverage/default/1.spi_device_flash_all.1157210811 May 14 01:27:21 PM PDT 24 May 14 01:27:25 PM PDT 24 18832642 ps
T947 /workspace/coverage/default/24.spi_device_read_buffer_direct.249445021 May 14 01:28:33 PM PDT 24 May 14 01:28:43 PM PDT 24 500305317 ps
T948 /workspace/coverage/default/47.spi_device_intercept.3263125377 May 14 01:29:40 PM PDT 24 May 14 01:29:45 PM PDT 24 144829869 ps
T949 /workspace/coverage/default/28.spi_device_flash_all.858782008 May 14 01:28:47 PM PDT 24 May 14 01:29:38 PM PDT 24 6419158279 ps
T950 /workspace/coverage/default/29.spi_device_flash_all.3662676738 May 14 01:28:47 PM PDT 24 May 14 01:30:14 PM PDT 24 50807311892 ps
T951 /workspace/coverage/default/34.spi_device_flash_mode.1210346947 May 14 01:29:08 PM PDT 24 May 14 01:29:21 PM PDT 24 5767403018 ps
T952 /workspace/coverage/default/48.spi_device_flash_all.488837596 May 14 01:29:50 PM PDT 24 May 14 01:32:36 PM PDT 24 23176056090 ps
T953 /workspace/coverage/default/14.spi_device_tpm_sts_read.1566723717 May 14 01:28:09 PM PDT 24 May 14 01:28:12 PM PDT 24 114139078 ps
T954 /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3735226800 May 14 01:28:40 PM PDT 24 May 14 01:28:48 PM PDT 24 2045687653 ps
T955 /workspace/coverage/default/33.spi_device_flash_all.3040493372 May 14 01:29:02 PM PDT 24 May 14 01:29:17 PM PDT 24 2577792123 ps
T27 /workspace/coverage/default/34.spi_device_stress_all.118738307 May 14 01:29:03 PM PDT 24 May 14 01:37:07 PM PDT 24 41831732416 ps
T956 /workspace/coverage/default/16.spi_device_alert_test.4234524134 May 14 01:28:07 PM PDT 24 May 14 01:28:09 PM PDT 24 18242115 ps
T957 /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4141971018 May 14 01:29:20 PM PDT 24 May 14 01:29:33 PM PDT 24 3058037225 ps
T958 /workspace/coverage/default/12.spi_device_read_buffer_direct.1844407027 May 14 01:28:01 PM PDT 24 May 14 01:28:15 PM PDT 24 10963364469 ps
T959 /workspace/coverage/default/4.spi_device_cfg_cmd.1742265931 May 14 01:27:32 PM PDT 24 May 14 01:27:38 PM PDT 24 551520580 ps
T960 /workspace/coverage/default/39.spi_device_tpm_sts_read.2380892668 May 14 01:29:20 PM PDT 24 May 14 01:29:25 PM PDT 24 334001803 ps
T961 /workspace/coverage/default/39.spi_device_read_buffer_direct.869355252 May 14 01:29:20 PM PDT 24 May 14 01:29:30 PM PDT 24 211999133 ps
T962 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.178368874 May 14 12:54:53 PM PDT 24 May 14 12:54:56 PM PDT 24 12305039 ps
T109 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.915649874 May 14 12:55:03 PM PDT 24 May 14 12:55:07 PM PDT 24 29029356 ps
T963 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1771849603 May 14 12:55:24 PM PDT 24 May 14 12:55:25 PM PDT 24 33601454 ps
T964 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.709586846 May 14 12:54:55 PM PDT 24 May 14 12:54:59 PM PDT 24 67229492 ps
T69 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.974500685 May 14 12:55:14 PM PDT 24 May 14 12:55:20 PM PDT 24 242456636 ps
T965 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3959004354 May 14 12:55:09 PM PDT 24 May 14 12:55:11 PM PDT 24 15516148 ps
T134 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.59836500 May 14 12:54:59 PM PDT 24 May 14 12:55:06 PM PDT 24 67341430 ps
T135 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3556467767 May 14 12:55:12 PM PDT 24 May 14 12:55:16 PM PDT 24 146278423 ps
T110 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4197981679 May 14 12:55:02 PM PDT 24 May 14 12:55:06 PM PDT 24 113205660 ps
T966 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3446339839 May 14 12:55:20 PM PDT 24 May 14 12:55:23 PM PDT 24 17401838 ps
T70 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.841738713 May 14 12:54:55 PM PDT 24 May 14 12:55:14 PM PDT 24 593072234 ps
T111 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3752186487 May 14 12:55:14 PM PDT 24 May 14 12:55:19 PM PDT 24 75702997 ps
T112 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1070553877 May 14 12:54:47 PM PDT 24 May 14 12:55:13 PM PDT 24 1868212173 ps
T113 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.25156998 May 14 12:54:55 PM PDT 24 May 14 12:54:59 PM PDT 24 410805240 ps
T136 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1097293435 May 14 12:55:15 PM PDT 24 May 14 12:55:21 PM PDT 24 320909350 ps
T71 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3496608181 May 14 12:54:58 PM PDT 24 May 14 12:55:03 PM PDT 24 187828339 ps
T967 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4115746510 May 14 12:55:14 PM PDT 24 May 14 12:55:18 PM PDT 24 62826659 ps
T968 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2840166388 May 14 12:55:15 PM PDT 24 May 14 12:55:18 PM PDT 24 21440121 ps
T969 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1400979216 May 14 12:55:15 PM PDT 24 May 14 12:55:19 PM PDT 24 10808610 ps
T96 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1331721314 May 14 12:55:06 PM PDT 24 May 14 12:55:19 PM PDT 24 188552302 ps
T970 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1763619146 May 14 12:55:16 PM PDT 24 May 14 12:55:21 PM PDT 24 26170898 ps
T95 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1566413515 May 14 12:54:55 PM PDT 24 May 14 12:55:02 PM PDT 24 158121874 ps
T98 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3405889561 May 14 12:55:14 PM PDT 24 May 14 12:55:19 PM PDT 24 282663374 ps
T114 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3860936379 May 14 12:54:53 PM PDT 24 May 14 12:54:56 PM PDT 24 53025137 ps
T971 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3611162319 May 14 12:55:16 PM PDT 24 May 14 12:55:20 PM PDT 24 19640812 ps
T103 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2997548512 May 14 12:55:13 PM PDT 24 May 14 12:55:18 PM PDT 24 312071904 ps
T137 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.462320062 May 14 12:55:17 PM PDT 24 May 14 12:55:22 PM PDT 24 40416589 ps
T142 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.704893110 May 14 12:55:18 PM PDT 24 May 14 12:55:45 PM PDT 24 3134609018 ps
T101 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3255519488 May 14 12:55:30 PM PDT 24 May 14 12:55:34 PM PDT 24 138771148 ps
T972 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1675461237 May 14 12:55:15 PM PDT 24 May 14 12:55:19 PM PDT 24 34952055 ps
T973 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.793999633 May 14 12:55:16 PM PDT 24 May 14 12:55:21 PM PDT 24 30908657 ps
T107 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.514709063 May 14 12:55:04 PM PDT 24 May 14 12:55:09 PM PDT 24 125100664 ps
T102 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1347855029 May 14 12:55:10 PM PDT 24 May 14 12:55:15 PM PDT 24 1385612779 ps
T106 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.832525013 May 14 12:55:16 PM PDT 24 May 14 12:55:21 PM PDT 24 242816765 ps
T974 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3203161210 May 14 12:55:18 PM PDT 24 May 14 12:55:24 PM PDT 24 153971088 ps
T105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2316195404 May 14 12:55:16 PM PDT 24 May 14 12:55:21 PM PDT 24 25547328 ps
T143 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4052984248 May 14 12:54:57 PM PDT 24 May 14 12:55:05 PM PDT 24 660167152 ps
T97 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3213030932 May 14 12:55:09 PM PDT 24 May 14 12:55:30 PM PDT 24 969964290 ps
T975 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1149743841 May 14 12:55:20 PM PDT 24 May 14 12:55:23 PM PDT 24 22234666 ps
T100 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1962472577 May 14 12:55:15 PM PDT 24 May 14 12:55:21 PM PDT 24 106150219 ps
T104 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1146943533 May 14 12:54:58 PM PDT 24 May 14 12:55:06 PM PDT 24 944554417 ps
T144 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3603968487 May 14 12:55:14 PM PDT 24 May 14 12:55:18 PM PDT 24 402503546 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1134560458 May 14 12:54:53 PM PDT 24 May 14 12:54:56 PM PDT 24 35528993 ps
T976 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4090597640 May 14 12:55:26 PM PDT 24 May 14 12:55:27 PM PDT 24 12563106 ps
T83 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3761337597 May 14 12:54:48 PM PDT 24 May 14 12:54:52 PM PDT 24 42006972 ps
T145 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3932824795 May 14 12:54:53 PM PDT 24 May 14 12:55:05 PM PDT 24 1731627186 ps
T115 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2068257473 May 14 12:54:55 PM PDT 24 May 14 12:55:00 PM PDT 24 678716647 ps
T116 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1095007788 May 14 12:55:10 PM PDT 24 May 14 12:55:13 PM PDT 24 93151075 ps
T977 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1688207116 May 14 12:55:35 PM PDT 24 May 14 12:55:37 PM PDT 24 14268368 ps
T978 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2595133763 May 14 12:55:10 PM PDT 24 May 14 12:55:14 PM PDT 24 44080339 ps
T979 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3138181101 May 14 12:55:09 PM PDT 24 May 14 12:55:12 PM PDT 24 28666380 ps
T146 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3408571898 May 14 12:55:25 PM PDT 24 May 14 12:55:50 PM PDT 24 7669727362 ps
T980 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2348457296 May 14 12:55:15 PM PDT 24 May 14 12:55:20 PM PDT 24 59188546 ps
T117 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.929234659 May 14 12:55:14 PM PDT 24 May 14 12:55:18 PM PDT 24 130929780 ps
T147 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4005671113 May 14 12:55:12 PM PDT 24 May 14 12:55:15 PM PDT 24 219603532 ps
T122 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.897210998 May 14 12:55:13 PM PDT 24 May 14 12:55:17 PM PDT 24 944900261 ps
T981 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2794297811 May 14 12:55:04 PM PDT 24 May 14 12:55:09 PM PDT 24 63518200 ps
T982 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2020737126 May 14 12:55:29 PM PDT 24 May 14 12:55:30 PM PDT 24 42766866 ps
T983 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3771017841 May 14 12:55:08 PM PDT 24 May 14 12:55:13 PM PDT 24 339756048 ps
T984 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1871770174 May 14 12:54:54 PM PDT 24 May 14 12:54:57 PM PDT 24 14416335 ps
T985 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2056048186 May 14 12:55:16 PM PDT 24 May 14 12:55:22 PM PDT 24 85419000 ps
T986 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3496200426 May 14 12:54:50 PM PDT 24 May 14 12:54:55 PM PDT 24 98706203 ps
T987 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4285429418 May 14 12:55:18 PM PDT 24 May 14 12:55:25 PM PDT 24 542406653 ps
T988 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.16445958 May 14 12:55:15 PM PDT 24 May 14 12:55:18 PM PDT 24 17544209 ps
T989 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1786284566 May 14 12:54:56 PM PDT 24 May 14 12:55:03 PM PDT 24 482243282 ps
T990 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.499054895 May 14 12:54:57 PM PDT 24 May 14 12:55:02 PM PDT 24 96055476 ps
T271 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4097337690 May 14 12:54:59 PM PDT 24 May 14 12:55:06 PM PDT 24 635773301 ps
T118 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1081215876 May 14 12:55:16 PM PDT 24 May 14 12:55:22 PM PDT 24 28025055 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2279270594 May 14 12:55:13 PM PDT 24 May 14 12:55:22 PM PDT 24 406347234 ps
T991 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3134388815 May 14 12:55:15 PM PDT 24 May 14 12:55:18 PM PDT 24 11276435 ps
T992 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1481147666 May 14 12:55:16 PM PDT 24 May 14 12:55:20 PM PDT 24 26163998 ps
T148 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1165403871 May 14 12:54:54 PM PDT 24 May 14 12:55:00 PM PDT 24 209859977 ps
T993 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.767486604 May 14 12:54:55 PM PDT 24 May 14 12:55:02 PM PDT 24 186290943 ps
T994 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1962940854 May 14 12:55:10 PM PDT 24 May 14 12:55:12 PM PDT 24 10939938 ps
T272 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2469978645 May 14 12:54:58 PM PDT 24 May 14 12:55:05 PM PDT 24 168855660 ps
T273 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3145277373 May 14 12:54:58 PM PDT 24 May 14 12:55:07 PM PDT 24 715382119 ps
T274 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.390760891 May 14 12:54:56 PM PDT 24 May 14 12:55:14 PM PDT 24 653728990 ps
T995 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1735203181 May 14 12:54:59 PM PDT 24 May 14 12:55:14 PM PDT 24 1005618782 ps
T996 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1841992204 May 14 12:55:11 PM PDT 24 May 14 12:55:13 PM PDT 24 50579158 ps
T997 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2073290843 May 14 12:54:55 PM PDT 24 May 14 12:54:59 PM PDT 24 26573722 ps
T998 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.456358839 May 14 12:55:08 PM PDT 24 May 14 12:55:09 PM PDT 24 13690305 ps
T999 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1441904567 May 14 12:55:17 PM PDT 24 May 14 12:55:21 PM PDT 24 27336080 ps
T120 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2394138809 May 14 12:55:02 PM PDT 24 May 14 12:55:37 PM PDT 24 2603057482 ps
T1000 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3409974853 May 14 12:54:57 PM PDT 24 May 14 12:55:01 PM PDT 24 35967194 ps
T1001 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.458961225 May 14 12:55:10 PM PDT 24 May 14 12:55:14 PM PDT 24 140703423 ps
T1002 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3549783723 May 14 12:54:55 PM PDT 24 May 14 12:55:14 PM PDT 24 648820712 ps
T84 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4166036465 May 14 12:54:55 PM PDT 24 May 14 12:54:59 PM PDT 24 21215462 ps
T275 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.110570224 May 14 12:54:58 PM PDT 24 May 14 12:55:09 PM PDT 24 270315944 ps
T1003 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.674265224 May 14 12:55:15 PM PDT 24 May 14 12:55:22 PM PDT 24 226488995 ps
T121 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4154495283 May 14 12:55:14 PM PDT 24 May 14 12:55:18 PM PDT 24 26640754 ps
T1004 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2043798666 May 14 12:54:53 PM PDT 24 May 14 12:54:57 PM PDT 24 230855722 ps
T1005 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.368924054 May 14 12:55:39 PM PDT 24 May 14 12:55:43 PM PDT 24 11285282 ps
T1006 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.657721464 May 14 12:54:56 PM PDT 24 May 14 12:55:01 PM PDT 24 32424883 ps
T1007 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3033855684 May 14 12:55:08 PM PDT 24 May 14 12:55:11 PM PDT 24 41908370 ps
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