Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.90	98.30	94.11	98.61	89.36	97.06	95.83	98.07

Total test records in report: 1081

T1008	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.272741463	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	22324740 ps
T1009	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.125700615	May 14 12:54:55 PM PDT 24	May 14 12:55:00 PM PDT 24	50911787 ps
T1010	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1614187697	May 14 12:54:56 PM PDT 24	May 14 12:55:03 PM PDT 24	101687253 ps
T1011	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3935081440	May 14 12:55:14 PM PDT 24	May 14 12:55:30 PM PDT 24	2130626168 ps
T1012	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2995078955	May 14 12:55:15 PM PDT 24	May 14 12:55:20 PM PDT 24	15700320 ps
T1013	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.707744437	May 14 12:55:16 PM PDT 24	May 14 12:55:24 PM PDT 24	99520378 ps
T1014	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3863993198	May 14 12:54:46 PM PDT 24	May 14 12:54:51 PM PDT 24	19766022 ps
T1015	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1737767342	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	48741566 ps
T1016	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3774789102	May 14 12:54:57 PM PDT 24	May 14 12:55:04 PM PDT 24	279053824 ps
T1017	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.4219157515	May 14 12:55:16 PM PDT 24	May 14 12:55:20 PM PDT 24	20323388 ps
T1018	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.593834344	May 14 12:55:14 PM PDT 24	May 14 12:55:18 PM PDT 24	28216362 ps
T1019	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1944470492	May 14 12:54:57 PM PDT 24	May 14 12:55:03 PM PDT 24	82954933 ps
T1020	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2844237174	May 14 12:55:13 PM PDT 24	May 14 12:55:17 PM PDT 24	77783158 ps
T1021	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.2149205403	May 14 12:55:16 PM PDT 24	May 14 12:55:20 PM PDT 24	43257296 ps
T1022	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2316146218	May 14 12:54:59 PM PDT 24	May 14 12:55:16 PM PDT 24	1856553532 ps
T1023	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.716409902	May 14 12:55:15 PM PDT 24	May 14 12:55:20 PM PDT 24	345347103 ps
T1024	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1749292566	May 14 12:55:11 PM PDT 24	May 14 12:55:16 PM PDT 24	365221216 ps
T1025	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.175451171	May 14 12:55:16 PM PDT 24	May 14 12:55:20 PM PDT 24	80756730 ps
T1026	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2351256983	May 14 12:54:58 PM PDT 24	May 14 12:55:03 PM PDT 24	400733691 ps
T1027	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3914279693	May 14 12:55:09 PM PDT 24	May 14 12:55:26 PM PDT 24	1147910489 ps
T276	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.275067253	May 14 12:55:09 PM PDT 24	May 14 12:55:27 PM PDT 24	1164891455 ps
T1028	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1396055245	May 14 12:54:56 PM PDT 24	May 14 12:55:03 PM PDT 24	349575108 ps
T1029	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1085884496	May 14 12:55:08 PM PDT 24	May 14 12:55:18 PM PDT 24	2781694924 ps
T1030	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3945539012	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	46207302 ps
T1031	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.723036121	May 14 12:55:13 PM PDT 24	May 14 12:55:18 PM PDT 24	313601196 ps
T1032	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3009263044	May 14 12:54:56 PM PDT 24	May 14 12:55:02 PM PDT 24	56786175 ps
T1033	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.191407691	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	25463407 ps
T1034	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.202714116	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	22714935 ps
T277	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2726584371	May 14 12:54:52 PM PDT 24	May 14 12:55:12 PM PDT 24	294813141 ps
T1035	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2685365834	May 14 12:54:59 PM PDT 24	May 14 12:55:04 PM PDT 24	55241162 ps
T1036	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3691560981	May 14 12:54:54 PM PDT 24	May 14 12:55:00 PM PDT 24	126332051 ps
T1037	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2202816641	May 14 12:54:51 PM PDT 24	May 14 12:55:06 PM PDT 24	2615901482 ps
T1038	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1490838855	May 14 12:54:57 PM PDT 24	May 14 12:55:04 PM PDT 24	156411061 ps
T1039	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3411463554	May 14 12:54:50 PM PDT 24	May 14 12:54:53 PM PDT 24	13784565 ps
T1040	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2903034481	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	21531698 ps
T279	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4266911015	May 14 12:54:57 PM PDT 24	May 14 12:55:07 PM PDT 24	397889253 ps
T1041	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.401919534	May 14 12:54:56 PM PDT 24	May 14 12:55:02 PM PDT 24	94838774 ps
T1042	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1943847835	May 14 12:55:15 PM PDT 24	May 14 12:55:20 PM PDT 24	13402225 ps
T1043	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.1387092837	May 14 12:54:54 PM PDT 24	May 14 12:54:57 PM PDT 24	11759188 ps
T1044	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1768199300	May 14 12:54:55 PM PDT 24	May 14 12:55:01 PM PDT 24	104507987 ps
T1045	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3799022034	May 14 12:55:04 PM PDT 24	May 14 12:55:26 PM PDT 24	324123930 ps
T1046	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.839076236	May 14 12:55:16 PM PDT 24	May 14 12:55:21 PM PDT 24	118788501 ps
T1047	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1510209224	May 14 12:54:57 PM PDT 24	May 14 12:55:13 PM PDT 24	1246742819 ps
T1048	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3958524639	May 14 12:55:12 PM PDT 24	May 14 12:55:15 PM PDT 24	150191869 ps
T1049	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2213682652	May 14 12:55:03 PM PDT 24	May 14 12:55:12 PM PDT 24	106565565 ps
T1050	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1118490736	May 14 12:55:14 PM PDT 24	May 14 12:55:17 PM PDT 24	14091578 ps
T1051	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.137820555	May 14 12:55:00 PM PDT 24	May 14 12:55:04 PM PDT 24	180114496 ps
T1052	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3152313209	May 14 12:55:11 PM PDT 24	May 14 12:55:15 PM PDT 24	39417371 ps
T1053	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1537233801	May 14 12:55:02 PM PDT 24	May 14 12:55:05 PM PDT 24	32140922 ps
T1054	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3837700728	May 14 12:55:12 PM PDT 24	May 14 12:55:16 PM PDT 24	82110029 ps
T1055	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4276220657	May 14 12:55:07 PM PDT 24	May 14 12:55:19 PM PDT 24	197398052 ps
T1056	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3217272139	May 14 12:54:52 PM PDT 24	May 14 12:54:56 PM PDT 24	249215454 ps
T1057	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1008217901	May 14 12:55:15 PM PDT 24	May 14 12:55:19 PM PDT 24	45867766 ps
T1058	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1926484570	May 14 12:54:56 PM PDT 24	May 14 12:55:02 PM PDT 24	212678062 ps
T1059	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1115915626	May 14 12:55:13 PM PDT 24	May 14 12:55:16 PM PDT 24	69885577 ps
T1060	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2697479017	May 14 12:55:22 PM PDT 24	May 14 12:55:24 PM PDT 24	28122974 ps
T280	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3023749348	May 14 12:55:14 PM PDT 24	May 14 12:55:35 PM PDT 24	313138379 ps
T1061	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2724628343	May 14 12:55:12 PM PDT 24	May 14 12:55:20 PM PDT 24	114717150 ps
T1062	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2961234743	May 14 12:55:04 PM PDT 24	May 14 12:55:08 PM PDT 24	44709904 ps
T1063	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2584882086	May 14 12:55:10 PM PDT 24	May 14 12:55:18 PM PDT 24	170331974 ps
T1064	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2928368597	May 14 12:54:59 PM PDT 24	May 14 12:55:03 PM PDT 24	27819917 ps
T1065	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1881990789	May 14 12:54:56 PM PDT 24	May 14 12:55:04 PM PDT 24	162938342 ps
T1066	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2546561647	May 14 12:55:16 PM PDT 24	May 14 12:55:21 PM PDT 24	13703245 ps
T278	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2375053765	May 14 12:54:55 PM PDT 24	May 14 12:55:11 PM PDT 24	1643687323 ps
T1067	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2244753700	May 14 12:55:09 PM PDT 24	May 14 12:55:18 PM PDT 24	333591680 ps
T1068	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.441321078	May 14 12:55:31 PM PDT 24	May 14 12:55:47 PM PDT 24	691177788 ps
T1069	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1428081666	May 14 12:55:10 PM PDT 24	May 14 12:55:12 PM PDT 24	13979505 ps
T1070	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1915858959	May 14 12:54:56 PM PDT 24	May 14 12:55:06 PM PDT 24	238782405 ps
T1071	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1702199475	May 14 12:55:14 PM PDT 24	May 14 12:55:18 PM PDT 24	352779609 ps
T1072	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.547426973	May 14 12:55:11 PM PDT 24	May 14 12:55:15 PM PDT 24	143924229 ps
T1073	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.333848248	May 14 12:55:17 PM PDT 24	May 14 12:55:21 PM PDT 24	15563107 ps
T1074	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3470717607	May 14 12:55:14 PM PDT 24	May 14 12:55:20 PM PDT 24	210831398 ps
T281	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3249459004	May 14 12:54:56 PM PDT 24	May 14 12:55:12 PM PDT 24	191745043 ps
T1075	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1674449432	May 14 12:55:09 PM PDT 24	May 14 12:55:11 PM PDT 24	44242005 ps
T1076	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2380750486	May 14 12:55:08 PM PDT 24	May 14 12:55:12 PM PDT 24	86753134 ps
T1077	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4073225877	May 14 12:54:55 PM PDT 24	May 14 12:54:58 PM PDT 24	21820631 ps
T1078	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1403372692	May 14 12:55:05 PM PDT 24	May 14 12:55:07 PM PDT 24	14214212 ps
T1079	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3137986610	May 14 12:54:58 PM PDT 24	May 14 12:55:05 PM PDT 24	78682562 ps
T1080	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.215317215	May 14 12:55:13 PM PDT 24	May 14 12:55:17 PM PDT 24	49913047 ps
T85	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3467285032	May 14 12:55:10 PM PDT 24	May 14 12:55:13 PM PDT 24	38946107 ps
T1081	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.4046267492	May 14 12:55:12 PM PDT 24	May 14 12:55:14 PM PDT 24	19855488 ps

Test location	/workspace/coverage/default/49.spi_device_flash_mode.2686058385
Short name	T1
Test name
Test status
Simulation time	229500769 ps
CPU time	3.48 seconds
Started	May 14 01:29:51 PM PDT 24
Finished	May 14 01:29:56 PM PDT 24
Peak memory	232388 kb
Host	smart-b31a281b-eb2e-4a32-9c70-cfc6290b584a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686058385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2686058385
Directory	/workspace/49.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/25.spi_device_flash_and_tpm.1963623563
Short name	T19
Test name
Test status
Simulation time	13233319343 ps
CPU time	51.54 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	249068 kb
Host	smart-8e68a48b-75c0-45e9-9b1a-d0d7b85bba9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963623563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1963623563
Directory	/workspace/25.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/41.spi_device_flash_all.1807971351
Short name	T24
Test name
Test status
Simulation time	14083881106 ps
CPU time	50.67 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:30:19 PM PDT 24
Peak memory	241008 kb
Host	smart-c18658bb-f0db-4aee-a0b2-8838a24c12f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807971351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1807971351
Directory	/workspace/41.spi_device_flash_all/latest

Test location	/workspace/coverage/default/29.spi_device_stress_all.4166692397
Short name	T47
Test name
Test status
Simulation time	200636307174 ps
CPU time	563.17 seconds
Started	May 14 01:28:50 PM PDT 24
Finished	May 14 01:38:15 PM PDT 24
Peak memory	273624 kb
Host	smart-4433608d-4018-465d-b097-85332efd7109
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166692397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre ss_all.4166692397
Directory	/workspace/29.spi_device_stress_all/latest

Test location	/workspace/coverage/default/11.spi_device_stress_all.792254972
Short name	T30
Test name
Test status
Simulation time	3996688807 ps
CPU time	80.11 seconds
Started	May 14 01:27:56 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	249396 kb
Host	smart-723a565f-d7f2-4e4d-b533-a738739e66c8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792254972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres s_all.792254972
Directory	/workspace/11.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.974500685
Short name	T69
Test name
Test status
Simulation time	242456636 ps
CPU time	2.79 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	216548 kb
Host	smart-bb506567-f39c-469b-8dd7-28831f93b4b1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974500685 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.974500685
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/11.spi_device_flash_and_tpm.74522505
Short name	T38
Test name
Test status
Simulation time	15239721357 ps
CPU time	94.1 seconds
Started	May 14 01:27:56 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	262864 kb
Host	smart-dec20051-128a-4b73-ae5e-909286dde50d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74522505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.74522505
Directory	/workspace/11.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2014480185
Short name	T45
Test name
Test status
Simulation time	7656828322 ps
CPU time	149.98 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:30:41 PM PDT 24
Peak memory	262360 kb
Host	smart-25cce158-2e7b-40cf-a8ae-05bd110bca9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014480185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl e.2014480185
Directory	/workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/0.spi_device_ram_cfg.3636719333
Short name	T74
Test name
Test status
Simulation time	15736087 ps
CPU time	0.77 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:24 PM PDT 24
Peak memory	215972 kb
Host	smart-e501fee0-ec91-4721-854a-21864983d68f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636719333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3636719333
Directory	/workspace/0.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/43.spi_device_stress_all.850351408
Short name	T88
Test name
Test status
Simulation time	74117568800 ps
CPU time	839.84 seconds
Started	May 14 01:29:35 PM PDT 24
Finished	May 14 01:43:37 PM PDT 24
Peak memory	301276 kb
Host	smart-c8f35edb-3dd0-42e4-baa2-49c698dede4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850351408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres s_all.850351408
Directory	/workspace/43.spi_device_stress_all/latest

Test location	/workspace/coverage/default/2.spi_device_sec_cm.2606065439
Short name	T2
Test name
Test status
Simulation time	57249433 ps
CPU time	1.14 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:37 PM PDT 24
Peak memory	234608 kb
Host	smart-0ca6ca3f-7b59-4c84-a93b-d23b29867d06
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606065439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2606065439
Directory	/workspace/2.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/1.spi_device_flash_and_tpm.3872571542
Short name	T80
Test name
Test status
Simulation time	155409969518 ps
CPU time	716.32 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:39:21 PM PDT 24
Peak memory	263944 kb
Host	smart-4fb617f0-d67d-4ee1-ba88-dcbb768469c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872571542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3872571542
Directory	/workspace/1.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/15.spi_device_flash_all.1590797457
Short name	T14
Test name
Test status
Simulation time	121791747043 ps
CPU time	224.42 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:32:02 PM PDT 24
Peak memory	250048 kb
Host	smart-a6e01cec-a960-4018-ba76-ccd625b2a317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590797457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1590797457
Directory	/workspace/15.spi_device_flash_all/latest

Test location	/workspace/coverage/default/25.spi_device_stress_all.2232642919
Short name	T25
Test name
Test status
Simulation time	84124233466 ps
CPU time	345.25 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:34:33 PM PDT 24
Peak memory	267436 kb
Host	smart-8812ea2f-0041-4e73-a453-7e660a659304
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232642919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre ss_all.2232642919
Directory	/workspace/25.spi_device_stress_all/latest

Test location	/workspace/coverage/default/32.spi_device_flash_and_tpm.1023409156
Short name	T192
Test name
Test status
Simulation time	37999710248 ps
CPU time	233.92 seconds
Started	May 14 01:28:52 PM PDT 24
Finished	May 14 01:32:48 PM PDT 24
Peak memory	265180 kb
Host	smart-36a1df43-8762-41e0-99b6-94dfea955e6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023409156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1023409156
Directory	/workspace/32.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.841738713
Short name	T70
Test name
Test status
Simulation time	593072234 ps
CPU time	16.4 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	215424 kb
Host	smart-71735fc5-a9b2-4d50-80d2-115c6acaabbc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841738713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_ tl_intg_err.841738713
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3752186487
Short name	T111
Test name
Test status
Simulation time	75702997 ps
CPU time	1.95 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	215092 kb
Host	smart-cbf15de6-cbc3-44d7-8d18-e68f5dd8ca54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752186487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 3752186487
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/default/20.spi_device_stress_all.2657174048
Short name	T44
Test name
Test status
Simulation time	74738853177 ps
CPU time	393.47 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:35:03 PM PDT 24
Peak memory	256700 kb
Host	smart-24db0427-0aa5-429e-b282-34d3c59e5938
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657174048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre ss_all.2657174048
Directory	/workspace/20.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1146943533
Short name	T104
Test name
Test status
Simulation time	944554417 ps
CPU time	5.11 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:06 PM PDT 24
Peak memory	215256 kb
Host	smart-72fa3edd-bb17-4ece-80a1-c84e46d64a9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146943533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1 146943533
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/5.spi_device_stress_all.2318152367
Short name	T150
Test name
Test status
Simulation time	9803327248 ps
CPU time	151.35 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:30:09 PM PDT 24
Peak memory	258656 kb
Host	smart-438ac3d9-a7d0-4d62-abce-315b442b6152
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318152367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres s_all.2318152367
Directory	/workspace/5.spi_device_stress_all/latest

Test location	/workspace/coverage/default/19.spi_device_stress_all.2750021095
Short name	T190
Test name
Test status
Simulation time	74381738469 ps
CPU time	582.43 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:38:05 PM PDT 24
Peak memory	265556 kb
Host	smart-1e002d94-773d-4f46-86b4-87b6de212853
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750021095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre ss_all.2750021095
Directory	/workspace/19.spi_device_stress_all/latest

Test location	/workspace/coverage/default/15.spi_device_stress_all.3185359706
Short name	T42
Test name
Test status
Simulation time	11939418202 ps
CPU time	109.87 seconds
Started	May 14 01:28:11 PM PDT 24
Finished	May 14 01:30:03 PM PDT 24
Peak memory	249516 kb
Host	smart-67b84b57-8d5a-4a80-8e53-8bba8712645d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185359706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre ss_all.3185359706
Directory	/workspace/15.spi_device_stress_all/latest

Test location	/workspace/coverage/default/24.spi_device_flash_and_tpm.3010933246
Short name	T228
Test name
Test status
Simulation time	98114609652 ps
CPU time	309.92 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:33:49 PM PDT 24
Peak memory	265384 kb
Host	smart-876a2293-5132-4a1b-a250-5c65fbf7d24b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010933246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3010933246
Directory	/workspace/24.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/3.spi_device_stress_all.665990384
Short name	T250
Test name
Test status
Simulation time	577466293972 ps
CPU time	1109.34 seconds
Started	May 14 01:27:29 PM PDT 24
Finished	May 14 01:45:59 PM PDT 24
Peak memory	284528 kb
Host	smart-0eade154-5cfe-489d-9eaf-6626fc367945
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665990384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress _all.665990384
Directory	/workspace/3.spi_device_stress_all/latest

Test location	/workspace/coverage/default/31.spi_device_flash_all.4157863325
Short name	T226
Test name
Test status
Simulation time	20833859374 ps
CPU time	167.69 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:31:47 PM PDT 24
Peak memory	248896 kb
Host	smart-408c9418-f817-4479-beef-2dee05617917
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157863325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4157863325
Directory	/workspace/31.spi_device_flash_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_all.1659536075
Short name	T333
Test name
Test status
Simulation time	3072145866 ps
CPU time	24.41 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:28:58 PM PDT 24
Peak memory	216176 kb
Host	smart-a4290414-1c79-4379-a2de-09cb1d59b40f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659536075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1659536075
Directory	/workspace/23.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/19.spi_device_alert_test.1736410350
Short name	T356
Test name
Test status
Simulation time	17529869 ps
CPU time	0.81 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	204632 kb
Host	smart-e6b8faa6-2099-43a6-b44e-34cb9083b446
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736410350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test. 1736410350
Directory	/workspace/19.spi_device_alert_test/latest

Test location	/workspace/coverage/default/41.spi_device_flash_and_tpm.2648101316
Short name	T261
Test name
Test status
Simulation time	36519968250 ps
CPU time	155.53 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:32:05 PM PDT 24
Peak memory	249092 kb
Host	smart-57c20ff4-9a4b-43a2-9a09-05691f965b51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2648101316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2648101316
Directory	/workspace/41.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/27.spi_device_stress_all.2448072798
Short name	T53
Test name
Test status
Simulation time	52111433379 ps
CPU time	167.74 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:31:30 PM PDT 24
Peak memory	255800 kb
Host	smart-468539d3-9bde-489e-98bf-ca89edb6919a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448072798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre ss_all.2448072798
Directory	/workspace/27.spi_device_stress_all/latest

Test location	/workspace/coverage/default/23.spi_device_flash_and_tpm.616422943
Short name	T232
Test name
Test status
Simulation time	50515921976 ps
CPU time	514.29 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:37:12 PM PDT 24
Peak memory	256228 kb
Host	smart-347fe1e5-d4bd-49aa-b69e-f575ad5061c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616422943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.616422943
Directory	/workspace/23.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1347855029
Short name	T102
Test name
Test status
Simulation time	1385612779 ps
CPU time	3.66 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:15 PM PDT 24
Peak memory	215236 kb
Host	smart-d53b01f0-3002-4eb2-ba70-8e9434ef9bdb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347855029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 1347855029
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/24.spi_device_flash_mode.4129732806
Short name	T94
Test name
Test status
Simulation time	109564015 ps
CPU time	4.78 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	224564 kb
Host	smart-88de856b-ec9a-43ba-ba4f-d01ea5d44058
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129732806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4129732806
Directory	/workspace/24.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2589796832
Short name	T265
Test name
Test status
Simulation time	5676905672 ps
CPU time	74.37 seconds
Started	May 14 01:29:08 PM PDT 24
Finished	May 14 01:30:24 PM PDT 24
Peak memory	256100 kb
Host	smart-1a64d183-81d3-4871-a13a-78f490cea018
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589796832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl e.2589796832
Directory	/workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3408571898
Short name	T146
Test name
Test status
Simulation time	7669727362 ps
CPU time	24.14 seconds
Started	May 14 12:55:25 PM PDT 24
Finished	May 14 12:55:50 PM PDT 24
Peak memory	215560 kb
Host	smart-44dd8a4a-eca1-4458-b750-23eb3ea47e48
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408571898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic e_tl_intg_err.3408571898
Directory	/workspace/18.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3008637046
Short name	T231
Test name
Test status
Simulation time	3274024493 ps
CPU time	66.64 seconds
Started	May 14 01:27:45 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	256768 kb
Host	smart-64fa3153-f759-4769-abb9-4c7032e2f3a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008637046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl e.3008637046
Directory	/workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/36.spi_device_stress_all.3022806156
Short name	T229
Test name
Test status
Simulation time	155489701279 ps
CPU time	685.31 seconds
Started	May 14 01:29:13 PM PDT 24
Finished	May 14 01:40:40 PM PDT 24
Peak memory	263964 kb
Host	smart-272806dd-1ad7-4af8-9485-b5a8b568a11a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022806156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre ss_all.3022806156
Directory	/workspace/36.spi_device_stress_all/latest

Test location	/workspace/coverage/default/41.spi_device_stress_all.2100196018
Short name	T259
Test name
Test status
Simulation time	158820672087 ps
CPU time	214.4 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:33:02 PM PDT 24
Peak memory	240876 kb
Host	smart-16ba8b5a-8a7e-428e-ae0d-c1e1577cbd2f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100196018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre ss_all.2100196018
Directory	/workspace/41.spi_device_stress_all/latest

Test location	/workspace/coverage/default/25.spi_device_flash_mode.3857014620
Short name	T138
Test name
Test status
Simulation time	1484125134 ps
CPU time	25.86 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	232528 kb
Host	smart-41ea3736-6238-4956-99c9-99c3058bcbd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857014620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3857014620
Directory	/workspace/25.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/16.spi_device_flash_and_tpm.2590813376
Short name	T251
Test name
Test status
Simulation time	12828305374 ps
CPU time	115.92 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:30:17 PM PDT 24
Peak memory	251024 kb
Host	smart-5f15fc8c-d85f-4c6d-9b9c-df00c6268a4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590813376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2590813376
Directory	/workspace/16.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/23.spi_device_flash_mode.1491260704
Short name	T656
Test name
Test status
Simulation time	646383371 ps
CPU time	12.54 seconds
Started	May 14 01:28:34 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	224404 kb
Host	smart-8cded535-4ddb-4a5d-886b-507d0e4062b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491260704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1491260704
Directory	/workspace/23.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1852830501
Short name	T173
Test name
Test status
Simulation time	122252890472 ps
CPU time	564.47 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:38:48 PM PDT 24
Peak memory	249096 kb
Host	smart-a89ccd9e-befb-478a-a9e9-136c9d8cb793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852830501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl e.1852830501
Directory	/workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/39.spi_device_flash_mode.1633551786
Short name	T325
Test name
Test status
Simulation time	972114886 ps
CPU time	20.36 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:29:44 PM PDT 24
Peak memory	230780 kb
Host	smart-3524ebe2-f32d-45ce-bbbd-7ecd53c32d89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633551786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1633551786
Directory	/workspace/39.spi_device_flash_mode/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3145277373
Short name	T273
Test name
Test status
Simulation time	715382119 ps
CPU time	5.23 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:07 PM PDT 24
Peak memory	215696 kb
Host	smart-176b8ed6-e8f2-491a-8866-5fd6a20ad6e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145277373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3 145277373
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3932824795
Short name	T145
Test name
Test status
Simulation time	1731627186 ps
CPU time	8.8 seconds
Started	May 14 12:54:53 PM PDT 24
Finished	May 14 12:55:05 PM PDT 24
Peak memory	215196 kb
Host	smart-70885869-9238-4f68-9bc3-0d8c45b239c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932824795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.3932824795
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3023749348
Short name	T280
Test name
Test status
Simulation time	313138379 ps
CPU time	17.77 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:35 PM PDT 24
Peak memory	215236 kb
Host	smart-f9219a74-dcd8-4198-947d-024000ec22ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023749348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic e_tl_intg_err.3023749348
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_sts_read.681651835
Short name	T17
Test name
Test status
Simulation time	75181230 ps
CPU time	0.89 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:27:25 PM PDT 24
Peak memory	206616 kb
Host	smart-a69af3a4-cc0d-488f-98a2-423afda8b4d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681651835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.681651835
Directory	/workspace/1.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm.3429783849
Short name	T223
Test name
Test status
Simulation time	9727110387 ps
CPU time	155.55 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:30:48 PM PDT 24
Peak memory	255308 kb
Host	smart-cbec515a-3950-4f21-8796-3a998d377a2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429783849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3429783849
Directory	/workspace/14.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/2.spi_device_flash_all.2379910718
Short name	T249
Test name
Test status
Simulation time	109809500511 ps
CPU time	373.74 seconds
Started	May 14 01:27:30 PM PDT 24
Finished	May 14 01:33:45 PM PDT 24
Peak memory	253388 kb
Host	smart-b5c591cb-f4a7-47dd-8914-401e358779db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379910718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2379910718
Directory	/workspace/2.spi_device_flash_all/latest

Test location	/workspace/coverage/default/22.spi_device_flash_all.3801639365
Short name	T185
Test name
Test status
Simulation time	445944751409 ps
CPU time	379.52 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:34:53 PM PDT 24
Peak memory	248996 kb
Host	smart-2414e192-8962-4096-858f-16045321316a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801639365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3801639365
Directory	/workspace/22.spi_device_flash_all/latest

Test location	/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2060040755
Short name	T258
Test name
Test status
Simulation time	11111423485 ps
CPU time	11.1 seconds
Started	May 14 01:29:01 PM PDT 24
Finished	May 14 01:29:13 PM PDT 24
Peak memory	236144 kb
Host	smart-4ad3aafe-7ab3-40fe-9536-b8c810aa11ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060040755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa p.2060040755
Directory	/workspace/35.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4111535622
Short name	T184
Test name
Test status
Simulation time	54993689401 ps
CPU time	203.57 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:32:44 PM PDT 24
Peak memory	256980 kb
Host	smart-c5616ad0-2e9e-444a-a64c-8e14383f3950
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111535622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl e.4111535622
Directory	/workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/42.spi_device_flash_all.1405372864
Short name	T236
Test name
Test status
Simulation time	737557602 ps
CPU time	15.62 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:44 PM PDT 24
Peak memory	240748 kb
Host	smart-5ad7982c-4555-4a7c-8326-6dba8a072c89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405372864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1405372864
Directory	/workspace/42.spi_device_flash_all/latest

Test location	/workspace/coverage/default/11.spi_device_mailbox.1827882022
Short name	T208
Test name
Test status
Simulation time	24404427747 ps
CPU time	73.31 seconds
Started	May 14 01:27:51 PM PDT 24
Finished	May 14 01:29:06 PM PDT 24
Peak memory	218484 kb
Host	smart-d8320613-19c3-4497-942f-6752fba1555e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827882022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1827882022
Directory	/workspace/11.spi_device_mailbox/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3761337597
Short name	T83
Test name
Test status
Simulation time	42006972 ps
CPU time	1.45 seconds
Started	May 14 12:54:48 PM PDT 24
Finished	May 14 12:54:52 PM PDT 24
Peak memory	216060 kb
Host	smart-6a55d5fd-90f9-430a-bc33-a026e1dbb5ca
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761337597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.3761337597
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3549783723
Short name	T1002
Test name
Test status
Simulation time	648820712 ps
CPU time	16.71 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	214996 kb
Host	smart-01f73a33-99a6-4653-a6a9-9ce225a07dc6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549783723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.3549783723
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1735203181
Short name	T995
Test name
Test status
Simulation time	1005618782 ps
CPU time	11.5 seconds
Started	May 14 12:54:59 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	206932 kb
Host	smart-aa2f00b6-cfdb-45a0-b64b-16635087b24b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735203181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_bit_bash.1735203181
Directory	/workspace/0.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1134560458
Short name	T82
Test name
Test status
Simulation time	35528993 ps
CPU time	1.15 seconds
Started	May 14 12:54:53 PM PDT 24
Finished	May 14 12:54:56 PM PDT 24
Peak memory	206888 kb
Host	smart-8fa900bc-5e50-4f3b-8648-03feab0867c0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134560458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.1134560458
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3774789102
Short name	T1016
Test name
Test status
Simulation time	279053824 ps
CPU time	3.6 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:04 PM PDT 24
Peak memory	217544 kb
Host	smart-449bc3fa-270b-4a23-aad0-531768c17ba4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774789102 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3774789102
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3217272139
Short name	T1056
Test name
Test status
Simulation time	249215454 ps
CPU time	2.05 seconds
Started	May 14 12:54:52 PM PDT 24
Finished	May 14 12:54:56 PM PDT 24
Peak memory	215016 kb
Host	smart-05f699b6-06ea-430e-b42c-ef8d00a13009
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217272139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3 217272139
Directory	/workspace/0.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.1871770174
Short name	T984
Test name
Test status
Simulation time	14416335 ps
CPU time	0.68 seconds
Started	May 14 12:54:54 PM PDT 24
Finished	May 14 12:54:57 PM PDT 24
Peak memory	203788 kb
Host	smart-9d07b0ea-2c10-4f88-96e4-7527df002634
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871770174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1 871770174
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1926484570
Short name	T1058
Test name
Test status
Simulation time	212678062 ps
CPU time	2.38 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:02 PM PDT 24
Peak memory	215184 kb
Host	smart-97a34907-f5a7-4d70-8e58-e20e057c332b
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926484570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.1926484570
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3863993198
Short name	T1014
Test name
Test status
Simulation time	19766022 ps
CPU time	0.66 seconds
Started	May 14 12:54:46 PM PDT 24
Finished	May 14 12:54:51 PM PDT 24
Peak memory	203280 kb
Host	smart-5279bf08-7337-4cdc-9f26-5dd6eeb7c700
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863993198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me m_walk.3863993198
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.125700615
Short name	T1009
Test name
Test status
Simulation time	50911787 ps
CPU time	1.68 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:00 PM PDT 24
Peak memory	215168 kb
Host	smart-ae9a0b53-ca65-4850-bb68-ae035ba26346
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125700615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp i_device_same_csr_outstanding.125700615
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1070553877
Short name	T112
Test name
Test status
Simulation time	1868212173 ps
CPU time	22.66 seconds
Started	May 14 12:54:47 PM PDT 24
Finished	May 14 12:55:13 PM PDT 24
Peak memory	215080 kb
Host	smart-455eff35-6c75-46c2-bac5-766310c808fd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070553877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_aliasing.1070553877
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2394138809
Short name	T120
Test name
Test status
Simulation time	2603057482 ps
CPU time	33.32 seconds
Started	May 14 12:55:02 PM PDT 24
Finished	May 14 12:55:37 PM PDT 24
Peak memory	206996 kb
Host	smart-c50c4a44-1201-47bb-86a6-612835ec827d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394138809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_bit_bash.2394138809
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4052984248
Short name	T143
Test name
Test status
Simulation time	660167152 ps
CPU time	4.29 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:05 PM PDT 24
Peak memory	216864 kb
Host	smart-e1a3a469-41ae-4e15-abb6-8456fabe2ba9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052984248 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4052984248
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2043798666
Short name	T1004
Test name
Test status
Simulation time	230855722 ps
CPU time	2.75 seconds
Started	May 14 12:54:53 PM PDT 24
Finished	May 14 12:54:57 PM PDT 24
Peak memory	206920 kb
Host	smart-ccc93ffb-411f-4062-90ee-1a22e38951ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043798666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2 043798666
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.3409974853
Short name	T1000
Test name
Test status
Simulation time	35967194 ps
CPU time	0.71 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:01 PM PDT 24
Peak memory	203512 kb
Host	smart-11cd7865-7204-4df4-a0b0-6f4c9c5ba8cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409974853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3 409974853
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3860936379
Short name	T114
Test name
Test status
Simulation time	53025137 ps
CPU time	1.74 seconds
Started	May 14 12:54:53 PM PDT 24
Finished	May 14 12:54:56 PM PDT 24
Peak memory	215232 kb
Host	smart-84c4a6e2-c8d5-4f2f-be82-f3702d48e88c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860936379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.3860936379
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.709586846
Short name	T964
Test name
Test status
Simulation time	67229492 ps
CPU time	0.69 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:54:59 PM PDT 24
Peak memory	203424 kb
Host	smart-567baef2-f05e-4d56-be26-72b6e03fa154
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709586846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem _walk.709586846
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3137986610
Short name	T1079
Test name
Test status
Simulation time	78682562 ps
CPU time	2.67 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:05 PM PDT 24
Peak memory	215128 kb
Host	smart-5c79f61c-d2e9-4471-9a44-c9740b8e11ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137986610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.3137986610
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3009263044
Short name	T1032
Test name
Test status
Simulation time	56786175 ps
CPU time	1.76 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:02 PM PDT 24
Peak memory	215296 kb
Host	smart-8da400ce-bf56-45cb-92de-986a946cf2bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009263044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3 009263044
Directory	/workspace/1.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1510209224
Short name	T1047
Test name
Test status
Simulation time	1246742819 ps
CPU time	12.11 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:13 PM PDT 24
Peak memory	215148 kb
Host	smart-0bf94c20-bbc2-48d6-ab2b-856dfe8dccde
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510209224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.1510209224
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.674265224
Short name	T1003
Test name
Test status
Simulation time	226488995 ps
CPU time	3.53 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:22 PM PDT 24
Peak memory	216660 kb
Host	smart-94563de0-064a-4f5e-8deb-55a552439a58
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674265224 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.674265224
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3152313209
Short name	T1052
Test name
Test status
Simulation time	39417371 ps
CPU time	2.28 seconds
Started	May 14 12:55:11 PM PDT 24
Finished	May 14 12:55:15 PM PDT 24
Peak memory	215072 kb
Host	smart-19001c59-0ae0-4caf-bd09-b80ecfab3d73
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152313209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 3152313209
Directory	/workspace/10.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1403372692
Short name	T1078
Test name
Test status
Simulation time	14214212 ps
CPU time	0.7 seconds
Started	May 14 12:55:05 PM PDT 24
Finished	May 14 12:55:07 PM PDT 24
Peak memory	203544 kb
Host	smart-5822a708-6e6e-4cb5-936c-39e9f6de7b67
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403372692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 1403372692
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1165403871
Short name	T148
Test name
Test status
Simulation time	209859977 ps
CPU time	4.04 seconds
Started	May 14 12:54:54 PM PDT 24
Finished	May 14 12:55:00 PM PDT 24
Peak memory	215124 kb
Host	smart-1965a4be-714e-4312-ae97-8949d37523d1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165403871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.1165403871
Directory	/workspace/10.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1566413515
Short name	T95
Test name
Test status
Simulation time	158121874 ps
CPU time	3.08 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:02 PM PDT 24
Peak memory	216392 kb
Host	smart-d0db1424-b1d2-43ab-acd2-ad520f3768f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566413515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 1566413515
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.390760891
Short name	T274
Test name
Test status
Simulation time	653728990 ps
CPU time	14.23 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	215168 kb
Host	smart-ba33f302-563e-48df-89f5-5e6ae1940c0a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390760891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device _tl_intg_err.390760891
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.514709063
Short name	T107
Test name
Test status
Simulation time	125100664 ps
CPU time	3.55 seconds
Started	May 14 12:55:04 PM PDT 24
Finished	May 14 12:55:09 PM PDT 24
Peak memory	217052 kb
Host	smart-e63bbb5b-ea47-4d45-8584-80fd6ec3ba02
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514709063 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.514709063
Directory	/workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4197981679
Short name	T110
Test name
Test status
Simulation time	113205660 ps
CPU time	1.9 seconds
Started	May 14 12:55:02 PM PDT 24
Finished	May 14 12:55:06 PM PDT 24
Peak memory	206912 kb
Host	smart-0cb85272-e4e3-47ca-bda6-018b3a225a4d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197981679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw. 4197981679
Directory	/workspace/11.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.333848248
Short name	T1073
Test name
Test status
Simulation time	15563107 ps
CPU time	0.75 seconds
Started	May 14 12:55:17 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	203460 kb
Host	smart-9eabf8c4-6f79-405e-977a-4f24ed022e44
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333848248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.333848248
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1490838855
Short name	T1038
Test name
Test status
Simulation time	156411061 ps
CPU time	2.64 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:04 PM PDT 24
Peak memory	215112 kb
Host	smart-467f1c15-ad88-4490-9b1c-82236648967d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490838855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.1490838855
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4097337690
Short name	T271
Test name
Test status
Simulation time	635773301 ps
CPU time	3.88 seconds
Started	May 14 12:54:59 PM PDT 24
Finished	May 14 12:55:06 PM PDT 24
Peak memory	215368 kb
Host	smart-12d298b5-87ac-4891-b0fa-4abc377d81df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097337690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors. 4097337690
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2375053765
Short name	T278
Test name
Test status
Simulation time	1643687323 ps
CPU time	12.94 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:11 PM PDT 24
Peak memory	216448 kb
Host	smart-addbf48e-3eab-4251-91f3-5d6184d9ed4d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375053765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.2375053765
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4285429418
Short name	T987
Test name
Test status
Simulation time	542406653 ps
CPU time	4.04 seconds
Started	May 14 12:55:18 PM PDT 24
Finished	May 14 12:55:25 PM PDT 24
Peak memory	216640 kb
Host	smart-713fb823-1c7f-4556-b6e1-72ebd8d2ed48
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285429418 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4285429418
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.462320062
Short name	T137
Test name
Test status
Simulation time	40416589 ps
CPU time	1.24 seconds
Started	May 14 12:55:17 PM PDT 24
Finished	May 14 12:55:22 PM PDT 24
Peak memory	215000 kb
Host	smart-6e55fa43-0437-4912-a447-472b3c15c827
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462320062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.462320062
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1841992204
Short name	T996
Test name
Test status
Simulation time	50579158 ps
CPU time	0.69 seconds
Started	May 14 12:55:11 PM PDT 24
Finished	May 14 12:55:13 PM PDT 24
Peak memory	203472 kb
Host	smart-6c21a883-10b8-4b83-9844-7c07b0a7f29f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841992204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 1841992204
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.723036121
Short name	T1031
Test name
Test status
Simulation time	313601196 ps
CPU time	3.99 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215104 kb
Host	smart-274776f0-8990-4bad-9e4d-2691802b2f64
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723036121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s pi_device_same_csr_outstanding.723036121
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3935081440
Short name	T1011
Test name
Test status
Simulation time	2130626168 ps
CPU time	13.59 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:30 PM PDT 24
Peak memory	215672 kb
Host	smart-025d5825-8d0a-403b-9a57-8e7e9f58ba2f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935081440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.3935081440
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1702199475
Short name	T1071
Test name
Test status
Simulation time	352779609 ps
CPU time	2.53 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	216612 kb
Host	smart-502b351a-3975-4123-abcf-c69ad702e93b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702199475 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1702199475
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3958524639
Short name	T1048
Test name
Test status
Simulation time	150191869 ps
CPU time	2.58 seconds
Started	May 14 12:55:12 PM PDT 24
Finished	May 14 12:55:15 PM PDT 24
Peak memory	215028 kb
Host	smart-85b38dcd-9a6e-46a0-8c48-c41a8528af39
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958524639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw. 3958524639
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1674449432
Short name	T1075
Test name
Test status
Simulation time	44242005 ps
CPU time	0.76 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:11 PM PDT 24
Peak memory	203736 kb
Host	smart-81b7daa9-10a8-465c-9ad7-2057a193b847
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674449432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 1674449432
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2595133763
Short name	T978
Test name
Test status
Simulation time	44080339 ps
CPU time	2.52 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	215088 kb
Host	smart-322a49d1-af68-45ca-b3e6-a2efb3261c22
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595133763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.2595133763
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3470717607
Short name	T1074
Test name
Test status
Simulation time	210831398 ps
CPU time	4.78 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	215440 kb
Host	smart-e6e339f6-b991-4a31-9c70-648b38a2f545
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470717607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 3470717607
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3213030932
Short name	T97
Test name
Test status
Simulation time	969964290 ps
CPU time	20.04 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:30 PM PDT 24
Peak memory	215260 kb
Host	smart-db8a21dd-7f90-4c64-8536-b67a1f1a548f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213030932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic e_tl_intg_err.3213030932
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4005671113
Short name	T147
Test name
Test status
Simulation time	219603532 ps
CPU time	1.73 seconds
Started	May 14 12:55:12 PM PDT 24
Finished	May 14 12:55:15 PM PDT 24
Peak memory	215232 kb
Host	smart-85e95856-2d67-42b7-8c52-79328698566f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005671113 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4005671113
Directory	/workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1081215876
Short name	T118
Test name
Test status
Simulation time	28025055 ps
CPU time	1.89 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:22 PM PDT 24
Peak memory	215064 kb
Host	smart-13971fdc-f1e5-4efe-9294-89b322717401
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081215876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 1081215876
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.4046267492
Short name	T1081
Test name
Test status
Simulation time	19855488 ps
CPU time	0.75 seconds
Started	May 14 12:55:12 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	203836 kb
Host	smart-168c72e4-4574-4369-a591-fab0f0c9d9eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046267492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 4046267492
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2844237174
Short name	T1020
Test name
Test status
Simulation time	77783158 ps
CPU time	1.81 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:17 PM PDT 24
Peak memory	214924 kb
Host	smart-e11ccfab-f062-4229-99ad-a8ec2c5f48d1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844237174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.2844237174
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3405889561
Short name	T98
Test name
Test status
Simulation time	282663374 ps
CPU time	3.48 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	215292 kb
Host	smart-46582dcc-925f-4a09-99bb-f0ec2bc314c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405889561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors. 3405889561
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4276220657
Short name	T1055
Test name
Test status
Simulation time	197398052 ps
CPU time	12.07 seconds
Started	May 14 12:55:07 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	215188 kb
Host	smart-7ece6ec9-a720-42a2-b4f7-c0e0447744fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276220657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.4276220657
Directory	/workspace/14.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1095007788
Short name	T116
Test name
Test status
Simulation time	93151075 ps
CPU time	1.19 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:13 PM PDT 24
Peak memory	206936 kb
Host	smart-7709b183-62fd-4faf-be5e-f49ac085d721
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095007788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 1095007788
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1428081666
Short name	T1069
Test name
Test status
Simulation time	13979505 ps
CPU time	0.72 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	203508 kb
Host	smart-6f796cd2-ad3d-460d-b6bd-2f2e395e223b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428081666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 1428081666
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1097293435
Short name	T136
Test name
Test status
Simulation time	320909350 ps
CPU time	4.03 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	215136 kb
Host	smart-1c12b257-3bdd-49f1-811e-695baa56ca5b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097293435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.1097293435
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2997548512
Short name	T103
Test name
Test status
Simulation time	312071904 ps
CPU time	3.88 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215348 kb
Host	smart-5aaf0c63-c632-47fb-820e-ce6b70a98124
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997548512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors. 2997548512
Directory	/workspace/15.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2244753700
Short name	T1067
Test name
Test status
Simulation time	333591680 ps
CPU time	7.48 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215672 kb
Host	smart-2e654ba6-caa9-4366-8965-17ca49790ca0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244753700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic e_tl_intg_err.2244753700
Directory	/workspace/15.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.215317215
Short name	T1080
Test name
Test status
Simulation time	49913047 ps
CPU time	1.72 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:17 PM PDT 24
Peak memory	215248 kb
Host	smart-a82a9904-78ce-4277-9855-c5f8b06f452b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215317215 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.215317215
Directory	/workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1115915626
Short name	T1059
Test name
Test status
Simulation time	69885577 ps
CPU time	1.84 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:16 PM PDT 24
Peak memory	215084 kb
Host	smart-44a6e199-9dc7-4983-b353-5b1b41861c7d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115915626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 1115915626
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1008217901
Short name	T1057
Test name
Test status
Simulation time	45867766 ps
CPU time	0.65 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203856 kb
Host	smart-52645d55-bba1-4943-b17d-130e637e6e56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008217901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test. 1008217901
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.593834344
Short name	T1018
Test name
Test status
Simulation time	28216362 ps
CPU time	1.66 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	206808 kb
Host	smart-3e3d564e-db2e-42db-bf0e-0c45a3b28e2a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593834344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s pi_device_same_csr_outstanding.593834344
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3771017841
Short name	T983
Test name
Test status
Simulation time	339756048 ps
CPU time	5.09 seconds
Started	May 14 12:55:08 PM PDT 24
Finished	May 14 12:55:13 PM PDT 24
Peak memory	215356 kb
Host	smart-280b0bd8-8a13-48f1-9ab5-de60eafd49f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771017841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 3771017841
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2724628343
Short name	T1061
Test name
Test status
Simulation time	114717150 ps
CPU time	6.82 seconds
Started	May 14 12:55:12 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	215172 kb
Host	smart-a1133fae-b2a6-4604-a3de-4fa58e1f75e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724628343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.2724628343
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3203161210
Short name	T974
Test name
Test status
Simulation time	153971088 ps
CPU time	2.96 seconds
Started	May 14 12:55:18 PM PDT 24
Finished	May 14 12:55:24 PM PDT 24
Peak memory	216880 kb
Host	smart-f4b96e47-eede-407e-a2c8-4c8e91e35bc8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203161210 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3203161210
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.897210998
Short name	T122
Test name
Test status
Simulation time	944900261 ps
CPU time	2.58 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:17 PM PDT 24
Peak memory	215088 kb
Host	smart-35f76ce1-b0d1-4e2d-ac9f-dc34a167ab57
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897210998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.897210998
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2903034481
Short name	T1040
Test name
Test status
Simulation time	21531698 ps
CPU time	0.71 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203348 kb
Host	smart-7b50d48b-7cfc-44e1-9217-29473238058e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903034481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test. 2903034481
Directory	/workspace/17.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3556467767
Short name	T135
Test name
Test status
Simulation time	146278423 ps
CPU time	2.6 seconds
Started	May 14 12:55:12 PM PDT 24
Finished	May 14 12:55:16 PM PDT 24
Peak memory	215020 kb
Host	smart-4a911a51-cff0-4d74-b5d4-be8dda4e1c90
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556467767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.3556467767
Directory	/workspace/17.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1962472577
Short name	T100
Test name
Test status
Simulation time	106150219 ps
CPU time	2.45 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	215116 kb
Host	smart-f2498e5f-eafc-490c-93e5-7a595f112da4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962472577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors. 1962472577
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3603968487
Short name	T144
Test name
Test status
Simulation time	402503546 ps
CPU time	2.59 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	217628 kb
Host	smart-71e5c535-b88b-45d3-9873-f3d317ef1585
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603968487 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3603968487
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.929234659
Short name	T117
Test name
Test status
Simulation time	130929780 ps
CPU time	2.11 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215068 kb
Host	smart-fc096f97-cfbb-49c3-9979-577d6a960dfc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929234659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.929234659
Directory	/workspace/18.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1481147666
Short name	T992
Test name
Test status
Simulation time	26163998 ps
CPU time	0.68 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203816 kb
Host	smart-9546df30-6721-439d-8bd3-507100769ab2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481147666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 1481147666
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2348457296
Short name	T980
Test name
Test status
Simulation time	59188546 ps
CPU time	1.82 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	206936 kb
Host	smart-31fb96ad-4ff6-43fa-b4aa-75500ae3cf4e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348457296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.2348457296
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2316195404
Short name	T105
Test name
Test status
Simulation time	25547328 ps
CPU time	1.62 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	215384 kb
Host	smart-c4f95ff6-cee0-43bf-be25-61d995df81c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316195404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 2316195404
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2056048186
Short name	T985
Test name
Test status
Simulation time	85419000 ps
CPU time	2.59 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:22 PM PDT 24
Peak memory	217384 kb
Host	smart-74a1c781-724e-4cf6-b58a-4f4034476ecc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056048186 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2056048186
Directory	/workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1763619146
Short name	T970
Test name
Test status
Simulation time	26170898 ps
CPU time	0.73 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	203524 kb
Host	smart-7d564c9d-b8c0-4e10-b0ed-5cca4c44bfd2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763619146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 1763619146
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.547426973
Short name	T1072
Test name
Test status
Simulation time	143924229 ps
CPU time	2.75 seconds
Started	May 14 12:55:11 PM PDT 24
Finished	May 14 12:55:15 PM PDT 24
Peak memory	215100 kb
Host	smart-9df24a32-9aef-468b-9ff5-e52a27d87fcf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547426973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s pi_device_same_csr_outstanding.547426973
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3255519488
Short name	T101
Test name
Test status
Simulation time	138771148 ps
CPU time	3.32 seconds
Started	May 14 12:55:30 PM PDT 24
Finished	May 14 12:55:34 PM PDT 24
Peak memory	215320 kb
Host	smart-27648c83-1d01-455f-acd8-2d6959415e26
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255519488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 3255519488
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.441321078
Short name	T1068
Test name
Test status
Simulation time	691177788 ps
CPU time	15.58 seconds
Started	May 14 12:55:31 PM PDT 24
Finished	May 14 12:55:47 PM PDT 24
Peak memory	215136 kb
Host	smart-78d6f5da-2389-4b17-bc99-ca797e7ada82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441321078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device _tl_intg_err.441321078
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3914279693
Short name	T1027
Test name
Test status
Simulation time	1147910489 ps
CPU time	15.93 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:26 PM PDT 24
Peak memory	206908 kb
Host	smart-c8ad9298-04e4-4bf7-aebc-581395eee8e2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914279693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.3914279693
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2316146218
Short name	T1022
Test name
Test status
Simulation time	1856553532 ps
CPU time	13.62 seconds
Started	May 14 12:54:59 PM PDT 24
Finished	May 14 12:55:16 PM PDT 24
Peak memory	206900 kb
Host	smart-972e2027-f740-4d6a-b52f-6c01f7485885
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316146218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.2316146218
Directory	/workspace/2.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4166036465
Short name	T84
Test name
Test status
Simulation time	21215462 ps
CPU time	1.14 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:54:59 PM PDT 24
Peak memory	206888 kb
Host	smart-c43a9e72-4284-4255-a0b0-3c12637b3c50
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166036465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.4166036465
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3138181101
Short name	T979
Test name
Test status
Simulation time	28666380 ps
CPU time	1.67 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	215212 kb
Host	smart-edde8ac3-092a-49eb-baaa-71263c630c14
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138181101 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3138181101
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.401919534
Short name	T1041
Test name
Test status
Simulation time	94838774 ps
CPU time	2.82 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:02 PM PDT 24
Peak memory	206892 kb
Host	smart-c6e2d349-5edf-48fc-9be5-c1e31f489500
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401919534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.401919534
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3411463554
Short name	T1039
Test name
Test status
Simulation time	13784565 ps
CPU time	0.72 seconds
Started	May 14 12:54:50 PM PDT 24
Finished	May 14 12:54:53 PM PDT 24
Peak memory	203484 kb
Host	smart-3f2e0f59-e841-40e4-875d-72eabf64520d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411463554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3 411463554
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2068257473
Short name	T115
Test name
Test status
Simulation time	678716647 ps
CPU time	1.34 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:00 PM PDT 24
Peak memory	215192 kb
Host	smart-88b4f5c6-35f0-46dd-b86f-03d0c4e613ba
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068257473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.2068257473
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.178368874
Short name	T962
Test name
Test status
Simulation time	12305039 ps
CPU time	0.65 seconds
Started	May 14 12:54:53 PM PDT 24
Finished	May 14 12:54:56 PM PDT 24
Peak memory	203416 kb
Host	smart-000e8ce4-b986-4433-b3d5-bcb1af5d8bb2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178368874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem _walk.178368874
Directory	/workspace/2.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3496200426
Short name	T986
Test name
Test status
Simulation time	98706203 ps
CPU time	1.91 seconds
Started	May 14 12:54:50 PM PDT 24
Finished	May 14 12:54:55 PM PDT 24
Peak memory	215196 kb
Host	smart-167ee731-9e63-4d6e-a4c4-33606a363f71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496200426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.3496200426
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3691560981
Short name	T1036
Test name
Test status
Simulation time	126332051 ps
CPU time	3.97 seconds
Started	May 14 12:54:54 PM PDT 24
Finished	May 14 12:55:00 PM PDT 24
Peak memory	216344 kb
Host	smart-bbd30de5-fbd8-4617-8c0b-ed6b9be0edc4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691560981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3 691560981
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.175451171
Short name	T1025
Test name
Test status
Simulation time	80756730 ps
CPU time	0.72 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203704 kb
Host	smart-7cd50359-136d-4424-9244-974dc475e202
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175451171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.175451171
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.839076236
Short name	T1046
Test name
Test status
Simulation time	118788501 ps
CPU time	0.66 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	203516 kb
Host	smart-e1458ec1-d101-43bb-b068-1e826938c4fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839076236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.839076236
Directory	/workspace/21.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1118490736
Short name	T1050
Test name
Test status
Simulation time	14091578 ps
CPU time	0.72 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:17 PM PDT 24
Peak memory	203512 kb
Host	smart-1ff3723e-d121-403d-a930-0ee039e001c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118490736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 1118490736
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.2149205403
Short name	T1021
Test name
Test status
Simulation time	43257296 ps
CPU time	0.72 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203736 kb
Host	smart-75f48c31-e562-46d0-865e-463586ea29e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149205403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test. 2149205403
Directory	/workspace/23.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3945539012
Short name	T1030
Test name
Test status
Simulation time	46207302 ps
CPU time	0.71 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203812 kb
Host	smart-1043110a-ad6a-423b-884e-d954141e1a99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945539012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 3945539012
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1943847835
Short name	T1042
Test name
Test status
Simulation time	13402225 ps
CPU time	0.73 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203836 kb
Host	smart-c3618c52-b849-42fc-8a64-14f514c40203
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943847835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test. 1943847835
Directory	/workspace/25.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2995078955
Short name	T1012
Test name
Test status
Simulation time	15700320 ps
CPU time	0.75 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203516 kb
Host	smart-5f2804e0-20f0-40ca-8d9d-c4cc127c2bae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995078955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test. 2995078955
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.202714116
Short name	T1034
Test name
Test status
Simulation time	22714935 ps
CPU time	0.69 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203540 kb
Host	smart-fb46aa86-46b2-482c-935e-169a146637d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202714116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.202714116
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1771849603
Short name	T963
Test name
Test status
Simulation time	33601454 ps
CPU time	0.75 seconds
Started	May 14 12:55:24 PM PDT 24
Finished	May 14 12:55:25 PM PDT 24
Peak memory	203680 kb
Host	smart-ae70b9f8-0178-432c-b48b-992d9cc6dce9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771849603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 1771849603
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1962940854
Short name	T994
Test name
Test status
Simulation time	10939938 ps
CPU time	0.7 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	203856 kb
Host	smart-8201862a-c5c8-428d-8387-2c68dad892b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962940854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test. 1962940854
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3799022034
Short name	T1045
Test name
Test status
Simulation time	324123930 ps
CPU time	20.06 seconds
Started	May 14 12:55:04 PM PDT 24
Finished	May 14 12:55:26 PM PDT 24
Peak memory	215032 kb
Host	smart-e8c43850-3f99-42b1-b33d-f9b3df7c51c4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799022034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.3799022034
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2202816641
Short name	T1037
Test name
Test status
Simulation time	2615901482 ps
CPU time	12.67 seconds
Started	May 14 12:54:51 PM PDT 24
Finished	May 14 12:55:06 PM PDT 24
Peak memory	207060 kb
Host	smart-51a934ec-67b4-4b66-8da8-3e9fa2d97eaa
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202816641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.2202816641
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3467285032
Short name	T85
Test name
Test status
Simulation time	38946107 ps
CPU time	1.41 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:13 PM PDT 24
Peak memory	206832 kb
Host	smart-401bd1bb-ad7b-473f-8334-2a5c1b07f5f9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467285032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.3467285032
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1786284566
Short name	T989
Test name
Test status
Simulation time	482243282 ps
CPU time	3.44 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	216508 kb
Host	smart-2332cb34-d113-4c91-b371-d16d1944549f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786284566 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1786284566
Directory	/workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3837700728
Short name	T1054
Test name
Test status
Simulation time	82110029 ps
CPU time	2.24 seconds
Started	May 14 12:55:12 PM PDT 24
Finished	May 14 12:55:16 PM PDT 24
Peak memory	215104 kb
Host	smart-414b0ccf-79e9-4a56-bf93-c40e26498dde
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837700728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3 837700728
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4073225877
Short name	T1077
Test name
Test status
Simulation time	21820631 ps
CPU time	0.72 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:54:58 PM PDT 24
Peak memory	203472 kb
Host	smart-be57ebf1-b978-408e-9d70-3f12113e24f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073225877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4 073225877
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.25156998
Short name	T113
Test name
Test status
Simulation time	410805240 ps
CPU time	1.75 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:54:59 PM PDT 24
Peak memory	214828 kb
Host	smart-d354e819-36fd-45db-936b-ee99a2124a7f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25156998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi _device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_d evice_mem_partial_access.25156998
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2928368597
Short name	T1064
Test name
Test status
Simulation time	27819917 ps
CPU time	0.66 seconds
Started	May 14 12:54:59 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	203312 kb
Host	smart-7c21db45-19c4-4db9-9c1c-f5a104d87ebc
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928368597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me m_walk.2928368597
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.59836500
Short name	T134
Test name
Test status
Simulation time	67341430 ps
CPU time	3.83 seconds
Started	May 14 12:54:59 PM PDT 24
Finished	May 14 12:55:06 PM PDT 24
Peak memory	215044 kb
Host	smart-11b0b6ba-cb0c-437d-8813-f2e8311ffd4d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59836500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_same_csr_outstanding.59836500
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2469978645
Short name	T272
Test name
Test status
Simulation time	168855660 ps
CPU time	4.15 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:05 PM PDT 24
Peak memory	216344 kb
Host	smart-6a7e54a5-9be0-48ee-aa48-c892e6e4bf2e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469978645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2 469978645
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2726584371
Short name	T277
Test name
Test status
Simulation time	294813141 ps
CPU time	17.76 seconds
Started	May 14 12:54:52 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	215216 kb
Host	smart-126e472f-b092-4727-8506-6bb37808a1ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726584371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.2726584371
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2546561647
Short name	T1066
Test name
Test status
Simulation time	13703245 ps
CPU time	0.74 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	203436 kb
Host	smart-825bfe82-9610-4c52-9ea8-2256005f534c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546561647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 2546561647
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.4115746510
Short name	T967
Test name
Test status
Simulation time	62826659 ps
CPU time	0.67 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	203420 kb
Host	smart-12e4f81a-16cf-4698-ae81-9b85cc36c7c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115746510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test. 4115746510
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1149743841
Short name	T975
Test name
Test status
Simulation time	22234666 ps
CPU time	0.71 seconds
Started	May 14 12:55:20 PM PDT 24
Finished	May 14 12:55:23 PM PDT 24
Peak memory	203828 kb
Host	smart-109d0d28-58c3-4d0b-b89b-2950c099b237
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149743841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test. 1149743841
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.3134388815
Short name	T991
Test name
Test status
Simulation time	11276435 ps
CPU time	0.76 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	203508 kb
Host	smart-c7dd6d91-090c-4c11-8f22-c204060dc69c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134388815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test. 3134388815
Directory	/workspace/33.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.2020737126
Short name	T982
Test name
Test status
Simulation time	42766866 ps
CPU time	0.72 seconds
Started	May 14 12:55:29 PM PDT 24
Finished	May 14 12:55:30 PM PDT 24
Peak memory	203836 kb
Host	smart-57aafa03-3dfd-44a0-8adc-e064c99e41f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020737126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 2020737126
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.191407691
Short name	T1033
Test name
Test status
Simulation time	25463407 ps
CPU time	0.76 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203508 kb
Host	smart-54b58600-3ee3-49d3-9f79-da9a178aa2d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191407691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.191407691
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.1441904567
Short name	T999
Test name
Test status
Simulation time	27336080 ps
CPU time	0.71 seconds
Started	May 14 12:55:17 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	203812 kb
Host	smart-9f5e3b00-f45c-4371-99a6-49df7c0b2eb9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441904567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test. 1441904567
Directory	/workspace/36.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.272741463
Short name	T1008
Test name
Test status
Simulation time	22324740 ps
CPU time	0.71 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203828 kb
Host	smart-fad9a93f-845c-4864-883c-dcd0eec56705
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272741463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.272741463
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2697479017
Short name	T1060
Test name
Test status
Simulation time	28122974 ps
CPU time	0.72 seconds
Started	May 14 12:55:22 PM PDT 24
Finished	May 14 12:55:24 PM PDT 24
Peak memory	203500 kb
Host	smart-0b4d7085-f558-4024-8bc8-51fc05ba3f64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697479017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 2697479017
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1737767342
Short name	T1015
Test name
Test status
Simulation time	48741566 ps
CPU time	0.76 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203804 kb
Host	smart-eb27ebfc-af30-4c07-9707-388671f56f21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737767342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 1737767342
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2213682652
Short name	T1049
Test name
Test status
Simulation time	106565565 ps
CPU time	7.26 seconds
Started	May 14 12:55:03 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	214952 kb
Host	smart-cdf1c409-db8f-4dd0-9d20-6fcb79248c4d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213682652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.2213682652
Directory	/workspace/4.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.704893110
Short name	T142
Test name
Test status
Simulation time	3134609018 ps
CPU time	23.59 seconds
Started	May 14 12:55:18 PM PDT 24
Finished	May 14 12:55:45 PM PDT 24
Peak memory	215108 kb
Host	smart-c49b4c1f-a556-45d5-98bc-8faf88d41e91
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704893110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _bit_bash.704893110
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.657721464
Short name	T1006
Test name
Test status
Simulation time	32424883 ps
CPU time	1.27 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:01 PM PDT 24
Peak memory	216112 kb
Host	smart-0ad4bc73-3ae5-44b6-aa85-10a513d8eceb
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657721464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _hw_reset.657721464
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1749292566
Short name	T1024
Test name
Test status
Simulation time	365221216 ps
CPU time	3.47 seconds
Started	May 14 12:55:11 PM PDT 24
Finished	May 14 12:55:16 PM PDT 24
Peak memory	217336 kb
Host	smart-2ac64739-cbba-4481-ae06-cac045a3dd03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749292566 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1749292566
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2279270594
Short name	T119
Test name
Test status
Simulation time	406347234 ps
CPU time	2.03 seconds
Started	May 14 12:55:13 PM PDT 24
Finished	May 14 12:55:22 PM PDT 24
Peak memory	215036 kb
Host	smart-25fbbc3f-f1d4-4726-9197-86f314188757
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279270594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2 279270594
Directory	/workspace/4.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.4219157515
Short name	T1017
Test name
Test status
Simulation time	20323388 ps
CPU time	0.66 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203344 kb
Host	smart-84d0055f-d696-4271-afc9-d1d13922bb29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219157515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4 219157515
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2685365834
Short name	T1035
Test name
Test status
Simulation time	55241162 ps
CPU time	2.05 seconds
Started	May 14 12:54:59 PM PDT 24
Finished	May 14 12:55:04 PM PDT 24
Peak memory	215240 kb
Host	smart-4378b049-bfaa-44a0-8846-84d546885a2d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685365834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.2685365834
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1400979216
Short name	T969
Test name
Test status
Simulation time	10808610 ps
CPU time	0.67 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203336 kb
Host	smart-1282b75b-f9ff-42b5-b6cc-bd7cdc7625d4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400979216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.1400979216
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2351256983
Short name	T1026
Test name
Test status
Simulation time	400733691 ps
CPU time	1.64 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	215172 kb
Host	smart-155b90ec-74f7-4665-b0ef-c8f8348d36b7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351256983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s pi_device_same_csr_outstanding.2351256983
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3496608181
Short name	T71
Test name
Test status
Simulation time	187828339 ps
CPU time	1.74 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	215284 kb
Host	smart-5a060267-fb1d-4403-866a-6f18a22c17c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496608181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3 496608181
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1331721314
Short name	T96
Test name
Test status
Simulation time	188552302 ps
CPU time	11.94 seconds
Started	May 14 12:55:06 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	215196 kb
Host	smart-5888d099-df27-479d-a09b-f0995955b1df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331721314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.1331721314
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.707744437
Short name	T1013
Test name
Test status
Simulation time	99520378 ps
CPU time	0.69 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:24 PM PDT 24
Peak memory	203840 kb
Host	smart-734337e5-7f66-410a-8118-74bf86f53b23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707744437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.707744437
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.4090597640
Short name	T976
Test name
Test status
Simulation time	12563106 ps
CPU time	0.67 seconds
Started	May 14 12:55:26 PM PDT 24
Finished	May 14 12:55:27 PM PDT 24
Peak memory	203504 kb
Host	smart-be2059a8-d666-42a8-9e09-f7e9b9002248
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090597640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 4090597640
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.368924054
Short name	T1005
Test name
Test status
Simulation time	11285282 ps
CPU time	0.72 seconds
Started	May 14 12:55:39 PM PDT 24
Finished	May 14 12:55:43 PM PDT 24
Peak memory	203468 kb
Host	smart-50e6ef62-34b9-442c-9cd8-d1d7b96d5d63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368924054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.368924054
Directory	/workspace/42.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.2840166388
Short name	T968
Test name
Test status
Simulation time	21440121 ps
CPU time	0.73 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	203544 kb
Host	smart-31dbd528-d2fa-488e-b5bf-41e7e7c81c7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840166388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 2840166388
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.16445958
Short name	T988
Test name
Test status
Simulation time	17544209 ps
CPU time	0.73 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	203536 kb
Host	smart-93b3e9db-619d-4957-aa86-872f4514b3c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16445958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.16445958
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.1675461237
Short name	T972
Test name
Test status
Simulation time	34952055 ps
CPU time	0.73 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:19 PM PDT 24
Peak memory	203516 kb
Host	smart-3107a0b2-de23-4363-9ae7-02b318ff06f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675461237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 1675461237
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.1688207116
Short name	T977
Test name
Test status
Simulation time	14268368 ps
CPU time	0.68 seconds
Started	May 14 12:55:35 PM PDT 24
Finished	May 14 12:55:37 PM PDT 24
Peak memory	203416 kb
Host	smart-373ba529-cf09-43f6-a332-1144418cb9c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688207116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test. 1688207116
Directory	/workspace/46.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3446339839
Short name	T966
Test name
Test status
Simulation time	17401838 ps
CPU time	0.7 seconds
Started	May 14 12:55:20 PM PDT 24
Finished	May 14 12:55:23 PM PDT 24
Peak memory	203740 kb
Host	smart-c1389147-f80e-45ed-9f6f-3a2b7c97ce73
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446339839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test. 3446339839
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.793999633
Short name	T973
Test name
Test status
Simulation time	30908657 ps
CPU time	0.75 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	203680 kb
Host	smart-10f8a2d4-c010-475c-a09c-8c557ea3867a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793999633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.793999633
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.3611162319
Short name	T971
Test name
Test status
Simulation time	19640812 ps
CPU time	0.7 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	203528 kb
Host	smart-da56ad41-536b-4b50-90e0-ba80d3629aca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611162319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test. 3611162319
Directory	/workspace/49.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1614187697
Short name	T1010
Test name
Test status
Simulation time	101687253 ps
CPU time	2.69 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	217624 kb
Host	smart-0e5a1357-51d4-43bb-afa8-57059a07ebb9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614187697 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1614187697
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.915649874
Short name	T109
Test name
Test status
Simulation time	29029356 ps
CPU time	1.72 seconds
Started	May 14 12:55:03 PM PDT 24
Finished	May 14 12:55:07 PM PDT 24
Peak memory	215000 kb
Host	smart-2f4c29aa-758d-4d8a-8771-d2b714b7096b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915649874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.915649874
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.2073290843
Short name	T997
Test name
Test status
Simulation time	26573722 ps
CPU time	0.69 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:54:59 PM PDT 24
Peak memory	203488 kb
Host	smart-4104d047-80b8-47e3-8212-141421021718
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073290843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2 073290843
Directory	/workspace/5.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1085884496
Short name	T1029
Test name
Test status
Simulation time	2781694924 ps
CPU time	3.31 seconds
Started	May 14 12:55:08 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215240 kb
Host	smart-98f76930-79c1-4364-ad59-37550c9d6c1e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085884496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s pi_device_same_csr_outstanding.1085884496
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4266911015
Short name	T279
Test name
Test status
Simulation time	397889253 ps
CPU time	6.82 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:07 PM PDT 24
Peak memory	215196 kb
Host	smart-cdc9c439-d25f-43de-9af8-39805741e21c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266911015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.4266911015
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.832525013
Short name	T106
Test name
Test status
Simulation time	242816765 ps
CPU time	1.77 seconds
Started	May 14 12:55:16 PM PDT 24
Finished	May 14 12:55:21 PM PDT 24
Peak memory	215000 kb
Host	smart-0b3b91c2-3da4-454d-a369-85d2b8dc2ea7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832525013 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.832525013
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.716409902
Short name	T1023
Test name
Test status
Simulation time	345347103 ps
CPU time	2.75 seconds
Started	May 14 12:55:15 PM PDT 24
Finished	May 14 12:55:20 PM PDT 24
Peak memory	214868 kb
Host	smart-2d0c2dee-dde3-4166-9f64-709f7695df32
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716409902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.716409902
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3959004354
Short name	T965
Test name
Test status
Simulation time	15516148 ps
CPU time	0.69 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:11 PM PDT 24
Peak memory	203536 kb
Host	smart-c50b36cd-baef-4ead-bc7d-d36ae110e3c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959004354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3 959004354
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2961234743
Short name	T1062
Test name
Test status
Simulation time	44709904 ps
CPU time	2.52 seconds
Started	May 14 12:55:04 PM PDT 24
Finished	May 14 12:55:08 PM PDT 24
Peak memory	214976 kb
Host	smart-b22b0274-7c25-4ef4-8dfd-dcb2760f6457
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961234743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s pi_device_same_csr_outstanding.2961234743
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.767486604
Short name	T993
Test name
Test status
Simulation time	186290943 ps
CPU time	3.04 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:02 PM PDT 24
Peak memory	215164 kb
Host	smart-a6bf9b0a-3b43-4c9c-adb6-c87d629886ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767486604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.767486604
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3249459004
Short name	T281
Test name
Test status
Simulation time	191745043 ps
CPU time	11.64 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	215176 kb
Host	smart-75627819-fdef-4eef-9654-87845f14c75a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249459004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.3249459004
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1768199300
Short name	T1044
Test name
Test status
Simulation time	104507987 ps
CPU time	2.68 seconds
Started	May 14 12:54:55 PM PDT 24
Finished	May 14 12:55:01 PM PDT 24
Peak memory	217648 kb
Host	smart-44d8441b-2a45-4580-ae94-b776e20f4ea1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768199300 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1768199300
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2380750486
Short name	T1076
Test name
Test status
Simulation time	86753134 ps
CPU time	2.19 seconds
Started	May 14 12:55:08 PM PDT 24
Finished	May 14 12:55:12 PM PDT 24
Peak memory	206968 kb
Host	smart-dd3f9e45-ee67-4d55-acd8-65321976d216
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380750486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2 380750486
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.456358839
Short name	T998
Test name
Test status
Simulation time	13690305 ps
CPU time	0.74 seconds
Started	May 14 12:55:08 PM PDT 24
Finished	May 14 12:55:09 PM PDT 24
Peak memory	203356 kb
Host	smart-013eecb4-e3b4-46ba-aa81-0407f3b7f08b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456358839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.456358839
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1944470492
Short name	T1019
Test name
Test status
Simulation time	82954933 ps
CPU time	2.92 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	214992 kb
Host	smart-82739f4b-0b44-4a20-ab12-008470ed9ccf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944470492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.1944470492
Directory	/workspace/7.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.458961225
Short name	T1001
Test name
Test status
Simulation time	140703423 ps
CPU time	2.29 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:14 PM PDT 24
Peak memory	215300 kb
Host	smart-cb0f0c29-9906-4210-8f5c-2e986cc7756d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458961225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.458961225
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2584882086
Short name	T1063
Test name
Test status
Simulation time	170331974 ps
CPU time	6.78 seconds
Started	May 14 12:55:10 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215164 kb
Host	smart-8565d80c-60a7-4f30-9269-5079f5c0966b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584882086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.2584882086
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1915858959
Short name	T1070
Test name
Test status
Simulation time	238782405 ps
CPU time	2.43 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:06 PM PDT 24
Peak memory	216988 kb
Host	smart-79afe3c0-66d6-45cc-88b9-e4feb9a783a4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915858959 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1915858959
Directory	/workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3033855684
Short name	T1007
Test name
Test status
Simulation time	41908370 ps
CPU time	1.32 seconds
Started	May 14 12:55:08 PM PDT 24
Finished	May 14 12:55:11 PM PDT 24
Peak memory	215172 kb
Host	smart-559fd155-440c-4b90-b532-b83a2e7b9b9f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033855684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3 033855684
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1537233801
Short name	T1053
Test name
Test status
Simulation time	32140922 ps
CPU time	0.77 seconds
Started	May 14 12:55:02 PM PDT 24
Finished	May 14 12:55:05 PM PDT 24
Peak memory	203520 kb
Host	smart-9dba1529-ce88-469b-979e-649d2d2fcec2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537233801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1 537233801
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2794297811
Short name	T981
Test name
Test status
Simulation time	63518200 ps
CPU time	3.61 seconds
Started	May 14 12:55:04 PM PDT 24
Finished	May 14 12:55:09 PM PDT 24
Peak memory	215148 kb
Host	smart-5798cd2b-e7d3-4f4f-95b8-10671fc2cfc7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794297811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.2794297811
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.499054895
Short name	T990
Test name
Test status
Simulation time	96055476 ps
CPU time	1.48 seconds
Started	May 14 12:54:57 PM PDT 24
Finished	May 14 12:55:02 PM PDT 24
Peak memory	215176 kb
Host	smart-04fd207f-9a4f-46bd-82e4-8384f4cb2a81
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499054895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.499054895
Directory	/workspace/8.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.275067253
Short name	T276
Test name
Test status
Simulation time	1164891455 ps
CPU time	17.68 seconds
Started	May 14 12:55:09 PM PDT 24
Finished	May 14 12:55:27 PM PDT 24
Peak memory	215136 kb
Host	smart-45ece1d8-9d79-4de2-b924-644795460a17
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275067253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_ tl_intg_err.275067253
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1881990789
Short name	T1065
Test name
Test status
Simulation time	162938342 ps
CPU time	4.17 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:04 PM PDT 24
Peak memory	217020 kb
Host	smart-8ee9afe7-3f2b-41c9-89bb-0318c03df6c6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881990789 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1881990789
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4154495283
Short name	T121
Test name
Test status
Simulation time	26640754 ps
CPU time	1.7 seconds
Started	May 14 12:55:14 PM PDT 24
Finished	May 14 12:55:18 PM PDT 24
Peak memory	215144 kb
Host	smart-dbf84fa5-e1a5-4294-b112-1eee50c216dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154495283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4 154495283
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.1387092837
Short name	T1043
Test name
Test status
Simulation time	11759188 ps
CPU time	0.71 seconds
Started	May 14 12:54:54 PM PDT 24
Finished	May 14 12:54:57 PM PDT 24
Peak memory	203540 kb
Host	smart-f2d0fac2-ee23-43d9-8c4e-567ae53b27cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387092837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1 387092837
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.137820555
Short name	T1051
Test name
Test status
Simulation time	180114496 ps
CPU time	1.67 seconds
Started	May 14 12:55:00 PM PDT 24
Finished	May 14 12:55:04 PM PDT 24
Peak memory	215092 kb
Host	smart-6a2a52b2-1390-4daa-8794-57d57424cc32
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137820555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp i_device_same_csr_outstanding.137820555
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1396055245
Short name	T1028
Test name
Test status
Simulation time	349575108 ps
CPU time	4.24 seconds
Started	May 14 12:54:56 PM PDT 24
Finished	May 14 12:55:03 PM PDT 24
Peak memory	215316 kb
Host	smart-73a288e9-9df0-45e4-b896-4da76d8bd131
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396055245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1 396055245
Directory	/workspace/9.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.110570224
Short name	T275
Test name
Test status
Simulation time	270315944 ps
CPU time	7.53 seconds
Started	May 14 12:54:58 PM PDT 24
Finished	May 14 12:55:09 PM PDT 24
Peak memory	215140 kb
Host	smart-d6f4c896-3e74-4401-aa33-1ac531937b76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110570224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_ tl_intg_err.110570224
Directory	/workspace/9.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/0.spi_device_alert_test.1602798101
Short name	T405
Test name
Test status
Simulation time	35655998 ps
CPU time	0.7 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:27:22 PM PDT 24
Peak memory	204684 kb
Host	smart-fa13dbd4-9803-4fa3-b814-c1d26131bc53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602798101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1 602798101
Directory	/workspace/0.spi_device_alert_test/latest

Test location	/workspace/coverage/default/0.spi_device_cfg_cmd.2181283115
Short name	T310
Test name
Test status
Simulation time	553842615 ps
CPU time	3.32 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:27 PM PDT 24
Peak memory	219504 kb
Host	smart-be1cae62-d737-4e1c-9aed-fc266c57451f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181283115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2181283115
Directory	/workspace/0.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/0.spi_device_csb_read.1796961669
Short name	T359
Test name
Test status
Simulation time	37844086 ps
CPU time	0.75 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:27:22 PM PDT 24
Peak memory	205376 kb
Host	smart-938e3cc3-408b-4aa7-8b4a-9f2895ecf44a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796961669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1796961669
Directory	/workspace/0.spi_device_csb_read/latest

Test location	/workspace/coverage/default/0.spi_device_flash_all.4079163507
Short name	T186
Test name
Test status
Simulation time	39274787511 ps
CPU time	81.09 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:28:44 PM PDT 24
Peak memory	238484 kb
Host	smart-92a95c3b-67fe-4210-bcc7-05711ab62b01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079163507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4079163507
Directory	/workspace/0.spi_device_flash_all/latest

Test location	/workspace/coverage/default/0.spi_device_flash_and_tpm.3027655457
Short name	T51
Test name
Test status
Simulation time	1449439403 ps
CPU time	43.36 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:28:04 PM PDT 24
Peak memory	240840 kb
Host	smart-b4ad337d-a0f3-4d8c-b853-a74c4aec1061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027655457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3027655457
Directory	/workspace/0.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.390720630
Short name	T235
Test name
Test status
Simulation time	5527122427 ps
CPU time	125.68 seconds
Started	May 14 01:27:17 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	265468 kb
Host	smart-c5c970ad-eaf6-4610-9c48-af2b3e842250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390720630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle. 390720630
Directory	/workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/0.spi_device_flash_mode.750050188
Short name	T49
Test name
Test status
Simulation time	430276008 ps
CPU time	3.42 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:23 PM PDT 24
Peak memory	224288 kb
Host	smart-acf27223-c3e3-4787-9395-6b1ce4b57ca8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750050188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.750050188
Directory	/workspace/0.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/0.spi_device_intercept.1168221615
Short name	T213
Test name
Test status
Simulation time	543950736 ps
CPU time	4.68 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:24 PM PDT 24
Peak memory	232936 kb
Host	smart-f9b27cfc-a386-4740-ba81-f0e8d7912126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168221615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1168221615
Directory	/workspace/0.spi_device_intercept/latest

Test location	/workspace/coverage/default/0.spi_device_mailbox.582182938
Short name	T219
Test name
Test status
Simulation time	17825523159 ps
CPU time	43.82 seconds
Started	May 14 01:27:23 PM PDT 24
Finished	May 14 01:28:08 PM PDT 24
Peak memory	237036 kb
Host	smart-2d700635-1a14-4233-8ebd-83c72219acb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582182938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.582182938
Directory	/workspace/0.spi_device_mailbox/latest

Test location	/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1904545991
Short name	T322
Test name
Test status
Simulation time	227557556 ps
CPU time	3.07 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:26 PM PDT 24
Peak memory	218412 kb
Host	smart-0b3cbe3b-278b-4447-9a7a-e530b028ae94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904545991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap .1904545991
Directory	/workspace/0.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/0.spi_device_pass_cmd_filtering.641920282
Short name	T315
Test name
Test status
Simulation time	245821947 ps
CPU time	3.38 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:25 PM PDT 24
Peak memory	233516 kb
Host	smart-987656f1-6f3e-4b26-af70-7381ecd6386e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641920282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.641920282
Directory	/workspace/0.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/0.spi_device_read_buffer_direct.2890534344
Short name	T389
Test name
Test status
Simulation time	3777376883 ps
CPU time	12.27 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:31 PM PDT 24
Peak memory	222732 kb
Host	smart-bb0ea0ed-7b0a-4430-bfe5-8532a8009080
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2890534344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire ct.2890534344
Directory	/workspace/0.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/0.spi_device_sec_cm.1969204815
Short name	T78
Test name
Test status
Simulation time	41094098 ps
CPU time	1.03 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:24 PM PDT 24
Peak memory	234456 kb
Host	smart-cee8acfa-8955-4e15-8f27-d3026a1c8ecd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969204815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1969204815
Directory	/workspace/0.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/0.spi_device_stress_all.991050754
Short name	T699
Test name
Test status
Simulation time	5089151962 ps
CPU time	45.92 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:28:08 PM PDT 24
Peak memory	240864 kb
Host	smart-88dbdf68-fa22-49d2-88b9-33275d539286
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991050754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress _all.991050754
Directory	/workspace/0.spi_device_stress_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_all.2326485015
Short name	T456
Test name
Test status
Simulation time	6285241937 ps
CPU time	15.81 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:27:36 PM PDT 24
Peak memory	219784 kb
Host	smart-e8cc9945-c3ed-4daa-9a7e-b95184d670a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326485015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2326485015
Directory	/workspace/0.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4207777872
Short name	T787
Test name
Test status
Simulation time	20188967169 ps
CPU time	19.85 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	216160 kb
Host	smart-835cf02b-d068-4596-beae-80c3f60c2a65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207777872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4207777872
Directory	/workspace/0.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_rw.1824734644
Short name	T646
Test name
Test status
Simulation time	458233320 ps
CPU time	1.66 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:21 PM PDT 24
Peak memory	216168 kb
Host	smart-be0e771e-b0b0-4c6b-b498-8b924710ef00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824734644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1824734644
Directory	/workspace/0.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_sts_read.3670548340
Short name	T128
Test name
Test status
Simulation time	64967776 ps
CPU time	0.85 seconds
Started	May 14 01:27:17 PM PDT 24
Finished	May 14 01:27:19 PM PDT 24
Peak memory	205680 kb
Host	smart-de33844d-cdf2-48ea-9296-d05513e6ae5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670548340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3670548340
Directory	/workspace/0.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/0.spi_device_upload.3806582906
Short name	T489
Test name
Test status
Simulation time	5853036476 ps
CPU time	21.56 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:27:46 PM PDT 24
Peak memory	237032 kb
Host	smart-0b9370b7-fe9a-4fb2-b26f-c684289f1c44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806582906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3806582906
Directory	/workspace/0.spi_device_upload/latest

Test location	/workspace/coverage/default/1.spi_device_alert_test.2568405317
Short name	T929
Test name
Test status
Simulation time	15336293 ps
CPU time	0.73 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:24 PM PDT 24
Peak memory	205260 kb
Host	smart-da478944-5827-4cc2-9d0c-913a667ae314
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568405317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2 568405317
Directory	/workspace/1.spi_device_alert_test/latest

Test location	/workspace/coverage/default/1.spi_device_cfg_cmd.4078823657
Short name	T157
Test name
Test status
Simulation time	137137224 ps
CPU time	2.49 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:26 PM PDT 24
Peak memory	232544 kb
Host	smart-7d7da6f0-4efb-4676-bc93-2af5e6dcefb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078823657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4078823657
Directory	/workspace/1.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/1.spi_device_csb_read.2738779441
Short name	T465
Test name
Test status
Simulation time	66372232 ps
CPU time	0.82 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:20 PM PDT 24
Peak memory	206336 kb
Host	smart-9c69ec92-8983-4d3a-9750-378238c75d1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738779441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2738779441
Directory	/workspace/1.spi_device_csb_read/latest

Test location	/workspace/coverage/default/1.spi_device_flash_all.1157210811
Short name	T946
Test name
Test status
Simulation time	18832642 ps
CPU time	0.8 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:25 PM PDT 24
Peak memory	215820 kb
Host	smart-e5ba149b-ab82-4fee-b983-fb96e3866f9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157210811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1157210811
Directory	/workspace/1.spi_device_flash_all/latest

Test location	/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.178493424
Short name	T682
Test name
Test status
Simulation time	57025922792 ps
CPU time	108.82 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	233532 kb
Host	smart-db1d0480-0b27-436f-b79a-399b2ac823e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178493424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle. 178493424
Directory	/workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/1.spi_device_flash_mode.2750411384
Short name	T58
Test name
Test status
Simulation time	7859952345 ps
CPU time	16.52 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	233984 kb
Host	smart-9cfd13f8-ec8f-4df2-ac19-b25477aec774
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750411384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2750411384
Directory	/workspace/1.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/1.spi_device_intercept.3515279136
Short name	T801
Test name
Test status
Simulation time	271609690 ps
CPU time	5.21 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:28 PM PDT 24
Peak memory	218528 kb
Host	smart-1f05b27e-1139-4113-9119-8853d17ac34a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515279136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3515279136
Directory	/workspace/1.spi_device_intercept/latest

Test location	/workspace/coverage/default/1.spi_device_mailbox.3509594838
Short name	T873
Test name
Test status
Simulation time	10117253110 ps
CPU time	16.66 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	233716 kb
Host	smart-6db9d804-3f81-4e4e-8e2a-9775c3a04f5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509594838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3509594838
Directory	/workspace/1.spi_device_mailbox/latest

Test location	/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.302008798
Short name	T690
Test name
Test status
Simulation time	2114337038 ps
CPU time	6.52 seconds
Started	May 14 01:27:17 PM PDT 24
Finished	May 14 01:27:25 PM PDT 24
Peak memory	233140 kb
Host	smart-c7ba9472-1399-42d8-9e07-cdf280834bf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302008798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap. 302008798
Directory	/workspace/1.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/1.spi_device_pass_cmd_filtering.2466434373
Short name	T679
Test name
Test status
Simulation time	1526531923 ps
CPU time	7.93 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:30 PM PDT 24
Peak memory	233528 kb
Host	smart-669f7fad-d7b9-4699-b639-732325320b3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466434373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2466434373
Directory	/workspace/1.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/1.spi_device_read_buffer_direct.2322868219
Short name	T726
Test name
Test status
Simulation time	577181713 ps
CPU time	8.61 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:31 PM PDT 24
Peak memory	220156 kb
Host	smart-a1de1dc6-d151-4569-aef3-c04a1f45bb49
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2322868219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire ct.2322868219
Directory	/workspace/1.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/1.spi_device_sec_cm.1947937473
Short name	T77
Test name
Test status
Simulation time	784004690 ps
CPU time	1.2 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:25 PM PDT 24
Peak memory	236152 kb
Host	smart-e9dd599e-30d8-4771-bb1c-2424b17d56e0
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947937473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1947937473
Directory	/workspace/1.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/1.spi_device_stress_all.4282725859
Short name	T905
Test name
Test status
Simulation time	3205398454 ps
CPU time	45.77 seconds
Started	May 14 01:27:19 PM PDT 24
Finished	May 14 01:28:07 PM PDT 24
Peak memory	239952 kb
Host	smart-2e0a6fbb-e3d7-44cf-9a40-d34ee7e34726
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282725859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres s_all.4282725859
Directory	/workspace/1.spi_device_stress_all/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_all.2656419131
Short name	T628
Test name
Test status
Simulation time	30190774 ps
CPU time	0.77 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:27:25 PM PDT 24
Peak memory	205536 kb
Host	smart-f3306d8c-7d4f-494d-b188-52f842b40708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656419131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2656419131
Directory	/workspace/1.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2140588
Short name	T632
Test name
Test status
Simulation time	8705465905 ps
CPU time	23.06 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:46 PM PDT 24
Peak memory	216152 kb
Host	smart-1108f906-eb87-42b1-85b3-00744d3e8116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2140588
Directory	/workspace/1.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_rw.2413408838
Short name	T564
Test name
Test status
Simulation time	54256107 ps
CPU time	1.59 seconds
Started	May 14 01:27:18 PM PDT 24
Finished	May 14 01:27:21 PM PDT 24
Peak memory	207956 kb
Host	smart-47778e3a-0688-4d5e-a7b5-30d24bcf07eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413408838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2413408838
Directory	/workspace/1.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/1.spi_device_upload.1343545046
Short name	T770
Test name
Test status
Simulation time	1037329831 ps
CPU time	8.96 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:27:33 PM PDT 24
Peak memory	227396 kb
Host	smart-2ff11601-728f-4fe5-9a95-5d51096e500d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343545046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1343545046
Directory	/workspace/1.spi_device_upload/latest

Test location	/workspace/coverage/default/10.spi_device_alert_test.647101680
Short name	T453
Test name
Test status
Simulation time	18186118 ps
CPU time	0.74 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:10 PM PDT 24
Peak memory	205244 kb
Host	smart-1a084b32-531d-4dee-baa8-d0fc8e00a177
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647101680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.647101680
Directory	/workspace/10.spi_device_alert_test/latest

Test location	/workspace/coverage/default/10.spi_device_cfg_cmd.771499595
Short name	T12
Test name
Test status
Simulation time	3853752011 ps
CPU time	8.05 seconds
Started	May 14 01:27:58 PM PDT 24
Finished	May 14 01:28:08 PM PDT 24
Peak memory	219948 kb
Host	smart-769c7777-bb22-4e03-a52b-9292855b6a0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771499595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.771499595
Directory	/workspace/10.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/10.spi_device_csb_read.2190120746
Short name	T635
Test name
Test status
Simulation time	16976963 ps
CPU time	0.78 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:50 PM PDT 24
Peak memory	206664 kb
Host	smart-6d2b61b5-517e-433d-bf0c-b7af69a6e2da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190120746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2190120746
Directory	/workspace/10.spi_device_csb_read/latest

Test location	/workspace/coverage/default/10.spi_device_flash_all.482184900
Short name	T700
Test name
Test status
Simulation time	2086405088 ps
CPU time	39.84 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	248940 kb
Host	smart-9c7698d3-0880-4a7b-8363-11dfe30ad7c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482184900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.482184900
Directory	/workspace/10.spi_device_flash_all/latest

Test location	/workspace/coverage/default/10.spi_device_flash_and_tpm.2352619553
Short name	T125
Test name
Test status
Simulation time	3141275496 ps
CPU time	48.99 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:28:58 PM PDT 24
Peak memory	239092 kb
Host	smart-45cc0913-c34e-4756-994b-808beaaf9c6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352619553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2352619553
Directory	/workspace/10.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/10.spi_device_flash_mode.4112468629
Short name	T269
Test name
Test status
Simulation time	143080616 ps
CPU time	5.98 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:13 PM PDT 24
Peak memory	232540 kb
Host	smart-3936344c-1769-4ab4-853c-5e11437bf526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112468629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4112468629
Directory	/workspace/10.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/10.spi_device_intercept.1667352049
Short name	T63
Test name
Test status
Simulation time	1437532427 ps
CPU time	7.28 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:27:59 PM PDT 24
Peak memory	219268 kb
Host	smart-a4902773-f023-4a1d-b290-39568a38697f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667352049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1667352049
Directory	/workspace/10.spi_device_intercept/latest

Test location	/workspace/coverage/default/10.spi_device_mailbox.1340721974
Short name	T131
Test name
Test status
Simulation time	2627180275 ps
CPU time	14.83 seconds
Started	May 14 01:27:57 PM PDT 24
Finished	May 14 01:28:13 PM PDT 24
Peak memory	231876 kb
Host	smart-41f6f6c3-cb35-44d3-a389-a36ed573f286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340721974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1340721974
Directory	/workspace/10.spi_device_mailbox/latest

Test location	/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1253287616
Short name	T725
Test name
Test status
Simulation time	951184316 ps
CPU time	9.3 seconds
Started	May 14 01:27:56 PM PDT 24
Finished	May 14 01:28:06 PM PDT 24
Peak memory	238708 kb
Host	smart-3b93713a-4a1e-4eb6-85a3-0093d21c88db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253287616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa p.1253287616
Directory	/workspace/10.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/10.spi_device_pass_cmd_filtering.534372937
Short name	T735
Test name
Test status
Simulation time	2933630400 ps
CPU time	5.73 seconds
Started	May 14 01:27:56 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	218856 kb
Host	smart-96013eb8-7342-4ef2-b0af-3f94cf26ee88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534372937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.534372937
Directory	/workspace/10.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/10.spi_device_read_buffer_direct.3254770354
Short name	T723
Test name
Test status
Simulation time	2086389811 ps
CPU time	23.91 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	219828 kb
Host	smart-7753731c-6fa1-4dfa-8872-47e129bd4103
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3254770354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir ect.3254770354
Directory	/workspace/10.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/10.spi_device_stress_all.3276330675
Short name	T200
Test name
Test status
Simulation time	142615848133 ps
CPU time	336.41 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:33:46 PM PDT 24
Peak memory	250592 kb
Host	smart-bd279f0e-3422-4003-a5eb-9d6c7aeb85b8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276330675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre ss_all.3276330675
Directory	/workspace/10.spi_device_stress_all/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_all.2564771906
Short name	T712
Test name
Test status
Simulation time	984728856 ps
CPU time	5.57 seconds
Started	May 14 01:27:58 PM PDT 24
Finished	May 14 01:28:05 PM PDT 24
Peak memory	216132 kb
Host	smart-5482bc8a-cae5-48f0-bfdd-e3a60cbf29c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564771906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2564771906
Directory	/workspace/10.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1663437901
Short name	T865
Test name
Test status
Simulation time	1566152514 ps
CPU time	4.52 seconds
Started	May 14 01:27:56 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	216016 kb
Host	smart-2d8f03f7-07d8-4e2b-8620-eca993ed7b3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663437901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1663437901
Directory	/workspace/10.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_rw.2223726660
Short name	T612
Test name
Test status
Simulation time	114876946 ps
CPU time	1.38 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	216112 kb
Host	smart-f46b3ee0-85aa-4b01-b087-ce14cf909b33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223726660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2223726660
Directory	/workspace/10.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_sts_read.660257779
Short name	T524
Test name
Test status
Simulation time	195447087 ps
CPU time	0.84 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	205708 kb
Host	smart-6ba0e391-6b3e-48be-962a-0b0daccba5f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660257779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.660257779
Directory	/workspace/10.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/10.spi_device_upload.908091182
Short name	T850
Test name
Test status
Simulation time	106790803 ps
CPU time	2.21 seconds
Started	May 14 01:27:56 PM PDT 24
Finished	May 14 01:27:59 PM PDT 24
Peak memory	207748 kb
Host	smart-0f65bcc3-057c-4857-b1ef-b27d38d1ba4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908091182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.908091182
Directory	/workspace/10.spi_device_upload/latest

Test location	/workspace/coverage/default/11.spi_device_alert_test.2728246792
Short name	T729
Test name
Test status
Simulation time	17433802 ps
CPU time	0.75 seconds
Started	May 14 01:28:02 PM PDT 24
Finished	May 14 01:28:06 PM PDT 24
Peak memory	205584 kb
Host	smart-a48f0a11-a38c-4889-bf7a-b38c4c4d5f2b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728246792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test. 2728246792
Directory	/workspace/11.spi_device_alert_test/latest

Test location	/workspace/coverage/default/11.spi_device_cfg_cmd.3248864643
Short name	T170
Test name
Test status
Simulation time	2764061298 ps
CPU time	5.86 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:59 PM PDT 24
Peak memory	224384 kb
Host	smart-0ee34176-8ce9-4fc0-8c1d-ead3c815f17c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248864643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3248864643
Directory	/workspace/11.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/11.spi_device_csb_read.661926663
Short name	T596
Test name
Test status
Simulation time	29007739 ps
CPU time	0.81 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:05 PM PDT 24
Peak memory	206728 kb
Host	smart-9b8b3d41-d6ff-4637-934b-c25f5ad98aab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661926663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.661926663
Directory	/workspace/11.spi_device_csb_read/latest

Test location	/workspace/coverage/default/11.spi_device_flash_all.2929655519
Short name	T36
Test name
Test status
Simulation time	66977425485 ps
CPU time	277.07 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:32:30 PM PDT 24
Peak memory	267500 kb
Host	smart-699ad537-e37a-4aaf-9783-4aa0b1f6c293
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929655519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2929655519
Directory	/workspace/11.spi_device_flash_all/latest

Test location	/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1103448875
Short name	T818
Test name
Test status
Simulation time	16860660157 ps
CPU time	139.46 seconds
Started	May 14 01:27:57 PM PDT 24
Finished	May 14 01:30:18 PM PDT 24
Peak memory	265268 kb
Host	smart-0c30ba3b-e4d9-4444-ab06-809e781afdec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103448875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl e.1103448875
Directory	/workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/11.spi_device_flash_mode.2815850188
Short name	T563
Test name
Test status
Simulation time	4032615957 ps
CPU time	21.04 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:28:11 PM PDT 24
Peak memory	232556 kb
Host	smart-12047dbe-ebe4-4d7c-898b-55c59a8bc3cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815850188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2815850188
Directory	/workspace/11.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/11.spi_device_intercept.839100895
Short name	T890
Test name
Test status
Simulation time	458316701 ps
CPU time	3.92 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:27:55 PM PDT 24
Peak memory	217800 kb
Host	smart-1768fe04-5f82-4754-8d08-1ece7000cc4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839100895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.839100895
Directory	/workspace/11.spi_device_intercept/latest

Test location	/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2599924875
Short name	T579
Test name
Test status
Simulation time	30233199 ps
CPU time	2.47 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:27:54 PM PDT 24
Peak memory	221360 kb
Host	smart-6f68961a-5e38-43d0-9452-ee4d591861cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599924875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa p.2599924875
Directory	/workspace/11.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/11.spi_device_pass_cmd_filtering.1683915252
Short name	T491
Test name
Test status
Simulation time	311719950 ps
CPU time	3.47 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:15 PM PDT 24
Peak memory	233884 kb
Host	smart-eab9a867-ac11-4e0e-bc91-b39974f32d2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683915252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1683915252
Directory	/workspace/11.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/11.spi_device_read_buffer_direct.3308762357
Short name	T369
Test name
Test status
Simulation time	226434224 ps
CPU time	4.54 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:57 PM PDT 24
Peak memory	220124 kb
Host	smart-08b662b1-9626-4021-b8a7-8f348d841c23
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3308762357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir ect.3308762357
Directory	/workspace/11.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_all.2370415017
Short name	T591
Test name
Test status
Simulation time	88641569 ps
CPU time	0.68 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:11 PM PDT 24
Peak memory	205532 kb
Host	smart-45d879f9-ecf4-458c-8276-2789563ab09b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370415017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2370415017
Directory	/workspace/11.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.243565110
Short name	T936
Test name
Test status
Simulation time	3082133964 ps
CPU time	6.86 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:17 PM PDT 24
Peak memory	216076 kb
Host	smart-b985fcf1-05f8-4972-a175-3e2bdb90d6d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243565110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.243565110
Directory	/workspace/11.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_rw.2961315971
Short name	T536
Test name
Test status
Simulation time	40212535 ps
CPU time	2.56 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:55 PM PDT 24
Peak memory	216088 kb
Host	smart-85b8fda5-ca1f-497c-92bb-107df4aac36a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961315971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2961315971
Directory	/workspace/11.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_sts_read.508765524
Short name	T430
Test name
Test status
Simulation time	31316047 ps
CPU time	0.77 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:18 PM PDT 24
Peak memory	205716 kb
Host	smart-02d828d9-bd8b-46a8-8bd1-ae40c2152d59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508765524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.508765524
Directory	/workspace/11.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/11.spi_device_upload.1759960207
Short name	T797
Test name
Test status
Simulation time	1492032362 ps
CPU time	5.58 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	222592 kb
Host	smart-ce117bfa-b774-4d8c-8fb8-3f874660d76f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759960207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1759960207
Directory	/workspace/11.spi_device_upload/latest

Test location	/workspace/coverage/default/12.spi_device_alert_test.3643071494
Short name	T507
Test name
Test status
Simulation time	15029272 ps
CPU time	0.74 seconds
Started	May 14 01:27:58 PM PDT 24
Finished	May 14 01:28:00 PM PDT 24
Peak memory	204736 kb
Host	smart-895ec87b-4b6a-4e00-a087-b51912c3ca35
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643071494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test. 3643071494
Directory	/workspace/12.spi_device_alert_test/latest

Test location	/workspace/coverage/default/12.spi_device_cfg_cmd.2908533097
Short name	T878
Test name
Test status
Simulation time	104389524 ps
CPU time	2.56 seconds
Started	May 14 01:27:57 PM PDT 24
Finished	May 14 01:28:01 PM PDT 24
Peak memory	215864 kb
Host	smart-125df27b-9b0b-48ad-be52-350f7fbf4c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908533097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2908533097
Directory	/workspace/12.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/12.spi_device_csb_read.2071062877
Short name	T377
Test name
Test status
Simulation time	44220628 ps
CPU time	0.78 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:12 PM PDT 24
Peak memory	205420 kb
Host	smart-b5775ebe-b052-4e15-8ceb-af66a2ab49bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071062877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2071062877
Directory	/workspace/12.spi_device_csb_read/latest

Test location	/workspace/coverage/default/12.spi_device_flash_all.2616857738
Short name	T194
Test name
Test status
Simulation time	1436441919 ps
CPU time	28.42 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	248932 kb
Host	smart-89084dc5-d48f-45dd-a7c8-02cf3dd04687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616857738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2616857738
Directory	/workspace/12.spi_device_flash_all/latest

Test location	/workspace/coverage/default/12.spi_device_flash_and_tpm.3503638337
Short name	T450
Test name
Test status
Simulation time	372691475 ps
CPU time	6.37 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	217360 kb
Host	smart-21c0c8bc-bee8-4b22-914d-4d054ac577d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503638337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3503638337
Directory	/workspace/12.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3064644292
Short name	T538
Test name
Test status
Simulation time	74154435651 ps
CPU time	53.54 seconds
Started	May 14 01:27:57 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	240472 kb
Host	smart-613f8a0a-b047-44e8-8441-c00448655bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064644292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl e.3064644292
Directory	/workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/12.spi_device_flash_mode.4268783428
Short name	T933
Test name
Test status
Simulation time	5434205007 ps
CPU time	65.16 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:29:14 PM PDT 24
Peak memory	240352 kb
Host	smart-4f0eb0f4-fed6-4c50-84f9-e70e57e38661
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268783428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4268783428
Directory	/workspace/12.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/12.spi_device_intercept.1248178531
Short name	T454
Test name
Test status
Simulation time	6023529209 ps
CPU time	13.1 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:17 PM PDT 24
Peak memory	219488 kb
Host	smart-08ce2c1c-ae70-44b6-ac42-107440885b5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248178531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1248178531
Directory	/workspace/12.spi_device_intercept/latest

Test location	/workspace/coverage/default/12.spi_device_mailbox.266464111
Short name	T857
Test name
Test status
Simulation time	105647866 ps
CPU time	2.31 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:04 PM PDT 24
Peak memory	215960 kb
Host	smart-54b5734d-ca82-455a-84f1-486021423891
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266464111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.266464111
Directory	/workspace/12.spi_device_mailbox/latest

Test location	/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3470361841
Short name	T589
Test name
Test status
Simulation time	28044361518 ps
CPU time	7.05 seconds
Started	May 14 01:28:00 PM PDT 24
Finished	May 14 01:28:10 PM PDT 24
Peak memory	219704 kb
Host	smart-d05fccef-d85e-4c3b-9325-c59115bb3a77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470361841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa p.3470361841
Directory	/workspace/12.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/12.spi_device_pass_cmd_filtering.3095156817
Short name	T199
Test name
Test status
Simulation time	13377634991 ps
CPU time	34.71 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:35 PM PDT 24
Peak memory	239240 kb
Host	smart-81c9df64-2f70-40ff-8418-e53e2d6b8a13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095156817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3095156817
Directory	/workspace/12.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/12.spi_device_read_buffer_direct.1844407027
Short name	T958
Test name
Test status
Simulation time	10963364469 ps
CPU time	10.63 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:15 PM PDT 24
Peak memory	218748 kb
Host	smart-6445ef31-1a6e-4330-9367-290ebc2c625c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1844407027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir ect.1844407027
Directory	/workspace/12.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/12.spi_device_stress_all.1686142017
Short name	T435
Test name
Test status
Simulation time	2691796346 ps
CPU time	54.22 seconds
Started	May 14 01:27:57 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	249004 kb
Host	smart-997a1f44-6d6c-4138-b6c0-78255951add5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686142017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre ss_all.1686142017
Directory	/workspace/12.spi_device_stress_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_all.3172335283
Short name	T704
Test name
Test status
Simulation time	6171757596 ps
CPU time	30.7 seconds
Started	May 14 01:28:02 PM PDT 24
Finished	May 14 01:28:35 PM PDT 24
Peak memory	216124 kb
Host	smart-caca14d2-0db3-4e8f-b68c-191f19ef64ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172335283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3172335283
Directory	/workspace/12.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3746885513
Short name	T654
Test name
Test status
Simulation time	911712460 ps
CPU time	6.61 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:10 PM PDT 24
Peak memory	215996 kb
Host	smart-f5f93c78-d2ae-4b17-9e52-d647b41e4f52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746885513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3746885513
Directory	/workspace/12.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_rw.1427174287
Short name	T620
Test name
Test status
Simulation time	68443814 ps
CPU time	1.45 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	216152 kb
Host	smart-29b6448c-b640-4965-a646-3217a9dab6ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427174287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1427174287
Directory	/workspace/12.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_sts_read.618098038
Short name	T883
Test name
Test status
Simulation time	41940200 ps
CPU time	0.86 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	205640 kb
Host	smart-e431b506-d406-48d5-ae54-0b2d150b6a33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618098038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.618098038
Directory	/workspace/12.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/12.spi_device_upload.2120496722
Short name	T221
Test name
Test status
Simulation time	1792875427 ps
CPU time	12.71 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	248264 kb
Host	smart-90c4c6fd-c139-43dc-8f37-c1e8a0bac3fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120496722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2120496722
Directory	/workspace/12.spi_device_upload/latest

Test location	/workspace/coverage/default/13.spi_device_alert_test.420637293
Short name	T469
Test name
Test status
Simulation time	38779835 ps
CPU time	0.74 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:04 PM PDT 24
Peak memory	205292 kb
Host	smart-c264d969-2f45-4d83-9882-d9a2ec30fce0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420637293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.420637293
Directory	/workspace/13.spi_device_alert_test/latest

Test location	/workspace/coverage/default/13.spi_device_cfg_cmd.3323067570
Short name	T869
Test name
Test status
Simulation time	454601139 ps
CPU time	4.4 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	219452 kb
Host	smart-6dcaa11d-7074-4b9c-80b4-50ac7c65ee18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323067570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3323067570
Directory	/workspace/13.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/13.spi_device_csb_read.1189700099
Short name	T531
Test name
Test status
Simulation time	25696855 ps
CPU time	0.83 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	206436 kb
Host	smart-3dc8d93f-7f2a-4322-a7fa-d3eb4ce67f10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189700099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1189700099
Directory	/workspace/13.spi_device_csb_read/latest

Test location	/workspace/coverage/default/13.spi_device_flash_all.998131884
Short name	T658
Test name
Test status
Simulation time	11863133964 ps
CPU time	97.39 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:29:47 PM PDT 24
Peak memory	252864 kb
Host	smart-37c62623-814b-4c01-a183-3d324c4069aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998131884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.998131884
Directory	/workspace/13.spi_device_flash_all/latest

Test location	/workspace/coverage/default/13.spi_device_flash_and_tpm.3500900773
Short name	T86
Test name
Test status
Simulation time	13838584734 ps
CPU time	28.65 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:31 PM PDT 24
Peak memory	241004 kb
Host	smart-72305305-459f-41ce-8818-0da5dd02ba71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500900773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3500900773
Directory	/workspace/13.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2987790996
Short name	T846
Test name
Test status
Simulation time	37241112354 ps
CPU time	347.66 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:33:51 PM PDT 24
Peak memory	249092 kb
Host	smart-74642e69-048c-4243-8d84-8b376c291b55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987790996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl e.2987790996
Directory	/workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/13.spi_device_flash_mode.3685090595
Short name	T569
Test name
Test status
Simulation time	129424062 ps
CPU time	4.81 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:12 PM PDT 24
Peak memory	232484 kb
Host	smart-a9e82ba6-a2a2-4b1b-84fb-d50b243605df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685090595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3685090595
Directory	/workspace/13.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/13.spi_device_intercept.4219262897
Short name	T674
Test name
Test status
Simulation time	3244164268 ps
CPU time	28.6 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:30 PM PDT 24
Peak memory	219544 kb
Host	smart-9fc49697-8cd3-49a1-914e-00539a1a9bd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219262897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4219262897
Directory	/workspace/13.spi_device_intercept/latest

Test location	/workspace/coverage/default/13.spi_device_mailbox.3512098919
Short name	T304
Test name
Test status
Simulation time	1858321227 ps
CPU time	10.8 seconds
Started	May 14 01:27:58 PM PDT 24
Finished	May 14 01:28:11 PM PDT 24
Peak memory	233312 kb
Host	smart-2a21dc8f-0589-4938-8b7c-457a11373292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3512098919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3512098919
Directory	/workspace/13.spi_device_mailbox/latest

Test location	/workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1759646847
Short name	T320
Test name
Test status
Simulation time	3476087499 ps
CPU time	10.41 seconds
Started	May 14 01:28:03 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	218536 kb
Host	smart-49374c05-215c-42aa-8734-802698eacb96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759646847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa p.1759646847
Directory	/workspace/13.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/13.spi_device_pass_cmd_filtering.696996498
Short name	T732
Test name
Test status
Simulation time	18285771436 ps
CPU time	15.9 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:19 PM PDT 24
Peak memory	239948 kb
Host	smart-dde5ae3a-eee0-4317-aa6f-2fa706f213c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696996498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.696996498
Directory	/workspace/13.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/13.spi_device_read_buffer_direct.2279254512
Short name	T651
Test name
Test status
Simulation time	1388919549 ps
CPU time	3.78 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:07 PM PDT 24
Peak memory	219356 kb
Host	smart-86339d81-03e0-4842-a267-b1c61e5f34ec
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2279254512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir ect.2279254512
Directory	/workspace/13.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/13.spi_device_stress_all.1516741341
Short name	T807
Test name
Test status
Simulation time	440564399 ps
CPU time	0.93 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	206792 kb
Host	smart-1cfb2333-228b-4ef5-86ec-dc3236214876
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516741341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre ss_all.1516741341
Directory	/workspace/13.spi_device_stress_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_all.770573634
Short name	T779
Test name
Test status
Simulation time	5329411086 ps
CPU time	24.52 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:28 PM PDT 24
Peak memory	216388 kb
Host	smart-7f75f1a2-aca4-494f-a1b2-e23789263f04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770573634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.770573634
Directory	/workspace/13.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1375444944
Short name	T52
Test name
Test status
Simulation time	9464341792 ps
CPU time	17.43 seconds
Started	May 14 01:28:00 PM PDT 24
Finished	May 14 01:28:20 PM PDT 24
Peak memory	216076 kb
Host	smart-0d8c93c3-9d34-4e72-8acd-c48602c4aa47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1375444944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1375444944
Directory	/workspace/13.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_rw.3653949170
Short name	T561
Test name
Test status
Simulation time	423197208 ps
CPU time	2.29 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:14 PM PDT 24
Peak memory	216156 kb
Host	smart-0480be7c-2713-4e6d-88c5-5d15f3c69260
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653949170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3653949170
Directory	/workspace/13.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_sts_read.2095954171
Short name	T555
Test name
Test status
Simulation time	66286346 ps
CPU time	0.93 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:11 PM PDT 24
Peak memory	205604 kb
Host	smart-c2c20356-4c46-4720-becd-9abfebb06628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095954171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2095954171
Directory	/workspace/13.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/13.spi_device_upload.3993974345
Short name	T625
Test name
Test status
Simulation time	126819485 ps
CPU time	3.8 seconds
Started	May 14 01:27:58 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	217144 kb
Host	smart-cd84e4de-7443-44c4-a913-51d635ed9916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993974345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3993974345
Directory	/workspace/13.spi_device_upload/latest

Test location	/workspace/coverage/default/14.spi_device_alert_test.4006168569
Short name	T677
Test name
Test status
Simulation time	20787764 ps
CPU time	0.71 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	204712 kb
Host	smart-3922f571-3200-4f4f-91ae-d211452b466d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006168569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test. 4006168569
Directory	/workspace/14.spi_device_alert_test/latest

Test location	/workspace/coverage/default/14.spi_device_cfg_cmd.1751216634
Short name	T645
Test name
Test status
Simulation time	707912914 ps
CPU time	4.24 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:17 PM PDT 24
Peak memory	219268 kb
Host	smart-d86103af-8949-4dab-bde0-a9b963ce3d33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751216634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1751216634
Directory	/workspace/14.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/14.spi_device_csb_read.1138452963
Short name	T455
Test name
Test status
Simulation time	49715319 ps
CPU time	0.78 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:13 PM PDT 24
Peak memory	205340 kb
Host	smart-9e1fd99e-5d0e-4d89-a152-bff8ce838638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138452963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1138452963
Directory	/workspace/14.spi_device_csb_read/latest

Test location	/workspace/coverage/default/14.spi_device_flash_all.2950287548
Short name	T283
Test name
Test status
Simulation time	2503205506 ps
CPU time	44.69 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:55 PM PDT 24
Peak memory	248960 kb
Host	smart-ba0d603c-7228-424f-8c91-5bb701794e27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950287548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2950287548
Directory	/workspace/14.spi_device_flash_all/latest

Test location	/workspace/coverage/default/14.spi_device_flash_mode.927164230
Short name	T884
Test name
Test status
Simulation time	1605199531 ps
CPU time	24.48 seconds
Started	May 14 01:28:03 PM PDT 24
Finished	May 14 01:28:30 PM PDT 24
Peak memory	234132 kb
Host	smart-9d418560-bccd-43e9-bab4-1efb44ae9ba9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927164230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.927164230
Directory	/workspace/14.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/14.spi_device_intercept.2357138131
Short name	T444
Test name
Test status
Simulation time	11485243219 ps
CPU time	13.17 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:14 PM PDT 24
Peak memory	234200 kb
Host	smart-d18dcdf5-8d82-4743-893f-7b8252275b45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357138131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2357138131
Directory	/workspace/14.spi_device_intercept/latest

Test location	/workspace/coverage/default/14.spi_device_mailbox.501936633
Short name	T701
Test name
Test status
Simulation time	768235925 ps
CPU time	19.94 seconds
Started	May 14 01:28:11 PM PDT 24
Finished	May 14 01:28:33 PM PDT 24
Peak memory	229972 kb
Host	smart-1ff98afe-1ea3-47e8-84b4-f8c9411ad32b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501936633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.501936633
Directory	/workspace/14.spi_device_mailbox/latest

Test location	/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3790435361
Short name	T9
Test name
Test status
Simulation time	14485056743 ps
CPU time	5.94 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:28:15 PM PDT 24
Peak memory	233220 kb
Host	smart-9f9a849c-a9ce-42bc-b6b5-ed767ca0255b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790435361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa p.3790435361
Directory	/workspace/14.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/14.spi_device_pass_cmd_filtering.4142141070
Short name	T222
Test name
Test status
Simulation time	54402084 ps
CPU time	2.25 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:12 PM PDT 24
Peak memory	218240 kb
Host	smart-cea81489-6503-48fb-a583-9d016f3bfd25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142141070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4142141070
Directory	/workspace/14.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/14.spi_device_read_buffer_direct.501561099
Short name	T610
Test name
Test status
Simulation time	148893119 ps
CPU time	4.84 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	222680 kb
Host	smart-5c45b943-05dd-4139-aae1-d6cf549b6dbc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=501561099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire ct.501561099
Directory	/workspace/14.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/14.spi_device_stress_all.596323494
Short name	T319
Test name
Test status
Simulation time	195132162430 ps
CPU time	464.34 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:35:55 PM PDT 24
Peak memory	257252 kb
Host	smart-729ed952-381a-4225-89d4-4e5c046f1d38
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596323494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres s_all.596323494
Directory	/workspace/14.spi_device_stress_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_all.535635427
Short name	T745
Test name
Test status
Simulation time	32901264457 ps
CPU time	31.73 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:44 PM PDT 24
Peak memory	216292 kb
Host	smart-4f9e2d32-10ef-447d-89aa-849c9c015f8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535635427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.535635427
Directory	/workspace/14.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3812967955
Short name	T510
Test name
Test status
Simulation time	3673650814 ps
CPU time	3.17 seconds
Started	May 14 01:28:00 PM PDT 24
Finished	May 14 01:28:05 PM PDT 24
Peak memory	207800 kb
Host	smart-a424023f-7d25-4e00-8254-ffd4dd134e4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812967955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3812967955
Directory	/workspace/14.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_rw.3137303804
Short name	T798
Test name
Test status
Simulation time	32877430 ps
CPU time	1.29 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	207172 kb
Host	smart-35a1a823-e2f4-4a84-93e0-9447b6a67557
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137303804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3137303804
Directory	/workspace/14.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_sts_read.1566723717
Short name	T953
Test name
Test status
Simulation time	114139078 ps
CPU time	0.78 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:12 PM PDT 24
Peak memory	205604 kb
Host	smart-379e2938-2eb2-4cb9-a5ac-9e043ddae629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566723717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1566723717
Directory	/workspace/14.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/14.spi_device_upload.1377018437
Short name	T397
Test name
Test status
Simulation time	378433476 ps
CPU time	2.34 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:12 PM PDT 24
Peak memory	215892 kb
Host	smart-63ac8c60-4c4e-4ae2-b998-2f4c7a5612fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377018437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1377018437
Directory	/workspace/14.spi_device_upload/latest

Test location	/workspace/coverage/default/15.spi_device_alert_test.2724530497
Short name	T459
Test name
Test status
Simulation time	66620421 ps
CPU time	0.75 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:13 PM PDT 24
Peak memory	205308 kb
Host	smart-507c1ee4-4d57-4066-ac53-654df0438a73
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724530497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test. 2724530497
Directory	/workspace/15.spi_device_alert_test/latest

Test location	/workspace/coverage/default/15.spi_device_cfg_cmd.4265921188
Short name	T215
Test name
Test status
Simulation time	116835543 ps
CPU time	3.46 seconds
Started	May 14 01:28:03 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	233708 kb
Host	smart-00712c39-a581-4bc1-9bc8-a14f31bbcffe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265921188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4265921188
Directory	/workspace/15.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/15.spi_device_csb_read.1508128507
Short name	T841
Test name
Test status
Simulation time	48936312 ps
CPU time	0.77 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:18 PM PDT 24
Peak memory	205448 kb
Host	smart-4196243d-5c23-418b-948e-e8a05c2c1de2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508128507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1508128507
Directory	/workspace/15.spi_device_csb_read/latest

Test location	/workspace/coverage/default/15.spi_device_flash_and_tpm.1250316131
Short name	T920
Test name
Test status
Simulation time	290692090 ps
CPU time	6.47 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	224220 kb
Host	smart-5c61e1ec-353d-416e-9e74-174957fb3c18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250316131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1250316131
Directory	/workspace/15.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2550163629
Short name	T649
Test name
Test status
Simulation time	19186471085 ps
CPU time	43.15 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:55 PM PDT 24
Peak memory	240824 kb
Host	smart-b9f810f8-abca-46aa-9433-3c6e4b93aa84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550163629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl e.2550163629
Directory	/workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/15.spi_device_flash_mode.3412223715
Short name	T565
Test name
Test status
Simulation time	4188443223 ps
CPU time	21.5 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:25 PM PDT 24
Peak memory	232620 kb
Host	smart-cb34ce84-ea66-4deb-938a-c6ef7738c5d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412223715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3412223715
Directory	/workspace/15.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/15.spi_device_intercept.426039033
Short name	T657
Test name
Test status
Simulation time	226745799 ps
CPU time	3.39 seconds
Started	May 14 01:28:00 PM PDT 24
Finished	May 14 01:28:06 PM PDT 24
Peak memory	218248 kb
Host	smart-5ca7fe5f-75f0-4ac0-b85b-e8bb3cb7daa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426039033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.426039033
Directory	/workspace/15.spi_device_intercept/latest

Test location	/workspace/coverage/default/15.spi_device_mailbox.1787720421
Short name	T586
Test name
Test status
Simulation time	61130785 ps
CPU time	2.33 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:20 PM PDT 24
Peak memory	221416 kb
Host	smart-25f8b8f5-ca03-4ba5-bbdc-35a3bbc5195a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787720421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1787720421
Directory	/workspace/15.spi_device_mailbox/latest

Test location	/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2093579000
Short name	T639
Test name
Test status
Simulation time	6869181159 ps
CPU time	20.6 seconds
Started	May 14 01:28:03 PM PDT 24
Finished	May 14 01:28:26 PM PDT 24
Peak memory	233104 kb
Host	smart-231eac2a-52c7-4535-b432-501f82d4f3d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093579000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa p.2093579000
Directory	/workspace/15.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/15.spi_device_pass_cmd_filtering.2496821535
Short name	T868
Test name
Test status
Simulation time	305820325 ps
CPU time	4.51 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:08 PM PDT 24
Peak memory	236012 kb
Host	smart-85133683-f5ea-4f69-91db-b503b7f34226
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496821535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2496821535
Directory	/workspace/15.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/15.spi_device_read_buffer_direct.3294856019
Short name	T32
Test name
Test status
Simulation time	1193044320 ps
CPU time	4.88 seconds
Started	May 14 01:28:01 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	219680 kb
Host	smart-f16d5318-2ec9-449a-882d-e89dd58cf801
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3294856019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir ect.3294856019
Directory	/workspace/15.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_all.2003864359
Short name	T592
Test name
Test status
Simulation time	831838889 ps
CPU time	16.2 seconds
Started	May 14 01:28:02 PM PDT 24
Finished	May 14 01:28:21 PM PDT 24
Peak memory	216104 kb
Host	smart-52449b73-e357-49b1-b36b-d8706cf6f9ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003864359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2003864359
Directory	/workspace/15.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3403851703
Short name	T471
Test name
Test status
Simulation time	1536555254 ps
CPU time	3.96 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:22 PM PDT 24
Peak memory	216012 kb
Host	smart-a50c386a-3fe0-44dd-8a2e-9155ec42f1a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403851703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3403851703
Directory	/workspace/15.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_rw.1414780388
Short name	T782
Test name
Test status
Simulation time	405989109 ps
CPU time	2.15 seconds
Started	May 14 01:28:02 PM PDT 24
Finished	May 14 01:28:07 PM PDT 24
Peak memory	216104 kb
Host	smart-d55122c8-5c43-4243-9d64-d22382350172
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414780388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1414780388
Directory	/workspace/15.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_sts_read.1049664342
Short name	T363
Test name
Test status
Simulation time	137707960 ps
CPU time	0.72 seconds
Started	May 14 01:27:58 PM PDT 24
Finished	May 14 01:28:01 PM PDT 24
Peak memory	205896 kb
Host	smart-a7704130-318c-47b1-8c52-d0bd79028807
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049664342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1049664342
Directory	/workspace/15.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/15.spi_device_upload.571862981
Short name	T607
Test name
Test status
Simulation time	421511235 ps
CPU time	3.37 seconds
Started	May 14 01:28:02 PM PDT 24
Finished	May 14 01:28:08 PM PDT 24
Peak memory	224252 kb
Host	smart-c8297363-7b7c-4724-acc1-34a1b5742089
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571862981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.571862981
Directory	/workspace/15.spi_device_upload/latest

Test location	/workspace/coverage/default/16.spi_device_alert_test.4234524134
Short name	T956
Test name
Test status
Simulation time	18242115 ps
CPU time	0.69 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	205172 kb
Host	smart-059e540a-92bb-4a9e-8d58-b2edc09f2702
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234524134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test. 4234524134
Directory	/workspace/16.spi_device_alert_test/latest

Test location	/workspace/coverage/default/16.spi_device_cfg_cmd.4134454944
Short name	T156
Test name
Test status
Simulation time	221041912 ps
CPU time	2.71 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:14 PM PDT 24
Peak memory	233916 kb
Host	smart-152b561f-98d2-4db3-b4f0-c9c308402267
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134454944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4134454944
Directory	/workspace/16.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/16.spi_device_csb_read.2865358461
Short name	T944
Test name
Test status
Simulation time	109717084 ps
CPU time	0.81 seconds
Started	May 14 01:28:08 PM PDT 24
Finished	May 14 01:28:11 PM PDT 24
Peak memory	206388 kb
Host	smart-359f9fe4-226c-4a65-b9e3-144d515ca5db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865358461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2865358461
Directory	/workspace/16.spi_device_csb_read/latest

Test location	/workspace/coverage/default/16.spi_device_flash_all.962591156
Short name	T750
Test name
Test status
Simulation time	8326305267 ps
CPU time	62.63 seconds
Started	May 14 01:28:05 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	232836 kb
Host	smart-97e71dbd-306a-4130-a3ca-b40fdc6a6b7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962591156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.962591156
Directory	/workspace/16.spi_device_flash_all/latest

Test location	/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.459965508
Short name	T808
Test name
Test status
Simulation time	6016820950 ps
CPU time	28.44 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:36 PM PDT 24
Peak memory	232672 kb
Host	smart-1f78efe4-0c27-4909-8baa-6b7462c9a539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459965508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle .459965508
Directory	/workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/16.spi_device_flash_mode.1086777445
Short name	T424
Test name
Test status
Simulation time	179542234 ps
CPU time	3.07 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:27 PM PDT 24
Peak memory	224260 kb
Host	smart-05ccf742-4ced-40ac-80db-f77be8ae8f71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086777445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1086777445
Directory	/workspace/16.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/16.spi_device_intercept.2541586171
Short name	T652
Test name
Test status
Simulation time	93610508 ps
CPU time	3.43 seconds
Started	May 14 01:27:59 PM PDT 24
Finished	May 14 01:28:04 PM PDT 24
Peak memory	233024 kb
Host	smart-e854e7fa-210e-4a0b-8711-51300cb244db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541586171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2541586171
Directory	/workspace/16.spi_device_intercept/latest

Test location	/workspace/coverage/default/16.spi_device_mailbox.920796631
Short name	T900
Test name
Test status
Simulation time	3905086982 ps
CPU time	38.32 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	239164 kb
Host	smart-85deb6ad-d812-4f94-99f0-86342f7a17e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920796631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.920796631
Directory	/workspace/16.spi_device_mailbox/latest

Test location	/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1201665837
Short name	T419
Test name
Test status
Simulation time	340719596 ps
CPU time	4.13 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	233088 kb
Host	smart-ff5ff7fd-5b97-4fe8-aa18-bda8c2bc2cb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201665837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa p.1201665837
Directory	/workspace/16.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/16.spi_device_pass_cmd_filtering.3148698690
Short name	T386
Test name
Test status
Simulation time	103704549136 ps
CPU time	30.37 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	229276 kb
Host	smart-0b189b34-4e9b-4594-8fdd-b5c3b6441e52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148698690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3148698690
Directory	/workspace/16.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/16.spi_device_read_buffer_direct.3998084842
Short name	T357
Test name
Test status
Simulation time	83358743 ps
CPU time	4.01 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:20 PM PDT 24
Peak memory	222224 kb
Host	smart-515dde00-9f2e-416d-9b2b-50e661993190
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3998084842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir ect.3998084842
Directory	/workspace/16.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/16.spi_device_stress_all.1105772268
Short name	T152
Test name
Test status
Simulation time	107939882248 ps
CPU time	200.3 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:31:36 PM PDT 24
Peak memory	255432 kb
Host	smart-770200bd-41e1-46e5-a75d-a640ec1f2547
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105772268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre ss_all.1105772268
Directory	/workspace/16.spi_device_stress_all/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_all.546135
Short name	T637
Test name
Test status
Simulation time	1197972320 ps
CPU time	12.03 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	216084 kb
Host	smart-ff4b3c24-d3df-4a9d-a654-6b1f0933907c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.546135
Directory	/workspace/16.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4076259204
Short name	T598
Test name
Test status
Simulation time	1619314090 ps
CPU time	8.76 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:20 PM PDT 24
Peak memory	216044 kb
Host	smart-59a5a272-a627-41b8-9686-946d2e48d217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076259204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4076259204
Directory	/workspace/16.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_rw.1345031000
Short name	T481
Test name
Test status
Simulation time	481825067 ps
CPU time	3.77 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:12 PM PDT 24
Peak memory	216092 kb
Host	smart-a07f1d48-c89a-4f68-92ee-855630dd3254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345031000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1345031000
Directory	/workspace/16.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_sts_read.2709499096
Short name	T18
Test name
Test status
Simulation time	48045065 ps
CPU time	0.75 seconds
Started	May 14 01:28:10 PM PDT 24
Finished	May 14 01:28:13 PM PDT 24
Peak memory	205608 kb
Host	smart-8a02f43c-d14d-48ca-a179-39d7ffe4da75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709499096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2709499096
Directory	/workspace/16.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/16.spi_device_upload.1661272305
Short name	T562
Test name
Test status
Simulation time	8521185171 ps
CPU time	11.69 seconds
Started	May 14 01:28:09 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	234272 kb
Host	smart-49efaedd-7eb5-47da-a563-c87c19d89dba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661272305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1661272305
Directory	/workspace/16.spi_device_upload/latest

Test location	/workspace/coverage/default/17.spi_device_alert_test.2708592416
Short name	T922
Test name
Test status
Simulation time	13662196 ps
CPU time	0.71 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:25 PM PDT 24
Peak memory	204740 kb
Host	smart-9de4a4b6-dba0-4805-b205-960e4a09319f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708592416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test. 2708592416
Directory	/workspace/17.spi_device_alert_test/latest

Test location	/workspace/coverage/default/17.spi_device_cfg_cmd.3419275609
Short name	T823
Test name
Test status
Simulation time	109775313 ps
CPU time	2.24 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:26 PM PDT 24
Peak memory	220572 kb
Host	smart-177169e0-5869-448a-87ea-8b28596f6dae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419275609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3419275609
Directory	/workspace/17.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/17.spi_device_csb_read.4096258901
Short name	T684
Test name
Test status
Simulation time	15090208 ps
CPU time	0.76 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:22 PM PDT 24
Peak memory	205704 kb
Host	smart-5008c1d4-c679-4e1e-b71e-7b8b3b1a4682
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096258901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4096258901
Directory	/workspace/17.spi_device_csb_read/latest

Test location	/workspace/coverage/default/17.spi_device_flash_all.1015674195
Short name	T668
Test name
Test status
Simulation time	49834826015 ps
CPU time	244.61 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:32:29 PM PDT 24
Peak memory	248904 kb
Host	smart-d37c3ee4-8ac8-403c-a00c-abdf4d02c204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015674195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1015674195
Directory	/workspace/17.spi_device_flash_all/latest

Test location	/workspace/coverage/default/17.spi_device_flash_and_tpm.3721132495
Short name	T661
Test name
Test status
Simulation time	1631479300 ps
CPU time	22.05 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:28:31 PM PDT 24
Peak memory	217276 kb
Host	smart-dcb55798-2072-4e3b-8e46-4ef26b202809
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721132495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3721132495
Directory	/workspace/17.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.962144196
Short name	T705
Test name
Test status
Simulation time	24476195235 ps
CPU time	33.29 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	223424 kb
Host	smart-2b849f92-d0ca-4429-bd11-bab8dfa42ef7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962144196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle .962144196
Directory	/workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/17.spi_device_flash_mode.1112943795
Short name	T659
Test name
Test status
Simulation time	1731282377 ps
CPU time	8.77 seconds
Started	May 14 01:28:04 PM PDT 24
Finished	May 14 01:28:15 PM PDT 24
Peak memory	224288 kb
Host	smart-61029eb1-a9e8-4743-8977-abe37ba419e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112943795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1112943795
Directory	/workspace/17.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/17.spi_device_intercept.3416697800
Short name	T832
Test name
Test status
Simulation time	865353525 ps
CPU time	6.9 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	233304 kb
Host	smart-9bfddff2-9a4f-48c7-a126-f27e673483b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416697800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3416697800
Directory	/workspace/17.spi_device_intercept/latest

Test location	/workspace/coverage/default/17.spi_device_mailbox.2093008517
Short name	T799
Test name
Test status
Simulation time	6101440360 ps
CPU time	41.48 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	240764 kb
Host	smart-af4f8719-fec3-4648-9086-7cc1adf7c65b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093008517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2093008517
Directory	/workspace/17.spi_device_mailbox/latest

Test location	/workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2715920791
Short name	T924
Test name
Test status
Simulation time	4661296616 ps
CPU time	9.56 seconds
Started	May 14 01:28:20 PM PDT 24
Finished	May 14 01:28:34 PM PDT 24
Peak memory	232528 kb
Host	smart-f14552a2-bacd-4cca-900f-767951674261
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715920791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa p.2715920791
Directory	/workspace/17.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/17.spi_device_pass_cmd_filtering.465024737
Short name	T344
Test name
Test status
Simulation time	76081178 ps
CPU time	2.13 seconds
Started	May 14 01:28:06 PM PDT 24
Finished	May 14 01:28:10 PM PDT 24
Peak memory	215932 kb
Host	smart-796c0f60-70ef-49e6-9643-7b3da861aa72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465024737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.465024737
Directory	/workspace/17.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/17.spi_device_read_buffer_direct.865453232
Short name	T3
Test name
Test status
Simulation time	7116680122 ps
CPU time	7.98 seconds
Started	May 14 01:28:14 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	219832 kb
Host	smart-ad06a169-1a58-405f-8d26-3048310667bd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=865453232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire ct.865453232
Directory	/workspace/17.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/17.spi_device_stress_all.482778841
Short name	T72
Test name
Test status
Simulation time	52357995825 ps
CPU time	273.59 seconds
Started	May 14 01:28:04 PM PDT 24
Finished	May 14 01:32:40 PM PDT 24
Peak memory	270964 kb
Host	smart-cd7e0765-69b7-45d1-bc75-048376899061
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482778841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres s_all.482778841
Directory	/workspace/17.spi_device_stress_all/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_all.3626200622
Short name	T896
Test name
Test status
Simulation time	4374916388 ps
CPU time	17.54 seconds
Started	May 14 01:28:14 PM PDT 24
Finished	May 14 01:28:33 PM PDT 24
Peak memory	216116 kb
Host	smart-147e1e7d-9616-4fc5-bad4-fe7b84334a01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626200622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3626200622
Directory	/workspace/17.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1046383720
Short name	T342
Test name
Test status
Simulation time	6436590714 ps
CPU time	4.51 seconds
Started	May 14 01:28:05 PM PDT 24
Finished	May 14 01:28:11 PM PDT 24
Peak memory	216132 kb
Host	smart-79baa221-00bb-495f-8ede-9f36abff8352
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046383720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1046383720
Directory	/workspace/17.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_rw.1187051746
Short name	T907
Test name
Test status
Simulation time	366077908 ps
CPU time	1.58 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:22 PM PDT 24
Peak memory	207704 kb
Host	smart-eabaa935-8665-4e6a-b1c3-f0c67ac1ce6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187051746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1187051746
Directory	/workspace/17.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_sts_read.1731951425
Short name	T793
Test name
Test status
Simulation time	123859180 ps
CPU time	0.85 seconds
Started	May 14 01:28:13 PM PDT 24
Finished	May 14 01:28:15 PM PDT 24
Peak memory	205632 kb
Host	smart-4682b80e-060a-40c9-b258-e3634cc68261
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731951425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1731951425
Directory	/workspace/17.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/17.spi_device_upload.3968609418
Short name	T203
Test name
Test status
Simulation time	1216885833 ps
CPU time	4.27 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:25 PM PDT 24
Peak memory	217220 kb
Host	smart-a6dc231b-c8f0-40da-b9b7-6edd4b30db4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968609418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3968609418
Directory	/workspace/17.spi_device_upload/latest

Test location	/workspace/coverage/default/18.spi_device_alert_test.385850940
Short name	T513
Test name
Test status
Simulation time	31821264 ps
CPU time	0.7 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	205100 kb
Host	smart-1086fe22-86f0-4c0a-a4ad-c24ab61951d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385850940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.385850940
Directory	/workspace/18.spi_device_alert_test/latest

Test location	/workspace/coverage/default/18.spi_device_cfg_cmd.393552576
Short name	T695
Test name
Test status
Simulation time	160137602 ps
CPU time	3.54 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	219416 kb
Host	smart-ee2d334a-c98e-4ad6-8c1a-93a418812806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393552576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.393552576
Directory	/workspace/18.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/18.spi_device_csb_read.2032470144
Short name	T784
Test name
Test status
Simulation time	166914169 ps
CPU time	0.77 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	206388 kb
Host	smart-fb5e1b2e-7c78-4758-a95b-0f77536304ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032470144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2032470144
Directory	/workspace/18.spi_device_csb_read/latest

Test location	/workspace/coverage/default/18.spi_device_flash_all.1979013586
Short name	T416
Test name
Test status
Simulation time	26427191316 ps
CPU time	83.95 seconds
Started	May 14 01:28:03 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	237796 kb
Host	smart-47342387-e95e-4925-b3de-04e2cb7d63fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979013586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1979013586
Directory	/workspace/18.spi_device_flash_all/latest

Test location	/workspace/coverage/default/18.spi_device_flash_and_tpm.1447774672
Short name	T795
Test name
Test status
Simulation time	9743404778 ps
CPU time	64.26 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	257080 kb
Host	smart-aba11de5-060a-4830-8806-75c447bced05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447774672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1447774672
Directory	/workspace/18.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.827063395
Short name	T284
Test name
Test status
Simulation time	18282457538 ps
CPU time	173.29 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:31:14 PM PDT 24
Peak memory	240844 kb
Host	smart-a74952ed-75ca-4ab5-9eda-b71b115cd005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827063395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle .827063395
Directory	/workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/18.spi_device_flash_mode.1980851594
Short name	T853
Test name
Test status
Simulation time	140167672 ps
CPU time	5.02 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	234776 kb
Host	smart-b14ecd57-ecf8-45bc-b11e-5bf15453497e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980851594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1980851594
Directory	/workspace/18.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/18.spi_device_intercept.2540207464
Short name	T155
Test name
Test status
Simulation time	317770332 ps
CPU time	4.08 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:28 PM PDT 24
Peak memory	218280 kb
Host	smart-a7e170fc-f2da-4536-9cbf-d85e500e1b00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540207464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2540207464
Directory	/workspace/18.spi_device_intercept/latest

Test location	/workspace/coverage/default/18.spi_device_mailbox.683346359
Short name	T724
Test name
Test status
Simulation time	182262031 ps
CPU time	4.11 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:25 PM PDT 24
Peak memory	234092 kb
Host	smart-6fe1fad6-a245-4866-a538-14eeca45b719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683346359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.683346359
Directory	/workspace/18.spi_device_mailbox/latest

Test location	/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3380805144
Short name	T296
Test name
Test status
Simulation time	391921760 ps
CPU time	3.38 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:27 PM PDT 24
Peak memory	233868 kb
Host	smart-bf862640-0121-4fdd-a382-7df279b41b69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380805144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa p.3380805144
Directory	/workspace/18.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/18.spi_device_pass_cmd_filtering.1254897411
Short name	T826
Test name
Test status
Simulation time	15765548661 ps
CPU time	26.89 seconds
Started	May 14 01:28:19 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	233408 kb
Host	smart-25b16eb9-592a-4560-a65a-40b1c03024a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254897411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1254897411
Directory	/workspace/18.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/18.spi_device_read_buffer_direct.1703763827
Short name	T492
Test name
Test status
Simulation time	2505918523 ps
CPU time	8.24 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	222720 kb
Host	smart-3aa1d087-1276-42ce-8c32-0901b0a3888a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1703763827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir ect.1703763827
Directory	/workspace/18.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/18.spi_device_stress_all.549776169
Short name	T162
Test name
Test status
Simulation time	97438545234 ps
CPU time	178.13 seconds
Started	May 14 01:28:20 PM PDT 24
Finished	May 14 01:31:22 PM PDT 24
Peak memory	237720 kb
Host	smart-b3db7865-2a4a-4e72-8e7c-766d5db6d7d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549776169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres s_all.549776169
Directory	/workspace/18.spi_device_stress_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_all.1842303077
Short name	T740
Test name
Test status
Simulation time	14558583878 ps
CPU time	28.09 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	216328 kb
Host	smart-01c7153c-8776-424f-9dd9-bee3a7e9929b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842303077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1842303077
Directory	/workspace/18.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_read_hw_reg.16333589
Short name	T581
Test name
Test status
Simulation time	6202269594 ps
CPU time	19.46 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	216060 kb
Host	smart-1392caba-9118-4df1-bab6-53762046330d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16333589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.16333589
Directory	/workspace/18.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_rw.863368344
Short name	T50
Test name
Test status
Simulation time	173999337 ps
CPU time	1.23 seconds
Started	May 14 01:28:13 PM PDT 24
Finished	May 14 01:28:16 PM PDT 24
Peak memory	215956 kb
Host	smart-d2a82c4a-18de-4259-ae78-e89b658a9b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863368344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.863368344
Directory	/workspace/18.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_sts_read.2523436221
Short name	T554
Test name
Test status
Simulation time	65401952 ps
CPU time	0.87 seconds
Started	May 14 01:28:07 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	205624 kb
Host	smart-997454c6-0659-4c8e-b07f-4b882afb665f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523436221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2523436221
Directory	/workspace/18.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/18.spi_device_upload.1804128287
Short name	T214
Test name
Test status
Simulation time	879248021 ps
CPU time	3.48 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	217228 kb
Host	smart-8b73ebf0-7210-45ff-aa20-e21672f088aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804128287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1804128287
Directory	/workspace/18.spi_device_upload/latest

Test location	/workspace/coverage/default/19.spi_device_cfg_cmd.1671170102
Short name	T602
Test name
Test status
Simulation time	238110706 ps
CPU time	3.02 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:26 PM PDT 24
Peak memory	218504 kb
Host	smart-d66e89aa-048d-405c-a88c-ff35a6a067ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671170102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1671170102
Directory	/workspace/19.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/19.spi_device_csb_read.315320912
Short name	T932
Test name
Test status
Simulation time	38537215 ps
CPU time	0.84 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:20 PM PDT 24
Peak memory	206400 kb
Host	smart-66f5df53-ed52-4f7f-bf3f-d860f8608faa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315320912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.315320912
Directory	/workspace/19.spi_device_csb_read/latest

Test location	/workspace/coverage/default/19.spi_device_flash_all.2085987825
Short name	T321
Test name
Test status
Simulation time	42929802513 ps
CPU time	68.75 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	250992 kb
Host	smart-5186a9e5-3320-48a6-8613-0720fe8e2deb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085987825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2085987825
Directory	/workspace/19.spi_device_flash_all/latest

Test location	/workspace/coverage/default/19.spi_device_flash_and_tpm.266332584
Short name	T268
Test name
Test status
Simulation time	19102284011 ps
CPU time	179.91 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:31:20 PM PDT 24
Peak memory	252848 kb
Host	smart-af96bc81-f847-4567-b327-780ec104b426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266332584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.266332584
Directory	/workspace/19.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1186646344
Short name	T237
Test name
Test status
Simulation time	90837709813 ps
CPU time	235.2 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:32:18 PM PDT 24
Peak memory	249056 kb
Host	smart-f5a9f3e8-2e19-4321-84d3-27e9a33ab361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186646344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl e.1186646344
Directory	/workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/19.spi_device_flash_mode.902274056
Short name	T395
Test name
Test status
Simulation time	1445365660 ps
CPU time	8.28 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:32 PM PDT 24
Peak memory	224348 kb
Host	smart-8af84e41-2e8a-4149-8a61-c3b25778e003
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902274056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.902274056
Directory	/workspace/19.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/19.spi_device_intercept.950265192
Short name	T93
Test name
Test status
Simulation time	163521610 ps
CPU time	4.09 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	235676 kb
Host	smart-6b565c27-b0a8-4cbb-9fdd-1f25f3b71230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950265192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.950265192
Directory	/workspace/19.spi_device_intercept/latest

Test location	/workspace/coverage/default/19.spi_device_mailbox.2189550737
Short name	T480
Test name
Test status
Simulation time	37686276 ps
CPU time	2.63 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:26 PM PDT 24
Peak memory	221320 kb
Host	smart-6a76c9e9-ff3c-4211-98c5-8c0e569fc679
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189550737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2189550737
Directory	/workspace/19.spi_device_mailbox/latest

Test location	/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4065002001
Short name	T176
Test name
Test status
Simulation time	10160345502 ps
CPU time	11.25 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:35 PM PDT 24
Peak memory	218600 kb
Host	smart-6ff920a3-9208-46f9-87c4-ebab7ee3820c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065002001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa p.4065002001
Directory	/workspace/19.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/19.spi_device_pass_cmd_filtering.4104811373
Short name	T39
Test name
Test status
Simulation time	1075828558 ps
CPU time	3.68 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:25 PM PDT 24
Peak memory	219236 kb
Host	smart-795e6e50-cc3a-4724-83cd-4dd24aa158f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104811373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4104811373
Directory	/workspace/19.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/19.spi_device_read_buffer_direct.1057117005
Short name	T519
Test name
Test status
Simulation time	462518212 ps
CPU time	5.74 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:30 PM PDT 24
Peak memory	219688 kb
Host	smart-41522e1b-150e-48bf-a096-5799b195fe15
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1057117005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir ect.1057117005
Directory	/workspace/19.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_all.1248282132
Short name	T438
Test name
Test status
Simulation time	11293622845 ps
CPU time	18.62 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	217364 kb
Host	smart-177460e6-f4f2-4dfb-8c37-5215ac7d87a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248282132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1248282132
Directory	/workspace/19.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3773570127
Short name	T376
Test name
Test status
Simulation time	34038587624 ps
CPU time	22.42 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:45 PM PDT 24
Peak memory	216172 kb
Host	smart-0dd4d351-0953-46ac-bc49-fb74578f8303
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773570127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3773570127
Directory	/workspace/19.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_rw.91850754
Short name	T789
Test name
Test status
Simulation time	155934653 ps
CPU time	2.36 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:19 PM PDT 24
Peak memory	216116 kb
Host	smart-a8a498e6-0b7a-4e03-9616-83e1127c0550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91850754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.91850754
Directory	/workspace/19.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_sts_read.2157796907
Short name	T673
Test name
Test status
Simulation time	94329825 ps
CPU time	1.01 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	205628 kb
Host	smart-389f0a96-2146-4461-8bfa-96153e3c3ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157796907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2157796907
Directory	/workspace/19.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/19.spi_device_upload.3877609393
Short name	T927
Test name
Test status
Simulation time	701211178 ps
CPU time	9.83 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	227116 kb
Host	smart-2e406b32-e462-422f-be19-d9468b125d04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877609393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3877609393
Directory	/workspace/19.spi_device_upload/latest

Test location	/workspace/coverage/default/2.spi_device_alert_test.1956327778
Short name	T809
Test name
Test status
Simulation time	18472351 ps
CPU time	0.76 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:37 PM PDT 24
Peak memory	205320 kb
Host	smart-d58cfed6-7ee8-4e35-bad3-7ddb54a41b57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956327778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1 956327778
Directory	/workspace/2.spi_device_alert_test/latest

Test location	/workspace/coverage/default/2.spi_device_cfg_cmd.2501144876
Short name	T754
Test name
Test status
Simulation time	680349665 ps
CPU time	2.35 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	215948 kb
Host	smart-66a52655-9397-4a49-8181-502aa229a9ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501144876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2501144876
Directory	/workspace/2.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/2.spi_device_csb_read.4212936439
Short name	T383
Test name
Test status
Simulation time	25510507 ps
CPU time	0.79 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:24 PM PDT 24
Peak memory	205420 kb
Host	smart-6444b1c9-8b20-4cc4-a964-4447c1c2fc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212936439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4212936439
Directory	/workspace/2.spi_device_csb_read/latest

Test location	/workspace/coverage/default/2.spi_device_flash_and_tpm.1594407940
Short name	T57
Test name
Test status
Simulation time	14029825915 ps
CPU time	59.68 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:28:34 PM PDT 24
Peak memory	250088 kb
Host	smart-3a6a092a-0631-4e69-81cd-9fa38b5c395c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594407940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1594407940
Directory	/workspace/2.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.169751498
Short name	T227
Test name
Test status
Simulation time	15212148425 ps
CPU time	89.91 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:29:07 PM PDT 24
Peak memory	250484 kb
Host	smart-5745a83d-991e-424f-bd18-c02c4e58fc6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169751498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle. 169751498
Directory	/workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/2.spi_device_flash_mode.4073629138
Short name	T753
Test name
Test status
Simulation time	3930546185 ps
CPU time	8.85 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:45 PM PDT 24
Peak memory	224368 kb
Host	smart-73045c3c-04b2-4777-9000-6dcb6095acf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073629138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4073629138
Directory	/workspace/2.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/2.spi_device_intercept.1053600349
Short name	T552
Test name
Test status
Simulation time	249965602 ps
CPU time	5.56 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:41 PM PDT 24
Peak memory	219452 kb
Host	smart-d40401f8-81ea-446d-9fcf-615f8265ff77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053600349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1053600349
Directory	/workspace/2.spi_device_intercept/latest

Test location	/workspace/coverage/default/2.spi_device_mailbox.1987305852
Short name	T680
Test name
Test status
Simulation time	29845874833 ps
CPU time	64.92 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	240704 kb
Host	smart-829d2170-1432-48fc-9774-fffa61fa1906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987305852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1987305852
Directory	/workspace/2.spi_device_mailbox/latest

Test location	/workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3460744405
Short name	T260
Test name
Test status
Simulation time	990065937 ps
CPU time	9.7 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:43 PM PDT 24
Peak memory	233140 kb
Host	smart-ca1f1b56-84ef-4767-b053-757ea8deb56b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460744405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap .3460744405
Directory	/workspace/2.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/2.spi_device_pass_cmd_filtering.3130380584
Short name	T158
Test name
Test status
Simulation time	396679193 ps
CPU time	2.59 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:27:26 PM PDT 24
Peak memory	216220 kb
Host	smart-439de2fd-9141-480b-a8c2-16b9cfa359bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130380584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3130380584
Directory	/workspace/2.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/2.spi_device_read_buffer_direct.3791821607
Short name	T664
Test name
Test status
Simulation time	5516157044 ps
CPU time	6.3 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	222344 kb
Host	smart-4c643ecf-8bbb-49ab-b3c4-9eef3ffcdb83
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3791821607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire ct.3791821607
Directory	/workspace/2.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/2.spi_device_stress_all.1568662120
Short name	T876
Test name
Test status
Simulation time	90013662 ps
CPU time	0.96 seconds
Started	May 14 01:27:30 PM PDT 24
Finished	May 14 01:27:32 PM PDT 24
Peak memory	206684 kb
Host	smart-5beb8b6d-9a39-4663-bdd7-17226696b2a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568662120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres s_all.1568662120
Directory	/workspace/2.spi_device_stress_all/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_all.2186181706
Short name	T334
Test name
Test status
Simulation time	5643816229 ps
CPU time	19.76 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:42 PM PDT 24
Peak memory	216236 kb
Host	smart-8e2a54fb-d5ec-4322-a55f-4b10c363ab49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186181706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2186181706
Directory	/workspace/2.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1356775364
Short name	T508
Test name
Test status
Simulation time	9360947313 ps
CPU time	12 seconds
Started	May 14 01:27:20 PM PDT 24
Finished	May 14 01:27:34 PM PDT 24
Peak memory	216036 kb
Host	smart-76617a37-08ad-46c0-8e5f-9cf99ab8e7d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356775364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1356775364
Directory	/workspace/2.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_rw.1608902220
Short name	T520
Test name
Test status
Simulation time	64646093 ps
CPU time	3.25 seconds
Started	May 14 01:27:22 PM PDT 24
Finished	May 14 01:27:27 PM PDT 24
Peak memory	216084 kb
Host	smart-aae2050f-dba7-4f5a-ae91-9efd3dc01925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608902220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1608902220
Directory	/workspace/2.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_sts_read.441142766
Short name	T505
Test name
Test status
Simulation time	226173830 ps
CPU time	0.88 seconds
Started	May 14 01:27:21 PM PDT 24
Finished	May 14 01:27:24 PM PDT 24
Peak memory	206208 kb
Host	smart-119afc7c-100e-4f64-bed9-44f2f70dedf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441142766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.441142766
Directory	/workspace/2.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/2.spi_device_upload.3074906824
Short name	T523
Test name
Test status
Simulation time	352181443 ps
CPU time	4.78 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	218912 kb
Host	smart-af690132-cbd5-4deb-9d30-43a890231f27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074906824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3074906824
Directory	/workspace/2.spi_device_upload/latest

Test location	/workspace/coverage/default/20.spi_device_alert_test.3765848525
Short name	T473
Test name
Test status
Simulation time	38813310 ps
CPU time	0.73 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	205300 kb
Host	smart-173e2692-d339-4910-a5ed-0b29806736f9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765848525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test. 3765848525
Directory	/workspace/20.spi_device_alert_test/latest

Test location	/workspace/coverage/default/20.spi_device_cfg_cmd.3135522000
Short name	T895
Test name
Test status
Simulation time	47796497 ps
CPU time	2.58 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:26 PM PDT 24
Peak memory	218424 kb
Host	smart-bf4ff326-d4a9-4524-a9be-0ed526724218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135522000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3135522000
Directory	/workspace/20.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/20.spi_device_csb_read.4037023202
Short name	T814
Test name
Test status
Simulation time	17747856 ps
CPU time	0.79 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:22 PM PDT 24
Peak memory	205424 kb
Host	smart-0f09a11c-01db-434b-977d-c84d3eef8d7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037023202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4037023202
Directory	/workspace/20.spi_device_csb_read/latest

Test location	/workspace/coverage/default/20.spi_device_flash_all.1310780778
Short name	T225
Test name
Test status
Simulation time	5709324199 ps
CPU time	12.59 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	236796 kb
Host	smart-f0a2969c-21fd-4299-810c-34cabdd5f7db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310780778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1310780778
Directory	/workspace/20.spi_device_flash_all/latest

Test location	/workspace/coverage/default/20.spi_device_flash_and_tpm.3440483123
Short name	T54
Test name
Test status
Simulation time	34981741231 ps
CPU time	318.19 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:33:47 PM PDT 24
Peak memory	249088 kb
Host	smart-3fda927e-6bb6-44ed-a900-9ee2284321fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440483123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3440483123
Directory	/workspace/20.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3536078374
Short name	T889
Test name
Test status
Simulation time	7179775221 ps
CPU time	84.81 seconds
Started	May 14 01:28:24 PM PDT 24
Finished	May 14 01:29:50 PM PDT 24
Peak memory	249896 kb
Host	smart-99312045-d2fb-40d5-8f20-d852da66893b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536078374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl e.3536078374
Directory	/workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/20.spi_device_flash_mode.98512521
Short name	T529
Test name
Test status
Simulation time	1389853652 ps
CPU time	9.26 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:27 PM PDT 24
Peak memory	224308 kb
Host	smart-3d27e7d5-26e8-4b45-94a3-ffc9495291ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98512521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.98512521
Directory	/workspace/20.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/20.spi_device_intercept.1072319751
Short name	T165
Test name
Test status
Simulation time	471034196 ps
CPU time	4.26 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	218356 kb
Host	smart-74948d86-dc94-45e2-82b7-7558e420618b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072319751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1072319751
Directory	/workspace/20.spi_device_intercept/latest

Test location	/workspace/coverage/default/20.spi_device_mailbox.4240428382
Short name	T301
Test name
Test status
Simulation time	983965195 ps
CPU time	7.14 seconds
Started	May 14 01:28:15 PM PDT 24
Finished	May 14 01:28:23 PM PDT 24
Peak memory	240328 kb
Host	smart-50138f53-3160-4ecc-b576-6db99e22cc0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240428382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4240428382
Directory	/workspace/20.spi_device_mailbox/latest

Test location	/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2169196416
Short name	T381
Test name
Test status
Simulation time	63278749 ps
CPU time	2.56 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:25 PM PDT 24
Peak memory	221320 kb
Host	smart-822016ed-3fd3-4f72-b7d8-a8b7b26bbe97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169196416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa p.2169196416
Directory	/workspace/20.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/20.spi_device_pass_cmd_filtering.4192938235
Short name	T282
Test name
Test status
Simulation time	11935450220 ps
CPU time	17.7 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	240040 kb
Host	smart-00e225fa-f860-461c-96c5-310e4d4f2ddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192938235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4192938235
Directory	/workspace/20.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/20.spi_device_read_buffer_direct.4015060480
Short name	T934
Test name
Test status
Simulation time	986937920 ps
CPU time	15.54 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:28:48 PM PDT 24
Peak memory	218064 kb
Host	smart-66e088d1-7b23-4935-a486-dbf9a8afebf9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4015060480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir ect.4015060480
Directory	/workspace/20.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_all.4184557109
Short name	T855
Test name
Test status
Simulation time	2174522306 ps
CPU time	30.66 seconds
Started	May 14 01:28:17 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	216264 kb
Host	smart-18e5a165-ff0f-44f0-a144-4742833a1131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184557109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4184557109
Directory	/workspace/20.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1127529192
Short name	T526
Test name
Test status
Simulation time	19209151 ps
CPU time	0.73 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:21 PM PDT 24
Peak memory	205568 kb
Host	smart-4136cc78-f9ee-473b-8fcc-6ecc46efcef6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1127529192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1127529192
Directory	/workspace/20.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_rw.2800449973
Short name	T346
Test name
Test status
Simulation time	67924371 ps
CPU time	0.91 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	207080 kb
Host	smart-68f78144-41fd-46e3-a72e-0026111c99fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800449973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2800449973
Directory	/workspace/20.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_sts_read.608791816
Short name	T918
Test name
Test status
Simulation time	198694198 ps
CPU time	0.92 seconds
Started	May 14 01:28:16 PM PDT 24
Finished	May 14 01:28:21 PM PDT 24
Peak memory	205644 kb
Host	smart-c3ab025e-8a52-4928-bc6c-05633d068e94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608791816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.608791816
Directory	/workspace/20.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/20.spi_device_upload.1789300576
Short name	T209
Test name
Test status
Simulation time	1708301585 ps
CPU time	8.81 seconds
Started	May 14 01:28:18 PM PDT 24
Finished	May 14 01:28:32 PM PDT 24
Peak memory	237472 kb
Host	smart-82fae999-0dd8-4012-8a58-26a29d3b5f00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789300576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1789300576
Directory	/workspace/20.spi_device_upload/latest

Test location	/workspace/coverage/default/21.spi_device_alert_test.711462168
Short name	T672
Test name
Test status
Simulation time	34706463 ps
CPU time	0.72 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	204716 kb
Host	smart-ff5c6355-7ba1-4270-9672-8ae9cf32eb3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711462168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.711462168
Directory	/workspace/21.spi_device_alert_test/latest

Test location	/workspace/coverage/default/21.spi_device_cfg_cmd.1654938072
Short name	T765
Test name
Test status
Simulation time	147097406 ps
CPU time	3.26 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:32 PM PDT 24
Peak memory	218568 kb
Host	smart-6dbc8bc1-b07c-44ba-8d7e-3d422b3159fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654938072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1654938072
Directory	/workspace/21.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/21.spi_device_csb_read.798248459
Short name	T368
Test name
Test status
Simulation time	16190414 ps
CPU time	0.75 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:28:31 PM PDT 24
Peak memory	206420 kb
Host	smart-cf205ad2-815b-47bf-906e-eba4909c694f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798248459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.798248459
Directory	/workspace/21.spi_device_csb_read/latest

Test location	/workspace/coverage/default/21.spi_device_flash_all.98895358
Short name	T676
Test name
Test status
Simulation time	62221395456 ps
CPU time	106.67 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:30:23 PM PDT 24
Peak memory	240812 kb
Host	smart-2113c73b-fb0e-4890-8bf4-1c4efdc56d83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98895358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.98895358
Directory	/workspace/21.spi_device_flash_all/latest

Test location	/workspace/coverage/default/21.spi_device_flash_and_tpm.1992372996
Short name	T124
Test name
Test status
Simulation time	9403327811 ps
CPU time	49.85 seconds
Started	May 14 01:28:24 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	235312 kb
Host	smart-ac663486-5a7f-46b4-b3a9-e72727b5c496
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992372996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1992372996
Directory	/workspace/21.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.516400499
Short name	T689
Test name
Test status
Simulation time	5160749757 ps
CPU time	65.78 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:29:33 PM PDT 24
Peak memory	248900 kb
Host	smart-f7bc8d7d-4cab-441e-9015-ce111fcac5a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516400499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle .516400499
Directory	/workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/21.spi_device_flash_mode.7285761
Short name	T330
Test name
Test status
Simulation time	1513014750 ps
CPU time	5.65 seconds
Started	May 14 01:28:24 PM PDT 24
Finished	May 14 01:28:32 PM PDT 24
Peak memory	224288 kb
Host	smart-ef10d144-ca46-49f5-ab6b-538a05eb125f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7285761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.7285761
Directory	/workspace/21.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/21.spi_device_intercept.598078428
Short name	T923
Test name
Test status
Simulation time	10009791250 ps
CPU time	25.57 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	234016 kb
Host	smart-38e7c0d9-de51-4bbe-954e-00f88ffc86b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598078428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.598078428
Directory	/workspace/21.spi_device_intercept/latest

Test location	/workspace/coverage/default/21.spi_device_mailbox.3470141168
Short name	T35
Test name
Test status
Simulation time	12485184764 ps
CPU time	24.19 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:29:02 PM PDT 24
Peak memory	236112 kb
Host	smart-08e9eb8a-9276-43a4-8d6d-af3185b9137a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470141168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3470141168
Directory	/workspace/21.spi_device_mailbox/latest

Test location	/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.492889717
Short name	T197
Test name
Test status
Simulation time	677584249 ps
CPU time	8.01 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	230156 kb
Host	smart-e8b899b3-11a7-4a97-aa5c-a7e540f8bda5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492889717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap .492889717
Directory	/workspace/21.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/21.spi_device_pass_cmd_filtering.2270497599
Short name	T306
Test name
Test status
Simulation time	985286198 ps
CPU time	12.81 seconds
Started	May 14 01:28:24 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	248888 kb
Host	smart-53e3bd56-3ee4-45a8-926c-2ef190b545aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270497599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2270497599
Directory	/workspace/21.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/21.spi_device_read_buffer_direct.1193711649
Short name	T439
Test name
Test status
Simulation time	139017368 ps
CPU time	4.6 seconds
Started	May 14 01:28:30 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	222672 kb
Host	smart-5539b911-300d-436b-82cf-b2a57b23dcbb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1193711649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir ect.1193711649
Directory	/workspace/21.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/21.spi_device_stress_all.2148887750
Short name	T633
Test name
Test status
Simulation time	53081126 ps
CPU time	1.11 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:28:31 PM PDT 24
Peak memory	206944 kb
Host	smart-efa6b8ff-e0ba-4651-8e6d-2208a5c3e2f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148887750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre ss_all.2148887750
Directory	/workspace/21.spi_device_stress_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_all.2126823917
Short name	T129
Test name
Test status
Simulation time	6459806051 ps
CPU time	9.04 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	216200 kb
Host	smart-9b511694-d50b-401f-84c9-522af81e7173
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126823917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2126823917
Directory	/workspace/21.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1795442238
Short name	T374
Test name
Test status
Simulation time	9627173510 ps
CPU time	7.97 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	216092 kb
Host	smart-2f9c6c19-e319-4ca6-b9c3-d448e0ae946c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795442238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1795442238
Directory	/workspace/21.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_rw.1638789471
Short name	T604
Test name
Test status
Simulation time	226522386 ps
CPU time	1.53 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:28:31 PM PDT 24
Peak memory	216168 kb
Host	smart-c72e93eb-89cd-48e0-991a-ccd6751e1539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638789471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1638789471
Directory	/workspace/21.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_sts_read.3642510632
Short name	T365
Test name
Test status
Simulation time	80314596 ps
CPU time	0.7 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:28:34 PM PDT 24
Peak memory	205476 kb
Host	smart-02d8c2c9-4e54-4f02-a501-4de3ea5ff516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642510632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3642510632
Directory	/workspace/21.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/21.spi_device_upload.4019508638
Short name	T571
Test name
Test status
Simulation time	747675960 ps
CPU time	3.16 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:28:32 PM PDT 24
Peak memory	235076 kb
Host	smart-db11ec8d-c9a9-43d3-b318-cbc3cce815f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019508638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4019508638
Directory	/workspace/21.spi_device_upload/latest

Test location	/workspace/coverage/default/22.spi_device_alert_test.3611570282
Short name	T375
Test name
Test status
Simulation time	26325296 ps
CPU time	0.7 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:28:32 PM PDT 24
Peak memory	204692 kb
Host	smart-bf66ab81-1e66-4ac5-9159-3bc4d50f7adb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611570282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test. 3611570282
Directory	/workspace/22.spi_device_alert_test/latest

Test location	/workspace/coverage/default/22.spi_device_cfg_cmd.3681494285
Short name	T308
Test name
Test status
Simulation time	1876610990 ps
CPU time	18.41 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:28:48 PM PDT 24
Peak memory	235116 kb
Host	smart-5b5066e3-2f3f-463b-8365-a97fe0887212
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681494285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3681494285
Directory	/workspace/22.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/22.spi_device_csb_read.1908091173
Short name	T780
Test name
Test status
Simulation time	15501596 ps
CPU time	0.79 seconds
Started	May 14 01:28:24 PM PDT 24
Finished	May 14 01:28:27 PM PDT 24
Peak memory	205740 kb
Host	smart-35e94415-9ef9-40b7-8550-b8e17f7c48d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908091173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1908091173
Directory	/workspace/22.spi_device_csb_read/latest

Test location	/workspace/coverage/default/22.spi_device_flash_and_tpm.3962846548
Short name	T743
Test name
Test status
Simulation time	22344488983 ps
CPU time	84.41 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:29:54 PM PDT 24
Peak memory	249064 kb
Host	smart-8f47acfe-227f-4531-8380-17fb929fe9ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962846548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3962846548
Directory	/workspace/22.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3212852261
Short name	T297
Test name
Test status
Simulation time	7478248264 ps
CPU time	62.74 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:29:33 PM PDT 24
Peak memory	240896 kb
Host	smart-b9a9a996-c971-4486-a45a-38e9f78c538b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212852261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl e.3212852261
Directory	/workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/22.spi_device_flash_mode.1576873075
Short name	T943
Test name
Test status
Simulation time	26249487439 ps
CPU time	79.94 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:29:53 PM PDT 24
Peak memory	249024 kb
Host	smart-e53c47cf-fa88-4b2b-a3cb-e5f3c116da70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576873075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1576873075
Directory	/workspace/22.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/22.spi_device_intercept.3140737940
Short name	T460
Test name
Test status
Simulation time	1093280575 ps
CPU time	7.68 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:36 PM PDT 24
Peak memory	232460 kb
Host	smart-80ee94e6-5358-4ce6-aa9b-ccfbf41e90e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140737940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3140737940
Directory	/workspace/22.spi_device_intercept/latest

Test location	/workspace/coverage/default/22.spi_device_mailbox.2313371256
Short name	T201
Test name
Test status
Simulation time	1796622105 ps
CPU time	6.52 seconds
Started	May 14 01:28:30 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	216164 kb
Host	smart-2b84ffef-e022-4db4-8751-d937c26882f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313371256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2313371256
Directory	/workspace/22.spi_device_mailbox/latest

Test location	/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.94687665
Short name	T255
Test name
Test status
Simulation time	1101894954 ps
CPU time	5.86 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:28:35 PM PDT 24
Peak memory	217684 kb
Host	smart-c2b72d2e-2ce9-472d-a85f-fd8fdc1ea054
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94687665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.94687665
Directory	/workspace/22.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/22.spi_device_pass_cmd_filtering.1690543372
Short name	T207
Test name
Test status
Simulation time	386046410 ps
CPU time	6.35 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	229948 kb
Host	smart-dd29c8d5-f432-4a5c-a8f7-ce4dfa95ebec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1690543372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1690543372
Directory	/workspace/22.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/22.spi_device_read_buffer_direct.4052307150
Short name	T629
Test name
Test status
Simulation time	1738112602 ps
CPU time	3.64 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:28:34 PM PDT 24
Peak memory	219004 kb
Host	smart-aba8de65-0b7a-49e8-8c1e-5ae8e3b3d32e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4052307150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir ect.4052307150
Directory	/workspace/22.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/22.spi_device_stress_all.559942377
Short name	T627
Test name
Test status
Simulation time	3436147204 ps
CPU time	25.9 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	224140 kb
Host	smart-8514ea39-36d0-4ed9-9f98-616f2629cc09
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559942377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres s_all.559942377
Directory	/workspace/22.spi_device_stress_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_all.1999530414
Short name	T851
Test name
Test status
Simulation time	4251723159 ps
CPU time	8.61 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	216332 kb
Host	smart-4013aaa5-17eb-4a5c-af0c-a3ccf126af90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999530414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1999530414
Directory	/workspace/22.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1209256992
Short name	T539
Test name
Test status
Simulation time	7689765192 ps
CPU time	8.09 seconds
Started	May 14 01:28:27 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	216004 kb
Host	smart-4a0af772-decb-4170-8ffe-8a18629c8e89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209256992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1209256992
Directory	/workspace/22.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_rw.1739863755
Short name	T881
Test name
Test status
Simulation time	156879045 ps
CPU time	1.02 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:28:34 PM PDT 24
Peak memory	206944 kb
Host	smart-4bd67930-7f75-470b-b69c-62240598a0f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739863755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1739863755
Directory	/workspace/22.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_sts_read.3227665085
Short name	T719
Test name
Test status
Simulation time	69211215 ps
CPU time	0.91 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:30 PM PDT 24
Peak memory	206048 kb
Host	smart-d88c4002-3034-4e9e-b9f2-3b09d4bb6b05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227665085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3227665085
Directory	/workspace/22.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/22.spi_device_upload.601132218
Short name	T11
Test name
Test status
Simulation time	469223910 ps
CPU time	4.32 seconds
Started	May 14 01:28:29 PM PDT 24
Finished	May 14 01:28:38 PM PDT 24
Peak memory	219532 kb
Host	smart-17cff5c7-6599-4375-b18b-37d30c8514ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601132218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.601132218
Directory	/workspace/22.spi_device_upload/latest

Test location	/workspace/coverage/default/23.spi_device_alert_test.3343173596
Short name	T928
Test name
Test status
Simulation time	19866867 ps
CPU time	0.7 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	205224 kb
Host	smart-ea1dd1bf-50cd-4fcb-8da7-5209e4a1bd4b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343173596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test. 3343173596
Directory	/workspace/23.spi_device_alert_test/latest

Test location	/workspace/coverage/default/23.spi_device_cfg_cmd.252708246
Short name	T831
Test name
Test status
Simulation time	208840925 ps
CPU time	4.28 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	233712 kb
Host	smart-353ff064-7669-4584-add4-d31d3d7178fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252708246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.252708246
Directory	/workspace/23.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/23.spi_device_csb_read.3574407070
Short name	T840
Test name
Test status
Simulation time	22033765 ps
CPU time	0.8 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:38 PM PDT 24
Peak memory	206756 kb
Host	smart-49fc73b6-b840-42b0-97b4-3d4bf8983d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574407070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3574407070
Directory	/workspace/23.spi_device_csb_read/latest

Test location	/workspace/coverage/default/23.spi_device_flash_all.4275538112
Short name	T423
Test name
Test status
Simulation time	59829138 ps
CPU time	1.04 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	215964 kb
Host	smart-b620e29d-87af-49c9-9e43-9dc2a02a1461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275538112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4275538112
Directory	/workspace/23.spi_device_flash_all/latest

Test location	/workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1579712271
Short name	T246
Test name
Test status
Simulation time	9043388696 ps
CPU time	55.98 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	252164 kb
Host	smart-cc06fcbf-c387-4151-b8a4-e06f8a757615
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579712271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl e.1579712271
Directory	/workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/23.spi_device_intercept.1551466509
Short name	T796
Test name
Test status
Simulation time	398669964 ps
CPU time	6.25 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	233908 kb
Host	smart-854b93b8-bbe3-4864-a06a-ef4a07fb838c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551466509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1551466509
Directory	/workspace/23.spi_device_intercept/latest

Test location	/workspace/coverage/default/23.spi_device_mailbox.4098198647
Short name	T727
Test name
Test status
Simulation time	1531363079 ps
CPU time	9.07 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:47 PM PDT 24
Peak memory	223632 kb
Host	smart-8f01e370-ed7d-4cc3-a2dc-902111915a9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098198647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4098198647
Directory	/workspace/23.spi_device_mailbox/latest

Test location	/workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2918054570
Short name	T577
Test name
Test status
Simulation time	3428262901 ps
CPU time	8.44 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	233992 kb
Host	smart-7ac25865-8e2c-4e78-9d7e-430b15277b3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918054570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa p.2918054570
Directory	/workspace/23.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/23.spi_device_pass_cmd_filtering.4034554609
Short name	T687
Test name
Test status
Simulation time	2119825606 ps
CPU time	6.18 seconds
Started	May 14 01:28:30 PM PDT 24
Finished	May 14 01:28:42 PM PDT 24
Peak memory	233176 kb
Host	smart-fba0e2a3-ecc2-49cd-a8c7-735780d5625f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034554609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4034554609
Directory	/workspace/23.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/23.spi_device_read_buffer_direct.1536933732
Short name	T590
Test name
Test status
Simulation time	130188955 ps
CPU time	4.27 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	222664 kb
Host	smart-597089a3-32e4-4792-acec-273418a788ff
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1536933732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir ect.1536933732
Directory	/workspace/23.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/23.spi_device_stress_all.2540319246
Short name	T802
Test name
Test status
Simulation time	3225831425 ps
CPU time	56.24 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:29:35 PM PDT 24
Peak memory	249244 kb
Host	smart-1a6967df-afd7-4179-9580-792e5aac70e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540319246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre ss_all.2540319246
Directory	/workspace/23.spi_device_stress_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3991812974
Short name	T875
Test name
Test status
Simulation time	1281106863 ps
CPU time	6.15 seconds
Started	May 14 01:28:28 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	215996 kb
Host	smart-922b42d4-695f-4b89-a06b-e052574b82c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991812974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3991812974
Directory	/workspace/23.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_rw.2297373404
Short name	T483
Test name
Test status
Simulation time	99708253 ps
CPU time	1.4 seconds
Started	May 14 01:28:25 PM PDT 24
Finished	May 14 01:28:29 PM PDT 24
Peak memory	216120 kb
Host	smart-5808980f-de21-463f-9743-73ff5f4f5353
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297373404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2297373404
Directory	/workspace/23.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_sts_read.335592787
Short name	T61
Test name
Test status
Simulation time	12011084 ps
CPU time	0.74 seconds
Started	May 14 01:28:26 PM PDT 24
Finished	May 14 01:28:30 PM PDT 24
Peak memory	205500 kb
Host	smart-4df82b41-5652-4cd2-aaec-0587ffb6904e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335592787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.335592787
Directory	/workspace/23.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/23.spi_device_upload.886726596
Short name	T64
Test name
Test status
Simulation time	42540389289 ps
CPU time	32.36 seconds
Started	May 14 01:28:34 PM PDT 24
Finished	May 14 01:29:12 PM PDT 24
Peak memory	239904 kb
Host	smart-5e29a6a0-a210-47ea-a68f-aea7c0a3aa92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886726596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.886726596
Directory	/workspace/23.spi_device_upload/latest

Test location	/workspace/coverage/default/24.spi_device_alert_test.1919843860
Short name	T893
Test name
Test status
Simulation time	12711316 ps
CPU time	0.75 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:38 PM PDT 24
Peak memory	204600 kb
Host	smart-1cc29262-a62b-419e-9ec2-236ac8864362
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919843860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test. 1919843860
Directory	/workspace/24.spi_device_alert_test/latest

Test location	/workspace/coverage/default/24.spi_device_cfg_cmd.3954260673
Short name	T618
Test name
Test status
Simulation time	2739452602 ps
CPU time	7.51 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:28:50 PM PDT 24
Peak memory	219704 kb
Host	smart-cbe5476f-840f-4ff2-83e0-9b77052b97f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954260673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3954260673
Directory	/workspace/24.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/24.spi_device_csb_read.2935095395
Short name	T683
Test name
Test status
Simulation time	112707129 ps
CPU time	0.79 seconds
Started	May 14 01:28:34 PM PDT 24
Finished	May 14 01:28:40 PM PDT 24
Peak memory	206476 kb
Host	smart-c3abcf2d-a6bb-4d50-bcac-cf5551ed4264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935095395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2935095395
Directory	/workspace/24.spi_device_csb_read/latest

Test location	/workspace/coverage/default/24.spi_device_flash_all.1479971971
Short name	T698
Test name
Test status
Simulation time	27700332026 ps
CPU time	190.6 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:31:47 PM PDT 24
Peak memory	249576 kb
Host	smart-1aa8a311-edb0-4484-9909-8480f24648f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479971971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1479971971
Directory	/workspace/24.spi_device_flash_all/latest

Test location	/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1915897137
Short name	T212
Test name
Test status
Simulation time	175124485157 ps
CPU time	357.53 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:34:39 PM PDT 24
Peak memory	265420 kb
Host	smart-a9ee54c2-8f1c-4611-bca4-174814533b15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915897137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl e.1915897137
Directory	/workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/24.spi_device_intercept.1144707982
Short name	T778
Test name
Test status
Simulation time	2489035701 ps
CPU time	18.88 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:56 PM PDT 24
Peak memory	219400 kb
Host	smart-4f6addad-860a-4611-bff3-bcc4f52a3d0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144707982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1144707982
Directory	/workspace/24.spi_device_intercept/latest

Test location	/workspace/coverage/default/24.spi_device_mailbox.3059631200
Short name	T930
Test name
Test status
Simulation time	3137859995 ps
CPU time	45.44 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	216224 kb
Host	smart-a772b6b7-51c7-417a-bd11-8cebb9a1c52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059631200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3059631200
Directory	/workspace/24.spi_device_mailbox/latest

Test location	/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1340553784
Short name	T31
Test name
Test status
Simulation time	1746108337 ps
CPU time	9.61 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:46 PM PDT 24
Peak memory	249052 kb
Host	smart-7c4d1ae3-5042-4aac-9208-e75dcd7e216f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340553784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa p.1340553784
Directory	/workspace/24.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/24.spi_device_pass_cmd_filtering.1910741307
Short name	T343
Test name
Test status
Simulation time	35049225 ps
CPU time	2.32 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:40 PM PDT 24
Peak memory	220976 kb
Host	smart-70acdc97-9516-4cb6-aa00-ea035a8e5cce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910741307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1910741307
Directory	/workspace/24.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/24.spi_device_read_buffer_direct.249445021
Short name	T947
Test name
Test status
Simulation time	500305317 ps
CPU time	5.12 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	219608 kb
Host	smart-be586975-30d3-464f-8a47-8fd728e9e702
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=249445021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire ct.249445021
Directory	/workspace/24.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/24.spi_device_stress_all.3947736733
Short name	T697
Test name
Test status
Simulation time	164407171 ps
CPU time	0.97 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	206864 kb
Host	smart-33de096e-5ace-49dc-9792-25789103dc40
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947736733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre ss_all.3947736733
Directory	/workspace/24.spi_device_stress_all/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_all.1436913721
Short name	T819
Test name
Test status
Simulation time	12098670080 ps
CPU time	14.79 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	216204 kb
Host	smart-b055a3ef-db2f-4b71-9513-f51f2ca64969
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436913721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1436913721
Directory	/workspace/24.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3805455267
Short name	T593
Test name
Test status
Simulation time	4823764619 ps
CPU time	15.6 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	216020 kb
Host	smart-741944f9-c81b-4f47-8bba-4b3c866ea6af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805455267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3805455267
Directory	/workspace/24.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_rw.444510168
Short name	T844
Test name
Test status
Simulation time	74927234 ps
CPU time	0.85 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:28:40 PM PDT 24
Peak memory	205672 kb
Host	smart-15868571-ad89-4ff8-b5f2-6600e0944ead
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444510168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.444510168
Directory	/workspace/24.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_sts_read.938261005
Short name	T935
Test name
Test status
Simulation time	36792079 ps
CPU time	0.7 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	205436 kb
Host	smart-9df8a0e7-7ac8-4824-8694-bf227de55b13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938261005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.938261005
Directory	/workspace/24.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/24.spi_device_upload.323182102
Short name	T783
Test name
Test status
Simulation time	5646462927 ps
CPU time	7.54 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:45 PM PDT 24
Peak memory	219064 kb
Host	smart-46818d93-a2b5-4bac-a7ac-645c9d5745d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323182102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.323182102
Directory	/workspace/24.spi_device_upload/latest

Test location	/workspace/coverage/default/25.spi_device_alert_test.3464042103
Short name	T910
Test name
Test status
Simulation time	183934835 ps
CPU time	0.73 seconds
Started	May 14 01:28:37 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	205240 kb
Host	smart-c1828d00-5f24-4300-9714-c85b5302d755
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464042103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test. 3464042103
Directory	/workspace/25.spi_device_alert_test/latest

Test location	/workspace/coverage/default/25.spi_device_cfg_cmd.3483342888
Short name	T515
Test name
Test status
Simulation time	2330115311 ps
CPU time	5.14 seconds
Started	May 14 01:28:36 PM PDT 24
Finished	May 14 01:28:45 PM PDT 24
Peak memory	218468 kb
Host	smart-d7da063d-8eb5-4579-a7e0-f498342fb5e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483342888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3483342888
Directory	/workspace/25.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/25.spi_device_csb_read.850287249
Short name	T600
Test name
Test status
Simulation time	18498831 ps
CPU time	0.89 seconds
Started	May 14 01:28:30 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	206484 kb
Host	smart-8165df8b-d2a5-446f-bbc1-e3238d30bef9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850287249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.850287249
Directory	/workspace/25.spi_device_csb_read/latest

Test location	/workspace/coverage/default/25.spi_device_flash_all.1441062643
Short name	T285
Test name
Test status
Simulation time	3175940232 ps
CPU time	31.04 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:29:10 PM PDT 24
Peak memory	249028 kb
Host	smart-e79bed5b-6c11-40d8-935f-703f2256fa0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441062643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1441062643
Directory	/workspace/25.spi_device_flash_all/latest

Test location	/workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.216060215
Short name	T601
Test name
Test status
Simulation time	17082955410 ps
CPU time	117.15 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:30:40 PM PDT 24
Peak memory	254528 kb
Host	smart-2096dd2e-09e1-48c2-b88e-19a56766e349
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216060215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle .216060215
Directory	/workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/25.spi_device_intercept.4096498068
Short name	T551
Test name
Test status
Simulation time	194939217 ps
CPU time	2.66 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:40 PM PDT 24
Peak memory	218300 kb
Host	smart-b77cfa63-42e0-4487-8f93-53e3d6484038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096498068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4096498068
Directory	/workspace/25.spi_device_intercept/latest

Test location	/workspace/coverage/default/25.spi_device_mailbox.3497906581
Short name	T13
Test name
Test status
Simulation time	1833553658 ps
CPU time	26.61 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:29:04 PM PDT 24
Peak memory	218328 kb
Host	smart-bc2abd52-968f-4a0e-8452-cf7092e19b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497906581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3497906581
Directory	/workspace/25.spi_device_mailbox/latest

Test location	/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2015519513
Short name	T764
Test name
Test status
Simulation time	1032021502 ps
CPU time	3.29 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	217520 kb
Host	smart-cde2f840-d617-4c64-8397-0882a35588fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015519513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa p.2015519513
Directory	/workspace/25.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/25.spi_device_pass_cmd_filtering.1623294612
Short name	T290
Test name
Test status
Simulation time	1102193681 ps
CPU time	8.3 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:46 PM PDT 24
Peak memory	218688 kb
Host	smart-4afb4ff8-33bb-4cd8-a576-83cfe5a942e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623294612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1623294612
Directory	/workspace/25.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/25.spi_device_read_buffer_direct.2597272721
Short name	T378
Test name
Test status
Simulation time	6263028433 ps
CPU time	11.33 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	219168 kb
Host	smart-d661f8ed-45f3-435c-aaac-70a6b83d4d54
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2597272721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir ect.2597272721
Directory	/workspace/25.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_all.1176760417
Short name	T89
Test name
Test status
Simulation time	1481847020 ps
CPU time	5.92 seconds
Started	May 14 01:28:32 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	217884 kb
Host	smart-53a7d465-94d3-4887-aab1-4a507a8c1088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176760417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1176760417
Directory	/workspace/25.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3235251159
Short name	T550
Test name
Test status
Simulation time	504426737 ps
CPU time	3.1 seconds
Started	May 14 01:28:34 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	216264 kb
Host	smart-094e2bf4-fa91-4f7d-b6d6-6f12920a5bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235251159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3235251159
Directory	/workspace/25.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_rw.1968044186
Short name	T7
Test name
Test status
Simulation time	29439453 ps
CPU time	1.32 seconds
Started	May 14 01:28:30 PM PDT 24
Finished	May 14 01:28:37 PM PDT 24
Peak memory	216040 kb
Host	smart-ff462972-7a7b-431b-9deb-a6434ea36a04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968044186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1968044186
Directory	/workspace/25.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_sts_read.3157325398
Short name	T670
Test name
Test status
Simulation time	20156299 ps
CPU time	0.75 seconds
Started	May 14 01:28:31 PM PDT 24
Finished	May 14 01:28:38 PM PDT 24
Peak memory	205660 kb
Host	smart-420301a7-1e96-43b5-9b81-16e5cce70afc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157325398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3157325398
Directory	/workspace/25.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/25.spi_device_upload.3881441759
Short name	T692
Test name
Test status
Simulation time	1996299120 ps
CPU time	13.83 seconds
Started	May 14 01:28:33 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	232248 kb
Host	smart-7be36ee2-4bc8-4671-996d-63c5388662d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881441759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3881441759
Directory	/workspace/25.spi_device_upload/latest

Test location	/workspace/coverage/default/26.spi_device_alert_test.2876726099
Short name	T488
Test name
Test status
Simulation time	11599487 ps
CPU time	0.72 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	204616 kb
Host	smart-7f71243e-a118-419f-85cc-2ee4d98ddd39
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876726099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test. 2876726099
Directory	/workspace/26.spi_device_alert_test/latest

Test location	/workspace/coverage/default/26.spi_device_cfg_cmd.1000728711
Short name	T556
Test name
Test status
Simulation time	8473008869 ps
CPU time	5.95 seconds
Started	May 14 01:28:37 PM PDT 24
Finished	May 14 01:28:47 PM PDT 24
Peak memory	234728 kb
Host	smart-204f2aec-0033-4258-9c70-9368ad5724b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000728711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1000728711
Directory	/workspace/26.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/26.spi_device_csb_read.1608673999
Short name	T871
Test name
Test status
Simulation time	32695615 ps
CPU time	0.83 seconds
Started	May 14 01:28:42 PM PDT 24
Finished	May 14 01:28:45 PM PDT 24
Peak memory	206420 kb
Host	smart-357d17f8-c940-4eff-bfc8-33b0c7ff3ddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608673999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1608673999
Directory	/workspace/26.spi_device_csb_read/latest

Test location	/workspace/coverage/default/26.spi_device_flash_all.783386428
Short name	T239
Test name
Test status
Simulation time	36721739182 ps
CPU time	309.71 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:33:51 PM PDT 24
Peak memory	251616 kb
Host	smart-0d29f265-58cd-443e-a3e0-14b16c486c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783386428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.783386428
Directory	/workspace/26.spi_device_flash_all/latest

Test location	/workspace/coverage/default/26.spi_device_flash_and_tpm.315091534
Short name	T585
Test name
Test status
Simulation time	84137821227 ps
CPU time	225.95 seconds
Started	May 14 01:28:42 PM PDT 24
Finished	May 14 01:32:30 PM PDT 24
Peak memory	249004 kb
Host	smart-52fd4b3f-bdd4-49ed-b6d1-10bd7d8c817e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315091534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.315091534
Directory	/workspace/26.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.398587636
Short name	T216
Test name
Test status
Simulation time	25269716092 ps
CPU time	77.31 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:29:59 PM PDT 24
Peak memory	252196 kb
Host	smart-8b85be3a-ca2e-4f83-bbc8-631da5b449e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398587636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle .398587636
Directory	/workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/26.spi_device_flash_mode.2621710863
Short name	T329
Test name
Test status
Simulation time	245152695 ps
CPU time	5.03 seconds
Started	May 14 01:28:43 PM PDT 24
Finished	May 14 01:28:50 PM PDT 24
Peak memory	240724 kb
Host	smart-fe7044e6-f000-42e9-beac-f00620efdda6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621710863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2621710863
Directory	/workspace/26.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/26.spi_device_intercept.1527882630
Short name	T537
Test name
Test status
Simulation time	298341338 ps
CPU time	5.97 seconds
Started	May 14 01:28:42 PM PDT 24
Finished	May 14 01:28:50 PM PDT 24
Peak memory	234192 kb
Host	smart-a95dd2bd-fdeb-41cd-bd2a-fdf93f220474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527882630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1527882630
Directory	/workspace/26.spi_device_intercept/latest

Test location	/workspace/coverage/default/26.spi_device_mailbox.3218277489
Short name	T574
Test name
Test status
Simulation time	14681255805 ps
CPU time	130.84 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:30:53 PM PDT 24
Peak memory	234276 kb
Host	smart-34c001e5-f8e0-4d54-8f6f-7c6767b15387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218277489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3218277489
Directory	/workspace/26.spi_device_mailbox/latest

Test location	/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4206495621
Short name	T168
Test name
Test status
Simulation time	413967339 ps
CPU time	6.78 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:28:48 PM PDT 24
Peak memory	222808 kb
Host	smart-d9543bd0-ce7b-4aa5-a093-710b2bf56946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206495621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa p.4206495621
Directory	/workspace/26.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/26.spi_device_pass_cmd_filtering.3735226800
Short name	T954
Test name
Test status
Simulation time	2045687653 ps
CPU time	5.54 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:28:48 PM PDT 24
Peak memory	233556 kb
Host	smart-3de593de-8b3e-4dfa-a87b-546db2ab4b76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735226800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3735226800
Directory	/workspace/26.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/26.spi_device_read_buffer_direct.574202838
Short name	T380
Test name
Test status
Simulation time	682660468 ps
CPU time	6.56 seconds
Started	May 14 01:28:41 PM PDT 24
Finished	May 14 01:28:50 PM PDT 24
Peak memory	219556 kb
Host	smart-9feb3bbc-42d0-4aea-a454-5cc42f9c20bd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=574202838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire ct.574202838
Directory	/workspace/26.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/26.spi_device_stress_all.464544796
Short name	T516
Test name
Test status
Simulation time	637567294605 ps
CPU time	622.73 seconds
Started	May 14 01:28:37 PM PDT 24
Finished	May 14 01:39:04 PM PDT 24
Peak memory	271576 kb
Host	smart-0c16cdd1-66be-4686-95e5-af22192d0714
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464544796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres s_all.464544796
Directory	/workspace/26.spi_device_stress_all/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_all.1742155754
Short name	T339
Test name
Test status
Simulation time	3302218742 ps
CPU time	18.61 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	216196 kb
Host	smart-6ea8cb63-48ea-43c2-b08e-f8632e0e37db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742155754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1742155754
Directory	/workspace/26.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2334885866
Short name	T849
Test name
Test status
Simulation time	977459446 ps
CPU time	3.91 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:28:46 PM PDT 24
Peak memory	216036 kb
Host	smart-e9b5a048-1b62-4662-95c6-cc5b0ebd3234
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334885866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2334885866
Directory	/workspace/26.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_rw.1447063167
Short name	T619
Test name
Test status
Simulation time	38045133 ps
CPU time	0.74 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:28:44 PM PDT 24
Peak memory	205464 kb
Host	smart-79de2e43-6128-4dad-a2d6-d49b8cbd57d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447063167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1447063167
Directory	/workspace/26.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_sts_read.539918789
Short name	T917
Test name
Test status
Simulation time	113103154 ps
CPU time	0.92 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	205704 kb
Host	smart-fb1d26ca-f8df-4971-950e-046b0f7f49de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539918789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.539918789
Directory	/workspace/26.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/26.spi_device_upload.696589887
Short name	T747
Test name
Test status
Simulation time	2860121187 ps
CPU time	18.29 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:29:00 PM PDT 24
Peak memory	239308 kb
Host	smart-9a015341-7c45-41cb-8673-3bfb275b2129
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696589887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.696589887
Directory	/workspace/26.spi_device_upload/latest

Test location	/workspace/coverage/default/27.spi_device_alert_test.1878863079
Short name	T361
Test name
Test status
Simulation time	24471479 ps
CPU time	0.74 seconds
Started	May 14 01:28:41 PM PDT 24
Finished	May 14 01:28:44 PM PDT 24
Peak memory	204632 kb
Host	smart-0a050252-3519-4466-ab81-d08ed199cb27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878863079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test. 1878863079
Directory	/workspace/27.spi_device_alert_test/latest

Test location	/workspace/coverage/default/27.spi_device_cfg_cmd.1130536899
Short name	T759
Test name
Test status
Simulation time	39052811 ps
CPU time	2.52 seconds
Started	May 14 01:28:44 PM PDT 24
Finished	May 14 01:28:47 PM PDT 24
Peak memory	233236 kb
Host	smart-b7f558a3-90e5-473d-94d0-adebf558a696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130536899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1130536899
Directory	/workspace/27.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/27.spi_device_csb_read.3732878792
Short name	T594
Test name
Test status
Simulation time	190728099 ps
CPU time	0.82 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	205420 kb
Host	smart-3373ecca-cdbf-4c85-a519-2ca57c39d74b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732878792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3732878792
Directory	/workspace/27.spi_device_csb_read/latest

Test location	/workspace/coverage/default/27.spi_device_flash_all.1434376117
Short name	T211
Test name
Test status
Simulation time	32082305549 ps
CPU time	244.63 seconds
Started	May 14 01:28:37 PM PDT 24
Finished	May 14 01:32:45 PM PDT 24
Peak memory	257192 kb
Host	smart-e8d40811-a59d-4e17-9c07-a037ef6578bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434376117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1434376117
Directory	/workspace/27.spi_device_flash_all/latest

Test location	/workspace/coverage/default/27.spi_device_flash_and_tpm.586908627
Short name	T245
Test name
Test status
Simulation time	2337680324 ps
CPU time	57.63 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:29:40 PM PDT 24
Peak memory	254976 kb
Host	smart-292e8a02-2dd4-4269-b5a4-52ce7789b4f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586908627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.586908627
Directory	/workspace/27.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1907381796
Short name	T843
Test name
Test status
Simulation time	187635080651 ps
CPU time	659.71 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:39:43 PM PDT 24
Peak memory	248976 kb
Host	smart-fd211be0-3963-4811-96ff-5365370356f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907381796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl e.1907381796
Directory	/workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/27.spi_device_flash_mode.565661015
Short name	T578
Test name
Test status
Simulation time	573125272 ps
CPU time	10.47 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	232612 kb
Host	smart-c8f5d1c2-ef17-486f-b6ff-4e4b09806739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=565661015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.565661015
Directory	/workspace/27.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/27.spi_device_intercept.3783902916
Short name	T760
Test name
Test status
Simulation time	1778932977 ps
CPU time	2.53 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:28:44 PM PDT 24
Peak memory	218460 kb
Host	smart-03e69a25-1a14-45f6-b061-b4a88a291b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783902916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3783902916
Directory	/workspace/27.spi_device_intercept/latest

Test location	/workspace/coverage/default/27.spi_device_mailbox.2223383987
Short name	T752
Test name
Test status
Simulation time	6261469888 ps
CPU time	30.54 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:29:12 PM PDT 24
Peak memory	231884 kb
Host	smart-a3cc2070-94f8-4d02-910b-dfdd3d598b65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223383987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2223383987
Directory	/workspace/27.spi_device_mailbox/latest

Test location	/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3312123982
Short name	T767
Test name
Test status
Simulation time	128312305 ps
CPU time	2.43 seconds
Started	May 14 01:28:37 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	218556 kb
Host	smart-5ef5eaaf-503a-47a4-9165-1db4061f0830
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312123982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa p.3312123982
Directory	/workspace/27.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/27.spi_device_pass_cmd_filtering.2805354817
Short name	T731
Test name
Test status
Simulation time	740696663 ps
CPU time	6.7 seconds
Started	May 14 01:28:42 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	236316 kb
Host	smart-f408af49-7221-430d-83e4-fde2f7d1a045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805354817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2805354817
Directory	/workspace/27.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/27.spi_device_read_buffer_direct.1244547199
Short name	T141
Test name
Test status
Simulation time	107755008 ps
CPU time	4.28 seconds
Started	May 14 01:28:42 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	220140 kb
Host	smart-fcd9802f-0c6c-4589-846b-d757323228dc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1244547199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir ect.1244547199
Directory	/workspace/27.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_all.4029413140
Short name	T337
Test name
Test status
Simulation time	11759821377 ps
CPU time	60.15 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	216176 kb
Host	smart-9b6b5d39-de09-4fff-a36a-1948db3076cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029413140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4029413140
Directory	/workspace/27.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2134121556
Short name	T373
Test name
Test status
Simulation time	891617492 ps
CPU time	4.69 seconds
Started	May 14 01:28:43 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	215968 kb
Host	smart-4e4a4ce3-4427-455a-9ec2-b230dc132f82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134121556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2134121556
Directory	/workspace/27.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_rw.744191891
Short name	T874
Test name
Test status
Simulation time	167265934 ps
CPU time	2.18 seconds
Started	May 14 01:28:38 PM PDT 24
Finished	May 14 01:28:44 PM PDT 24
Peak memory	216164 kb
Host	smart-7db02a4e-6759-4219-a7d0-3493db41acc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744191891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.744191891
Directory	/workspace/27.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_sts_read.2067728110
Short name	T737
Test name
Test status
Simulation time	14964053 ps
CPU time	0.72 seconds
Started	May 14 01:28:39 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	205556 kb
Host	smart-5dd31869-f501-43c7-85ab-a4896a97184c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067728110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2067728110
Directory	/workspace/27.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/27.spi_device_upload.1185258639
Short name	T751
Test name
Test status
Simulation time	79330438787 ps
CPU time	44.8 seconds
Started	May 14 01:28:43 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	226148 kb
Host	smart-2810fd8c-4743-41bc-bd28-b97d5ed8e3a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185258639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1185258639
Directory	/workspace/27.spi_device_upload/latest

Test location	/workspace/coverage/default/28.spi_device_alert_test.2709904326
Short name	T860
Test name
Test status
Simulation time	36520764 ps
CPU time	0.72 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	205244 kb
Host	smart-63f59209-cea8-4df5-9670-cf14391788cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709904326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test. 2709904326
Directory	/workspace/28.spi_device_alert_test/latest

Test location	/workspace/coverage/default/28.spi_device_cfg_cmd.3866605570
Short name	T91
Test name
Test status
Simulation time	551490820 ps
CPU time	3.99 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:54 PM PDT 24
Peak memory	233736 kb
Host	smart-bcb39a77-c6c1-4b72-acda-04f0ba09c6f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866605570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3866605570
Directory	/workspace/28.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/28.spi_device_csb_read.1168851852
Short name	T542
Test name
Test status
Simulation time	19615475 ps
CPU time	0.84 seconds
Started	May 14 01:28:40 PM PDT 24
Finished	May 14 01:28:43 PM PDT 24
Peak memory	206436 kb
Host	smart-ea476f20-d031-4eb8-9972-7360ad20f421
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168851852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1168851852
Directory	/workspace/28.spi_device_csb_read/latest

Test location	/workspace/coverage/default/28.spi_device_flash_all.858782008
Short name	T949
Test name
Test status
Simulation time	6419158279 ps
CPU time	49.56 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	240732 kb
Host	smart-43eef1df-277a-41a7-b8f1-1f97ecadbf22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858782008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.858782008
Directory	/workspace/28.spi_device_flash_all/latest

Test location	/workspace/coverage/default/28.spi_device_flash_and_tpm.1161914007
Short name	T442
Test name
Test status
Simulation time	20548183412 ps
CPU time	106.72 seconds
Started	May 14 01:28:49 PM PDT 24
Finished	May 14 01:30:38 PM PDT 24
Peak memory	252260 kb
Host	smart-8f6a80ad-7e8e-44a4-8421-807295c34cb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161914007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1161914007
Directory	/workspace/28.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.466925651
Short name	T240
Test name
Test status
Simulation time	5722082660 ps
CPU time	55.68 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:29:44 PM PDT 24
Peak memory	249084 kb
Host	smart-2d5b4b1e-2a64-4bf4-b59d-fb4f3fa2899a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466925651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle .466925651
Directory	/workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/28.spi_device_flash_mode.4034130301
Short name	T696
Test name
Test status
Simulation time	580780923 ps
CPU time	7.46 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:58 PM PDT 24
Peak memory	232492 kb
Host	smart-bae029bc-aefb-491e-b01d-156674521b51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034130301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4034130301
Directory	/workspace/28.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/28.spi_device_intercept.3945503915
Short name	T678
Test name
Test status
Simulation time	272534453 ps
CPU time	5.59 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:55 PM PDT 24
Peak memory	218632 kb
Host	smart-27c0c06f-88c9-45c0-b376-7a70d1a8efd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945503915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3945503915
Directory	/workspace/28.spi_device_intercept/latest

Test location	/workspace/coverage/default/28.spi_device_mailbox.1080989728
Short name	T824
Test name
Test status
Simulation time	2459625145 ps
CPU time	36.01 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:29:26 PM PDT 24
Peak memory	236324 kb
Host	smart-afb47dd8-1195-4554-b91b-ef044d546214
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080989728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1080989728
Directory	/workspace/28.spi_device_mailbox/latest

Test location	/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1166331205
Short name	T318
Test name
Test status
Simulation time	6773632878 ps
CPU time	16.69 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	233044 kb
Host	smart-979feec7-d6c5-4dee-aa26-62c8aa07691b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166331205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa p.1166331205
Directory	/workspace/28.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/28.spi_device_pass_cmd_filtering.1678920269
Short name	T159
Test name
Test status
Simulation time	86794695 ps
CPU time	2.48 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	218820 kb
Host	smart-28c6c096-e281-4c5b-be9b-c27bb840d899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678920269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1678920269
Directory	/workspace/28.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/28.spi_device_read_buffer_direct.1404401374
Short name	T606
Test name
Test status
Simulation time	620775261 ps
CPU time	5.65 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	222896 kb
Host	smart-20220452-3955-4b95-b123-ec0d30409b10
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1404401374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir ect.1404401374
Directory	/workspace/28.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/28.spi_device_stress_all.10506615
Short name	T503
Test name
Test status
Simulation time	72796672 ps
CPU time	1.25 seconds
Started	May 14 01:28:49 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	206884 kb
Host	smart-37085ae1-9cd1-4ccf-bdec-1a774b86809e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress _all.10506615
Directory	/workspace/28.spi_device_stress_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_all.4244182139
Short name	T815
Test name
Test status
Simulation time	1402914512 ps
CPU time	14.89 seconds
Started	May 14 01:28:44 PM PDT 24
Finished	May 14 01:29:00 PM PDT 24
Peak memory	216048 kb
Host	smart-c9e6ea11-058f-4847-89f6-087d49263fc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244182139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4244182139
Directory	/workspace/28.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3746144517
Short name	T392
Test name
Test status
Simulation time	1718021699 ps
CPU time	5.45 seconds
Started	May 14 01:28:42 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	215936 kb
Host	smart-e86817be-4d7b-4597-8dea-31a23615a151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746144517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3746144517
Directory	/workspace/28.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_rw.4027300096
Short name	T407
Test name
Test status
Simulation time	26259723 ps
CPU time	1.1 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:28:48 PM PDT 24
Peak memory	206944 kb
Host	smart-26803078-92c5-42fd-9793-d3c94128fb9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027300096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4027300096
Directory	/workspace/28.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_sts_read.3226330484
Short name	T490
Test name
Test status
Simulation time	35794455 ps
CPU time	0.87 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	205648 kb
Host	smart-6887f257-992f-4ea2-9e39-460b06b6b0ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226330484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3226330484
Directory	/workspace/28.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/28.spi_device_upload.2302962993
Short name	T888
Test name
Test status
Simulation time	8817735834 ps
CPU time	33.61 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	238372 kb
Host	smart-a0556889-db8f-48f3-8828-ef61e2103c47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302962993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2302962993
Directory	/workspace/28.spi_device_upload/latest

Test location	/workspace/coverage/default/29.spi_device_alert_test.4052711154
Short name	T10
Test name
Test status
Simulation time	22679844 ps
CPU time	0.74 seconds
Started	May 14 01:28:49 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	205284 kb
Host	smart-7d50b7dc-8696-4f56-9139-5ee25c9e6e19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052711154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test. 4052711154
Directory	/workspace/29.spi_device_alert_test/latest

Test location	/workspace/coverage/default/29.spi_device_cfg_cmd.3174374594
Short name	T312
Test name
Test status
Simulation time	12724434457 ps
CPU time	10.88 seconds
Started	May 14 01:28:52 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	219492 kb
Host	smart-8a2e766b-daab-453a-87c0-e43162d41edb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174374594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3174374594
Directory	/workspace/29.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/29.spi_device_csb_read.2828451702
Short name	T23
Test name
Test status
Simulation time	35408091 ps
CPU time	0.77 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	205392 kb
Host	smart-dc1c84d6-7e70-4fc3-9242-617f0639e0a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828451702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2828451702
Directory	/workspace/29.spi_device_csb_read/latest

Test location	/workspace/coverage/default/29.spi_device_flash_all.3662676738
Short name	T950
Test name
Test status
Simulation time	50807311892 ps
CPU time	85.1 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:30:14 PM PDT 24
Peak memory	232536 kb
Host	smart-6385568a-ab62-4428-bea8-7156ea4ccaa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662676738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3662676738
Directory	/workspace/29.spi_device_flash_all/latest

Test location	/workspace/coverage/default/29.spi_device_flash_and_tpm.309097230
Short name	T230
Test name
Test status
Simulation time	7016360451 ps
CPU time	84.92 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:30:13 PM PDT 24
Peak memory	254828 kb
Host	smart-53d523e3-d585-4181-8845-6b7b4aec93a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309097230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.309097230
Directory	/workspace/29.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.911298630
Short name	T55
Test name
Test status
Simulation time	6663536818 ps
CPU time	138.31 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:31:09 PM PDT 24
Peak memory	254568 kb
Host	smart-59977169-f264-4747-b140-cad3135b7a6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=911298630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle .911298630
Directory	/workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/29.spi_device_flash_mode.903031380
Short name	T140
Test name
Test status
Simulation time	2003275452 ps
CPU time	11.23 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:28:57 PM PDT 24
Peak memory	224292 kb
Host	smart-cff13700-43f1-4ebd-b45f-93ddb013f0e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903031380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.903031380
Directory	/workspace/29.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/29.spi_device_intercept.3311486400
Short name	T599
Test name
Test status
Simulation time	810593963 ps
CPU time	4.26 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:55 PM PDT 24
Peak memory	217596 kb
Host	smart-23594f89-00c8-4a18-9724-d4b9bc21fd04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311486400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3311486400
Directory	/workspace/29.spi_device_intercept/latest

Test location	/workspace/coverage/default/29.spi_device_mailbox.4262540201
Short name	T940
Test name
Test status
Simulation time	28902900749 ps
CPU time	21.92 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:29:13 PM PDT 24
Peak memory	218676 kb
Host	smart-bb096d02-fd3e-4951-b941-a64355ff4f16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262540201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4262540201
Directory	/workspace/29.spi_device_mailbox/latest

Test location	/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2481022773
Short name	T99
Test name
Test status
Simulation time	69472430 ps
CPU time	2.4 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:52 PM PDT 24
Peak memory	233480 kb
Host	smart-726e2676-aeca-4d5d-88e2-bbba2cd07d6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481022773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa p.2481022773
Directory	/workspace/29.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/29.spi_device_pass_cmd_filtering.4085668915
Short name	T894
Test name
Test status
Simulation time	3528853216 ps
CPU time	12.28 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:29:03 PM PDT 24
Peak memory	238608 kb
Host	smart-63c4d5c2-8f17-4e34-bc8e-72bff19d1a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085668915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4085668915
Directory	/workspace/29.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/29.spi_device_read_buffer_direct.236047737
Short name	T609
Test name
Test status
Simulation time	229037722 ps
CPU time	4.64 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:54 PM PDT 24
Peak memory	218588 kb
Host	smart-d8dc5945-7773-47cd-9768-231922fa3fa3
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=236047737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire ct.236047737
Directory	/workspace/29.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_all.3056381302
Short name	T575
Test name
Test status
Simulation time	23089140853 ps
CPU time	17.72 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	216204 kb
Host	smart-fbc19f60-6cda-4cda-bbf7-52cda94902f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056381302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3056381302
Directory	/workspace/29.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3721390850
Short name	T568
Test name
Test status
Simulation time	9791581880 ps
CPU time	7.48 seconds
Started	May 14 01:28:49 PM PDT 24
Finished	May 14 01:28:59 PM PDT 24
Peak memory	216092 kb
Host	smart-db0158fd-76ca-446a-863d-2ea1097fe40b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721390850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3721390850
Directory	/workspace/29.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_rw.1693256674
Short name	T916
Test name
Test status
Simulation time	346240787 ps
CPU time	1.97 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:51 PM PDT 24
Peak memory	216120 kb
Host	smart-14417435-ae97-439e-ab5d-de62caf3c8f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693256674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1693256674
Directory	/workspace/29.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_sts_read.845416155
Short name	T847
Test name
Test status
Simulation time	99869242 ps
CPU time	0.82 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	205680 kb
Host	smart-c9c6b49c-7a35-4c41-a87c-ab8592d3e80a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845416155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.845416155
Directory	/workspace/29.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/29.spi_device_upload.268674752
Short name	T792
Test name
Test status
Simulation time	20242351871 ps
CPU time	19.94 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:29:07 PM PDT 24
Peak memory	233624 kb
Host	smart-5807961a-abdc-46ac-9c21-f1ba50d48274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268674752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.268674752
Directory	/workspace/29.spi_device_upload/latest

Test location	/workspace/coverage/default/3.spi_device_alert_test.1674353209
Short name	T394
Test name
Test status
Simulation time	229296927 ps
CPU time	0.78 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:33 PM PDT 24
Peak memory	204712 kb
Host	smart-b4957ab3-d67b-4498-97b2-f1422f0a0b6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674353209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1 674353209
Directory	/workspace/3.spi_device_alert_test/latest

Test location	/workspace/coverage/default/3.spi_device_cfg_cmd.2435600712
Short name	T206
Test name
Test status
Simulation time	9616474018 ps
CPU time	27.43 seconds
Started	May 14 01:27:29 PM PDT 24
Finished	May 14 01:27:57 PM PDT 24
Peak memory	221520 kb
Host	smart-d9c33592-0bdf-40ad-acd7-a983c93bef70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435600712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2435600712
Directory	/workspace/3.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/3.spi_device_csb_read.1379417257
Short name	T825
Test name
Test status
Simulation time	34445198 ps
CPU time	0.74 seconds
Started	May 14 01:27:29 PM PDT 24
Finished	May 14 01:27:30 PM PDT 24
Peak memory	205356 kb
Host	smart-f533b320-6309-4eb3-95cf-00f5c2e259d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379417257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1379417257
Directory	/workspace/3.spi_device_csb_read/latest

Test location	/workspace/coverage/default/3.spi_device_flash_all.2513578275
Short name	T292
Test name
Test status
Simulation time	10628329433 ps
CPU time	92.37 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:29:06 PM PDT 24
Peak memory	240868 kb
Host	smart-6621b880-d90b-43e7-8653-279c295c12cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513578275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2513578275
Directory	/workspace/3.spi_device_flash_all/latest

Test location	/workspace/coverage/default/3.spi_device_flash_and_tpm.3840964876
Short name	T175
Test name
Test status
Simulation time	12329803201 ps
CPU time	103.5 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:29:16 PM PDT 24
Peak memory	256308 kb
Host	smart-7a18b3d6-bed8-4af9-9d7d-357ff843a220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840964876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3840964876
Directory	/workspace/3.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1020309831
Short name	T238
Test name
Test status
Simulation time	92132454224 ps
CPU time	497.02 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:35:54 PM PDT 24
Peak memory	263224 kb
Host	smart-5252c34d-c803-4093-8fee-7500e45b8c99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020309831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle .1020309831
Directory	/workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/3.spi_device_flash_mode.2088874094
Short name	T859
Test name
Test status
Simulation time	215879686 ps
CPU time	2.58 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:40 PM PDT 24
Peak memory	232456 kb
Host	smart-ea5b8343-a7de-43c0-937d-41e6ba306c2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088874094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2088874094
Directory	/workspace/3.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/3.spi_device_intercept.2213299795
Short name	T813
Test name
Test status
Simulation time	882391663 ps
CPU time	8.49 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:45 PM PDT 24
Peak memory	235148 kb
Host	smart-b823d22b-fc8a-4457-af08-5bee40947cd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213299795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2213299795
Directory	/workspace/3.spi_device_intercept/latest

Test location	/workspace/coverage/default/3.spi_device_mailbox.3304066019
Short name	T4
Test name
Test status
Simulation time	7090508011 ps
CPU time	27.91 seconds
Started	May 14 01:27:29 PM PDT 24
Finished	May 14 01:27:58 PM PDT 24
Peak memory	240264 kb
Host	smart-50303f39-1d71-4866-991d-3fb07423e8fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304066019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3304066019
Directory	/workspace/3.spi_device_mailbox/latest

Test location	/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2758059309
Short name	T739
Test name
Test status
Simulation time	43020902865 ps
CPU time	14.57 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:50 PM PDT 24
Peak memory	239064 kb
Host	smart-ab61824c-3ae0-4a5b-b3d5-9fe8a60b9570
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758059309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap .2758059309
Directory	/workspace/3.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/3.spi_device_pass_cmd_filtering.4049300480
Short name	T198
Test name
Test status
Simulation time	34896342 ps
CPU time	2.07 seconds
Started	May 14 01:27:29 PM PDT 24
Finished	May 14 01:27:32 PM PDT 24
Peak memory	224268 kb
Host	smart-9efd5a95-92d9-4d0b-977e-ceb0c2a4caf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049300480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4049300480
Directory	/workspace/3.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/3.spi_device_read_buffer_direct.1142376756
Short name	T560
Test name
Test status
Simulation time	2868970420 ps
CPU time	7.41 seconds
Started	May 14 01:27:30 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	220092 kb
Host	smart-e3dfdc89-d5da-4b1a-aaa6-f5377e416cc0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1142376756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire ct.1142376756
Directory	/workspace/3.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/3.spi_device_sec_cm.4272371736
Short name	T76
Test name
Test status
Simulation time	227175175 ps
CPU time	1.07 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	234516 kb
Host	smart-2a1ab1dd-470c-4528-8926-f21a2f262516
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272371736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4272371736
Directory	/workspace/3.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_all.862163904
Short name	T710
Test name
Test status
Simulation time	773077004 ps
CPU time	9.22 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:47 PM PDT 24
Peak memory	216512 kb
Host	smart-ca2f21b7-cfe3-4fa9-b3c2-0a289fdcef14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862163904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.862163904
Directory	/workspace/3.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4241653720
Short name	T786
Test name
Test status
Simulation time	52227568 ps
CPU time	0.76 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:36 PM PDT 24
Peak memory	205456 kb
Host	smart-482d7f73-8765-4a70-ae9c-5d18c0c811e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241653720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4241653720
Directory	/workspace/3.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_rw.1899403939
Short name	T514
Test name
Test status
Simulation time	357423649 ps
CPU time	2.18 seconds
Started	May 14 01:27:30 PM PDT 24
Finished	May 14 01:27:34 PM PDT 24
Peak memory	216096 kb
Host	smart-a36e0b12-5564-48bb-b00d-6f1dc7254e6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899403939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1899403939
Directory	/workspace/3.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_sts_read.780266732
Short name	T446
Test name
Test status
Simulation time	320612435 ps
CPU time	1.04 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:35 PM PDT 24
Peak memory	205652 kb
Host	smart-7096afd8-fffa-4f1e-8e49-854b9f018edd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780266732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.780266732
Directory	/workspace/3.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/3.spi_device_upload.3736590723
Short name	T766
Test name
Test status
Simulation time	1128264312 ps
CPU time	9.03 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:45 PM PDT 24
Peak memory	227164 kb
Host	smart-9727af30-da03-42f5-9ccf-17c3257c4470
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736590723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3736590723
Directory	/workspace/3.spi_device_upload/latest

Test location	/workspace/coverage/default/30.spi_device_alert_test.1176801538
Short name	T127
Test name
Test status
Simulation time	89342625 ps
CPU time	0.74 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	204696 kb
Host	smart-6cb0034b-66fc-44f8-83ea-1362422f0ed9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176801538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test. 1176801538
Directory	/workspace/30.spi_device_alert_test/latest

Test location	/workspace/coverage/default/30.spi_device_cfg_cmd.2151458769
Short name	T429
Test name
Test status
Simulation time	1433977853 ps
CPU time	9.69 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	234020 kb
Host	smart-cfc41176-660e-4f26-8bf0-6438c0b34ac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151458769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2151458769
Directory	/workspace/30.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/30.spi_device_csb_read.3009304788
Short name	T891
Test name
Test status
Simulation time	32451735 ps
CPU time	0.76 seconds
Started	May 14 01:28:50 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	206424 kb
Host	smart-fdd6e56e-77b5-4d4c-a57c-c5443e2b94b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009304788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3009304788
Directory	/workspace/30.spi_device_csb_read/latest

Test location	/workspace/coverage/default/30.spi_device_flash_all.1425675933
Short name	T299
Test name
Test status
Simulation time	21131199920 ps
CPU time	157.2 seconds
Started	May 14 01:28:54 PM PDT 24
Finished	May 14 01:31:32 PM PDT 24
Peak memory	248960 kb
Host	smart-02fed2c2-af80-468d-9f31-26b65f02d1ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425675933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1425675933
Directory	/workspace/30.spi_device_flash_all/latest

Test location	/workspace/coverage/default/30.spi_device_flash_and_tpm.3339017706
Short name	T309
Test name
Test status
Simulation time	2011301168 ps
CPU time	33.96 seconds
Started	May 14 01:28:53 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	253048 kb
Host	smart-c329d05c-8245-43b3-a2c5-8af6cbb8a628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339017706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3339017706
Directory	/workspace/30.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3739874473
Short name	T264
Test name
Test status
Simulation time	14779161428 ps
CPU time	108.85 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:30:46 PM PDT 24
Peak memory	255404 kb
Host	smart-f1098043-a54e-455d-85f5-c96a867b2b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739874473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl e.3739874473
Directory	/workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/30.spi_device_flash_mode.1685410174
Short name	T108
Test name
Test status
Simulation time	364277816 ps
CPU time	5.53 seconds
Started	May 14 01:28:52 PM PDT 24
Finished	May 14 01:28:59 PM PDT 24
Peak memory	224260 kb
Host	smart-97dc6c41-5db3-45e6-a7ae-9f96908b3211
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685410174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1685410174
Directory	/workspace/30.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/30.spi_device_intercept.1019250587
Short name	T174
Test name
Test status
Simulation time	167101923 ps
CPU time	3.16 seconds
Started	May 14 01:28:53 PM PDT 24
Finished	May 14 01:28:58 PM PDT 24
Peak memory	219296 kb
Host	smart-8baaf21f-ea66-448b-bf71-45c53a93b8cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019250587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1019250587
Directory	/workspace/30.spi_device_intercept/latest

Test location	/workspace/coverage/default/30.spi_device_mailbox.1492635048
Short name	T202
Test name
Test status
Simulation time	12043198559 ps
CPU time	122.33 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:31:08 PM PDT 24
Peak memory	230256 kb
Host	smart-c960258f-c10d-41ed-b095-32e8d44fa4fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492635048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1492635048
Directory	/workspace/30.spi_device_mailbox/latest

Test location	/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1436946279
Short name	T773
Test name
Test status
Simulation time	2222799705 ps
CPU time	7.18 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:57 PM PDT 24
Peak memory	218708 kb
Host	smart-17cc2aab-85d2-4f18-bc14-f7df97d866dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436946279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa p.1436946279
Directory	/workspace/30.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/30.spi_device_pass_cmd_filtering.1948014008
Short name	T220
Test name
Test status
Simulation time	385057138 ps
CPU time	4.83 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:56 PM PDT 24
Peak memory	233092 kb
Host	smart-b584b5b4-78b3-494c-8f60-9e078cac1c23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948014008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1948014008
Directory	/workspace/30.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/30.spi_device_read_buffer_direct.3422579291
Short name	T90
Test name
Test status
Simulation time	604483294 ps
CPU time	9.53 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	220116 kb
Host	smart-486d2ea5-ebcd-4364-a002-df020042fb7d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3422579291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir ect.3422579291
Directory	/workspace/30.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/30.spi_device_stress_all.890265036
Short name	T317
Test name
Test status
Simulation time	20395611044 ps
CPU time	84.47 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:30:25 PM PDT 24
Peak memory	248952 kb
Host	smart-54b1fcba-4f70-4f39-8e48-f4a03866f35a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890265036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres s_all.890265036
Directory	/workspace/30.spi_device_stress_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_all.4220071476
Short name	T384
Test name
Test status
Simulation time	1366424814 ps
CPU time	6.27 seconds
Started	May 14 01:28:47 PM PDT 24
Finished	May 14 01:28:56 PM PDT 24
Peak memory	216164 kb
Host	smart-043f4ebf-8ed4-4c7e-8954-430d23713bf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220071476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4220071476
Directory	/workspace/30.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_read_hw_reg.699573755
Short name	T360
Test name
Test status
Simulation time	683827194 ps
CPU time	4.27 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:55 PM PDT 24
Peak memory	216028 kb
Host	smart-21e40582-6c82-44c9-be54-aeb4beb755ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699573755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.699573755
Directory	/workspace/30.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_rw.3599629253
Short name	T721
Test name
Test status
Simulation time	120695021 ps
CPU time	2.22 seconds
Started	May 14 01:28:48 PM PDT 24
Finished	May 14 01:28:53 PM PDT 24
Peak memory	216140 kb
Host	smart-56d2220c-5095-4199-9f6e-2f28a676cb61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599629253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3599629253
Directory	/workspace/30.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_sts_read.780694460
Short name	T842
Test name
Test status
Simulation time	47090626 ps
CPU time	0.9 seconds
Started	May 14 01:28:46 PM PDT 24
Finished	May 14 01:28:49 PM PDT 24
Peak memory	205684 kb
Host	smart-2dbcb6f9-d156-4694-9eef-d541a25322e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780694460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.780694460
Directory	/workspace/30.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/30.spi_device_upload.409318090
Short name	T812
Test name
Test status
Simulation time	1470584864 ps
CPU time	7.63 seconds
Started	May 14 01:28:59 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	233692 kb
Host	smart-a2369663-c8fc-4dd8-ad6e-75d2b95b85b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409318090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.409318090
Directory	/workspace/30.spi_device_upload/latest

Test location	/workspace/coverage/default/31.spi_device_alert_test.2784738838
Short name	T436
Test name
Test status
Simulation time	26380734 ps
CPU time	0.71 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:28:58 PM PDT 24
Peak memory	205268 kb
Host	smart-3f0c521a-3e4b-4081-ad97-668864e74994
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784738838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test. 2784738838
Directory	/workspace/31.spi_device_alert_test/latest

Test location	/workspace/coverage/default/31.spi_device_cfg_cmd.1657320919
Short name	T806
Test name
Test status
Simulation time	4797541360 ps
CPU time	14.79 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:20 PM PDT 24
Peak memory	218348 kb
Host	smart-856e75c4-87db-4487-8a89-8c992958dc7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657320919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1657320919
Directory	/workspace/31.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/31.spi_device_csb_read.515598626
Short name	T694
Test name
Test status
Simulation time	33074974 ps
CPU time	0.8 seconds
Started	May 14 01:28:53 PM PDT 24
Finished	May 14 01:28:56 PM PDT 24
Peak memory	205304 kb
Host	smart-7b1d5464-1e7a-447e-95a5-a770f3d83921
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515598626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.515598626
Directory	/workspace/31.spi_device_csb_read/latest

Test location	/workspace/coverage/default/31.spi_device_flash_and_tpm.3376121909
Short name	T882
Test name
Test status
Simulation time	6733256034 ps
CPU time	30.54 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	238632 kb
Host	smart-210dca73-44fa-4f91-bd25-8eec0e062041
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376121909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3376121909
Directory	/workspace/31.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.581235234
Short name	T133
Test name
Test status
Simulation time	52677534192 ps
CPU time	540.71 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:37:58 PM PDT 24
Peak memory	256468 kb
Host	smart-b2fd06a2-cf3f-4e28-9001-8c90ac391134
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581235234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle .581235234
Directory	/workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/31.spi_device_flash_mode.225338990
Short name	T391
Test name
Test status
Simulation time	1632286995 ps
CPU time	14.17 seconds
Started	May 14 01:28:53 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	240672 kb
Host	smart-217cfe07-5450-4d62-9394-e76f1d365b09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225338990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.225338990
Directory	/workspace/31.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/31.spi_device_intercept.700843122
Short name	T180
Test name
Test status
Simulation time	13680607962 ps
CPU time	15.15 seconds
Started	May 14 01:28:55 PM PDT 24
Finished	May 14 01:29:11 PM PDT 24
Peak memory	220256 kb
Host	smart-63255bc7-832a-4f92-b526-a4779ccd0313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700843122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.700843122
Directory	/workspace/31.spi_device_intercept/latest

Test location	/workspace/coverage/default/31.spi_device_mailbox.722044433
Short name	T584
Test name
Test status
Simulation time	6716695439 ps
CPU time	41.91 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	233684 kb
Host	smart-719c56c6-84e4-4403-aac8-14d79f058550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722044433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.722044433
Directory	/workspace/31.spi_device_mailbox/latest

Test location	/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.50548651
Short name	T6
Test name
Test status
Simulation time	21072214740 ps
CPU time	19.85 seconds
Started	May 14 01:28:54 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	239248 kb
Host	smart-c6b9fb40-6618-49f7-ac83-1b94f8f571bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50548651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.50548651
Directory	/workspace/31.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/31.spi_device_pass_cmd_filtering.3836042532
Short name	T421
Test name
Test status
Simulation time	1118588206 ps
CPU time	4.9 seconds
Started	May 14 01:28:54 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	235196 kb
Host	smart-94ec0f94-9c28-467f-baea-8b7f8942db51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836042532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3836042532
Directory	/workspace/31.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/31.spi_device_read_buffer_direct.65442424
Short name	T498
Test name
Test status
Simulation time	1218713383 ps
CPU time	8.67 seconds
Started	May 14 01:28:59 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	221984 kb
Host	smart-ae50376e-bed1-4002-977b-563afb28c392
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=65442424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direc t.65442424
Directory	/workspace/31.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/31.spi_device_stress_all.1582804235
Short name	T149
Test name
Test status
Simulation time	76421268933 ps
CPU time	160.27 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:31:40 PM PDT 24
Peak memory	249044 kb
Host	smart-926611f3-1b06-4f64-8c3a-b7d53a275257
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582804235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre ss_all.1582804235
Directory	/workspace/31.spi_device_stress_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_all.92830720
Short name	T336
Test name
Test status
Simulation time	37805194726 ps
CPU time	23.08 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	216080 kb
Host	smart-e4bf5d12-cecc-444b-9850-359ee4572bb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92830720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.92830720
Directory	/workspace/31.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.259401274
Short name	T532
Test name
Test status
Simulation time	462545995 ps
CPU time	1.47 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	207548 kb
Host	smart-8288b3ee-fa2a-4af8-94db-238867fb7533
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259401274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.259401274
Directory	/workspace/31.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_rw.3415589245
Short name	T708
Test name
Test status
Simulation time	49413518 ps
CPU time	1.36 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	216052 kb
Host	smart-934eb1ff-e158-4a91-9e8a-8afa59b849ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415589245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3415589245
Directory	/workspace/31.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_sts_read.442242149
Short name	T693
Test name
Test status
Simulation time	15982740 ps
CPU time	0.79 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	205612 kb
Host	smart-39d04c9a-be40-4df2-8233-9cad6593615d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442242149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.442242149
Directory	/workspace/31.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/31.spi_device_upload.4291107463
Short name	T630
Test name
Test status
Simulation time	3878205626 ps
CPU time	7.66 seconds
Started	May 14 01:28:54 PM PDT 24
Finished	May 14 01:29:03 PM PDT 24
Peak memory	217332 kb
Host	smart-4dc7ef6d-ac6d-48ea-99d1-f15493f0edfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291107463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4291107463
Directory	/workspace/31.spi_device_upload/latest

Test location	/workspace/coverage/default/32.spi_device_alert_test.3376457403
Short name	T707
Test name
Test status
Simulation time	23309559 ps
CPU time	0.73 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	205276 kb
Host	smart-750de9ba-d71a-4056-a95e-5ee8167ecd4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376457403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test. 3376457403
Directory	/workspace/32.spi_device_alert_test/latest

Test location	/workspace/coverage/default/32.spi_device_cfg_cmd.3777417676
Short name	T92
Test name
Test status
Simulation time	113535558 ps
CPU time	3.86 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:29:02 PM PDT 24
Peak memory	219352 kb
Host	smart-38869a4f-6ebd-4de0-b9dd-922185e048c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777417676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3777417676
Directory	/workspace/32.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/32.spi_device_csb_read.2941116038
Short name	T21
Test name
Test status
Simulation time	58322949 ps
CPU time	0.75 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:28:59 PM PDT 24
Peak memory	205348 kb
Host	smart-6af42891-edad-407c-9731-093637ed70a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941116038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2941116038
Directory	/workspace/32.spi_device_csb_read/latest

Test location	/workspace/coverage/default/32.spi_device_flash_all.31765694
Short name	T666
Test name
Test status
Simulation time	13267753229 ps
CPU time	18.05 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	240764 kb
Host	smart-93c19774-df6f-4634-bf90-9ea772ce741f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31765694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.31765694
Directory	/workspace/32.spi_device_flash_all/latest

Test location	/workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3051511567
Short name	T734
Test name
Test status
Simulation time	70756703176 ps
CPU time	88.35 seconds
Started	May 14 01:28:55 PM PDT 24
Finished	May 14 01:30:25 PM PDT 24
Peak memory	248972 kb
Host	smart-23c4a193-f28d-4c0b-bf04-204097da757c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051511567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl e.3051511567
Directory	/workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/32.spi_device_flash_mode.2803201057
Short name	T567
Test name
Test status
Simulation time	405693222 ps
CPU time	11.52 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	224360 kb
Host	smart-3e9d6988-ed28-47ab-a36f-71124fa0107b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803201057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2803201057
Directory	/workspace/32.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/32.spi_device_intercept.984641774
Short name	T617
Test name
Test status
Simulation time	251675572 ps
CPU time	2.74 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	224312 kb
Host	smart-6c6e3783-3744-4799-981f-9926fb491294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984641774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.984641774
Directory	/workspace/32.spi_device_intercept/latest

Test location	/workspace/coverage/default/32.spi_device_mailbox.953154867
Short name	T836
Test name
Test status
Simulation time	8664790386 ps
CPU time	27.31 seconds
Started	May 14 01:28:59 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	235216 kb
Host	smart-ad901307-54a6-457a-bd06-f79ac162f4be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953154867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.953154867
Directory	/workspace/32.spi_device_mailbox/latest

Test location	/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1349792634
Short name	T553
Test name
Test status
Simulation time	102824371 ps
CPU time	2.8 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:29:00 PM PDT 24
Peak memory	220936 kb
Host	smart-5d2e000d-b164-4bf0-9d23-017a0343855d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349792634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa p.1349792634
Directory	/workspace/32.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/32.spi_device_pass_cmd_filtering.2551085753
Short name	T189
Test name
Test status
Simulation time	3199683992 ps
CPU time	5.72 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:29:03 PM PDT 24
Peak memory	232632 kb
Host	smart-db8aaf26-7599-4b2d-ab43-6ee9a18bd8ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551085753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2551085753
Directory	/workspace/32.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/32.spi_device_read_buffer_direct.1621994144
Short name	T139
Test name
Test status
Simulation time	286571474 ps
CPU time	4.93 seconds
Started	May 14 01:28:55 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	222316 kb
Host	smart-30efcc5d-b63e-48a6-b50d-0d65779ed476
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1621994144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir ect.1621994144
Directory	/workspace/32.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/32.spi_device_stress_all.4006883110
Short name	T418
Test name
Test status
Simulation time	36338129 ps
CPU time	0.92 seconds
Started	May 14 01:28:59 PM PDT 24
Finished	May 14 01:29:01 PM PDT 24
Peak memory	206684 kb
Host	smart-785a4486-0a96-40d7-8b6e-5527a799d490
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006883110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre ss_all.4006883110
Directory	/workspace/32.spi_device_stress_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_all.4183466673
Short name	T566
Test name
Test status
Simulation time	4226621939 ps
CPU time	25.35 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	216152 kb
Host	smart-c1dc1bf8-1b98-451f-92e3-df106a5b1d80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183466673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4183466673
Directory	/workspace/32.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1890425795
Short name	T403
Test name
Test status
Simulation time	14848160061 ps
CPU time	21.72 seconds
Started	May 14 01:28:53 PM PDT 24
Finished	May 14 01:29:16 PM PDT 24
Peak memory	216116 kb
Host	smart-df601bbf-b81c-4394-bc83-36271101f255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1890425795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1890425795
Directory	/workspace/32.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_rw.2725964586
Short name	T867
Test name
Test status
Simulation time	20630955 ps
CPU time	0.79 seconds
Started	May 14 01:28:55 PM PDT 24
Finished	May 14 01:28:57 PM PDT 24
Peak memory	205440 kb
Host	smart-f97e21a8-15a3-419b-afd8-d9ee616f1d5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725964586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2725964586
Directory	/workspace/32.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_sts_read.3481945751
Short name	T404
Test name
Test status
Simulation time	28565174 ps
CPU time	0.84 seconds
Started	May 14 01:28:54 PM PDT 24
Finished	May 14 01:28:56 PM PDT 24
Peak memory	205672 kb
Host	smart-7d18744e-a09d-4d61-a9c1-c3bd2c2df416
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481945751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3481945751
Directory	/workspace/32.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/32.spi_device_upload.4155472851
Short name	T854
Test name
Test status
Simulation time	94588979 ps
CPU time	2.58 seconds
Started	May 14 01:28:58 PM PDT 24
Finished	May 14 01:29:02 PM PDT 24
Peak memory	221324 kb
Host	smart-433bc2fe-f75c-4aff-9916-1b73069e7ca6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155472851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4155472851
Directory	/workspace/32.spi_device_upload/latest

Test location	/workspace/coverage/default/33.spi_device_alert_test.3182678182
Short name	T354
Test name
Test status
Simulation time	13511298 ps
CPU time	0.75 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	204688 kb
Host	smart-0e07ad03-8c58-4c29-8242-3e8e19fb9c5d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182678182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test. 3182678182
Directory	/workspace/33.spi_device_alert_test/latest

Test location	/workspace/coverage/default/33.spi_device_cfg_cmd.87546927
Short name	T722
Test name
Test status
Simulation time	2203259225 ps
CPU time	7.59 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:19 PM PDT 24
Peak memory	218616 kb
Host	smart-fcd35749-0398-41bc-b4e2-b2914f76bb3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87546927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.87546927
Directory	/workspace/33.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/33.spi_device_csb_read.2043609633
Short name	T501
Test name
Test status
Simulation time	34161030 ps
CPU time	0.75 seconds
Started	May 14 01:28:56 PM PDT 24
Finished	May 14 01:28:58 PM PDT 24
Peak memory	205764 kb
Host	smart-0d8b305c-dd82-4650-b9a3-b3b483ecc348
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043609633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2043609633
Directory	/workspace/33.spi_device_csb_read/latest

Test location	/workspace/coverage/default/33.spi_device_flash_all.3040493372
Short name	T955
Test name
Test status
Simulation time	2577792123 ps
CPU time	14.6 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	224344 kb
Host	smart-e08b233f-03c0-48f0-9392-eeda3720a319
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040493372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3040493372
Directory	/workspace/33.spi_device_flash_all/latest

Test location	/workspace/coverage/default/33.spi_device_flash_and_tpm.3893941453
Short name	T252
Test name
Test status
Simulation time	79882732116 ps
CPU time	239.97 seconds
Started	May 14 01:29:06 PM PDT 24
Finished	May 14 01:33:07 PM PDT 24
Peak memory	265216 kb
Host	smart-218b4038-5c17-4e3d-a5b4-11f29ff6c3c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893941453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3893941453
Directory	/workspace/33.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.744785202
Short name	T653
Test name
Test status
Simulation time	30483069707 ps
CPU time	301.04 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:34:06 PM PDT 24
Peak memory	249024 kb
Host	smart-87bc80f2-08e4-4198-a83f-62ac43526922
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744785202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle .744785202
Directory	/workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/33.spi_device_flash_mode.1262017424
Short name	T915
Test name
Test status
Simulation time	747828105 ps
CPU time	5.92 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	237056 kb
Host	smart-5fa871a0-6cca-4ab5-9780-1a2073a3a8df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262017424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1262017424
Directory	/workspace/33.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/33.spi_device_intercept.3962123893
Short name	T781
Test name
Test status
Simulation time	1136286154 ps
CPU time	8.65 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:14 PM PDT 24
Peak memory	218124 kb
Host	smart-b3ba578c-b964-40fc-9b11-ceec1295685c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962123893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3962123893
Directory	/workspace/33.spi_device_intercept/latest

Test location	/workspace/coverage/default/33.spi_device_mailbox.2280872701
Short name	T741
Test name
Test status
Simulation time	721003838 ps
CPU time	6.1 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:11 PM PDT 24
Peak memory	232472 kb
Host	smart-e32a8689-e5ce-48fe-94c3-1fd8116b4d70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280872701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2280872701
Directory	/workspace/33.spi_device_mailbox/latest

Test location	/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.304154640
Short name	T852
Test name
Test status
Simulation time	67759140 ps
CPU time	2.92 seconds
Started	May 14 01:29:01 PM PDT 24
Finished	May 14 01:29:05 PM PDT 24
Peak memory	233672 kb
Host	smart-97b43609-7a6a-42c8-bc0a-d6095be1b50f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304154640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap .304154640
Directory	/workspace/33.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/33.spi_device_pass_cmd_filtering.4098267934
Short name	T688
Test name
Test status
Simulation time	6934374287 ps
CPU time	7.89 seconds
Started	May 14 01:29:01 PM PDT 24
Finished	May 14 01:29:10 PM PDT 24
Peak memory	218664 kb
Host	smart-799b3e58-03aa-418c-9b70-e8aa93ccfafa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098267934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4098267934
Directory	/workspace/33.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/33.spi_device_read_buffer_direct.1945525108
Short name	T458
Test name
Test status
Simulation time	1213443485 ps
CPU time	4.48 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	220004 kb
Host	smart-a91f20ad-377f-4522-903f-5f97fe41b5cd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1945525108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir ect.1945525108
Directory	/workspace/33.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/33.spi_device_stress_all.1438981622
Short name	T558
Test name
Test status
Simulation time	71989000 ps
CPU time	0.9 seconds
Started	May 14 01:29:06 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	206764 kb
Host	smart-2883308a-69e4-4e67-85cc-2f172d8e5203
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438981622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre ss_all.1438981622
Directory	/workspace/33.spi_device_stress_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_all.1523334361
Short name	T87
Test name
Test status
Simulation time	1321187748 ps
CPU time	12.15 seconds
Started	May 14 01:28:53 PM PDT 24
Finished	May 14 01:29:07 PM PDT 24
Peak memory	216116 kb
Host	smart-b271db88-527f-4a28-b7f5-c1874867b899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523334361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1523334361
Directory	/workspace/33.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3604483218
Short name	T540
Test name
Test status
Simulation time	23499393 ps
CPU time	0.73 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:00 PM PDT 24
Peak memory	205488 kb
Host	smart-eb8bf999-b0f1-4b25-a588-d06910c65c53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604483218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3604483218
Directory	/workspace/33.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_rw.1354156470
Short name	T811
Test name
Test status
Simulation time	184628238 ps
CPU time	1.22 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:07 PM PDT 24
Peak memory	216056 kb
Host	smart-41c98a19-a573-475b-8048-644b08dbbfea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354156470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1354156470
Directory	/workspace/33.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_sts_read.739300228
Short name	T411
Test name
Test status
Simulation time	26573059 ps
CPU time	0.88 seconds
Started	May 14 01:28:57 PM PDT 24
Finished	May 14 01:29:00 PM PDT 24
Peak memory	205596 kb
Host	smart-a17a108f-e4f1-4aab-be2f-06ae096b7185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739300228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.739300228
Directory	/workspace/33.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/33.spi_device_upload.1069386526
Short name	T660
Test name
Test status
Simulation time	14577469693 ps
CPU time	28.79 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:34 PM PDT 24
Peak memory	242224 kb
Host	smart-9b4940d4-bf28-43ab-8215-7e40a5cc8594
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069386526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1069386526
Directory	/workspace/33.spi_device_upload/latest

Test location	/workspace/coverage/default/34.spi_device_alert_test.3041152882
Short name	T466
Test name
Test status
Simulation time	62349277 ps
CPU time	0.74 seconds
Started	May 14 01:29:00 PM PDT 24
Finished	May 14 01:29:02 PM PDT 24
Peak memory	205208 kb
Host	smart-fed27b45-3ca8-443a-bc61-9ac86fc3214b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041152882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test. 3041152882
Directory	/workspace/34.spi_device_alert_test/latest

Test location	/workspace/coverage/default/34.spi_device_cfg_cmd.2970493280
Short name	T195
Test name
Test status
Simulation time	80927570 ps
CPU time	2.8 seconds
Started	May 14 01:29:04 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	233880 kb
Host	smart-8778df80-3210-48b0-a41d-1495e2da09ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970493280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2970493280
Directory	/workspace/34.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/34.spi_device_csb_read.1152421006
Short name	T426
Test name
Test status
Simulation time	14069959 ps
CPU time	0.76 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:06 PM PDT 24
Peak memory	205412 kb
Host	smart-f4a9fbb6-5765-49d7-b21c-1ec01b36bde0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152421006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1152421006
Directory	/workspace/34.spi_device_csb_read/latest

Test location	/workspace/coverage/default/34.spi_device_flash_all.2866602009
Short name	T545
Test name
Test status
Simulation time	55832496 ps
CPU time	0.85 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:04 PM PDT 24
Peak memory	215964 kb
Host	smart-80517a8c-5d88-4a48-ae0c-241a2891237a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866602009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2866602009
Directory	/workspace/34.spi_device_flash_all/latest

Test location	/workspace/coverage/default/34.spi_device_flash_and_tpm.2009242766
Short name	T56
Test name
Test status
Simulation time	171015501223 ps
CPU time	210.68 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:32:36 PM PDT 24
Peak memory	249028 kb
Host	smart-801f1226-7304-4415-ae08-a0b2cd78300c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009242766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2009242766
Directory	/workspace/34.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.315422917
Short name	T188
Test name
Test status
Simulation time	56060113110 ps
CPU time	536.07 seconds
Started	May 14 01:29:05 PM PDT 24
Finished	May 14 01:38:03 PM PDT 24
Peak memory	254648 kb
Host	smart-11e2e51f-001f-4cd6-9172-49381f1edb11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315422917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle .315422917
Directory	/workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/34.spi_device_flash_mode.1210346947
Short name	T951
Test name
Test status
Simulation time	5767403018 ps
CPU time	11.96 seconds
Started	May 14 01:29:08 PM PDT 24
Finished	May 14 01:29:21 PM PDT 24
Peak memory	224476 kb
Host	smart-ffd557ce-ab43-4914-8185-d4a714540874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210346947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1210346947
Directory	/workspace/34.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/34.spi_device_intercept.2668192482
Short name	T355
Test name
Test status
Simulation time	29232537 ps
CPU time	2.39 seconds
Started	May 14 01:29:01 PM PDT 24
Finished	May 14 01:29:04 PM PDT 24
Peak memory	221184 kb
Host	smart-1dec1203-b397-47a8-a638-b8cc3425dfb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668192482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2668192482
Directory	/workspace/34.spi_device_intercept/latest

Test location	/workspace/coverage/default/34.spi_device_mailbox.3669909454
Short name	T132
Test name
Test status
Simulation time	11709632613 ps
CPU time	23.37 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	233776 kb
Host	smart-5043e675-9f92-4013-9868-3b4d270069b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669909454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3669909454
Directory	/workspace/34.spi_device_mailbox/latest

Test location	/workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1955183640
Short name	T316
Test name
Test status
Simulation time	1116188682 ps
CPU time	5.51 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:10 PM PDT 24
Peak memory	236496 kb
Host	smart-9b5b793c-ea4b-4f9f-be85-1a204d3bd961
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955183640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa p.1955183640
Directory	/workspace/34.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/34.spi_device_pass_cmd_filtering.3925339102
Short name	T494
Test name
Test status
Simulation time	4796038548 ps
CPU time	5.82 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:10 PM PDT 24
Peak memory	218608 kb
Host	smart-704d04d9-941c-43cc-a147-50bf2a39d96e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925339102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3925339102
Directory	/workspace/34.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/34.spi_device_read_buffer_direct.1093786942
Short name	T432
Test name
Test status
Simulation time	8778993594 ps
CPU time	12.81 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	219104 kb
Host	smart-96f6c223-1a0f-4ee0-966c-d590bae829d2
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1093786942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir ect.1093786942
Directory	/workspace/34.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/34.spi_device_stress_all.118738307
Short name	T27
Test name
Test status
Simulation time	41831732416 ps
CPU time	481.6 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:37:07 PM PDT 24
Peak memory	281824 kb
Host	smart-370e28f9-63a1-4d96-a19e-36c60447571c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118738307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres s_all.118738307
Directory	/workspace/34.spi_device_stress_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_all.94036131
Short name	T544
Test name
Test status
Simulation time	1061462695 ps
CPU time	10.61 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:16 PM PDT 24
Peak memory	216128 kb
Host	smart-f51f1142-7ec3-4dfd-8d48-e104e006ac2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94036131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.94036131
Directory	/workspace/34.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1901405666
Short name	T372
Test name
Test status
Simulation time	12299147774 ps
CPU time	12.16 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	216096 kb
Host	smart-1eb4313f-2b44-4dda-9aed-2bb0ca87ac24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901405666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1901405666
Directory	/workspace/34.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_rw.3551585697
Short name	T613
Test name
Test status
Simulation time	104812485 ps
CPU time	1.46 seconds
Started	May 14 01:29:05 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	216060 kb
Host	smart-fd78eb47-6f5d-42f2-b10d-35fdf7e5fd3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551585697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3551585697
Directory	/workspace/34.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_sts_read.614771522
Short name	T475
Test name
Test status
Simulation time	65059463 ps
CPU time	0.86 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:04 PM PDT 24
Peak memory	205600 kb
Host	smart-e73f08e3-1ea6-457c-a893-6c3caad1af1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614771522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.614771522
Directory	/workspace/34.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/34.spi_device_upload.3492335681
Short name	T937
Test name
Test status
Simulation time	254338730 ps
CPU time	3.56 seconds
Started	May 14 01:29:06 PM PDT 24
Finished	May 14 01:29:11 PM PDT 24
Peak memory	236572 kb
Host	smart-b2a26871-d026-477d-9a14-370af6fa0461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492335681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3492335681
Directory	/workspace/34.spi_device_upload/latest

Test location	/workspace/coverage/default/35.spi_device_alert_test.2747358485
Short name	T385
Test name
Test status
Simulation time	35596998 ps
CPU time	0.72 seconds
Started	May 14 01:29:12 PM PDT 24
Finished	May 14 01:29:14 PM PDT 24
Peak memory	204688 kb
Host	smart-79e9bee0-df70-4833-b4f2-4ba4405f3d4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747358485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test. 2747358485
Directory	/workspace/35.spi_device_alert_test/latest

Test location	/workspace/coverage/default/35.spi_device_cfg_cmd.1738174217
Short name	T396
Test name
Test status
Simulation time	125570859 ps
CPU time	3.87 seconds
Started	May 14 01:29:08 PM PDT 24
Finished	May 14 01:29:14 PM PDT 24
Peak memory	234484 kb
Host	smart-1b1755f7-c9d2-407f-bec8-abdde419b1ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738174217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1738174217
Directory	/workspace/35.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/35.spi_device_csb_read.245883980
Short name	T390
Test name
Test status
Simulation time	20605123 ps
CPU time	0.8 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:06 PM PDT 24
Peak memory	205436 kb
Host	smart-41a22b88-a882-43d2-a506-24841d9729ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245883980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.245883980
Directory	/workspace/35.spi_device_csb_read/latest

Test location	/workspace/coverage/default/35.spi_device_flash_all.3299905578
Short name	T452
Test name
Test status
Simulation time	12799162864 ps
CPU time	93.75 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:30:46 PM PDT 24
Peak memory	248968 kb
Host	smart-3c484ba0-1593-4fc6-85f3-cb1d3b55cd46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299905578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3299905578
Directory	/workspace/35.spi_device_flash_all/latest

Test location	/workspace/coverage/default/35.spi_device_flash_and_tpm.527378656
Short name	T669
Test name
Test status
Simulation time	50016891300 ps
CPU time	238.18 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:33:18 PM PDT 24
Peak memory	249024 kb
Host	smart-d4f3de4c-91c3-482e-ba2e-79caac0c1dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=527378656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.527378656
Directory	/workspace/35.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3887539471
Short name	T267
Test name
Test status
Simulation time	14004483622 ps
CPU time	42.78 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:55 PM PDT 24
Peak memory	240660 kb
Host	smart-f1f22bbb-4699-45bf-9a46-cd8f99553906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3887539471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl e.3887539471
Directory	/workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/35.spi_device_flash_mode.143224497
Short name	T328
Test name
Test status
Simulation time	4132953435 ps
CPU time	44.7 seconds
Started	May 14 01:29:02 PM PDT 24
Finished	May 14 01:29:48 PM PDT 24
Peak memory	248920 kb
Host	smart-fae08f8f-fb64-4485-ab10-13576afef545
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143224497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.143224497
Directory	/workspace/35.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/35.spi_device_intercept.504204087
Short name	T461
Test name
Test status
Simulation time	7028813000 ps
CPU time	18.03 seconds
Started	May 14 01:29:06 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	233968 kb
Host	smart-eb033879-037f-4403-b69e-f3f8bbadf87b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504204087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.504204087
Directory	/workspace/35.spi_device_intercept/latest

Test location	/workspace/coverage/default/35.spi_device_mailbox.1129865597
Short name	T533
Test name
Test status
Simulation time	14326535279 ps
CPU time	75.88 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:30:21 PM PDT 24
Peak memory	231540 kb
Host	smart-9950b7e5-1c14-4b7a-adef-eaab7fd29662
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129865597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1129865597
Directory	/workspace/35.spi_device_mailbox/latest

Test location	/workspace/coverage/default/35.spi_device_pass_cmd_filtering.2992723206
Short name	T210
Test name
Test status
Simulation time	28792089321 ps
CPU time	13.44 seconds
Started	May 14 01:29:03 PM PDT 24
Finished	May 14 01:29:19 PM PDT 24
Peak memory	230540 kb
Host	smart-cf68991c-b51c-4a12-a042-c98526c08c75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992723206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2992723206
Directory	/workspace/35.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/35.spi_device_read_buffer_direct.1440721514
Short name	T415
Test name
Test status
Simulation time	5546546731 ps
CPU time	16.27 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:27 PM PDT 24
Peak memory	219128 kb
Host	smart-46de86ba-776b-4498-ad13-91e8c08d4eb4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1440721514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir ect.1440721514
Directory	/workspace/35.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/35.spi_device_stress_all.611117601
Short name	T46
Test name
Test status
Simulation time	18906794930 ps
CPU time	102.22 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:31:02 PM PDT 24
Peak memory	252336 kb
Host	smart-6dc87764-11a4-4099-9c6f-20df89ad517a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611117601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres s_all.611117601
Directory	/workspace/35.spi_device_stress_all/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_all.3586848479
Short name	T29
Test name
Test status
Simulation time	6206597424 ps
CPU time	17.84 seconds
Started	May 14 01:29:04 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	216148 kb
Host	smart-7d290059-95e7-4498-af7a-f73b5b6cb7ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586848479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3586848479
Directory	/workspace/35.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2123590437
Short name	T583
Test name
Test status
Simulation time	44886939504 ps
CPU time	17.71 seconds
Started	May 14 01:29:08 PM PDT 24
Finished	May 14 01:29:27 PM PDT 24
Peak memory	216064 kb
Host	smart-daedc63e-21be-4222-8c0d-ec7fb1100a4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123590437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2123590437
Directory	/workspace/35.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_rw.1226453791
Short name	T643
Test name
Test status
Simulation time	70953379 ps
CPU time	0.87 seconds
Started	May 14 01:29:06 PM PDT 24
Finished	May 14 01:29:08 PM PDT 24
Peak memory	206756 kb
Host	smart-9858cf3b-5887-48c1-97d3-296962db4148
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226453791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1226453791
Directory	/workspace/35.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_sts_read.3473811313
Short name	T914
Test name
Test status
Simulation time	54352825 ps
CPU time	0.79 seconds
Started	May 14 01:29:07 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	205712 kb
Host	smart-a4e18ba0-f8f6-4e09-8c31-a0cc6c81b4a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473811313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3473811313
Directory	/workspace/35.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/35.spi_device_upload.3774578723
Short name	T768
Test name
Test status
Simulation time	28459989625 ps
CPU time	23.2 seconds
Started	May 14 01:29:07 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	236628 kb
Host	smart-1f1a68f0-fb9e-4807-bce4-6f40ea385ce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774578723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3774578723
Directory	/workspace/35.spi_device_upload/latest

Test location	/workspace/coverage/default/36.spi_device_alert_test.1996841172
Short name	T350
Test name
Test status
Simulation time	43935726 ps
CPU time	0.69 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:12 PM PDT 24
Peak memory	205576 kb
Host	smart-a6d52390-caa1-4954-8f00-2793e56277bf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996841172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test. 1996841172
Directory	/workspace/36.spi_device_alert_test/latest

Test location	/workspace/coverage/default/36.spi_device_cfg_cmd.1641220964
Short name	T525
Test name
Test status
Simulation time	34252416 ps
CPU time	2.58 seconds
Started	May 14 01:29:14 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	221340 kb
Host	smart-62eb115f-4581-4d2f-adff-b831a6860e8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641220964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1641220964
Directory	/workspace/36.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/36.spi_device_csb_read.2346077844
Short name	T755
Test name
Test status
Simulation time	93597457 ps
CPU time	0.84 seconds
Started	May 14 01:29:12 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	206456 kb
Host	smart-e8468a40-43e6-4207-89ee-1e513c063a88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346077844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2346077844
Directory	/workspace/36.spi_device_csb_read/latest

Test location	/workspace/coverage/default/36.spi_device_flash_all.2392029574
Short name	T642
Test name
Test status
Simulation time	58082776044 ps
CPU time	78.31 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:30:31 PM PDT 24
Peak memory	237508 kb
Host	smart-11c152d0-1b1d-4e3a-a142-70f093ca1e58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392029574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2392029574
Directory	/workspace/36.spi_device_flash_all/latest

Test location	/workspace/coverage/default/36.spi_device_flash_and_tpm.1333601130
Short name	T775
Test name
Test status
Simulation time	3315438214 ps
CPU time	21.02 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	217300 kb
Host	smart-a714b483-b4c1-4176-aca6-e0e4d2b182ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333601130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1333601130
Directory	/workspace/36.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/36.spi_device_flash_mode.2491169511
Short name	T332
Test name
Test status
Simulation time	1014698258 ps
CPU time	9.13 seconds
Started	May 14 01:29:14 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	224324 kb
Host	smart-b06d9130-1794-41c0-b8fe-8d84e273f7b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491169511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2491169511
Directory	/workspace/36.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/36.spi_device_intercept.1483420465
Short name	T300
Test name
Test status
Simulation time	2851448000 ps
CPU time	4.23 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	216500 kb
Host	smart-5ba1f4f7-5e8d-4fd3-bef8-f003e0baf167
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483420465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1483420465
Directory	/workspace/36.spi_device_intercept/latest

Test location	/workspace/coverage/default/36.spi_device_mailbox.3614159520
Short name	T204
Test name
Test status
Simulation time	3064596221 ps
CPU time	24.68 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	233108 kb
Host	smart-3befbd86-d966-4336-ad56-ef9571a3315c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614159520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3614159520
Directory	/workspace/36.spi_device_mailbox/latest

Test location	/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1725215354
Short name	T256
Test name
Test status
Simulation time	8509228357 ps
CPU time	7.45 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	224376 kb
Host	smart-988d59db-b708-409f-86fc-44afbfcf4083
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725215354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa p.1725215354
Directory	/workspace/36.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/36.spi_device_pass_cmd_filtering.4192967934
Short name	T616
Test name
Test status
Simulation time	1000841914 ps
CPU time	5.41 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	218504 kb
Host	smart-b526f61b-bf1b-4f88-9365-fa63329dd316
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192967934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4192967934
Directory	/workspace/36.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/36.spi_device_read_buffer_direct.2206486101
Short name	T742
Test name
Test status
Simulation time	278135669 ps
CPU time	3.7 seconds
Started	May 14 01:29:12 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	222624 kb
Host	smart-890f4000-4cce-4357-8d25-f5e7e4fa99a0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2206486101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir ect.2206486101
Directory	/workspace/36.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_all.1811895550
Short name	T713
Test name
Test status
Simulation time	4716941790 ps
CPU time	7.7 seconds
Started	May 14 01:29:12 PM PDT 24
Finished	May 14 01:29:21 PM PDT 24
Peak memory	216240 kb
Host	smart-1182fa88-5d4f-4f89-8b53-7e62b936b1fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811895550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1811895550
Directory	/workspace/36.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1537313691
Short name	T758
Test name
Test status
Simulation time	2327134181 ps
CPU time	5.76 seconds
Started	May 14 01:29:08 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	216064 kb
Host	smart-9434d54f-b039-4018-97ad-b253ba88aa92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537313691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1537313691
Directory	/workspace/36.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_rw.4160747762
Short name	T938
Test name
Test status
Simulation time	152230115 ps
CPU time	1.32 seconds
Started	May 14 01:29:15 PM PDT 24
Finished	May 14 01:29:18 PM PDT 24
Peak memory	215836 kb
Host	smart-281ee8de-e44a-41b7-a933-db6a19d45fb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160747762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4160747762
Directory	/workspace/36.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_sts_read.2639722940
Short name	T443
Test name
Test status
Simulation time	150171480 ps
CPU time	0.92 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:12 PM PDT 24
Peak memory	205576 kb
Host	smart-43671ec9-360e-49c5-adb5-0ac8b63c7e31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639722940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2639722940
Directory	/workspace/36.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/36.spi_device_upload.834115935
Short name	T595
Test name
Test status
Simulation time	1420240748 ps
CPU time	11.65 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	234284 kb
Host	smart-16d720e8-199b-4b8d-9e60-955fec6f43f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834115935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.834115935
Directory	/workspace/36.spi_device_upload/latest

Test location	/workspace/coverage/default/37.spi_device_alert_test.1133915333
Short name	T717
Test name
Test status
Simulation time	13362424 ps
CPU time	0.73 seconds
Started	May 14 01:29:13 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	205524 kb
Host	smart-62159cc4-f89b-4b28-91d7-99a9ef74333d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133915333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test. 1133915333
Directory	/workspace/37.spi_device_alert_test/latest

Test location	/workspace/coverage/default/37.spi_device_cfg_cmd.1742799977
Short name	T535
Test name
Test status
Simulation time	188132557 ps
CPU time	3.94 seconds
Started	May 14 01:29:08 PM PDT 24
Finished	May 14 01:29:14 PM PDT 24
Peak memory	233792 kb
Host	smart-e7d1292b-a34d-4db8-8470-780a54bd24b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742799977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1742799977
Directory	/workspace/37.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/37.spi_device_csb_read.3338790480
Short name	T611
Test name
Test status
Simulation time	13914990 ps
CPU time	0.81 seconds
Started	May 14 01:29:14 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	206440 kb
Host	smart-08478885-aa02-49d2-b999-0ecffd42501a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338790480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3338790480
Directory	/workspace/37.spi_device_csb_read/latest

Test location	/workspace/coverage/default/37.spi_device_flash_all.973299182
Short name	T769
Test name
Test status
Simulation time	41538498556 ps
CPU time	60.69 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:30:14 PM PDT 24
Peak memory	249936 kb
Host	smart-9e11f941-b52d-460a-80ac-4e8059040c29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973299182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.973299182
Directory	/workspace/37.spi_device_flash_all/latest

Test location	/workspace/coverage/default/37.spi_device_flash_and_tpm.1900441498
Short name	T247
Test name
Test status
Simulation time	208406484268 ps
CPU time	279.66 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:33:53 PM PDT 24
Peak memory	255928 kb
Host	smart-9e246bfa-091e-4f11-b271-966a6f454c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900441498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1900441498
Directory	/workspace/37.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3869042147
Short name	T559
Test name
Test status
Simulation time	29558848206 ps
CPU time	119.69 seconds
Started	May 14 01:29:13 PM PDT 24
Finished	May 14 01:31:15 PM PDT 24
Peak memory	249020 kb
Host	smart-8698028c-ca37-4db4-8558-68bb527e52be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869042147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl e.3869042147
Directory	/workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/37.spi_device_flash_mode.1685863423
Short name	T303
Test name
Test status
Simulation time	230948264 ps
CPU time	3.6 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:15 PM PDT 24
Peak memory	232792 kb
Host	smart-66539830-5c80-4a96-b328-f2f15716b2df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685863423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1685863423
Directory	/workspace/37.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/37.spi_device_intercept.248572587
Short name	T880
Test name
Test status
Simulation time	119620617 ps
CPU time	2.94 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:29:16 PM PDT 24
Peak memory	232968 kb
Host	smart-82925fa6-7922-4b20-aa97-c2d8178567af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248572587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.248572587
Directory	/workspace/37.spi_device_intercept/latest

Test location	/workspace/coverage/default/37.spi_device_mailbox.613769031
Short name	T183
Test name
Test status
Simulation time	922672604 ps
CPU time	8.24 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:29:21 PM PDT 24
Peak memory	233680 kb
Host	smart-7e827bbd-dd2c-45a3-aacb-a6a5360bbeb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613769031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.613769031
Directory	/workspace/37.spi_device_mailbox/latest

Test location	/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2122602240
Short name	T182
Test name
Test status
Simulation time	291603501 ps
CPU time	3.84 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	232980 kb
Host	smart-48374a9a-18ee-4ac4-a25f-3b13c169b4c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122602240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa p.2122602240
Directory	/workspace/37.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/37.spi_device_pass_cmd_filtering.3137964050
Short name	T287
Test name
Test status
Simulation time	6864780305 ps
CPU time	19.4 seconds
Started	May 14 01:29:15 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	229096 kb
Host	smart-02b33ab5-1ba0-4fbb-afc7-1ee812058c1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137964050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3137964050
Directory	/workspace/37.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/37.spi_device_read_buffer_direct.1661490108
Short name	T838
Test name
Test status
Simulation time	3820331603 ps
CPU time	21.77 seconds
Started	May 14 01:29:14 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	218412 kb
Host	smart-0395e28c-6ef2-4e68-ada8-7ac5ea7b4c0e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1661490108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir ect.1661490108
Directory	/workspace/37.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/37.spi_device_stress_all.446158805
Short name	T224
Test name
Test status
Simulation time	73883063119 ps
CPU time	672.9 seconds
Started	May 14 01:29:11 PM PDT 24
Finished	May 14 01:40:26 PM PDT 24
Peak memory	270748 kb
Host	smart-9f5b06b6-7f27-4fcd-9dc6-ad5f1682719a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446158805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres s_all.446158805
Directory	/workspace/37.spi_device_stress_all/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_all.3351721869
Short name	T774
Test name
Test status
Simulation time	4590925843 ps
CPU time	12.75 seconds
Started	May 14 01:29:09 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	216348 kb
Host	smart-88631e19-c043-4402-97c5-6131c5112b0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351721869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3351721869
Directory	/workspace/37.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2545713039
Short name	T509
Test name
Test status
Simulation time	3210533187 ps
CPU time	5.61 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	216084 kb
Host	smart-f8c6cbb6-cfca-4175-9d0b-82c71f4ee559
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545713039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2545713039
Directory	/workspace/37.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_rw.3070262289
Short name	T626
Test name
Test status
Simulation time	26119998 ps
CPU time	1.11 seconds
Started	May 14 01:29:14 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	207808 kb
Host	smart-5754cfe5-9d8e-4024-afbb-6046764e2d3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070262289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3070262289
Directory	/workspace/37.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_sts_read.1356383584
Short name	T427
Test name
Test status
Simulation time	52148170 ps
CPU time	0.72 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:13 PM PDT 24
Peak memory	205620 kb
Host	smart-cd02c02a-259d-476f-a138-601d4a59e1ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356383584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1356383584
Directory	/workspace/37.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/37.spi_device_upload.3068229323
Short name	T263
Test name
Test status
Simulation time	5839728334 ps
CPU time	6.92 seconds
Started	May 14 01:29:10 PM PDT 24
Finished	May 14 01:29:19 PM PDT 24
Peak memory	234312 kb
Host	smart-47c4d242-10fb-41ae-bdae-be6af508a50c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068229323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3068229323
Directory	/workspace/37.spi_device_upload/latest

Test location	/workspace/coverage/default/38.spi_device_alert_test.3411232811
Short name	T353
Test name
Test status
Simulation time	32307420 ps
CPU time	0.71 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:29:20 PM PDT 24
Peak memory	205204 kb
Host	smart-21ae1b16-82ac-4564-8c79-9942bd356589
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411232811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test. 3411232811
Directory	/workspace/38.spi_device_alert_test/latest

Test location	/workspace/coverage/default/38.spi_device_cfg_cmd.3969519429
Short name	T887
Test name
Test status
Simulation time	456981458 ps
CPU time	6.73 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	218660 kb
Host	smart-3b071bfe-cca0-4405-80bc-cde981b43592
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969519429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3969519429
Directory	/workspace/38.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/38.spi_device_csb_read.1106406527
Short name	T364
Test name
Test status
Simulation time	14936531 ps
CPU time	0.77 seconds
Started	May 14 01:29:14 PM PDT 24
Finished	May 14 01:29:17 PM PDT 24
Peak memory	205416 kb
Host	smart-0a9febac-d55b-4a83-a94f-a2d7360c84ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106406527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1106406527
Directory	/workspace/38.spi_device_csb_read/latest

Test location	/workspace/coverage/default/38.spi_device_flash_all.1157291593
Short name	T187
Test name
Test status
Simulation time	8332498961 ps
CPU time	81.56 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:30:42 PM PDT 24
Peak memory	235980 kb
Host	smart-437b4eef-15b5-4d6d-8591-ab4056b036ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157291593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1157291593
Directory	/workspace/38.spi_device_flash_all/latest

Test location	/workspace/coverage/default/38.spi_device_flash_and_tpm.21561839
Short name	T81
Test name
Test status
Simulation time	21861214974 ps
CPU time	216.2 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:33:01 PM PDT 24
Peak memory	248944 kb
Host	smart-e2512def-7766-45b4-ad12-6be4b71eb336
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21561839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.21561839
Directory	/workspace/38.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/38.spi_device_flash_mode.516418157
Short name	T484
Test name
Test status
Simulation time	185276284 ps
CPU time	3.89 seconds
Started	May 14 01:29:17 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	224292 kb
Host	smart-7f355190-cc0e-4842-9cbc-d3f87bade014
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516418157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.516418157
Directory	/workspace/38.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/38.spi_device_intercept.379677820
Short name	T543
Test name
Test status
Simulation time	122531125 ps
CPU time	2.53 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	221496 kb
Host	smart-66509ae8-d391-4466-a144-dc59826641c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379677820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.379677820
Directory	/workspace/38.spi_device_intercept/latest

Test location	/workspace/coverage/default/38.spi_device_mailbox.1024680183
Short name	T901
Test name
Test status
Simulation time	3932046792 ps
CPU time	38.82 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:30:00 PM PDT 24
Peak memory	223032 kb
Host	smart-ae1ce04c-86ed-4ae6-b169-6aaf6d29a2a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024680183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1024680183
Directory	/workspace/38.spi_device_mailbox/latest

Test location	/workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4141971018
Short name	T957
Test name
Test status
Simulation time	3058037225 ps
CPU time	9.98 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:33 PM PDT 24
Peak memory	219696 kb
Host	smart-d9df8247-4520-4aae-bb78-1c9990731d1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141971018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa p.4141971018
Directory	/workspace/38.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/38.spi_device_pass_cmd_filtering.4269529205
Short name	T291
Test name
Test status
Simulation time	17031168868 ps
CPU time	15.32 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	219776 kb
Host	smart-0855d038-d59e-4656-8e2f-f5f7f67d9b75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269529205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4269529205
Directory	/workspace/38.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/38.spi_device_read_buffer_direct.2052994869
Short name	T919
Test name
Test status
Simulation time	1407028813 ps
CPU time	5.48 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	219088 kb
Host	smart-1232efa2-abbf-4c8a-ad34-b7373f43181d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2052994869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir ect.2052994869
Directory	/workspace/38.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/38.spi_device_stress_all.1763029956
Short name	T715
Test name
Test status
Simulation time	10952093663 ps
CPU time	43.6 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:30:03 PM PDT 24
Peak memory	234784 kb
Host	smart-19435ee4-4c1a-4ee9-a0e4-3cb074937cc9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763029956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre ss_all.1763029956
Directory	/workspace/38.spi_device_stress_all/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_all.1115977952
Short name	T763
Test name
Test status
Simulation time	10655184681 ps
CPU time	56.78 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:30:19 PM PDT 24
Peak memory	216108 kb
Host	smart-9157a165-d69f-422d-9820-4590c26f8080
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115977952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1115977952
Directory	/workspace/38.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4026886378
Short name	T347
Test name
Test status
Simulation time	4511215352 ps
CPU time	7.4 seconds
Started	May 14 01:29:15 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	216064 kb
Host	smart-dc9f317e-ffbd-4309-8904-8d2371800551
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026886378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4026886378
Directory	/workspace/38.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_rw.3718658734
Short name	T714
Test name
Test status
Simulation time	553385790 ps
CPU time	6.34 seconds
Started	May 14 01:29:15 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	216252 kb
Host	smart-3c41d8db-6c08-4e3d-a6bc-b1020e79f225
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718658734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3718658734
Directory	/workspace/38.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_sts_read.640186631
Short name	T638
Test name
Test status
Simulation time	18816438 ps
CPU time	0.76 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	205568 kb
Host	smart-1f06079d-3943-4470-a1c1-89bed66f511a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640186631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.640186631
Directory	/workspace/38.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/38.spi_device_upload.3152995080
Short name	T636
Test name
Test status
Simulation time	259062424 ps
CPU time	5.55 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:29:26 PM PDT 24
Peak memory	239400 kb
Host	smart-b4e6c37c-28f2-4c7a-8c18-46c6d945734b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152995080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3152995080
Directory	/workspace/38.spi_device_upload/latest

Test location	/workspace/coverage/default/39.spi_device_alert_test.187009222
Short name	T634
Test name
Test status
Simulation time	26811946 ps
CPU time	0.75 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	205208 kb
Host	smart-7bc2f1ea-7666-47de-87b6-351f2454a8e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187009222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.187009222
Directory	/workspace/39.spi_device_alert_test/latest

Test location	/workspace/coverage/default/39.spi_device_cfg_cmd.3309774801
Short name	T805
Test name
Test status
Simulation time	1719488620 ps
CPU time	8.96 seconds
Started	May 14 01:29:17 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	234192 kb
Host	smart-92319d70-9081-4d33-8100-a641ccb33a1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309774801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3309774801
Directory	/workspace/39.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/39.spi_device_csb_read.1056334934
Short name	T431
Test name
Test status
Simulation time	53407307 ps
CPU time	0.79 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	206712 kb
Host	smart-1a343874-9d3a-41f9-aaa5-c369b454d6b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056334934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1056334934
Directory	/workspace/39.spi_device_csb_read/latest

Test location	/workspace/coverage/default/39.spi_device_flash_all.311528098
Short name	T286
Test name
Test status
Simulation time	819599838 ps
CPU time	7.73 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	233556 kb
Host	smart-fc3dd8a9-0808-4692-80d4-0c35d77eccb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311528098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.311528098
Directory	/workspace/39.spi_device_flash_all/latest

Test location	/workspace/coverage/default/39.spi_device_flash_and_tpm.3302281188
Short name	T720
Test name
Test status
Simulation time	2968169105 ps
CPU time	19.56 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	238988 kb
Host	smart-b3f0e9da-9d2b-4737-8d30-1f6b0178b52a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302281188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3302281188
Directory	/workspace/39.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3569932004
Short name	T126
Test name
Test status
Simulation time	5374769860 ps
CPU time	53.11 seconds
Started	May 14 01:29:17 PM PDT 24
Finished	May 14 01:30:12 PM PDT 24
Peak memory	240948 kb
Host	smart-34927c79-8f20-461c-bdff-2ef0d43938ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569932004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl e.3569932004
Directory	/workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/39.spi_device_intercept.1419478156
Short name	T485
Test name
Test status
Simulation time	90416819 ps
CPU time	3.53 seconds
Started	May 14 01:29:16 PM PDT 24
Finished	May 14 01:29:21 PM PDT 24
Peak memory	233388 kb
Host	smart-e25b646e-b061-41bc-8b39-a81334593d9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419478156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1419478156
Directory	/workspace/39.spi_device_intercept/latest

Test location	/workspace/coverage/default/39.spi_device_mailbox.1212689676
Short name	T785
Test name
Test status
Simulation time	1098906935 ps
CPU time	26.89 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:49 PM PDT 24
Peak memory	249204 kb
Host	smart-4c7f98d8-0d31-493a-8578-637926a2300a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212689676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1212689676
Directory	/workspace/39.spi_device_mailbox/latest

Test location	/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.876072710
Short name	T33
Test name
Test status
Simulation time	16732967476 ps
CPU time	26.54 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:48 PM PDT 24
Peak memory	248916 kb
Host	smart-033a0af1-db20-497f-a87c-1d30c92a43f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876072710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap .876072710
Directory	/workspace/39.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/39.spi_device_pass_cmd_filtering.1868247238
Short name	T761
Test name
Test status
Simulation time	144175455 ps
CPU time	2.06 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	218580 kb
Host	smart-fd28650d-7514-4332-98a2-2e244f615584
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1868247238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1868247238
Directory	/workspace/39.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/39.spi_device_read_buffer_direct.869355252
Short name	T961
Test name
Test status
Simulation time	211999133 ps
CPU time	5.72 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	219652 kb
Host	smart-bd20cb62-5d80-4f74-8863-4dfbed1ae57e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=869355252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire ct.869355252
Directory	/workspace/39.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/39.spi_device_stress_all.503692209
Short name	T73
Test name
Test status
Simulation time	93326507965 ps
CPU time	221.79 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:33:04 PM PDT 24
Peak memory	252168 kb
Host	smart-f679b657-d465-48ce-83a0-e8664fa561b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503692209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres s_all.503692209
Directory	/workspace/39.spi_device_stress_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_all.2985493378
Short name	T681
Test name
Test status
Simulation time	2052492713 ps
CPU time	11.2 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:35 PM PDT 24
Peak memory	216072 kb
Host	smart-5017d5bd-9776-476a-ae88-fcd278a86213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985493378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2985493378
Directory	/workspace/39.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2640217472
Short name	T816
Test name
Test status
Simulation time	2377570381 ps
CPU time	4.77 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	215980 kb
Host	smart-0584a794-34d9-40b2-b9a2-bb85ce54674f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640217472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2640217472
Directory	/workspace/39.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_rw.3820286347
Short name	T59
Test name
Test status
Simulation time	84655108 ps
CPU time	1.93 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	216156 kb
Host	smart-73469b04-d328-4c85-b4e4-dcb96ed5869c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820286347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3820286347
Directory	/workspace/39.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_sts_read.2380892668
Short name	T960
Test name
Test status
Simulation time	334001803 ps
CPU time	0.81 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	205640 kb
Host	smart-171a0e81-8164-415d-b370-2efe48b9a39c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380892668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2380892668
Directory	/workspace/39.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/39.spi_device_upload.2486508990
Short name	T193
Test name
Test status
Simulation time	2583075629 ps
CPU time	12.18 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	240668 kb
Host	smart-5cc083f2-5090-4abb-ad26-d3a46f05df1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486508990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2486508990
Directory	/workspace/39.spi_device_upload/latest

Test location	/workspace/coverage/default/4.spi_device_alert_test.3395568264
Short name	T362
Test name
Test status
Simulation time	96816904 ps
CPU time	0.79 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:36 PM PDT 24
Peak memory	204644 kb
Host	smart-62504647-b33d-43ff-aea9-c89ca5862c33
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395568264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3 395568264
Directory	/workspace/4.spi_device_alert_test/latest

Test location	/workspace/coverage/default/4.spi_device_cfg_cmd.1742265931
Short name	T959
Test name
Test status
Simulation time	551520580 ps
CPU time	2.94 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	218552 kb
Host	smart-acc54feb-f266-4c17-b2b4-e8a40f7752eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742265931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1742265931
Directory	/workspace/4.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/4.spi_device_csb_read.2473916398
Short name	T160
Test name
Test status
Simulation time	18019462 ps
CPU time	0.77 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:37 PM PDT 24
Peak memory	205044 kb
Host	smart-afbb6b44-c189-4931-b676-b96159a017a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473916398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2473916398
Directory	/workspace/4.spi_device_csb_read/latest

Test location	/workspace/coverage/default/4.spi_device_flash_all.1912309775
Short name	T541
Test name
Test status
Simulation time	637506211 ps
CPU time	13.57 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:50 PM PDT 24
Peak memory	233508 kb
Host	smart-e4a7ea84-db0f-4033-887a-dadce5411bea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912309775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1912309775
Directory	/workspace/4.spi_device_flash_all/latest

Test location	/workspace/coverage/default/4.spi_device_flash_and_tpm.3094991170
Short name	T266
Test name
Test status
Simulation time	9408280395 ps
CPU time	66.38 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:28:41 PM PDT 24
Peak memory	249036 kb
Host	smart-a0502dc2-d5fb-4f23-80e8-d0213a2f31b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094991170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3094991170
Directory	/workspace/4.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3426490034
Short name	T28
Test name
Test status
Simulation time	8205071769 ps
CPU time	61.76 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:28:39 PM PDT 24
Peak memory	249292 kb
Host	smart-72f322bb-a5a3-4d64-88e6-76d8487069bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426490034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle .3426490034
Directory	/workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/4.spi_device_flash_mode.1860632323
Short name	T298
Test name
Test status
Simulation time	716461681 ps
CPU time	9.09 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:44 PM PDT 24
Peak memory	232448 kb
Host	smart-88307c65-af76-4df6-8e05-5a21b03a5218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860632323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1860632323
Directory	/workspace/4.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/4.spi_device_intercept.145815036
Short name	T191
Test name
Test status
Simulation time	2108329737 ps
CPU time	4.84 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:40 PM PDT 24
Peak memory	236092 kb
Host	smart-6acb4aba-5921-458d-bc60-93938c6ecc07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145815036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.145815036
Directory	/workspace/4.spi_device_intercept/latest

Test location	/workspace/coverage/default/4.spi_device_mailbox.2977689633
Short name	T608
Test name
Test status
Simulation time	27728469165 ps
CPU time	51.24 seconds
Started	May 14 01:27:30 PM PDT 24
Finished	May 14 01:28:22 PM PDT 24
Peak memory	247156 kb
Host	smart-81ba7539-9e1e-426b-b1aa-0292e08b3e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977689633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2977689633
Directory	/workspace/4.spi_device_mailbox/latest

Test location	/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3363932763
Short name	T243
Test name
Test status
Simulation time	941732218 ps
CPU time	11.88 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:44 PM PDT 24
Peak memory	240724 kb
Host	smart-a2386c8e-6e30-4b9b-a541-ea4776ff36df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363932763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap .3363932763
Directory	/workspace/4.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/4.spi_device_pass_cmd_filtering.3631198364
Short name	T856
Test name
Test status
Simulation time	7536925970 ps
CPU time	23.87 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:28:00 PM PDT 24
Peak memory	237964 kb
Host	smart-7ada680f-117c-4619-9db8-9f0d1a8d0ad0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631198364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3631198364
Directory	/workspace/4.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/4.spi_device_read_buffer_direct.1096161242
Short name	T685
Test name
Test status
Simulation time	846731569 ps
CPU time	5.9 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:43 PM PDT 24
Peak memory	222668 kb
Host	smart-48d46ef2-dfb0-4283-8d67-b6cd1cc18c56
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1096161242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire ct.1096161242
Directory	/workspace/4.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/4.spi_device_sec_cm.1195230677
Short name	T75
Test name
Test status
Simulation time	222705722 ps
CPU time	1.21 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	234564 kb
Host	smart-b8e7fa6c-ed33-4c71-82ba-99903c090011
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195230677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1195230677
Directory	/workspace/4.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/4.spi_device_stress_all.593840286
Short name	T26
Test name
Test status
Simulation time	329232665138 ps
CPU time	538.64 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:36:36 PM PDT 24
Peak memory	265164 kb
Host	smart-f8b99e7e-f2ff-4fa9-958b-ff60a738478d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593840286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress _all.593840286
Directory	/workspace/4.spi_device_stress_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_all.2073657968
Short name	T671
Test name
Test status
Simulation time	8344531518 ps
CPU time	22.41 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:57 PM PDT 24
Peak memory	220176 kb
Host	smart-3fa62167-7f30-49fe-a580-81e7d4250f3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073657968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2073657968
Directory	/workspace/4.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2926335932
Short name	T351
Test name
Test status
Simulation time	7818041515 ps
CPU time	17.51 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:51 PM PDT 24
Peak memory	216340 kb
Host	smart-c41b90d1-52ca-47b1-b1fa-9872908be068
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926335932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2926335932
Directory	/workspace/4.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_rw.3687577616
Short name	T757
Test name
Test status
Simulation time	28617436 ps
CPU time	1 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:27:37 PM PDT 24
Peak memory	207840 kb
Host	smart-13bd54e8-1ccc-47ea-9be2-3c5b5eeacb2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687577616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3687577616
Directory	/workspace/4.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_sts_read.1220453261
Short name	T864
Test name
Test status
Simulation time	23276087 ps
CPU time	0.81 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:35 PM PDT 24
Peak memory	205676 kb
Host	smart-626bdd3d-9f2a-42c0-b820-41acfaa6e8e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220453261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1220453261
Directory	/workspace/4.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/4.spi_device_upload.4290253291
Short name	T172
Test name
Test status
Simulation time	1444541425 ps
CPU time	6.4 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	224324 kb
Host	smart-405fa54e-0b2b-4909-be3a-34ed6d32b40a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290253291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4290253291
Directory	/workspace/4.spi_device_upload/latest

Test location	/workspace/coverage/default/40.spi_device_alert_test.100496544
Short name	T517
Test name
Test status
Simulation time	51284189 ps
CPU time	0.76 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	205304 kb
Host	smart-e4aa4e12-c7ac-4e81-90e2-43d171cbf6b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100496544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.100496544
Directory	/workspace/40.spi_device_alert_test/latest

Test location	/workspace/coverage/default/40.spi_device_cfg_cmd.677298014
Short name	T472
Test name
Test status
Simulation time	1755179685 ps
CPU time	3.36 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	219528 kb
Host	smart-4ab0aced-12cd-4e10-ac5b-7bcdb18f9207
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677298014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.677298014
Directory	/workspace/40.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/40.spi_device_csb_read.1131930088
Short name	T16
Test name
Test status
Simulation time	72982192 ps
CPU time	0.83 seconds
Started	May 14 01:29:17 PM PDT 24
Finished	May 14 01:29:19 PM PDT 24
Peak memory	206716 kb
Host	smart-bd6fdc3c-d6a4-4799-bd6d-c34c3c4064bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131930088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1131930088
Directory	/workspace/40.spi_device_csb_read/latest

Test location	/workspace/coverage/default/40.spi_device_flash_all.1356992627
Short name	T858
Test name
Test status
Simulation time	33332739796 ps
CPU time	255.04 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:33:38 PM PDT 24
Peak memory	256952 kb
Host	smart-d1f041fc-cd19-4c97-b13a-0a6288e7bb4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356992627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1356992627
Directory	/workspace/40.spi_device_flash_all/latest

Test location	/workspace/coverage/default/40.spi_device_flash_and_tpm.3730556987
Short name	T902
Test name
Test status
Simulation time	69511061409 ps
CPU time	93.67 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:30:59 PM PDT 24
Peak memory	249024 kb
Host	smart-b2e56e83-a6b9-4321-ab70-9bf6aeb7f796
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730556987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3730556987
Directory	/workspace/40.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/40.spi_device_flash_mode.3451092929
Short name	T331
Test name
Test status
Simulation time	168785085 ps
CPU time	5.32 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:34 PM PDT 24
Peak memory	232584 kb
Host	smart-fb08cda4-f6b4-4cb0-8e51-9bde4da3b9ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451092929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3451092929
Directory	/workspace/40.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/40.spi_device_intercept.2327930395
Short name	T205
Test name
Test status
Simulation time	196057409 ps
CPU time	4.58 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	224356 kb
Host	smart-88596864-31c8-46f8-8ecd-c359725f9202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327930395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2327930395
Directory	/workspace/40.spi_device_intercept/latest

Test location	/workspace/coverage/default/40.spi_device_mailbox.4027374556
Short name	T647
Test name
Test status
Simulation time	630066205 ps
CPU time	5.62 seconds
Started	May 14 01:29:22 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	224348 kb
Host	smart-89c9f132-afe4-48e1-8b84-b774e9242fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027374556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4027374556
Directory	/workspace/40.spi_device_mailbox/latest

Test location	/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2233525500
Short name	T218
Test name
Test status
Simulation time	1046041313 ps
CPU time	5.5 seconds
Started	May 14 01:29:17 PM PDT 24
Finished	May 14 01:29:25 PM PDT 24
Peak memory	237868 kb
Host	smart-15d6eef6-c450-4338-9de5-55b82189bae7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233525500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa p.2233525500
Directory	/workspace/40.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/40.spi_device_pass_cmd_filtering.977580809
Short name	T746
Test name
Test status
Simulation time	4132827564 ps
CPU time	12.58 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:35 PM PDT 24
Peak memory	240004 kb
Host	smart-3c2bd888-b759-472d-9e4d-2873d3a0ca3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977580809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.977580809
Directory	/workspace/40.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/40.spi_device_read_buffer_direct.3478877222
Short name	T835
Test name
Test status
Simulation time	420869748 ps
CPU time	6.4 seconds
Started	May 14 01:29:18 PM PDT 24
Finished	May 14 01:29:26 PM PDT 24
Peak memory	222888 kb
Host	smart-2e87998f-7ce9-425b-a7a0-fcdfc8a57ff0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3478877222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir ect.3478877222
Directory	/workspace/40.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/40.spi_device_stress_all.3831523301
Short name	T776
Test name
Test status
Simulation time	196815361011 ps
CPU time	464.51 seconds
Started	May 14 01:29:17 PM PDT 24
Finished	May 14 01:37:04 PM PDT 24
Peak memory	250424 kb
Host	smart-ca3037c7-4d72-4702-8c02-6d0a9af54968
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831523301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre ss_all.3831523301
Directory	/workspace/40.spi_device_stress_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_all.3075105921
Short name	T662
Test name
Test status
Simulation time	1394416624 ps
CPU time	14.68 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	219776 kb
Host	smart-dbfda870-75f4-4b7c-b5d3-0a27627b99fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075105921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3075105921
Directory	/workspace/40.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1456735691
Short name	T457
Test name
Test status
Simulation time	5581318809 ps
CPU time	9.22 seconds
Started	May 14 01:29:15 PM PDT 24
Finished	May 14 01:29:26 PM PDT 24
Peak memory	216108 kb
Host	smart-379f640a-7190-4138-8731-f9c40d5717ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456735691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1456735691
Directory	/workspace/40.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_rw.327049746
Short name	T270
Test name
Test status
Simulation time	91599991 ps
CPU time	3.13 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:29:28 PM PDT 24
Peak memory	216104 kb
Host	smart-593c9b9c-545f-42e1-995b-81073a51cd88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327049746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.327049746
Directory	/workspace/40.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_sts_read.1469874947
Short name	T848
Test name
Test status
Simulation time	75936672 ps
CPU time	0.81 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:23 PM PDT 24
Peak memory	205640 kb
Host	smart-a3a17d35-fd9d-4c76-aa71-83dbc119500c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469874947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1469874947
Directory	/workspace/40.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/40.spi_device_upload.1788962711
Short name	T477
Test name
Test status
Simulation time	196524227 ps
CPU time	4.37 seconds
Started	May 14 01:29:20 PM PDT 24
Finished	May 14 01:29:27 PM PDT 24
Peak memory	233964 kb
Host	smart-cded9556-b2df-48a8-b5ac-3f8560dcdbf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788962711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1788962711
Directory	/workspace/40.spi_device_upload/latest

Test location	/workspace/coverage/default/41.spi_device_alert_test.2061944919
Short name	T413
Test name
Test status
Simulation time	35474149 ps
CPU time	0.74 seconds
Started	May 14 01:29:28 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	205224 kb
Host	smart-ce463241-cb5a-429c-bd2e-e98f8b0b8089
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061944919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test. 2061944919
Directory	/workspace/41.spi_device_alert_test/latest

Test location	/workspace/coverage/default/41.spi_device_cfg_cmd.936378051
Short name	T179
Test name
Test status
Simulation time	292037965 ps
CPU time	4.33 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:33 PM PDT 24
Peak memory	234300 kb
Host	smart-bfdf55c9-30af-4929-94b3-adc1ac382001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936378051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.936378051
Directory	/workspace/41.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/41.spi_device_csb_read.931131397
Short name	T821
Test name
Test status
Simulation time	45435766 ps
CPU time	0.77 seconds
Started	May 14 01:29:22 PM PDT 24
Finished	May 14 01:29:26 PM PDT 24
Peak memory	206732 kb
Host	smart-2142689c-4451-453e-bd3d-d5481e6f7dc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931131397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.931131397
Directory	/workspace/41.spi_device_csb_read/latest

Test location	/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1178567530
Short name	T22
Test name
Test status
Simulation time	13782939661 ps
CPU time	54.22 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:30:23 PM PDT 24
Peak memory	249988 kb
Host	smart-0770b63f-5c9b-4954-805f-43543eb7e992
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178567530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl e.1178567530
Directory	/workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/41.spi_device_flash_mode.3626289543
Short name	T879
Test name
Test status
Simulation time	884907633 ps
CPU time	7.64 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:35 PM PDT 24
Peak memory	232504 kb
Host	smart-9a452502-abdd-452e-bb20-a83cca93cbff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626289543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3626289543
Directory	/workspace/41.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/41.spi_device_intercept.3329201447
Short name	T295
Test name
Test status
Simulation time	419240154 ps
CPU time	9.09 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	219252 kb
Host	smart-bc46cb14-eb70-4bf6-8bcb-73283f5c8c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329201447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3329201447
Directory	/workspace/41.spi_device_intercept/latest

Test location	/workspace/coverage/default/41.spi_device_mailbox.1519467674
Short name	T730
Test name
Test status
Simulation time	2571439579 ps
CPU time	8.38 seconds
Started	May 14 01:29:28 PM PDT 24
Finished	May 14 01:29:39 PM PDT 24
Peak memory	233628 kb
Host	smart-3e3e0f64-b28c-4a0c-a642-d12a13133996
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519467674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1519467674
Directory	/workspace/41.spi_device_mailbox/latest

Test location	/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.785800889
Short name	T41
Test name
Test status
Simulation time	814572838 ps
CPU time	9.42 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	233552 kb
Host	smart-99794114-42e2-4cc4-97a6-666d93e96266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785800889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap .785800889
Directory	/workspace/41.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/41.spi_device_pass_cmd_filtering.3004757284
Short name	T557
Test name
Test status
Simulation time	4233587548 ps
CPU time	8.19 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	233432 kb
Host	smart-3d507d08-ff22-40a6-b4c6-a4ccb82b57fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004757284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3004757284
Directory	/workspace/41.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/41.spi_device_read_buffer_direct.4290087711
Short name	T463
Test name
Test status
Simulation time	355147418 ps
CPU time	5.32 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	220440 kb
Host	smart-9b371d0c-5814-472d-bfce-b21d4a31fec7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4290087711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir ect.4290087711
Directory	/workspace/41.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_all.2962845746
Short name	T833
Test name
Test status
Simulation time	598626815 ps
CPU time	3.73 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	216068 kb
Host	smart-d7bc3b12-23ec-4a89-a8f8-2df9e9814425
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962845746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2962845746
Directory	/workspace/41.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2017097413
Short name	T379
Test name
Test status
Simulation time	1990291777 ps
CPU time	1.95 seconds
Started	May 14 01:29:19 PM PDT 24
Finished	May 14 01:29:24 PM PDT 24
Peak memory	206772 kb
Host	smart-31fbbece-0ec0-46ec-8422-127005f486b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017097413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2017097413
Directory	/workspace/41.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_rw.3340371648
Short name	T686
Test name
Test status
Simulation time	684441252 ps
CPU time	2.78 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	207960 kb
Host	smart-44efadcf-35a7-4362-a9cc-ef9bed60e671
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340371648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3340371648
Directory	/workspace/41.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_sts_read.365416336
Short name	T939
Test name
Test status
Simulation time	143967091 ps
CPU time	0.97 seconds
Started	May 14 01:29:23 PM PDT 24
Finished	May 14 01:29:27 PM PDT 24
Peak memory	205684 kb
Host	smart-360a22f9-e585-4f9d-b605-cfc403ca41dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365416336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.365416336
Directory	/workspace/41.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/41.spi_device_upload.1769862764
Short name	T738
Test name
Test status
Simulation time	12162152488 ps
CPU time	7.05 seconds
Started	May 14 01:29:23 PM PDT 24
Finished	May 14 01:29:33 PM PDT 24
Peak memory	217160 kb
Host	smart-c7a69c37-a179-4426-8cb4-460d13a79525
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769862764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1769862764
Directory	/workspace/41.spi_device_upload/latest

Test location	/workspace/coverage/default/42.spi_device_alert_test.209112166
Short name	T788
Test name
Test status
Simulation time	27035011 ps
CPU time	0.71 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	204592 kb
Host	smart-3c8d5986-c9a4-4c5d-b3a6-8fa0275f195c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209112166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.209112166
Directory	/workspace/42.spi_device_alert_test/latest

Test location	/workspace/coverage/default/42.spi_device_cfg_cmd.1390086386
Short name	T817
Test name
Test status
Simulation time	665793170 ps
CPU time	5.67 seconds
Started	May 14 01:29:21 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	233860 kb
Host	smart-a5d8108d-15b8-4f7b-89a2-c9b84f13ab11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390086386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1390086386
Directory	/workspace/42.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/42.spi_device_csb_read.2865602866
Short name	T161
Test name
Test status
Simulation time	33348606 ps
CPU time	0.79 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:29 PM PDT 24
Peak memory	205336 kb
Host	smart-be44c06b-3856-40af-b386-c0b3d3c681d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865602866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2865602866
Directory	/workspace/42.spi_device_csb_read/latest

Test location	/workspace/coverage/default/42.spi_device_flash_and_tpm.3366768714
Short name	T167
Test name
Test status
Simulation time	43938091222 ps
CPU time	100.6 seconds
Started	May 14 01:29:23 PM PDT 24
Finished	May 14 01:31:07 PM PDT 24
Peak memory	255440 kb
Host	smart-f5a93521-93f5-4fc3-aa8e-db62edc79624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366768714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3366768714
Directory	/workspace/42.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.238854324
Short name	T253
Test name
Test status
Simulation time	2985944093 ps
CPU time	61.74 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:30:30 PM PDT 24
Peak memory	251040 kb
Host	smart-2a886c53-4f48-440f-8056-bb0e87c6c9f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238854324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle .238854324
Directory	/workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/42.spi_device_flash_mode.4057552507
Short name	T597
Test name
Test status
Simulation time	107878023 ps
CPU time	3.53 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	224160 kb
Host	smart-3267e3aa-b7e1-4f84-a534-6fec970bf53a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057552507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4057552507
Directory	/workspace/42.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/42.spi_device_intercept.2558924958
Short name	T926
Test name
Test status
Simulation time	384249454 ps
CPU time	4.92 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:34 PM PDT 24
Peak memory	224232 kb
Host	smart-f8a3644d-7d9e-487b-9c4e-5091cd7d262b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558924958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2558924958
Directory	/workspace/42.spi_device_intercept/latest

Test location	/workspace/coverage/default/42.spi_device_mailbox.3386085839
Short name	T912
Test name
Test status
Simulation time	600110332 ps
CPU time	7.73 seconds
Started	May 14 01:29:27 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	233388 kb
Host	smart-cb922e57-f05d-43e2-acbc-452ecdc14d77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386085839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3386085839
Directory	/workspace/42.spi_device_mailbox/latest

Test location	/workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3724475255
Short name	T345
Test name
Test status
Simulation time	65330520 ps
CPU time	2.5 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	220912 kb
Host	smart-44cca649-55ef-4485-8062-095616845b89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724475255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa p.3724475255
Directory	/workspace/42.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/42.spi_device_pass_cmd_filtering.2337621327
Short name	T398
Test name
Test status
Simulation time	911713077 ps
CPU time	4.57 seconds
Started	May 14 01:29:23 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	219132 kb
Host	smart-1e4062b0-f7a7-46b3-8378-dbe35d121a51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337621327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2337621327
Directory	/workspace/42.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/42.spi_device_read_buffer_direct.2819547829
Short name	T433
Test name
Test status
Simulation time	148560628 ps
CPU time	3.92 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	219912 kb
Host	smart-91dea378-711f-41a0-a2b3-fdf0e118907c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2819547829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir ect.2819547829
Directory	/workspace/42.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/42.spi_device_stress_all.616424506
Short name	T151
Test name
Test status
Simulation time	306085492281 ps
CPU time	491.71 seconds
Started	May 14 01:29:27 PM PDT 24
Finished	May 14 01:37:42 PM PDT 24
Peak memory	253112 kb
Host	smart-332e267c-844e-4814-81eb-580dd74df6cb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616424506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres s_all.616424506
Directory	/workspace/42.spi_device_stress_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_all.1460804314
Short name	T335
Test name
Test status
Simulation time	2218911683 ps
CPU time	9.61 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	216480 kb
Host	smart-b57ec791-d84c-492f-af94-d1cedda5814d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460804314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1460804314
Directory	/workspace/42.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_read_hw_reg.783939670
Short name	T506
Test name
Test status
Simulation time	1283403725 ps
CPU time	4.4 seconds
Started	May 14 01:29:24 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	216064 kb
Host	smart-2e8043ad-c9ea-4609-afa5-818a08eb3472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783939670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.783939670
Directory	/workspace/42.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_rw.1994149192
Short name	T348
Test name
Test status
Simulation time	57227261 ps
CPU time	1.15 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	207572 kb
Host	smart-4656ad39-5d63-4127-8806-2a613579cb05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994149192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1994149192
Directory	/workspace/42.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_sts_read.3681503020
Short name	T420
Test name
Test status
Simulation time	75963243 ps
CPU time	0.92 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	205684 kb
Host	smart-3041632e-375d-4545-a161-9fe734c70345
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681503020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3681503020
Directory	/workspace/42.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/42.spi_device_upload.2550351106
Short name	T171
Test name
Test status
Simulation time	1447303408 ps
CPU time	4.76 seconds
Started	May 14 01:29:23 PM PDT 24
Finished	May 14 01:29:31 PM PDT 24
Peak memory	217196 kb
Host	smart-03f0dac2-d9d6-4acb-bce3-a279eb22110f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550351106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2550351106
Directory	/workspace/42.spi_device_upload/latest

Test location	/workspace/coverage/default/43.spi_device_alert_test.3444043789
Short name	T8
Test name
Test status
Simulation time	18131743 ps
CPU time	0.73 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	205216 kb
Host	smart-b5df2e26-0182-4d64-9ad9-9a3b3c49199e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444043789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test. 3444043789
Directory	/workspace/43.spi_device_alert_test/latest

Test location	/workspace/coverage/default/43.spi_device_cfg_cmd.3002417309
Short name	T718
Test name
Test status
Simulation time	134210740 ps
CPU time	2.31 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	218612 kb
Host	smart-ccffb4ba-c5d7-4efa-a624-57fd5b09e719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002417309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3002417309
Directory	/workspace/43.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/43.spi_device_csb_read.2382820583
Short name	T422
Test name
Test status
Simulation time	86200643 ps
CPU time	0.78 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:29:39 PM PDT 24
Peak memory	206640 kb
Host	smart-2d40477d-e2b3-438d-83b5-8a23c3421706
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382820583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2382820583
Directory	/workspace/43.spi_device_csb_read/latest

Test location	/workspace/coverage/default/43.spi_device_flash_all.1117980893
Short name	T34
Test name
Test status
Simulation time	14071548726 ps
CPU time	105.77 seconds
Started	May 14 01:29:30 PM PDT 24
Finished	May 14 01:31:17 PM PDT 24
Peak memory	237832 kb
Host	smart-e41b30cd-8c9b-4f1d-9dcc-bdb2b4d6fbeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117980893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1117980893
Directory	/workspace/43.spi_device_flash_all/latest

Test location	/workspace/coverage/default/43.spi_device_flash_and_tpm.481208173
Short name	T166
Test name
Test status
Simulation time	30723457890 ps
CPU time	91.72 seconds
Started	May 14 01:29:32 PM PDT 24
Finished	May 14 01:31:05 PM PDT 24
Peak memory	249400 kb
Host	smart-b425cf91-bb44-422e-9b0d-0afa50e3bb19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481208173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.481208173
Directory	/workspace/43.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.500734540
Short name	T906
Test name
Test status
Simulation time	6383902070 ps
CPU time	27.35 seconds
Started	May 14 01:29:31 PM PDT 24
Finished	May 14 01:29:59 PM PDT 24
Peak memory	224384 kb
Host	smart-2819f192-1c57-47ea-8943-18df5f277aca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500734540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle .500734540
Directory	/workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/43.spi_device_flash_mode.2770221435
Short name	T327
Test name
Test status
Simulation time	9100717876 ps
CPU time	25.54 seconds
Started	May 14 01:29:22 PM PDT 24
Finished	May 14 01:29:51 PM PDT 24
Peak memory	240784 kb
Host	smart-b753709b-f510-45b4-8851-5e4303a4983e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770221435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2770221435
Directory	/workspace/43.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/43.spi_device_intercept.2574149412
Short name	T307
Test name
Test status
Simulation time	527769207 ps
CPU time	7.14 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	233948 kb
Host	smart-15ea2128-a21b-4371-b78c-90b9770838e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574149412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2574149412
Directory	/workspace/43.spi_device_intercept/latest

Test location	/workspace/coverage/default/43.spi_device_mailbox.1476495157
Short name	T5
Test name
Test status
Simulation time	6819010546 ps
CPU time	23.64 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:30:02 PM PDT 24
Peak memory	245116 kb
Host	smart-c94f5826-6049-4809-8181-4bc5654cf74d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476495157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1476495157
Directory	/workspace/43.spi_device_mailbox/latest

Test location	/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.813330781
Short name	T257
Test name
Test status
Simulation time	9156216501 ps
CPU time	10.47 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:29:49 PM PDT 24
Peak memory	233000 kb
Host	smart-f2ff09dd-65f9-49d0-90e2-a53ce1738c2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813330781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap .813330781
Directory	/workspace/43.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/43.spi_device_pass_cmd_filtering.670558817
Short name	T904
Test name
Test status
Simulation time	2345028022 ps
CPU time	7.85 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:29:46 PM PDT 24
Peak memory	227972 kb
Host	smart-6030c83e-9f39-47ea-9158-841dd8e2e412
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670558817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.670558817
Directory	/workspace/43.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/43.spi_device_read_buffer_direct.700512519
Short name	T828
Test name
Test status
Simulation time	1089498510 ps
CPU time	6.5 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	218956 kb
Host	smart-4229f8dd-f0e7-4e5e-936e-67be49e3c6b5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=700512519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire ct.700512519
Directory	/workspace/43.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_all.3402305741
Short name	T476
Test name
Test status
Simulation time	2152964892 ps
CPU time	29.12 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:58 PM PDT 24
Peak memory	216340 kb
Host	smart-90320b60-90e7-4ddb-abdc-f07690f73dff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402305741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3402305741
Directory	/workspace/43.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1015736413
Short name	T352
Test name
Test status
Simulation time	927857412 ps
CPU time	3.29 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	216328 kb
Host	smart-172e6918-2981-4413-b626-a12f2f76cd1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015736413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1015736413
Directory	/workspace/43.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_rw.3616722594
Short name	T367
Test name
Test status
Simulation time	80876061 ps
CPU time	1.53 seconds
Started	May 14 01:29:37 PM PDT 24
Finished	May 14 01:29:40 PM PDT 24
Peak memory	207952 kb
Host	smart-57037343-d3fc-4e27-9f2c-12d05dfef205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616722594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3616722594
Directory	/workspace/43.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_sts_read.1742707138
Short name	T479
Test name
Test status
Simulation time	116356406 ps
CPU time	1.03 seconds
Started	May 14 01:29:26 PM PDT 24
Finished	May 14 01:29:30 PM PDT 24
Peak memory	205684 kb
Host	smart-2007bdec-7d74-4bec-af5a-c34bca2e23c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742707138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1742707138
Directory	/workspace/43.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/43.spi_device_upload.2238709180
Short name	T154
Test name
Test status
Simulation time	293853872 ps
CPU time	4.37 seconds
Started	May 14 01:29:25 PM PDT 24
Finished	May 14 01:29:32 PM PDT 24
Peak memory	235460 kb
Host	smart-952dedf8-0c22-4552-8b85-e0445be51afb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238709180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2238709180
Directory	/workspace/43.spi_device_upload/latest

Test location	/workspace/coverage/default/44.spi_device_alert_test.4082904397
Short name	T65
Test name
Test status
Simulation time	15132080 ps
CPU time	0.7 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:40 PM PDT 24
Peak memory	204636 kb
Host	smart-72d8f4fa-81e8-481f-89a6-3cf0621c81c6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082904397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test. 4082904397
Directory	/workspace/44.spi_device_alert_test/latest

Test location	/workspace/coverage/default/44.spi_device_cfg_cmd.3446105887
Short name	T621
Test name
Test status
Simulation time	78123546 ps
CPU time	2.84 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:39 PM PDT 24
Peak memory	234572 kb
Host	smart-357713aa-14d3-49d3-a42e-4518506b2f06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446105887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3446105887
Directory	/workspace/44.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/44.spi_device_csb_read.4028637952
Short name	T388
Test name
Test status
Simulation time	19254487 ps
CPU time	0.82 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	206424 kb
Host	smart-19a460be-e7dc-4fc5-ac01-9df2b0cfff01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028637952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4028637952
Directory	/workspace/44.spi_device_csb_read/latest

Test location	/workspace/coverage/default/44.spi_device_flash_all.3022625673
Short name	T495
Test name
Test status
Simulation time	6337747818 ps
CPU time	44.92 seconds
Started	May 14 01:29:31 PM PDT 24
Finished	May 14 01:30:18 PM PDT 24
Peak memory	240744 kb
Host	smart-3bf13927-fc13-4886-8611-608524120a93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022625673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3022625673
Directory	/workspace/44.spi_device_flash_all/latest

Test location	/workspace/coverage/default/44.spi_device_flash_and_tpm.4213200298
Short name	T845
Test name
Test status
Simulation time	12709201269 ps
CPU time	37.13 seconds
Started	May 14 01:29:31 PM PDT 24
Finished	May 14 01:30:10 PM PDT 24
Peak memory	250744 kb
Host	smart-9e75f0e1-03a9-4b15-b833-97d7cb95218e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213200298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4213200298
Directory	/workspace/44.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.510588355
Short name	T293
Test name
Test status
Simulation time	3290564767 ps
CPU time	44.75 seconds
Started	May 14 01:29:31 PM PDT 24
Finished	May 14 01:30:17 PM PDT 24
Peak memory	240740 kb
Host	smart-253b1439-2887-4e0f-972a-8b7d8e7164ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510588355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle .510588355
Directory	/workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/44.spi_device_flash_mode.2823461380
Short name	T862
Test name
Test status
Simulation time	557504942 ps
CPU time	10.32 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:46 PM PDT 24
Peak memory	224304 kb
Host	smart-c0dbcaf3-027b-4946-a38f-1bf91bee9bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823461380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2823461380
Directory	/workspace/44.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/44.spi_device_intercept.1489224155
Short name	T302
Test name
Test status
Simulation time	380197389 ps
CPU time	7.86 seconds
Started	May 14 01:29:32 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	219480 kb
Host	smart-fc5fe7b0-bc17-4058-8c64-27f06d76b383
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489224155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1489224155
Directory	/workspace/44.spi_device_intercept/latest

Test location	/workspace/coverage/default/44.spi_device_mailbox.3689511080
Short name	T777
Test name
Test status
Simulation time	739200937 ps
CPU time	10.85 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:47 PM PDT 24
Peak memory	235916 kb
Host	smart-217bcbeb-8a07-422b-aef1-dbf24c78f185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689511080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3689511080
Directory	/workspace/44.spi_device_mailbox/latest

Test location	/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.273946834
Short name	T371
Test name
Test status
Simulation time	29451691 ps
CPU time	2.19 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:39 PM PDT 24
Peak memory	215944 kb
Host	smart-8655db00-6a6a-48f7-8b08-1aeb867cd29b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273946834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap .273946834
Directory	/workspace/44.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/44.spi_device_pass_cmd_filtering.2846208881
Short name	T370
Test name
Test status
Simulation time	123475544 ps
CPU time	2.67 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	221164 kb
Host	smart-78a3f987-2e3b-4984-b3b6-3e2d8e27749c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846208881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2846208881
Directory	/workspace/44.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/44.spi_device_read_buffer_direct.2724190108
Short name	T48
Test name
Test status
Simulation time	8319004081 ps
CPU time	18.02 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:53 PM PDT 24
Peak memory	222344 kb
Host	smart-67bf7e2f-bc3e-44ea-b67f-6b69062ed54c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2724190108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir ect.2724190108
Directory	/workspace/44.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/44.spi_device_stress_all.3585309697
Short name	T262
Test name
Test status
Simulation time	36022192078 ps
CPU time	108.05 seconds
Started	May 14 01:29:35 PM PDT 24
Finished	May 14 01:31:25 PM PDT 24
Peak memory	249348 kb
Host	smart-e93f7dd7-06d4-4039-813c-797fed43fa48
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585309697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre ss_all.3585309697
Directory	/workspace/44.spi_device_stress_all/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_all.1048690231
Short name	T401
Test name
Test status
Simulation time	1064580652 ps
CPU time	13.7 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:50 PM PDT 24
Peak memory	216220 kb
Host	smart-ee7c4fc6-29dd-4b92-9795-50065f58dfc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048690231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1048690231
Directory	/workspace/44.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.704612745
Short name	T667
Test name
Test status
Simulation time	1748243713 ps
CPU time	5.98 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	216028 kb
Host	smart-26b5845a-8963-4b10-b16c-9f2fe33fde2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704612745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.704612745
Directory	/workspace/44.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_rw.2744552328
Short name	T340
Test name
Test status
Simulation time	70057312 ps
CPU time	1.19 seconds
Started	May 14 01:29:32 PM PDT 24
Finished	May 14 01:29:35 PM PDT 24
Peak memory	207780 kb
Host	smart-838a72f3-6390-46cb-a3da-81a18349108e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744552328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2744552328
Directory	/workspace/44.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_sts_read.3174385959
Short name	T547
Test name
Test status
Simulation time	84928293 ps
CPU time	0.97 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	205708 kb
Host	smart-8a60eb17-488f-4b4e-a50a-537bba88ed31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174385959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3174385959
Directory	/workspace/44.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/44.spi_device_upload.3054032844
Short name	T478
Test name
Test status
Simulation time	24289792616 ps
CPU time	35.59 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:30:12 PM PDT 24
Peak memory	233116 kb
Host	smart-8a028c27-1adb-44c3-be8d-a23c258377ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054032844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3054032844
Directory	/workspace/44.spi_device_upload/latest

Test location	/workspace/coverage/default/45.spi_device_alert_test.1442519380
Short name	T839
Test name
Test status
Simulation time	35218051 ps
CPU time	0.76 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	205588 kb
Host	smart-1af1bf4d-7b68-48f0-962a-0151f7ea151f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442519380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test. 1442519380
Directory	/workspace/45.spi_device_alert_test/latest

Test location	/workspace/coverage/default/45.spi_device_cfg_cmd.362408897
Short name	T665
Test name
Test status
Simulation time	1231159916 ps
CPU time	4.78 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	234672 kb
Host	smart-064f5e97-76c6-4889-a7e5-d60881d5f055
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362408897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.362408897
Directory	/workspace/45.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/45.spi_device_csb_read.3434972880
Short name	T417
Test name
Test status
Simulation time	32740565 ps
CPU time	0.74 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:36 PM PDT 24
Peak memory	206404 kb
Host	smart-7fbb4080-42d1-46cd-9474-dfb3e456aa41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434972880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3434972880
Directory	/workspace/45.spi_device_csb_read/latest

Test location	/workspace/coverage/default/45.spi_device_flash_all.2132100687
Short name	T67
Test name
Test status
Simulation time	95065732750 ps
CPU time	92.61 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:31:07 PM PDT 24
Peak memory	240796 kb
Host	smart-a1016c9c-cc95-4033-88a2-2929069d2151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132100687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2132100687
Directory	/workspace/45.spi_device_flash_all/latest

Test location	/workspace/coverage/default/45.spi_device_flash_and_tpm.1170752502
Short name	T829
Test name
Test status
Simulation time	6028154970 ps
CPU time	25.02 seconds
Started	May 14 01:29:32 PM PDT 24
Finished	May 14 01:29:58 PM PDT 24
Peak memory	219032 kb
Host	smart-afe73912-d39a-4a52-b0d0-2c559e46aa97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170752502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1170752502
Directory	/workspace/45.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4164447902
Short name	T546
Test name
Test status
Simulation time	2019123987 ps
CPU time	32.4 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:30:07 PM PDT 24
Peak memory	217136 kb
Host	smart-6e288099-f7b4-4837-8316-87b600e72e0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164447902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl e.4164447902
Directory	/workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/45.spi_device_flash_mode.3044873842
Short name	T326
Test name
Test status
Simulation time	1787714362 ps
CPU time	26.96 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:30:02 PM PDT 24
Peak memory	240424 kb
Host	smart-3e500c8c-0b0a-4050-98fd-5c10af7231a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044873842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3044873842
Directory	/workspace/45.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/45.spi_device_intercept.3105573982
Short name	T447
Test name
Test status
Simulation time	4838375223 ps
CPU time	23.89 seconds
Started	May 14 01:29:32 PM PDT 24
Finished	May 14 01:29:58 PM PDT 24
Peak memory	234372 kb
Host	smart-3afbab8d-e632-4236-b2b3-1b534af7d268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105573982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3105573982
Directory	/workspace/45.spi_device_intercept/latest

Test location	/workspace/coverage/default/45.spi_device_mailbox.359121132
Short name	T548
Test name
Test status
Simulation time	62123865 ps
CPU time	2.41 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	221164 kb
Host	smart-38958ef6-3b1d-4555-8a23-43e57ea96544
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359121132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.359121132
Directory	/workspace/45.spi_device_mailbox/latest

Test location	/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.323653399
Short name	T528
Test name
Test status
Simulation time	617579544 ps
CPU time	3.65 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:40 PM PDT 24
Peak memory	232940 kb
Host	smart-78ce127b-1631-4510-9f79-b74b1b2241d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323653399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap .323653399
Directory	/workspace/45.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/45.spi_device_pass_cmd_filtering.1729979250
Short name	T425
Test name
Test status
Simulation time	2112125934 ps
CPU time	5.46 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	218608 kb
Host	smart-df216d16-b185-4182-b827-a6d30c2f2019
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729979250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1729979250
Directory	/workspace/45.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/45.spi_device_read_buffer_direct.305993312
Short name	T702
Test name
Test status
Simulation time	2484555334 ps
CPU time	9.93 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:46 PM PDT 24
Peak memory	222292 kb
Host	smart-485edea7-df45-4fe3-80b9-4438d4f66fb9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=305993312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire ct.305993312
Directory	/workspace/45.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/45.spi_device_stress_all.1420164116
Short name	T153
Test name
Test status
Simulation time	9943606371 ps
CPU time	47.17 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:30:28 PM PDT 24
Peak memory	237464 kb
Host	smart-3251f0fa-a1e6-47b9-bff5-78fd6e780a3b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420164116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre ss_all.1420164116
Directory	/workspace/45.spi_device_stress_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_all.1083148748
Short name	T790
Test name
Test status
Simulation time	18985712630 ps
CPU time	22.15 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:58 PM PDT 24
Peak memory	216136 kb
Host	smart-8d989593-8fa1-4921-9aee-dae6d3c67dba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083148748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1083148748
Directory	/workspace/45.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1443839071
Short name	T744
Test name
Test status
Simulation time	30937161017 ps
CPU time	24.11 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:30:00 PM PDT 24
Peak memory	216116 kb
Host	smart-296a7213-7b76-47f5-bc4a-3cdde9fff9e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443839071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1443839071
Directory	/workspace/45.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_rw.3842783907
Short name	T338
Test name
Test status
Simulation time	71162695 ps
CPU time	0.82 seconds
Started	May 14 01:29:32 PM PDT 24
Finished	May 14 01:29:34 PM PDT 24
Peak memory	205836 kb
Host	smart-ce684dfc-ae6b-4ee1-98e7-de509161c362
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842783907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3842783907
Directory	/workspace/45.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_sts_read.3281043176
Short name	T822
Test name
Test status
Simulation time	117877867 ps
CPU time	0.79 seconds
Started	May 14 01:29:31 PM PDT 24
Finished	May 14 01:29:33 PM PDT 24
Peak memory	205628 kb
Host	smart-1e0c865a-0860-468e-ba52-c0c201e9abd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281043176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3281043176
Directory	/workspace/45.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/45.spi_device_upload.1584613574
Short name	T441
Test name
Test status
Simulation time	413037330 ps
CPU time	2.24 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	215960 kb
Host	smart-1168fa21-a4b0-4376-8a8c-2a52939cf434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584613574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1584613574
Directory	/workspace/45.spi_device_upload/latest

Test location	/workspace/coverage/default/46.spi_device_alert_test.3462429011
Short name	T925
Test name
Test status
Simulation time	11030003 ps
CPU time	0.73 seconds
Started	May 14 01:29:41 PM PDT 24
Finished	May 14 01:29:44 PM PDT 24
Peak memory	204652 kb
Host	smart-a7f1cfcf-a04f-4921-9f64-7da17410279d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462429011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test. 3462429011
Directory	/workspace/46.spi_device_alert_test/latest

Test location	/workspace/coverage/default/46.spi_device_cfg_cmd.2341542158
Short name	T908
Test name
Test status
Simulation time	729053340 ps
CPU time	6.4 seconds
Started	May 14 01:29:41 PM PDT 24
Finished	May 14 01:29:49 PM PDT 24
Peak memory	234012 kb
Host	smart-138c1804-3025-4af3-902a-7ae20c8e5fa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341542158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2341542158
Directory	/workspace/46.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/46.spi_device_csb_read.3935253451
Short name	T803
Test name
Test status
Simulation time	30361270 ps
CPU time	0.8 seconds
Started	May 14 01:29:33 PM PDT 24
Finished	May 14 01:29:35 PM PDT 24
Peak memory	206768 kb
Host	smart-5d5a5343-c1be-4af4-a89c-5f53440f4a0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935253451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3935253451
Directory	/workspace/46.spi_device_csb_read/latest

Test location	/workspace/coverage/default/46.spi_device_flash_all.2376780527
Short name	T294
Test name
Test status
Simulation time	11316257320 ps
CPU time	44.05 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:30:27 PM PDT 24
Peak memory	249068 kb
Host	smart-1ac7c298-9bd8-459e-b2b0-224c5b6aed2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376780527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2376780527
Directory	/workspace/46.spi_device_flash_all/latest

Test location	/workspace/coverage/default/46.spi_device_flash_and_tpm.3638770666
Short name	T244
Test name
Test status
Simulation time	8351098521 ps
CPU time	40.88 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:30:24 PM PDT 24
Peak memory	240684 kb
Host	smart-e31995d6-285a-408b-bf8c-79a80fd0b407
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638770666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3638770666
Directory	/workspace/46.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1238815795
Short name	T655
Test name
Test status
Simulation time	5366050417 ps
CPU time	80.32 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:31:01 PM PDT 24
Peak memory	250056 kb
Host	smart-bd806b22-02e3-460e-98c8-829128e2554f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238815795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl e.1238815795
Directory	/workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/46.spi_device_flash_mode.2890101844
Short name	T323
Test name
Test status
Simulation time	5263022469 ps
CPU time	17.26 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:30:00 PM PDT 24
Peak memory	235856 kb
Host	smart-f0a5a398-4959-4420-af54-2a10909c7bae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890101844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2890101844
Directory	/workspace/46.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/46.spi_device_intercept.758255157
Short name	T486
Test name
Test status
Simulation time	63854910 ps
CPU time	2.27 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	232572 kb
Host	smart-a9fbe384-55d5-453e-acdf-49bcb9c881ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758255157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.758255157
Directory	/workspace/46.spi_device_intercept/latest

Test location	/workspace/coverage/default/46.spi_device_mailbox.279960117
Short name	T810
Test name
Test status
Simulation time	804869027 ps
CPU time	13.7 seconds
Started	May 14 01:29:42 PM PDT 24
Finished	May 14 01:29:57 PM PDT 24
Peak memory	234124 kb
Host	smart-2ce68513-98c8-4d06-9ce2-6d4ae5f164ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279960117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.279960117
Directory	/workspace/46.spi_device_mailbox/latest

Test location	/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3732774862
Short name	T534
Test name
Test status
Simulation time	2295785721 ps
CPU time	10.64 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:53 PM PDT 24
Peak memory	248160 kb
Host	smart-aa8e216b-6426-4eb4-978b-ada2ccf47f71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732774862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa p.3732774862
Directory	/workspace/46.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/46.spi_device_pass_cmd_filtering.4094793121
Short name	T493
Test name
Test status
Simulation time	655002804 ps
CPU time	5.81 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:49 PM PDT 24
Peak memory	218636 kb
Host	smart-3de00842-e0e0-4cea-ba04-95fe07d8f018
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094793121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4094793121
Directory	/workspace/46.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/46.spi_device_read_buffer_direct.4105759305
Short name	T440
Test name
Test status
Simulation time	856989703 ps
CPU time	4.72 seconds
Started	May 14 01:29:42 PM PDT 24
Finished	May 14 01:29:49 PM PDT 24
Peak memory	218480 kb
Host	smart-b4612a6f-9d8e-4772-8dba-a3a005a49402
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4105759305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir ect.4105759305
Directory	/workspace/46.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/46.spi_device_stress_all.1916455388
Short name	T941
Test name
Test status
Simulation time	2978994137 ps
CPU time	8.3 seconds
Started	May 14 01:29:39 PM PDT 24
Finished	May 14 01:29:50 PM PDT 24
Peak memory	219456 kb
Host	smart-9b7067a1-af31-4467-906f-32d4dea13e98
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916455388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre ss_all.1916455388
Directory	/workspace/46.spi_device_stress_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_all.2863536455
Short name	T130
Test name
Test status
Simulation time	16888974 ps
CPU time	0.74 seconds
Started	May 14 01:29:35 PM PDT 24
Finished	May 14 01:29:38 PM PDT 24
Peak memory	205456 kb
Host	smart-935589aa-9ecd-4a9c-89e8-89e364489cfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863536455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2863536455
Directory	/workspace/46.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1914175297
Short name	T358
Test name
Test status
Simulation time	18880240 ps
CPU time	0.72 seconds
Started	May 14 01:29:34 PM PDT 24
Finished	May 14 01:29:37 PM PDT 24
Peak memory	205444 kb
Host	smart-7fdc7568-f826-4160-ab44-2f4aaf0e021e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914175297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1914175297
Directory	/workspace/46.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_rw.2983191304
Short name	T341
Test name
Test status
Simulation time	946277076 ps
CPU time	2.81 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:43 PM PDT 24
Peak memory	216096 kb
Host	smart-69e5f80e-38b4-4a09-9fe9-eba1223f4bf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983191304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2983191304
Directory	/workspace/46.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_sts_read.919809670
Short name	T410
Test name
Test status
Simulation time	20838002 ps
CPU time	0.83 seconds
Started	May 14 01:29:39 PM PDT 24
Finished	May 14 01:29:42 PM PDT 24
Peak memory	205652 kb
Host	smart-c5c1d48f-4353-4543-b197-2c2ab3864884
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919809670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.919809670
Directory	/workspace/46.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/46.spi_device_upload.281560411
Short name	T178
Test name
Test status
Simulation time	28682331727 ps
CPU time	24.6 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:30:05 PM PDT 24
Peak memory	233864 kb
Host	smart-dd21b05f-6e33-45df-a2e2-26191d3a2cc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281560411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.281560411
Directory	/workspace/46.spi_device_upload/latest

Test location	/workspace/coverage/default/47.spi_device_alert_test.1827291567
Short name	T706
Test name
Test status
Simulation time	41140423 ps
CPU time	0.73 seconds
Started	May 14 01:29:45 PM PDT 24
Finished	May 14 01:29:46 PM PDT 24
Peak memory	205636 kb
Host	smart-8a52f58a-1ece-4533-a861-55bcf1a95538
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827291567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test. 1827291567
Directory	/workspace/47.spi_device_alert_test/latest

Test location	/workspace/coverage/default/47.spi_device_cfg_cmd.860102524
Short name	T614
Test name
Test status
Simulation time	1119330778 ps
CPU time	9.98 seconds
Started	May 14 01:29:43 PM PDT 24
Finished	May 14 01:29:54 PM PDT 24
Peak memory	233956 kb
Host	smart-8ff3dfda-1594-4122-976a-ea81270940a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860102524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.860102524
Directory	/workspace/47.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/47.spi_device_csb_read.1848606663
Short name	T624
Test name
Test status
Simulation time	53184881 ps
CPU time	0.78 seconds
Started	May 14 01:29:43 PM PDT 24
Finished	May 14 01:29:45 PM PDT 24
Peak memory	206476 kb
Host	smart-daf2c93b-4b17-423b-9b78-30af1b734869
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848606663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1848606663
Directory	/workspace/47.spi_device_csb_read/latest

Test location	/workspace/coverage/default/47.spi_device_flash_all.2504909735
Short name	T234
Test name
Test status
Simulation time	37372958715 ps
CPU time	259.95 seconds
Started	May 14 01:29:41 PM PDT 24
Finished	May 14 01:34:03 PM PDT 24
Peak memory	248992 kb
Host	smart-52de1a1d-9f7b-44aa-a43f-dd8c2c5b0402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504909735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2504909735
Directory	/workspace/47.spi_device_flash_all/latest

Test location	/workspace/coverage/default/47.spi_device_flash_and_tpm.4232517875
Short name	T123
Test name
Test status
Simulation time	31692428620 ps
CPU time	347.99 seconds
Started	May 14 01:29:41 PM PDT 24
Finished	May 14 01:35:31 PM PDT 24
Peak memory	256332 kb
Host	smart-5d9fb74b-1257-44de-8652-589bf89403ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232517875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4232517875
Directory	/workspace/47.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.219387148
Short name	T406
Test name
Test status
Simulation time	14890700725 ps
CPU time	108 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:31:31 PM PDT 24
Peak memory	240756 kb
Host	smart-a298ed50-102f-449a-ae4e-6c3bcff97c9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219387148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle .219387148
Directory	/workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/47.spi_device_flash_mode.2791622006
Short name	T615
Test name
Test status
Simulation time	9282795718 ps
CPU time	39.15 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:30:21 PM PDT 24
Peak memory	232644 kb
Host	smart-d77d8d40-17a0-4d70-9645-297bdd357e45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791622006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2791622006
Directory	/workspace/47.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/47.spi_device_intercept.3263125377
Short name	T948
Test name
Test status
Simulation time	144829869 ps
CPU time	2.45 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:45 PM PDT 24
Peak memory	224272 kb
Host	smart-7c8ddc3e-05b2-464d-a1e4-cdb3b12c378d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263125377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3263125377
Directory	/workspace/47.spi_device_intercept/latest

Test location	/workspace/coverage/default/47.spi_device_mailbox.4047846243
Short name	T445
Test name
Test status
Simulation time	31654864 ps
CPU time	2.24 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	221292 kb
Host	smart-6f1392dd-4bc5-4bd1-8f2c-af48d4d01109
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047846243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4047846243
Directory	/workspace/47.spi_device_mailbox/latest

Test location	/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.859931810
Short name	T60
Test name
Test status
Simulation time	12580002322 ps
CPU time	12.54 seconds
Started	May 14 01:29:41 PM PDT 24
Finished	May 14 01:29:56 PM PDT 24
Peak memory	239300 kb
Host	smart-10399027-624c-4442-8196-ac4299f76957
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859931810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap .859931810
Directory	/workspace/47.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/47.spi_device_pass_cmd_filtering.920657437
Short name	T500
Test name
Test status
Simulation time	2354860670 ps
CPU time	10.09 seconds
Started	May 14 01:29:44 PM PDT 24
Finished	May 14 01:29:55 PM PDT 24
Peak memory	238992 kb
Host	smart-cbd166f9-8def-4dbf-baf8-9a6985be3c2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920657437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.920657437
Directory	/workspace/47.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/47.spi_device_read_buffer_direct.3637545167
Short name	T921
Test name
Test status
Simulation time	1029569875 ps
CPU time	5.76 seconds
Started	May 14 01:29:39 PM PDT 24
Finished	May 14 01:29:47 PM PDT 24
Peak memory	222776 kb
Host	smart-076a89de-2369-40c6-9f88-02566495a307
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3637545167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir ect.3637545167
Directory	/workspace/47.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/47.spi_device_stress_all.4263950388
Short name	T79
Test name
Test status
Simulation time	64997988469 ps
CPU time	528.26 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:38:29 PM PDT 24
Peak memory	256036 kb
Host	smart-81a3eb7f-19bb-46ad-8a86-2a0a3205e486
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263950388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre ss_all.4263950388
Directory	/workspace/47.spi_device_stress_all/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_all.4292260291
Short name	T482
Test name
Test status
Simulation time	35923233859 ps
CPU time	49.84 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:30:32 PM PDT 24
Peak memory	216120 kb
Host	smart-017220da-4493-4ea8-b51d-693a1d007555
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292260291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4292260291
Directory	/workspace/47.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.659743597
Short name	T736
Test name
Test status
Simulation time	1839105454 ps
CPU time	8.44 seconds
Started	May 14 01:29:39 PM PDT 24
Finished	May 14 01:29:50 PM PDT 24
Peak memory	216032 kb
Host	smart-c6763ceb-46c3-4ef7-8f9f-7d0677b16bff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659743597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.659743597
Directory	/workspace/47.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_rw.934953427
Short name	T580
Test name
Test status
Simulation time	1140983744 ps
CPU time	1.49 seconds
Started	May 14 01:29:39 PM PDT 24
Finished	May 14 01:29:43 PM PDT 24
Peak memory	216088 kb
Host	smart-f6f5df29-d67f-4250-843b-82cbd2788846
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934953427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.934953427
Directory	/workspace/47.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_sts_read.2088994122
Short name	T521
Test name
Test status
Simulation time	18671101 ps
CPU time	0.77 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	205620 kb
Host	smart-08897c5d-2e30-45f0-b7e0-99db4e8e1335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088994122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2088994122
Directory	/workspace/47.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/47.spi_device_upload.1298821874
Short name	T641
Test name
Test status
Simulation time	204115468 ps
CPU time	3.5 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:46 PM PDT 24
Peak memory	235772 kb
Host	smart-5f2894df-49cd-446a-8674-64b91a40b199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298821874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1298821874
Directory	/workspace/47.spi_device_upload/latest

Test location	/workspace/coverage/default/48.spi_device_alert_test.1561971570
Short name	T872
Test name
Test status
Simulation time	45407366 ps
CPU time	0.71 seconds
Started	May 14 01:29:54 PM PDT 24
Finished	May 14 01:29:56 PM PDT 24
Peak memory	204624 kb
Host	smart-f53087f7-a28e-4644-a226-b83d644c9b0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561971570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test. 1561971570
Directory	/workspace/48.spi_device_alert_test/latest

Test location	/workspace/coverage/default/48.spi_device_cfg_cmd.372661640
Short name	T66
Test name
Test status
Simulation time	177972579 ps
CPU time	2.43 seconds
Started	May 14 01:29:54 PM PDT 24
Finished	May 14 01:29:57 PM PDT 24
Peak memory	235308 kb
Host	smart-a08c7238-7c43-4cf7-a34d-c92e8752de19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372661640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.372661640
Directory	/workspace/48.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/48.spi_device_csb_read.971382848
Short name	T728
Test name
Test status
Simulation time	56506894 ps
CPU time	0.77 seconds
Started	May 14 01:29:38 PM PDT 24
Finished	May 14 01:29:41 PM PDT 24
Peak memory	206476 kb
Host	smart-5b37c68f-9960-4370-ac15-753ea765a7ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971382848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.971382848
Directory	/workspace/48.spi_device_csb_read/latest

Test location	/workspace/coverage/default/48.spi_device_flash_all.488837596
Short name	T952
Test name
Test status
Simulation time	23176056090 ps
CPU time	164.27 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:32:36 PM PDT 24
Peak memory	240596 kb
Host	smart-bffbf753-c526-4d06-b202-3eca75d8d119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488837596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.488837596
Directory	/workspace/48.spi_device_flash_all/latest

Test location	/workspace/coverage/default/48.spi_device_flash_and_tpm.343790197
Short name	T522
Test name
Test status
Simulation time	5945828453 ps
CPU time	73.42 seconds
Started	May 14 01:29:52 PM PDT 24
Finished	May 14 01:31:06 PM PDT 24
Peak memory	249268 kb
Host	smart-d40b4fba-3448-4917-8154-24d43ae727e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343790197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.343790197
Directory	/workspace/48.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3911034589
Short name	T898
Test name
Test status
Simulation time	74953744321 ps
CPU time	690.98 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:41:22 PM PDT 24
Peak memory	261084 kb
Host	smart-e44e9646-f306-483a-a09d-5c6823e3e592
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911034589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl e.3911034589
Directory	/workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/48.spi_device_flash_mode.3650879085
Short name	T576
Test name
Test status
Simulation time	334225694 ps
CPU time	8.25 seconds
Started	May 14 01:29:48 PM PDT 24
Finished	May 14 01:29:57 PM PDT 24
Peak memory	233584 kb
Host	smart-022b03e2-8d35-4c88-8671-a6e8f506dc6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650879085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3650879085
Directory	/workspace/48.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/48.spi_device_intercept.1133214249
Short name	T942
Test name
Test status
Simulation time	13093565604 ps
CPU time	7.22 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:50 PM PDT 24
Peak memory	218324 kb
Host	smart-5066f826-1e20-4194-8948-1f02d7800f43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133214249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1133214249
Directory	/workspace/48.spi_device_intercept/latest

Test location	/workspace/coverage/default/48.spi_device_mailbox.1335187104
Short name	T549
Test name
Test status
Simulation time	671335723 ps
CPU time	7.2 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:29:59 PM PDT 24
Peak memory	227944 kb
Host	smart-e8f8f5f9-c104-4b90-bc8e-76db6eea35eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335187104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1335187104
Directory	/workspace/48.spi_device_mailbox/latest

Test location	/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.369080909
Short name	T233
Test name
Test status
Simulation time	1578872035 ps
CPU time	5.11 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:47 PM PDT 24
Peak memory	226700 kb
Host	smart-e188aa7d-15c9-4f27-83df-2f412835e004
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369080909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap .369080909
Directory	/workspace/48.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/48.spi_device_pass_cmd_filtering.1059858489
Short name	T866
Test name
Test status
Simulation time	64989812334 ps
CPU time	28.95 seconds
Started	May 14 01:29:42 PM PDT 24
Finished	May 14 01:30:13 PM PDT 24
Peak memory	219412 kb
Host	smart-2468ecf2-958f-4e56-8ebe-9c8c52bb8998
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059858489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1059858489
Directory	/workspace/48.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/48.spi_device_read_buffer_direct.1533704525
Short name	T434
Test name
Test status
Simulation time	201631160 ps
CPU time	4.87 seconds
Started	May 14 01:29:48 PM PDT 24
Finished	May 14 01:29:54 PM PDT 24
Peak memory	219884 kb
Host	smart-546b8fe0-f075-44d1-9baf-13bd327f4b84
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1533704525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir ect.1533704525
Directory	/workspace/48.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/48.spi_device_stress_all.1881510997
Short name	T414
Test name
Test status
Simulation time	51746242291 ps
CPU time	129.35 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:32:01 PM PDT 24
Peak memory	251020 kb
Host	smart-903e866d-a76a-40a4-80af-1fbf8c0a65db
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881510997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre ss_all.1881510997
Directory	/workspace/48.spi_device_stress_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_all.1184931013
Short name	T648
Test name
Test status
Simulation time	6901702200 ps
CPU time	42.18 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:30:24 PM PDT 24
Peak memory	216152 kb
Host	smart-2b155412-c5df-4fef-af4d-b014ca853ff4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184931013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1184931013
Directory	/workspace/48.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2763748643
Short name	T504
Test name
Test status
Simulation time	3070757298 ps
CPU time	8.81 seconds
Started	May 14 01:29:40 PM PDT 24
Finished	May 14 01:29:52 PM PDT 24
Peak memory	216028 kb
Host	smart-6c0d83a0-18c0-4128-a264-ffc7359f6726
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763748643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2763748643
Directory	/workspace/48.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_rw.3827972617
Short name	T877
Test name
Test status
Simulation time	1760669762 ps
CPU time	1.88 seconds
Started	May 14 01:29:39 PM PDT 24
Finished	May 14 01:29:43 PM PDT 24
Peak memory	216044 kb
Host	smart-4a282a61-7cbd-4196-90a8-759e20f88c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827972617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3827972617
Directory	/workspace/48.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_sts_read.766723745
Short name	T530
Test name
Test status
Simulation time	232310618 ps
CPU time	0.88 seconds
Started	May 14 01:29:42 PM PDT 24
Finished	May 14 01:29:45 PM PDT 24
Peak memory	205716 kb
Host	smart-3e771a96-6488-42cb-b844-4061cb86a58f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766723745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.766723745
Directory	/workspace/48.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/48.spi_device_upload.3619994057
Short name	T37
Test name
Test status
Simulation time	8034527059 ps
CPU time	23.31 seconds
Started	May 14 01:29:51 PM PDT 24
Finished	May 14 01:30:16 PM PDT 24
Peak memory	218696 kb
Host	smart-4041d9f2-21f3-492c-af7c-1f81cd819adb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619994057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3619994057
Directory	/workspace/48.spi_device_upload/latest

Test location	/workspace/coverage/default/49.spi_device_alert_test.299024364
Short name	T518
Test name
Test status
Simulation time	47219856 ps
CPU time	0.75 seconds
Started	May 14 01:29:52 PM PDT 24
Finished	May 14 01:29:53 PM PDT 24
Peak memory	205208 kb
Host	smart-c9f7c3b4-fe67-483f-9c16-00764515e786
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299024364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.299024364
Directory	/workspace/49.spi_device_alert_test/latest

Test location	/workspace/coverage/default/49.spi_device_cfg_cmd.2816034679
Short name	T163
Test name
Test status
Simulation time	588492944 ps
CPU time	5.5 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:29:57 PM PDT 24
Peak memory	221052 kb
Host	smart-2007075f-a4f9-4884-92e0-ea3d1cfd43e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816034679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2816034679
Directory	/workspace/49.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/49.spi_device_csb_read.2148263885
Short name	T716
Test name
Test status
Simulation time	17726178 ps
CPU time	0.75 seconds
Started	May 14 01:29:49 PM PDT 24
Finished	May 14 01:29:51 PM PDT 24
Peak memory	205404 kb
Host	smart-285ba621-cb55-4449-99ce-88293c76877b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148263885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2148263885
Directory	/workspace/49.spi_device_csb_read/latest

Test location	/workspace/coverage/default/49.spi_device_flash_all.1344084146
Short name	T588
Test name
Test status
Simulation time	131561318 ps
CPU time	0.92 seconds
Started	May 14 01:29:52 PM PDT 24
Finished	May 14 01:29:54 PM PDT 24
Peak memory	215948 kb
Host	smart-9055ddea-db3a-4d4e-9337-d2335535f2c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344084146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1344084146
Directory	/workspace/49.spi_device_flash_all/latest

Test location	/workspace/coverage/default/49.spi_device_flash_and_tpm.592892547
Short name	T467
Test name
Test status
Simulation time	11509610817 ps
CPU time	62.28 seconds
Started	May 14 01:29:54 PM PDT 24
Finished	May 14 01:30:57 PM PDT 24
Peak memory	249020 kb
Host	smart-4c93fb60-c87d-402d-aac3-e442845dca1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592892547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.592892547
Directory	/workspace/49.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4058669188
Short name	T756
Test name
Test status
Simulation time	12668889725 ps
CPU time	133.78 seconds
Started	May 14 01:29:54 PM PDT 24
Finished	May 14 01:32:09 PM PDT 24
Peak memory	248968 kb
Host	smart-c003152a-2ac0-4b92-8588-eb86f0fd4e45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058669188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl e.4058669188
Directory	/workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/49.spi_device_intercept.3531331707
Short name	T305
Test name
Test status
Simulation time	463800918 ps
CPU time	7.89 seconds
Started	May 14 01:29:52 PM PDT 24
Finished	May 14 01:30:01 PM PDT 24
Peak memory	219524 kb
Host	smart-957f9f77-fc33-4438-9898-38d6b875f0c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531331707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3531331707
Directory	/workspace/49.spi_device_intercept/latest

Test location	/workspace/coverage/default/49.spi_device_mailbox.3976412007
Short name	T487
Test name
Test status
Simulation time	8774573302 ps
CPU time	21.17 seconds
Started	May 14 01:29:54 PM PDT 24
Finished	May 14 01:30:16 PM PDT 24
Peak memory	229748 kb
Host	smart-b9561b44-6f12-4e3e-bd48-0eea3aa3c6b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976412007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3976412007
Directory	/workspace/49.spi_device_mailbox/latest

Test location	/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.149794776
Short name	T527
Test name
Test status
Simulation time	4534600409 ps
CPU time	10.41 seconds
Started	May 14 01:29:51 PM PDT 24
Finished	May 14 01:30:02 PM PDT 24
Peak memory	218396 kb
Host	smart-932f43d5-0b80-4e38-9665-20d712416dcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149794776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap .149794776
Directory	/workspace/49.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/49.spi_device_pass_cmd_filtering.3689871659
Short name	T468
Test name
Test status
Simulation time	1059673379 ps
CPU time	2.34 seconds
Started	May 14 01:29:51 PM PDT 24
Finished	May 14 01:29:54 PM PDT 24
Peak memory	217860 kb
Host	smart-0de6338b-c347-432e-9fcc-ba59e90301e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689871659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3689871659
Directory	/workspace/49.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/49.spi_device_read_buffer_direct.4208718969
Short name	T399
Test name
Test status
Simulation time	119342163 ps
CPU time	4.15 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:29:55 PM PDT 24
Peak memory	219832 kb
Host	smart-d9aac246-1fee-4467-b8a7-e91c812be37a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4208718969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir ect.4208718969
Directory	/workspace/49.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/49.spi_device_stress_all.3538078741
Short name	T499
Test name
Test status
Simulation time	70250824 ps
CPU time	1.19 seconds
Started	May 14 01:29:54 PM PDT 24
Finished	May 14 01:29:56 PM PDT 24
Peak memory	207688 kb
Host	smart-587d16da-a5ed-4f5a-8e32-4f18b8541172
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538078741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre ss_all.3538078741
Directory	/workspace/49.spi_device_stress_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_all.1190352825
Short name	T448
Test name
Test status
Simulation time	7643476069 ps
CPU time	42.66 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:30:34 PM PDT 24
Peak memory	216240 kb
Host	smart-81e2acec-a36d-4aab-b082-c44645255a32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190352825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1190352825
Directory	/workspace/49.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.337558329
Short name	T640
Test name
Test status
Simulation time	8389640966 ps
CPU time	13.08 seconds
Started	May 14 01:29:49 PM PDT 24
Finished	May 14 01:30:03 PM PDT 24
Peak memory	216120 kb
Host	smart-7d42f663-a518-4a23-9418-7dbb1a092e89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337558329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.337558329
Directory	/workspace/49.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_rw.3311273643
Short name	T393
Test name
Test status
Simulation time	1561228517 ps
CPU time	4.72 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:29:55 PM PDT 24
Peak memory	216164 kb
Host	smart-244c707c-3766-49ce-bfa8-e7e3c7ec7f51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311273643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3311273643
Directory	/workspace/49.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_sts_read.1746532454
Short name	T885
Test name
Test status
Simulation time	41784679 ps
CPU time	0.7 seconds
Started	May 14 01:29:50 PM PDT 24
Finished	May 14 01:29:52 PM PDT 24
Peak memory	205480 kb
Host	smart-4dc7798a-8dc3-4c90-8f3b-693dd3684ab8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746532454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1746532454
Directory	/workspace/49.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/49.spi_device_upload.1552384022
Short name	T311
Test name
Test status
Simulation time	10263811710 ps
CPU time	25.61 seconds
Started	May 14 01:29:55 PM PDT 24
Finished	May 14 01:30:21 PM PDT 24
Peak memory	241012 kb
Host	smart-55051e8e-b8b9-4727-86fd-278d51b8b3c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552384022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1552384022
Directory	/workspace/49.spi_device_upload/latest

Test location	/workspace/coverage/default/5.spi_device_alert_test.4283630312
Short name	T68
Test name
Test status
Simulation time	25437919 ps
CPU time	0.79 seconds
Started	May 14 01:27:36 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	205604 kb
Host	smart-84d7011c-798d-4bbc-9e43-79e69d75caaa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283630312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4 283630312
Directory	/workspace/5.spi_device_alert_test/latest

Test location	/workspace/coverage/default/5.spi_device_cfg_cmd.1948934566
Short name	T748
Test name
Test status
Simulation time	5730750222 ps
CPU time	6.8 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:42 PM PDT 24
Peak memory	220196 kb
Host	smart-a8f1c809-90ab-4d84-b060-528464eb3809
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948934566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1948934566
Directory	/workspace/5.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/5.spi_device_csb_read.1148075209
Short name	T497
Test name
Test status
Simulation time	80753817 ps
CPU time	0.81 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	206440 kb
Host	smart-c937290d-f9fe-4da3-8814-44a947c8a5e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148075209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1148075209
Directory	/workspace/5.spi_device_csb_read/latest

Test location	/workspace/coverage/default/5.spi_device_flash_all.2979441082
Short name	T622
Test name
Test status
Simulation time	24970300823 ps
CPU time	185.55 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:30:42 PM PDT 24
Peak memory	257100 kb
Host	smart-cc9fbfcc-6717-4a39-8d5f-1a28db390b89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979441082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2979441082
Directory	/workspace/5.spi_device_flash_all/latest

Test location	/workspace/coverage/default/5.spi_device_flash_and_tpm.3809479307
Short name	T703
Test name
Test status
Simulation time	77170968520 ps
CPU time	165.53 seconds
Started	May 14 01:27:33 PM PDT 24
Finished	May 14 01:30:23 PM PDT 24
Peak memory	240820 kb
Host	smart-8faa8151-a7e0-4fd1-9a5f-9633c0d3bcd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809479307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3809479307
Directory	/workspace/5.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.476673125
Short name	T400
Test name
Test status
Simulation time	1713248146 ps
CPU time	11.03 seconds
Started	May 14 01:27:35 PM PDT 24
Finished	May 14 01:27:49 PM PDT 24
Peak memory	221088 kb
Host	smart-c3abdb3e-46c3-4ab3-84c5-a4bb05dda1ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476673125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle. 476673125
Directory	/workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/5.spi_device_flash_mode.1514614633
Short name	T324
Test name
Test status
Simulation time	155404689 ps
CPU time	6.71 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:44 PM PDT 24
Peak memory	232396 kb
Host	smart-736f3403-4497-412b-9716-3d2fccde5191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514614633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1514614633
Directory	/workspace/5.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/5.spi_device_intercept.1010529980
Short name	T709
Test name
Test status
Simulation time	10694155816 ps
CPU time	28.65 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:28:02 PM PDT 24
Peak memory	220428 kb
Host	smart-33cdd8e2-eb3f-4b11-ad4f-619770c63884
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010529980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1010529980
Directory	/workspace/5.spi_device_intercept/latest

Test location	/workspace/coverage/default/5.spi_device_mailbox.4037111557
Short name	T899
Test name
Test status
Simulation time	15336039017 ps
CPU time	46.08 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:28:22 PM PDT 24
Peak memory	234144 kb
Host	smart-196b04e3-b43f-490d-bdaa-c4f776af5ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037111557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4037111557
Directory	/workspace/5.spi_device_mailbox/latest

Test location	/workspace/coverage/default/5.spi_device_pass_addr_payload_swap.392680737
Short name	T733
Test name
Test status
Simulation time	3305423928 ps
CPU time	5.94 seconds
Started	May 14 01:27:30 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	234204 kb
Host	smart-6777ab7b-ff7f-4936-a7b6-9434b27b5dca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392680737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap. 392680737
Directory	/workspace/5.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/5.spi_device_pass_cmd_filtering.1941978914
Short name	T749
Test name
Test status
Simulation time	10318153657 ps
CPU time	11.72 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:49 PM PDT 24
Peak memory	224008 kb
Host	smart-0c9715d4-3e2e-4e98-a645-2fbfdc455abe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941978914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1941978914
Directory	/workspace/5.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/5.spi_device_read_buffer_direct.702884155
Short name	T804
Test name
Test status
Simulation time	2718804428 ps
CPU time	7.28 seconds
Started	May 14 01:27:35 PM PDT 24
Finished	May 14 01:27:45 PM PDT 24
Peak memory	221728 kb
Host	smart-2307727b-aaf9-4a1b-af09-6a3c3fa1ca8a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=702884155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc t.702884155
Directory	/workspace/5.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_all.1207402482
Short name	T945
Test name
Test status
Simulation time	13708642 ps
CPU time	0.73 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:34 PM PDT 24
Peak memory	205460 kb
Host	smart-382b96b9-1450-462d-8045-a6b456ba3b71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207402482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1207402482
Directory	/workspace/5.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.782451887
Short name	T820
Test name
Test status
Simulation time	519954083 ps
CPU time	4.83 seconds
Started	May 14 01:27:31 PM PDT 24
Finished	May 14 01:27:38 PM PDT 24
Peak memory	216056 kb
Host	smart-c9b1f7fc-b6c8-413a-a9ef-db858d48b502
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782451887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.782451887
Directory	/workspace/5.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_rw.1319886355
Short name	T387
Test name
Test status
Simulation time	363306358 ps
CPU time	1.37 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	216068 kb
Host	smart-022124fd-2a7f-4282-9fc1-9e1bf8ace368
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319886355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1319886355
Directory	/workspace/5.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_sts_read.326256429
Short name	T791
Test name
Test status
Simulation time	41215860 ps
CPU time	0.72 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	205452 kb
Host	smart-9090cf84-b60d-4bde-9ffe-fb0cf3b5a26e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326256429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.326256429
Directory	/workspace/5.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/5.spi_device_upload.194431250
Short name	T837
Test name
Test status
Simulation time	1089292847 ps
CPU time	8.88 seconds
Started	May 14 01:27:34 PM PDT 24
Finished	May 14 01:27:46 PM PDT 24
Peak memory	234136 kb
Host	smart-42ee5a4e-9dac-46ca-ac38-23a482c91597
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194431250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.194431250
Directory	/workspace/5.spi_device_upload/latest

Test location	/workspace/coverage/default/6.spi_device_alert_test.377601245
Short name	T573
Test name
Test status
Simulation time	57968646 ps
CPU time	0.72 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:27:52 PM PDT 24
Peak memory	205276 kb
Host	smart-5c9fa469-2f2c-45bb-b09a-02e46f24d995
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377601245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.377601245
Directory	/workspace/6.spi_device_alert_test/latest

Test location	/workspace/coverage/default/6.spi_device_cfg_cmd.2574127964
Short name	T314
Test name
Test status
Simulation time	443771991 ps
CPU time	3.95 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:54 PM PDT 24
Peak memory	233168 kb
Host	smart-07336a07-dd8b-475f-ab51-d52ea796edc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574127964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2574127964
Directory	/workspace/6.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/6.spi_device_csb_read.753614274
Short name	T572
Test name
Test status
Simulation time	25325266 ps
CPU time	0.81 seconds
Started	May 14 01:27:35 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	206404 kb
Host	smart-9a92d763-4560-440e-90bb-20371a3671c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753614274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.753614274
Directory	/workspace/6.spi_device_csb_read/latest

Test location	/workspace/coverage/default/6.spi_device_flash_all.3955782667
Short name	T512
Test name
Test status
Simulation time	10927879785 ps
CPU time	80.53 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:29:11 PM PDT 24
Peak memory	248904 kb
Host	smart-1a15654e-6f5f-4ded-8871-63239c0518a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955782667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3955782667
Directory	/workspace/6.spi_device_flash_all/latest

Test location	/workspace/coverage/default/6.spi_device_flash_and_tpm.845447633
Short name	T663
Test name
Test status
Simulation time	55822910956 ps
CPU time	142.02 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:30:14 PM PDT 24
Peak memory	256916 kb
Host	smart-f5eeb6e7-d941-410e-8ca6-75f3405ecf95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845447633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.845447633
Directory	/workspace/6.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1591894667
Short name	T675
Test name
Test status
Simulation time	47914206979 ps
CPU time	83.09 seconds
Started	May 14 01:27:45 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	239768 kb
Host	smart-360030af-95ad-4135-9715-d11ef328d258
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591894667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle .1591894667
Directory	/workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/6.spi_device_flash_mode.45028752
Short name	T587
Test name
Test status
Simulation time	2651086097 ps
CPU time	12.64 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	240772 kb
Host	smart-5ef4503c-6d02-41b0-bd7a-6b704f69d8c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45028752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.45028752
Directory	/workspace/6.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/6.spi_device_intercept.1420116632
Short name	T462
Test name
Test status
Simulation time	95113511 ps
CPU time	2.11 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:27:54 PM PDT 24
Peak memory	215876 kb
Host	smart-229e515e-7144-46b4-a45b-b015375fb36c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420116632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1420116632
Directory	/workspace/6.spi_device_intercept/latest

Test location	/workspace/coverage/default/6.spi_device_mailbox.3895292864
Short name	T313
Test name
Test status
Simulation time	8876268550 ps
CPU time	27.05 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:28:19 PM PDT 24
Peak memory	248952 kb
Host	smart-1bf95f81-1db0-4d2a-937f-8e51457f3673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895292864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3895292864
Directory	/workspace/6.spi_device_mailbox/latest

Test location	/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2688075520
Short name	T289
Test name
Test status
Simulation time	473383693 ps
CPU time	4.07 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:52 PM PDT 24
Peak memory	218616 kb
Host	smart-b3e696e3-0553-4e6a-80e5-b8449195257f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688075520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap .2688075520
Directory	/workspace/6.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/6.spi_device_pass_cmd_filtering.2006198312
Short name	T496
Test name
Test status
Simulation time	114005160 ps
CPU time	2.37 seconds
Started	May 14 01:27:45 PM PDT 24
Finished	May 14 01:27:48 PM PDT 24
Peak memory	218376 kb
Host	smart-25253b93-0d02-4b30-8699-06bb70fc871a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006198312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2006198312
Directory	/workspace/6.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/6.spi_device_read_buffer_direct.3001224793
Short name	T827
Test name
Test status
Simulation time	934474614 ps
CPU time	5.16 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:54 PM PDT 24
Peak memory	221588 kb
Host	smart-ad4604fa-4ee2-4aa2-85e1-5803947aa19c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3001224793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire ct.3001224793
Directory	/workspace/6.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/6.spi_device_stress_all.1380050622
Short name	T241
Test name
Test status
Simulation time	21097839953 ps
CPU time	205.33 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:31:14 PM PDT 24
Peak memory	238684 kb
Host	smart-507f8126-0b32-41c0-8185-908692c7d31e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380050622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres s_all.1380050622
Directory	/workspace/6.spi_device_stress_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_all.2825740314
Short name	T428
Test name
Test status
Simulation time	31152598278 ps
CPU time	43.97 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:28:19 PM PDT 24
Peak memory	216128 kb
Host	smart-1deb7d18-aaa1-4d28-8e2a-6315909dfc2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825740314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2825740314
Directory	/workspace/6.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3781487412
Short name	T834
Test name
Test status
Simulation time	12069134 ps
CPU time	0.73 seconds
Started	May 14 01:27:36 PM PDT 24
Finished	May 14 01:27:39 PM PDT 24
Peak memory	205528 kb
Host	smart-b915d502-b878-4efb-8419-44085cf3ca17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781487412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3781487412
Directory	/workspace/6.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_rw.266273510
Short name	T931
Test name
Test status
Simulation time	142539445 ps
CPU time	2.24 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:37 PM PDT 24
Peak memory	207896 kb
Host	smart-82c108c5-0fb5-44ce-968f-5aa8428f976f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266273510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.266273510
Directory	/workspace/6.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_sts_read.1942027078
Short name	T382
Test name
Test status
Simulation time	60103653 ps
CPU time	0.89 seconds
Started	May 14 01:27:32 PM PDT 24
Finished	May 14 01:27:36 PM PDT 24
Peak memory	205828 kb
Host	smart-7177d53a-1693-43e5-9f56-927038abe165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942027078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1942027078
Directory	/workspace/6.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/6.spi_device_upload.3527080603
Short name	T164
Test name
Test status
Simulation time	4586672081 ps
CPU time	14.63 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	219836 kb
Host	smart-d9472bac-6f94-4642-8b7c-970e01735bae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527080603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3527080603
Directory	/workspace/6.spi_device_upload/latest

Test location	/workspace/coverage/default/7.spi_device_alert_test.1439432801
Short name	T863
Test name
Test status
Simulation time	14401208 ps
CPU time	0.77 seconds
Started	May 14 01:27:38 PM PDT 24
Finished	May 14 01:27:40 PM PDT 24
Peak memory	205260 kb
Host	smart-6fe3f8aa-9073-43f0-a108-8835ac8f026c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439432801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1 439432801
Directory	/workspace/7.spi_device_alert_test/latest

Test location	/workspace/coverage/default/7.spi_device_cfg_cmd.3259850477
Short name	T762
Test name
Test status
Simulation time	1254824954 ps
CPU time	6.41 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:27:57 PM PDT 24
Peak memory	219704 kb
Host	smart-e64850ce-308e-47cd-9b2f-01f51d29777f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259850477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3259850477
Directory	/workspace/7.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/7.spi_device_csb_read.2067970728
Short name	T511
Test name
Test status
Simulation time	31804066 ps
CPU time	0.79 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:51 PM PDT 24
Peak memory	206444 kb
Host	smart-b0b0c1e2-19c0-42ce-a552-b9d7f2c28dd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067970728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2067970728
Directory	/workspace/7.spi_device_csb_read/latest

Test location	/workspace/coverage/default/7.spi_device_flash_all.1189607721
Short name	T409
Test name
Test status
Simulation time	6543888860 ps
CPU time	9.76 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:01 PM PDT 24
Peak memory	235548 kb
Host	smart-1c8cbe54-656c-41f2-96ab-b210e5fe7dc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189607721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1189607721
Directory	/workspace/7.spi_device_flash_all/latest

Test location	/workspace/coverage/default/7.spi_device_flash_and_tpm.2070358248
Short name	T15
Test name
Test status
Simulation time	232818821272 ps
CPU time	65.68 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:28:54 PM PDT 24
Peak memory	217596 kb
Host	smart-8b14f87f-0a97-4ff5-992c-980722064853
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070358248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2070358248
Directory	/workspace/7.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1629094616
Short name	T20
Test name
Test status
Simulation time	3480937410 ps
CPU time	18.29 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	234864 kb
Host	smart-24ee3edb-832a-46a8-8a3c-5d0b738b9230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629094616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle .1629094616
Directory	/workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/7.spi_device_flash_mode.2774645450
Short name	T909
Test name
Test status
Simulation time	773269285 ps
CPU time	3.57 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:51 PM PDT 24
Peak memory	224328 kb
Host	smart-9d91d554-7bf5-40f2-acf3-1bd8e06b3c9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774645450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2774645450
Directory	/workspace/7.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/7.spi_device_intercept.3148633859
Short name	T603
Test name
Test status
Simulation time	118913919 ps
CPU time	4.28 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	233644 kb
Host	smart-7e6d03ef-4865-4363-a8ec-1eab122d70c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148633859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3148633859
Directory	/workspace/7.spi_device_intercept/latest

Test location	/workspace/coverage/default/7.spi_device_mailbox.2505597262
Short name	T870
Test name
Test status
Simulation time	150315161 ps
CPU time	2.99 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	218392 kb
Host	smart-5588bfad-ea43-429b-9fd4-c6899c19ca18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505597262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2505597262
Directory	/workspace/7.spi_device_mailbox/latest

Test location	/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3994545124
Short name	T800
Test name
Test status
Simulation time	163871997 ps
CPU time	3.61 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:54 PM PDT 24
Peak memory	224228 kb
Host	smart-ddb2443e-f64a-4cec-bbdc-57a2b5cbae5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994545124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap .3994545124
Directory	/workspace/7.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/7.spi_device_pass_cmd_filtering.745307931
Short name	T570
Test name
Test status
Simulation time	585217148 ps
CPU time	7.45 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:57 PM PDT 24
Peak memory	220060 kb
Host	smart-3f00d0b1-7092-4c46-8e40-99d1a6212d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745307931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.745307931
Directory	/workspace/7.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/7.spi_device_read_buffer_direct.1902542038
Short name	T437
Test name
Test status
Simulation time	695717594 ps
CPU time	5.94 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:56 PM PDT 24
Peak memory	221176 kb
Host	smart-b2efc3b0-3ef4-44d9-a57f-1a4bc85e620a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1902542038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire ct.1902542038
Directory	/workspace/7.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/7.spi_device_stress_all.2652959853
Short name	T254
Test name
Test status
Simulation time	7181806295 ps
CPU time	83.67 seconds
Started	May 14 01:27:44 PM PDT 24
Finished	May 14 01:29:09 PM PDT 24
Peak memory	255880 kb
Host	smart-412d2440-e1f7-4af2-ac28-ba4de1331b23
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652959853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres s_all.2652959853
Directory	/workspace/7.spi_device_stress_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_all.3457563124
Short name	T691
Test name
Test status
Simulation time	2594435470 ps
CPU time	21.1 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:28:08 PM PDT 24
Peak memory	216420 kb
Host	smart-aee63af7-548a-4c88-a3a7-a3c258bd9ba3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457563124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3457563124
Directory	/workspace/7.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3330994001
Short name	T412
Test name
Test status
Simulation time	4034539788 ps
CPU time	2.64 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:50 PM PDT 24
Peak memory	216076 kb
Host	smart-95d64703-261f-4c30-b21a-e6119bac2ace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330994001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3330994001
Directory	/workspace/7.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_rw.3591090166
Short name	T451
Test name
Test status
Simulation time	157467588 ps
CPU time	2.33 seconds
Started	May 14 01:27:44 PM PDT 24
Finished	May 14 01:27:47 PM PDT 24
Peak memory	216136 kb
Host	smart-8a068555-dd41-4118-8ced-373fde3dae4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591090166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3591090166
Directory	/workspace/7.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_sts_read.2392660317
Short name	T830
Test name
Test status
Simulation time	201062727 ps
CPU time	0.9 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:49 PM PDT 24
Peak memory	205708 kb
Host	smart-754a7f62-6fc3-4d9b-939d-7e816eb2302b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392660317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2392660317
Directory	/workspace/7.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/7.spi_device_upload.2703227126
Short name	T288
Test name
Test status
Simulation time	493681765 ps
CPU time	8.89 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:28:01 PM PDT 24
Peak memory	229788 kb
Host	smart-18e70676-57ba-4c97-b150-9e876da0e60f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703227126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2703227126
Directory	/workspace/7.spi_device_upload/latest

Test location	/workspace/coverage/default/8.spi_device_alert_test.1903460125
Short name	T449
Test name
Test status
Simulation time	15194540 ps
CPU time	0.71 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:27:52 PM PDT 24
Peak memory	205168 kb
Host	smart-879c6dc9-8ba1-4029-ae86-b2c8efe651a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903460125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1 903460125
Directory	/workspace/8.spi_device_alert_test/latest

Test location	/workspace/coverage/default/8.spi_device_cfg_cmd.1130716931
Short name	T217
Test name
Test status
Simulation time	35517402 ps
CPU time	2.45 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:49 PM PDT 24
Peak memory	233544 kb
Host	smart-66a574c5-f775-4ee1-bf0b-e865bb8868b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130716931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1130716931
Directory	/workspace/8.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/8.spi_device_csb_read.864480731
Short name	T62
Test name
Test status
Simulation time	92644997 ps
CPU time	0.78 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:49 PM PDT 24
Peak memory	206396 kb
Host	smart-b502da74-62ad-4633-bad9-4e37a3fd4697
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864480731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.864480731
Directory	/workspace/8.spi_device_csb_read/latest

Test location	/workspace/coverage/default/8.spi_device_flash_all.1842048117
Short name	T474
Test name
Test status
Simulation time	60685927612 ps
CPU time	113.67 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:29:43 PM PDT 24
Peak memory	249520 kb
Host	smart-2dd0b84d-2935-4c12-8493-dc983adbe348
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842048117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1842048117
Directory	/workspace/8.spi_device_flash_all/latest

Test location	/workspace/coverage/default/8.spi_device_flash_and_tpm.2082473218
Short name	T897
Test name
Test status
Simulation time	94128608123 ps
CPU time	208.63 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:31:21 PM PDT 24
Peak memory	249268 kb
Host	smart-a90642a5-eb1f-44cb-ab08-33f93a8bb0d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082473218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2082473218
Directory	/workspace/8.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3495863971
Short name	T43
Test name
Test status
Simulation time	82548805778 ps
CPU time	174.04 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:30:45 PM PDT 24
Peak memory	239820 kb
Host	smart-033943f6-0cf0-4ffa-b670-0772f01950d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495863971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle .3495863971
Directory	/workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/8.spi_device_flash_mode.2437535482
Short name	T366
Test name
Test status
Simulation time	1350583528 ps
CPU time	18.79 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:10 PM PDT 24
Peak memory	235208 kb
Host	smart-1c83b100-a5fa-4326-97e6-b15ed31b4739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437535482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2437535482
Directory	/workspace/8.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/8.spi_device_intercept.3472437713
Short name	T631
Test name
Test status
Simulation time	7449705549 ps
CPU time	19.62 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:10 PM PDT 24
Peak memory	218332 kb
Host	smart-1869846d-de2f-45a8-922a-46c770125563
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472437713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3472437713
Directory	/workspace/8.spi_device_intercept/latest

Test location	/workspace/coverage/default/8.spi_device_mailbox.436298326
Short name	T794
Test name
Test status
Simulation time	17700323029 ps
CPU time	82.29 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:29:12 PM PDT 24
Peak memory	230800 kb
Host	smart-aee1eaf4-b20a-4473-8a3e-b4f7002d1381
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436298326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.436298326
Directory	/workspace/8.spi_device_mailbox/latest

Test location	/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.288247504
Short name	T242
Test name
Test status
Simulation time	13919311598 ps
CPU time	14.98 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:28:04 PM PDT 24
Peak memory	221876 kb
Host	smart-a104bed0-30ad-4d63-ac3c-285398712907
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288247504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap. 288247504
Directory	/workspace/8.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/8.spi_device_pass_cmd_filtering.1418560005
Short name	T196
Test name
Test status
Simulation time	7523705945 ps
CPU time	12.46 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	227860 kb
Host	smart-51106582-63f8-49df-a68e-cb596e796cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418560005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1418560005
Directory	/workspace/8.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/8.spi_device_read_buffer_direct.3263543669
Short name	T772
Test name
Test status
Simulation time	2118637365 ps
CPU time	5.29 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:58 PM PDT 24
Peak memory	222240 kb
Host	smart-bec1be69-0205-4025-85b1-ffd7fb217544
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3263543669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire ct.3263543669
Directory	/workspace/8.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/8.spi_device_stress_all.2867627186
Short name	T169
Test name
Test status
Simulation time	27714137937 ps
CPU time	355.98 seconds
Started	May 14 01:27:51 PM PDT 24
Finished	May 14 01:33:49 PM PDT 24
Peak memory	270656 kb
Host	smart-ed94ba54-fb84-4723-858b-abef81e1d304
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867627186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres s_all.2867627186
Directory	/workspace/8.spi_device_stress_all/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_all.3178490024
Short name	T911
Test name
Test status
Simulation time	5844225894 ps
CPU time	23.76 seconds
Started	May 14 01:27:51 PM PDT 24
Finished	May 14 01:28:17 PM PDT 24
Peak memory	216180 kb
Host	smart-013d62a2-2ff0-422e-96e3-9fc97ee7e383
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178490024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3178490024
Directory	/workspace/8.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1590437755
Short name	T408
Test name
Test status
Simulation time	704404826 ps
CPU time	5.33 seconds
Started	May 14 01:27:46 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	216008 kb
Host	smart-7b530b48-a6a0-44f9-8ea5-c10e4070e416
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590437755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1590437755
Directory	/workspace/8.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_rw.615855156
Short name	T349
Test name
Test status
Simulation time	19636793 ps
CPU time	0.85 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:27:50 PM PDT 24
Peak memory	206508 kb
Host	smart-660ec47a-da4d-4bac-807d-56923033c19d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615855156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.615855156
Directory	/workspace/8.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_sts_read.3668044188
Short name	T644
Test name
Test status
Simulation time	66916128 ps
CPU time	0.88 seconds
Started	May 14 01:27:44 PM PDT 24
Finished	May 14 01:27:46 PM PDT 24
Peak memory	205676 kb
Host	smart-95bb4a49-0ad1-4d4a-8d60-2a9c2b90013c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668044188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3668044188
Directory	/workspace/8.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/8.spi_device_upload.1451998992
Short name	T892
Test name
Test status
Simulation time	2140715816 ps
CPU time	14.99 seconds
Started	May 14 01:27:47 PM PDT 24
Finished	May 14 01:28:05 PM PDT 24
Peak memory	218084 kb
Host	smart-83134355-16ac-4b51-afd5-7e6deffe380f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451998992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1451998992
Directory	/workspace/8.spi_device_upload/latest

Test location	/workspace/coverage/default/9.spi_device_alert_test.1405742899
Short name	T623
Test name
Test status
Simulation time	232291557 ps
CPU time	0.74 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	205588 kb
Host	smart-d7f8437a-0c66-4164-a2db-b875c2adbc0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405742899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1 405742899
Directory	/workspace/9.spi_device_alert_test/latest

Test location	/workspace/coverage/default/9.spi_device_cfg_cmd.795610284
Short name	T582
Test name
Test status
Simulation time	271744274 ps
CPU time	2.66 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:55 PM PDT 24
Peak memory	233908 kb
Host	smart-4f37be1b-2691-4d94-b0bc-e4207527fe3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795610284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.795610284
Directory	/workspace/9.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/9.spi_device_csb_read.1590121133
Short name	T605
Test name
Test status
Simulation time	73800839 ps
CPU time	0.81 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	206352 kb
Host	smart-95408b28-e525-460e-acd9-740a249de8e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590121133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1590121133
Directory	/workspace/9.spi_device_csb_read/latest

Test location	/workspace/coverage/default/9.spi_device_flash_all.2880111240
Short name	T177
Test name
Test status
Simulation time	27042124120 ps
CPU time	220.51 seconds
Started	May 14 01:27:54 PM PDT 24
Finished	May 14 01:31:36 PM PDT 24
Peak memory	256920 kb
Host	smart-d4e1b425-8d92-4019-8ce1-c9ff77f02817
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880111240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2880111240
Directory	/workspace/9.spi_device_flash_all/latest

Test location	/workspace/coverage/default/9.spi_device_flash_and_tpm.1028282331
Short name	T886
Test name
Test status
Simulation time	2421104342 ps
CPU time	32.54 seconds
Started	May 14 01:27:54 PM PDT 24
Finished	May 14 01:28:28 PM PDT 24
Peak memory	224432 kb
Host	smart-8cac06c8-c99f-4bfc-8d73-efbc73ea003e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028282331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1028282331
Directory	/workspace/9.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.928511379
Short name	T464
Test name
Test status
Simulation time	4006388458 ps
CPU time	35.28 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:28:27 PM PDT 24
Peak memory	224380 kb
Host	smart-373d990f-9d1a-4264-86a8-a8904b7db28e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928511379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle. 928511379
Directory	/workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/9.spi_device_flash_mode.3699302541
Short name	T903
Test name
Test status
Simulation time	788351243 ps
CPU time	4.08 seconds
Started	May 14 01:27:53 PM PDT 24
Finished	May 14 01:27:58 PM PDT 24
Peak memory	224320 kb
Host	smart-59e5b655-ad51-4c17-803b-d93ba6907e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699302541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3699302541
Directory	/workspace/9.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/9.spi_device_intercept.1592700561
Short name	T181
Test name
Test status
Simulation time	2799534278 ps
CPU time	26.18 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:28:17 PM PDT 24
Peak memory	219408 kb
Host	smart-edae4e68-17ab-4860-8329-b3e354d9a643
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592700561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1592700561
Directory	/workspace/9.spi_device_intercept/latest

Test location	/workspace/coverage/default/9.spi_device_mailbox.3106999784
Short name	T502
Test name
Test status
Simulation time	5466888242 ps
CPU time	31.52 seconds
Started	May 14 01:27:49 PM PDT 24
Finished	May 14 01:28:24 PM PDT 24
Peak memory	218504 kb
Host	smart-85cf10e4-5717-4428-8702-b44976d2000a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106999784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3106999784
Directory	/workspace/9.spi_device_mailbox/latest

Test location	/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.640748564
Short name	T470
Test name
Test status
Simulation time	8335480116 ps
CPU time	8.13 seconds
Started	May 14 01:27:54 PM PDT 24
Finished	May 14 01:28:03 PM PDT 24
Peak memory	233572 kb
Host	smart-6abb144c-853a-4f09-9303-a298a0cdbea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640748564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap. 640748564
Directory	/workspace/9.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/9.spi_device_pass_cmd_filtering.1864209798
Short name	T40
Test name
Test status
Simulation time	9453847269 ps
CPU time	15.74 seconds
Started	May 14 01:27:51 PM PDT 24
Finished	May 14 01:28:09 PM PDT 24
Peak memory	239080 kb
Host	smart-0d24b56c-c778-4909-84d1-db7102cbd246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864209798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1864209798
Directory	/workspace/9.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/9.spi_device_read_buffer_direct.4241587223
Short name	T402
Test name
Test status
Simulation time	1441016619 ps
CPU time	5.59 seconds
Started	May 14 01:27:52 PM PDT 24
Finished	May 14 01:27:59 PM PDT 24
Peak memory	222580 kb
Host	smart-e4737466-f702-4c5a-bd6e-98a7561bb830
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4241587223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire ct.4241587223
Directory	/workspace/9.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/9.spi_device_stress_all.945766341
Short name	T248
Test name
Test status
Simulation time	93369703496 ps
CPU time	218.05 seconds
Started	May 14 01:27:54 PM PDT 24
Finished	May 14 01:31:33 PM PDT 24
Peak memory	253772 kb
Host	smart-c2c75049-3ac1-4c9c-9fd9-9df9bb374472
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945766341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress _all.945766341
Directory	/workspace/9.spi_device_stress_all/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_all.4238274528
Short name	T771
Test name
Test status
Simulation time	1570842080 ps
CPU time	2.52 seconds
Started	May 14 01:27:48 PM PDT 24
Finished	May 14 01:27:53 PM PDT 24
Peak memory	216256 kb
Host	smart-d577a235-1993-420c-b9d7-81e6ecc10faa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238274528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4238274528
Directory	/workspace/9.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3469635748
Short name	T861
Test name
Test status
Simulation time	4097190001 ps
CPU time	5.15 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:57 PM PDT 24
Peak memory	216164 kb
Host	smart-7e12fa3e-62ff-467b-a01f-acc8d07fc2c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469635748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3469635748
Directory	/workspace/9.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_rw.3442538155
Short name	T711
Test name
Test status
Simulation time	69479805 ps
CPU time	4.33 seconds
Started	May 14 01:27:52 PM PDT 24
Finished	May 14 01:27:58 PM PDT 24
Peak memory	216216 kb
Host	smart-b2f30fc0-6478-465f-8962-22dcd08ebd3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442538155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3442538155
Directory	/workspace/9.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_sts_read.2659406435
Short name	T650
Test name
Test status
Simulation time	24542421 ps
CPU time	0.75 seconds
Started	May 14 01:27:50 PM PDT 24
Finished	May 14 01:27:54 PM PDT 24
Peak memory	205648 kb
Host	smart-71f8e7e3-3e64-48dc-850c-b3d10dc22eaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659406435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2659406435
Directory	/workspace/9.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/9.spi_device_upload.1153772590
Short name	T913
Test name
Test status
Simulation time	211892183 ps
CPU time	4.39 seconds
Started	May 14 01:27:54 PM PDT 24
Finished	May 14 01:27:59 PM PDT 24
Peak memory	233676 kb
Host	smart-aa078329-6fbd-41fe-a298-71ddd38870a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153772590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1153772590
Directory	/workspace/9.spi_device_upload/latest