Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3602558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3988720

1

T1

882

T2

18127

T3

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4320894	1			T1	6		T2	10831		T3	3600
values[0x0]	1633495	1			T1	433		T2	8863		T3	25
values[0x1]	1636889	1			T1	448		T2	9009		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2559632	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5031646

1

T1

883

T2

21367

T3

1223

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28169	1			T2	107		T3	13		T5	108
valid_sources[0x01]	32732	1			T2	126		T3	11		T5	126
valid_sources[0x02]	29222	1			T2	100		T3	17		T5	110
valid_sources[0x03]	35677	1			T2	101		T3	9		T5	144
valid_sources[0x04]	27853	1			T2	106		T3	21		T5	97
valid_sources[0x05]	28401	1			T2	124		T3	18		T4	32
valid_sources[0x06]	35455	1			T1	23		T2	104		T3	10
valid_sources[0x07]	41679	1			T2	119		T3	15		T5	105
valid_sources[0x08]	30067	1			T2	139		T3	16		T4	10
valid_sources[0x09]	26073	1			T2	109		T3	15		T5	121
valid_sources[0x0a]	30949	1			T2	111		T3	10		T5	116
valid_sources[0x0b]	30881	1			T1	7		T2	111		T3	9
valid_sources[0x0c]	30671	1			T2	108		T3	19		T4	1
valid_sources[0x0d]	28890	1			T2	103		T3	8		T5	141
valid_sources[0x0e]	32797	1			T1	13		T2	110		T3	19
valid_sources[0x0f]	29024	1			T2	121		T3	13		T5	106
valid_sources[0x10]	30620	1			T1	22		T2	105		T3	17
valid_sources[0x11]	26285	1			T2	100		T3	11		T5	106
valid_sources[0x12]	27430	1			T2	114		T3	13		T5	122
valid_sources[0x13]	26717	1			T2	110		T3	19		T5	91
valid_sources[0x14]	29224	1			T2	135		T3	12		T4	10
valid_sources[0x15]	29700	1			T2	97		T3	12		T4	22
valid_sources[0x16]	32338	1			T2	105		T3	18		T5	144
valid_sources[0x17]	28200	1			T2	107		T3	23		T5	107
valid_sources[0x18]	27436	1			T2	134		T3	13		T5	154
valid_sources[0x19]	29893	1			T1	3		T2	98		T3	10
valid_sources[0x1a]	31749	1			T1	17		T2	109		T3	15
valid_sources[0x1b]	26222	1			T2	125		T3	19		T5	141
valid_sources[0x1c]	28731	1			T2	104		T3	13		T5	111
valid_sources[0x1d]	33840	1			T2	98		T3	16		T5	117
valid_sources[0x1e]	31034	1			T2	123		T3	15		T5	111
valid_sources[0x1f]	28653	1			T2	115		T3	16		T5	120
valid_sources[0x20]	29068	1			T2	115		T3	18		T4	9
valid_sources[0x21]	28292	1			T2	101		T3	5		T5	110
valid_sources[0x22]	26566	1			T2	104		T3	13		T5	124
valid_sources[0x23]	29285	1			T1	3		T2	106		T3	10
valid_sources[0x24]	27218	1			T2	95		T3	15		T5	129
valid_sources[0x25]	29220	1			T2	102		T3	14		T4	3
valid_sources[0x26]	30052	1			T2	104		T3	10		T5	109
valid_sources[0x27]	32113	1			T2	124		T3	6		T5	128
valid_sources[0x28]	26968	1			T2	101		T3	15		T5	140
valid_sources[0x29]	30894	1			T1	43		T2	106		T3	12
valid_sources[0x2a]	29818	1			T2	115		T3	19		T5	122
valid_sources[0x2b]	26468	1			T1	16		T2	104		T3	10
valid_sources[0x2c]	29591	1			T2	110		T3	16		T5	132
valid_sources[0x2d]	27043	1			T1	5		T2	115		T3	13
valid_sources[0x2e]	28974	1			T1	6		T2	92		T3	16
valid_sources[0x2f]	28655	1			T2	109		T3	13		T5	150
valid_sources[0x30]	26787	1			T2	95		T3	14		T5	128
valid_sources[0x31]	31404	1			T1	4		T2	104		T3	9
valid_sources[0x32]	31331	1			T2	114		T3	18		T4	4
valid_sources[0x33]	31210	1			T2	125		T3	20		T5	90
valid_sources[0x34]	31750	1			T1	1		T2	135		T3	13
valid_sources[0x35]	29064	1			T2	127		T3	11		T4	16
valid_sources[0x36]	33507	1			T2	121		T3	13		T4	19
valid_sources[0x37]	28966	1			T1	5		T2	108		T3	10
valid_sources[0x38]	30226	1			T1	11		T2	104		T3	8
valid_sources[0x39]	30244	1			T2	112		T3	28		T5	115
valid_sources[0x3a]	31369	1			T2	96		T3	19		T4	11
valid_sources[0x3b]	27352	1			T2	138		T3	17		T5	128
valid_sources[0x3c]	27740	1			T2	111		T3	8		T5	113
valid_sources[0x3d]	31694	1			T1	6		T2	129		T3	16
valid_sources[0x3e]	28204	1			T2	123		T3	15		T5	136
valid_sources[0x3f]	29148	1			T1	1		T2	112		T3	12
valid_sources[0x40]	30424	1			T2	115		T3	20		T4	9
valid_sources[0x41]	29281	1			T2	117		T3	10		T4	8
valid_sources[0x42]	26770	1			T1	16		T2	103		T3	13
valid_sources[0x43]	28110	1			T2	116		T3	9		T5	120
valid_sources[0x44]	31017	1			T2	114		T3	13		T4	9
valid_sources[0x45]	30188	1			T1	4		T2	127		T3	20
valid_sources[0x46]	28406	1			T2	105		T3	18		T5	123
valid_sources[0x47]	30803	1			T2	108		T3	10		T4	15
valid_sources[0x48]	29692	1			T2	110		T3	19		T5	108
valid_sources[0x49]	35728	1			T2	102		T3	14		T5	129
valid_sources[0x4a]	27809	1			T2	123		T3	22		T5	121
valid_sources[0x4b]	25897	1			T2	91		T3	21		T5	131
valid_sources[0x4c]	28074	1			T1	10		T2	103		T3	18
valid_sources[0x4d]	28568	1			T2	115		T3	13		T5	127
valid_sources[0x4e]	29005	1			T1	41		T2	141		T3	15
valid_sources[0x4f]	25429	1			T2	127		T3	16		T5	133
valid_sources[0x50]	35006	1			T2	112		T3	12		T5	117
valid_sources[0x51]	30217	1			T1	4		T2	102		T3	15
valid_sources[0x52]	39061	1			T1	4		T2	97		T3	12
valid_sources[0x53]	28109	1			T2	112		T3	15		T4	20
valid_sources[0x54]	27489	1			T2	109		T3	13		T5	140
valid_sources[0x55]	29229	1			T2	112		T3	8		T5	105
valid_sources[0x56]	28198	1			T2	107		T3	14		T4	8
valid_sources[0x57]	27657	1			T2	107		T3	18		T5	122
valid_sources[0x58]	35371	1			T2	116		T3	16		T5	93
valid_sources[0x59]	29445	1			T2	115		T3	16		T5	89
valid_sources[0x5a]	26971	1			T2	130		T3	13		T4	4
valid_sources[0x5b]	28785	1			T2	108		T3	18		T4	18
valid_sources[0x5c]	28864	1			T2	128		T3	15		T5	160
valid_sources[0x5d]	30160	1			T2	129		T3	13		T5	138
valid_sources[0x5e]	29233	1			T2	118		T3	15		T5	99
valid_sources[0x5f]	30172	1			T2	113		T3	15		T5	144
valid_sources[0x60]	28246	1			T2	131		T3	15		T5	128
valid_sources[0x61]	31299	1			T2	128		T3	22		T5	102
valid_sources[0x62]	34514	1			T2	115		T3	15		T4	8
valid_sources[0x63]	32422	1			T1	25		T2	92		T3	8
valid_sources[0x64]	28388	1			T2	108		T3	15		T5	190
valid_sources[0x65]	27811	1			T1	12		T2	101		T3	17
valid_sources[0x66]	26305	1			T1	3		T2	110		T3	11
valid_sources[0x67]	29291	1			T1	3		T2	123		T3	22
valid_sources[0x68]	28600	1			T2	138		T3	12		T5	121
valid_sources[0x69]	28429	1			T1	4		T2	125		T3	18
valid_sources[0x6a]	28078	1			T2	126		T3	21		T4	18
valid_sources[0x6b]	28710	1			T2	123		T3	14		T5	141
valid_sources[0x6c]	29721	1			T2	99		T3	9		T4	29
valid_sources[0x6d]	26807	1			T2	128		T3	19		T5	123
valid_sources[0x6e]	28048	1			T2	116		T3	11		T4	5
valid_sources[0x6f]	29443	1			T2	98		T3	14		T5	106
valid_sources[0x70]	29476	1			T2	114		T3	23		T4	1
valid_sources[0x71]	29867	1			T1	13		T2	106		T3	18
valid_sources[0x72]	31047	1			T1	41		T2	113		T3	16
valid_sources[0x73]	26992	1			T1	9		T2	119		T3	7
valid_sources[0x74]	32030	1			T1	7		T2	105		T3	15
valid_sources[0x75]	29705	1			T2	121		T3	13		T4	1
valid_sources[0x76]	26704	1			T2	116		T3	18		T5	124
valid_sources[0x77]	26772	1			T1	6		T2	125		T3	11
valid_sources[0x78]	28144	1			T2	105		T3	13		T5	103
valid_sources[0x79]	29741	1			T1	4		T2	122		T3	21
valid_sources[0x7a]	30097	1			T2	99		T3	11		T4	22
valid_sources[0x7b]	28566	1			T2	86		T3	15		T4	11
valid_sources[0x7c]	68280	1			T2	130		T3	12		T4	12
valid_sources[0x7d]	29595	1			T1	20		T2	128		T3	6
valid_sources[0x7e]	30003	1			T1	2		T2	121		T3	19
valid_sources[0x7f]	26767	1			T2	93		T3	12		T5	125
valid_sources[0x80]	26574	1			T1	14		T2	104		T3	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1046874

1

T1

3

T2

1823

T3

31

values[0x0]

all_enables

biggest_size

1481912

1

T1

432

T2

8158

T3

14

values[0x1]

all_enables

biggest_size

1459934

1

T1

447

T2

8146

T3

16