Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3624826

1

T1

5

T2

10576

T3

3595

full_word

3989830

1

T1

882

T2

18127

T3

61

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7614276	1			T1	887		T2	28703		T3	3656
auto[TlIntgErrCmd]	136	1			T55	6		T89	3		T90	5
auto[TlIntgErrData]	129	1			T55	3		T89	4		T90	4
auto[TlIntgErrBoth]	115	1			T55	1		T89	3		T90	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4324233

1

T1

6

T2

10831

T3

3600

auto[1]

3290423

1

T1

881

T2

17872

T3

56

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3276943	1			T1	3		T2	9008		T3	3569
auto[TlIntgErrNone]	partial	auto[1]	347535	1			T1	2		T2	1568		T3	26
auto[TlIntgErrNone]	full_word	auto[0]	1047120	1			T1	3		T2	1823		T3	31
auto[TlIntgErrNone]	full_word	auto[1]	2942678	1			T1	879		T2	16304		T3	30
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T55	2		T90	1		T141	5
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T55	3		T89	3		T90	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T55	1		T90	1		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T145	1		T173	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T55	1		T89	2		T90	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T55	2		T89	2		T90	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T141	1		T175	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T177	1		T178	1		T145	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T89	2		T141	4		T179	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T55	1		T89	1		T90	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T145	1		T180	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T178	1		T173	1		T182	1