Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T5,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T5,T9

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1209670509	2275	0	0
SrcPulseCheck_M	398544333	2275	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1209670509	2275	0	0
T2	743168	12	0	0
T3	11702	0	0	0
T4	222139	0	0	0
T5	130615	8	0	0
T6	1987	0	0	0
T7	8169	0	0	0
T8	707601	0	0	0
T9	152546	2	0	0
T10	288162	20	0	0
T11	299969	0	0	0
T20	1022144	10	0	0
T21	0	6	0	0
T23	0	8	0	0
T24	204228	20	0	0
T27	0	7	0	0
T33	1922310	16	0	0
T34	102360	7	0	0
T35	26106	7	0	0
T36	0	2	0	0
T74	0	7	0	0
T81	14378	0	0	0
T83	0	7	0	0
T100	22406	0	0	0
T130	0	7	0	0
T131	0	7	0	0
T132	0	7	0	0
T133	0	7	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	14506	0	0	0
T137	414878	0	0	0
T138	186276	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398544333	2275	0	0
T2	754963	12	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	8	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	2	0	0
T10	715962	20	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	1702076	10	0	0
T21	0	6	0	0
T23	0	8	0	0
T24	256180	20	0	0
T27	0	7	0	0
T33	900462	16	0	0
T34	24088	7	0	0
T35	29600	7	0	0
T36	0	2	0	0
T74	0	7	0	0
T81	2016	0	0	0
T83	0	7	0	0
T100	25750	0	0	0
T130	0	7	0	0
T131	0	7	0	0
T132	0	7	0	0
T133	0	7	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	28864	0	0	0
T137	406796	0	0	0
T138	81986	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T74

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T74
1	1	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	403223503	182	0	0
SrcPulseCheck_M	132848111	182	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	182	0	0
T20	511072	0	0	0
T24	102114	0	0	0
T33	961155	0	0	0
T34	51180	2	0	0
T35	13053	2	0	0
T36	0	1	0	0
T74	0	2	0	0
T81	7189	0	0	0
T83	0	2	0	0
T100	11203	0	0	0
T130	0	4	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T135	0	2	0	0
T136	7253	0	0	0
T137	207439	0	0	0
T138	93138	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	182	0	0
T20	851038	0	0	0
T24	128090	0	0	0
T33	450231	0	0	0
T34	12044	2	0	0
T35	14800	2	0	0
T36	0	1	0	0
T74	0	2	0	0
T81	1008	0	0	0
T83	0	2	0	0
T100	12875	0	0	0
T130	0	4	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T135	0	2	0	0
T136	14432	0	0	0
T137	203398	0	0	0
T138	40993	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T74

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T74
1	1	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	403223503	328	0	0
SrcPulseCheck_M	132848111	328	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	328	0	0
T20	511072	0	0	0
T24	102114	0	0	0
T33	961155	0	0	0
T34	51180	5	0	0
T35	13053	5	0	0
T36	0	1	0	0
T74	0	5	0	0
T81	7189	0	0	0
T83	0	5	0	0
T100	11203	0	0	0
T130	0	3	0	0
T131	0	5	0	0
T132	0	5	0	0
T133	0	5	0	0
T134	0	5	0	0
T136	7253	0	0	0
T137	207439	0	0	0
T138	93138	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	328	0	0
T20	851038	0	0	0
T24	128090	0	0	0
T33	450231	0	0	0
T34	12044	5	0	0
T35	14800	5	0	0
T36	0	1	0	0
T74	0	5	0	0
T81	1008	0	0	0
T83	0	5	0	0
T100	12875	0	0	0
T130	0	3	0	0
T131	0	5	0	0
T132	0	5	0	0
T133	0	5	0	0
T134	0	5	0	0
T136	14432	0	0	0
T137	203398	0	0	0
T138	40993	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T5,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T5,T9

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	403223503	1765	0	0
SrcPulseCheck_M	132848111	1765	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1765	0	0
T2	743168	12	0	0
T3	11702	0	0	0
T4	222139	0	0	0
T5	130615	8	0	0
T6	1987	0	0	0
T7	8169	0	0	0
T8	707601	0	0	0
T9	152546	2	0	0
T10	288162	20	0	0
T11	299969	0	0	0
T20	0	10	0	0
T21	0	6	0	0
T23	0	8	0	0
T24	0	20	0	0
T27	0	7	0	0
T33	0	16	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	1765	0	0
T2	754963	12	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	8	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	2	0	0
T10	715962	20	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	10	0	0
T21	0	6	0	0
T23	0	8	0	0
T24	0	20	0	0
T27	0	7	0	0
T33	0	16	0	0