Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405602196	6215514	0	0
DepthKnown_A	405602196	405477137	0	0
RvalidKnown_A	405602196	405477137	0	0
WreadyKnown_A	405602196	405477137	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	6215514	0	0
T1	207663	55	0	0
T2	743168	17858	0	0
T3	11702	3627	0	0
T4	222139	68	0	0
T5	130615	25817	0	0
T6	1987	57	0	0
T7	8169	600	0	0
T8	707601	11383	0	0
T9	152546	28874	0	0
T10	288162	6204	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	405477137	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	405477137	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	405477137	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405602196	13325922	0	0
DepthKnown_A	405602196	405477137	0	0
RvalidKnown_A	405602196	405477137	0	0
WreadyKnown_A	405602196	405477137	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	13325922	0	0
T1	207663	55	0	0
T2	743168	17655	0	0
T3	11702	3627	0	0
T4	222139	68	0	0
T5	130615	25696	0	0
T6	1987	234	0	0
T7	8169	2770	0	0
T8	707601	11362	0	0
T9	152546	118509	0	0
T10	288162	6100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	405477137	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	405477137	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405602196	405477137	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0