Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T2,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	668919725	534673419	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	668919725	3097331	0	0
GntImpliesValid_A	668919725	3097331	0	0
GrantKnown_A	668919725	534673419	0	0
IdxKnown_A	668919725	534673419	0	0
IndexIsCorrect_A	668919725	3097331	0	0
LockArbDecision_A	668919725	0	0	0
NoReadyValidNoGrant_A	668919725	0	0	0
ReadyAndValidImplyGrant_A	668919725	3097331	0	0
ReqAndReadyImplyGrant_A	668919725	3097331	0	0
ReqImpliesValid_A	668919725	3097331	0	0
ReqStaysHighUntilGranted0_M	668919725	0	0	0
RoundRobin_A	668919725	2	0	906
ValidKnown_A	668919725	534673419	0	0
gen_data_port_assertion.DataFlow_A	668919725	3097331	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	534673419	0	0
T1	248563	248482	0	0
T2	2253094	1489501	0	0
T3	15254	13405	0	0
T4	331403	276717	0	0
T5	983783	553470	0	0
T6	1987	1936	0	0
T7	10321	8909	0	0
T8	914075	805523	0	0
T9	663440	403215	0	0
T10	1720086	1000356	0	0
T11	193156	96578	0	0
T12	188563	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	534673419	0	0
T1	248563	248482	0	0
T2	2253094	1489501	0	0
T3	15254	13405	0	0
T4	331403	276717	0	0
T5	983783	553470	0	0
T6	1987	1936	0	0
T7	10321	8909	0	0
T8	914075	805523	0	0
T9	663440	403215	0	0
T10	1720086	1000356	0	0
T11	193156	96578	0	0
T12	188563	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	534673419	0	0
T1	248563	248482	0	0
T2	2253094	1489501	0	0
T3	15254	13405	0	0
T4	331403	276717	0	0
T5	983783	553470	0	0
T6	1987	1936	0	0
T7	10321	8909	0	0
T8	914075	805523	0	0
T9	663440	403215	0	0
T10	1720086	1000356	0	0
T11	193156	96578	0	0
T12	188563	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	2	0	906
T38	751951	1	0	1
T39	0	1	0	0
T40	3587	0	0	1
T41	672878	0	0	1
T42	87357	0	0	1
T43	1468	0	0	1
T44	122310	0	0	1
T45	9463	0	0	1
T46	69098	0	0	1
T47	273865	0	0	1
T48	255867	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	534673419	0	0
T1	248563	248482	0	0
T2	2253094	1489501	0	0
T3	15254	13405	0	0
T4	331403	276717	0	0
T5	983783	553470	0	0
T6	1987	1936	0	0
T7	10321	8909	0	0
T8	914075	805523	0	0
T9	663440	403215	0	0
T10	1720086	1000356	0	0
T11	193156	96578	0	0
T12	188563	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668919725	3097331	0	0
T1	207663	832	0	0
T2	2253094	19900	0	0
T3	15254	181	0	0
T4	331403	832	0	0
T5	983783	13069	0	0
T6	1987	0	0	0
T7	10321	92	0	0
T8	914075	6675	0	0
T9	663440	10845	0	0
T10	1720086	18652	0	0
T11	193156	832	0	0
T12	377126	0	0	0
T20	0	3336	0	0
T21	0	2376	0	0
T22	0	1064	0	0
T23	0	7122	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132848111	29300339	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	132848111	635435	0	0
GntImpliesValid_A	132848111	635435	0	0
GrantKnown_A	132848111	29300339	0	0
IdxKnown_A	132848111	29300339	0	0
IndexIsCorrect_A	132848111	635435	0	0
LockArbDecision_A	132848111	0	0	0
NoReadyValidNoGrant_A	132848111	0	0	0
ReadyAndValidImplyGrant_A	132848111	635435	0	0
ReqAndReadyImplyGrant_A	132848111	635435	0	0
ReqImpliesValid_A	132848111	635435	0	0
ReqStaysHighUntilGranted0_M	132848111	0	0	0
RoundRobin_A	132848111	0	0	0
ValidKnown_A	132848111	29300339	0	0
gen_data_port_assertion.DataFlow_A	132848111	635435	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	29300339	0	0
T2	754963	275984	0	0
T3	1776	1776	0	0
T4	54632	0	0	0
T5	426584	74504	0	0
T7	1076	824	0	0
T8	103237	98008	0	0
T9	255447	131472	0	0
T10	715962	225456	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	29300339	0	0
T2	754963	275984	0	0
T3	1776	1776	0	0
T4	54632	0	0	0
T5	426584	74504	0	0
T7	1076	824	0	0
T8	103237	98008	0	0
T9	255447	131472	0	0
T10	715962	225456	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	29300339	0	0
T2	754963	275984	0	0
T3	1776	1776	0	0
T4	54632	0	0	0
T5	426584	74504	0	0
T7	1076	824	0	0
T8	103237	98008	0	0
T9	255447	131472	0	0
T10	715962	225456	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	29300339	0	0
T2	754963	275984	0	0
T3	1776	1776	0	0
T4	54632	0	0	0
T5	426584	74504	0	0
T7	1076	824	0	0
T8	103237	98008	0	0
T9	255447	131472	0	0
T10	715962	225456	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T15	0	85320	0	0
T16	0	360	0	0
T37	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	635435	0	0
T2	754963	5921	0	0
T3	1776	135	0	0
T4	54632	0	0	0
T5	426584	2505	0	0
T7	1076	72	0	0
T8	103237	4421	0	0
T9	255447	6172	0	0
T10	715962	2756	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T21	0	1082	0	0
T22	0	1064	0	0
T23	0	4874	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T2,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132848111	102230959	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	132848111	465362	0	0
GntImpliesValid_A	132848111	465362	0	0
GrantKnown_A	132848111	102230959	0	0
IdxKnown_A	132848111	102230959	0	0
IndexIsCorrect_A	132848111	465362	0	0
LockArbDecision_A	132848111	0	0	0
NoReadyValidNoGrant_A	132848111	0	0	0
ReadyAndValidImplyGrant_A	132848111	465362	0	0
ReqAndReadyImplyGrant_A	132848111	465362	0	0
ReqImpliesValid_A	132848111	465362	0	0
ReqStaysHighUntilGranted0_M	132848111	0	0	0
RoundRobin_A	132848111	0	0	0
ValidKnown_A	132848111	102230959	0	0
gen_data_port_assertion.DataFlow_A	132848111	465362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	102230959	0	0
T1	40900	40900	0	0
T2	754963	470599	0	0
T3	1776	0	0	0
T4	54632	54632	0	0
T5	426584	348360	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	119205	0	0
T10	715962	486813	0	0
T11	96578	96578	0	0
T12	0	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	102230959	0	0
T1	40900	40900	0	0
T2	754963	470599	0	0
T3	1776	0	0	0
T4	54632	54632	0	0
T5	426584	348360	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	119205	0	0
T10	715962	486813	0	0
T11	96578	96578	0	0
T12	0	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	102230959	0	0
T1	40900	40900	0	0
T2	754963	470599	0	0
T3	1776	0	0	0
T4	54632	54632	0	0
T5	426584	348360	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	119205	0	0
T10	715962	486813	0	0
T11	96578	96578	0	0
T12	0	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	102230959	0	0
T1	40900	40900	0	0
T2	754963	470599	0	0
T3	1776	0	0	0
T4	54632	54632	0	0
T5	426584	348360	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	119205	0	0
T10	715962	486813	0	0
T11	96578	96578	0	0
T12	0	187800	0	0
T13	0	81120	0	0
T14	0	60728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132848111	465362	0	0
T2	754963	790	0	0
T3	1776	0	0	0
T4	54632	0	0	0
T5	426584	4849	0	0
T7	1076	0	0	0
T8	103237	0	0	0
T9	255447	3	0	0
T10	715962	2686	0	0
T11	96578	0	0	0
T12	188563	0	0	0
T20	0	3336	0	0
T21	0	1294	0	0
T23	0	2248	0	0
T24	0	12074	0	0
T27	0	1295	0	0
T33	0	4952	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403223503	403142121	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	403223503	1996534	0	0
GntImpliesValid_A	403223503	1996534	0	0
GrantKnown_A	403223503	403142121	0	0
IdxKnown_A	403223503	403142121	0	0
IndexIsCorrect_A	403223503	1996534	0	0
LockArbDecision_A	403223503	0	0	0
NoReadyValidNoGrant_A	403223503	0	0	0
ReadyAndValidImplyGrant_A	403223503	1996534	0	0
ReqAndReadyImplyGrant_A	403223503	1996534	0	0
ReqImpliesValid_A	403223503	1996534	0	0
ReqStaysHighUntilGranted0_M	403223503	0	0	0
RoundRobin_A	403223503	2	0	906
ValidKnown_A	403223503	403142121	0	0
gen_data_port_assertion.DataFlow_A	403223503	1996534	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	403142121	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	403142121	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	403142121	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	2	0	906
T38	751951	1	0	1
T39	0	1	0	0
T40	3587	0	0	1
T41	672878	0	0	1
T42	87357	0	0	1
T43	1468	0	0	1
T44	122310	0	0	1
T45	9463	0	0	1
T46	69098	0	0	1
T47	273865	0	0	1
T48	255867	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	403142121	0	0
T1	207663	207582	0	0
T2	743168	742918	0	0
T3	11702	11629	0	0
T4	222139	222085	0	0
T5	130615	130606	0	0
T6	1987	1936	0	0
T7	8169	8085	0	0
T8	707601	707515	0	0
T9	152546	152538	0	0
T10	288162	288087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403223503	1996534	0	0
T1	207663	832	0	0
T2	743168	13189	0	0
T3	11702	46	0	0
T4	222139	832	0	0
T5	130615	5715	0	0
T6	1987	0	0	0
T7	8169	20	0	0
T8	707601	2254	0	0
T9	152546	4670	0	0
T10	288162	13210	0	0
T11	0	832	0	0