Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
3621 |
0 |
0 |
T54 |
5171 |
236 |
0 |
0 |
T55 |
34825 |
1 |
0 |
0 |
T56 |
5804 |
86 |
0 |
0 |
T88 |
18880 |
226 |
0 |
0 |
T90 |
9475 |
1 |
0 |
0 |
T91 |
4426 |
131 |
0 |
0 |
T92 |
13528 |
193 |
0 |
0 |
T93 |
6038 |
152 |
0 |
0 |
T97 |
8377 |
7 |
0 |
0 |
T98 |
4825 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2026 |
0 |
0 |
T55 |
34825 |
32 |
0 |
0 |
T106 |
38441 |
271 |
0 |
0 |
T139 |
12494 |
49 |
0 |
0 |
T140 |
7114 |
16 |
0 |
0 |
T141 |
98916 |
46 |
0 |
0 |
T142 |
5701 |
7 |
0 |
0 |
T143 |
9655 |
12 |
0 |
0 |
T144 |
10033 |
16 |
0 |
0 |
T145 |
70686 |
65 |
0 |
0 |
T146 |
65789 |
61 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1981 |
0 |
0 |
T55 |
34825 |
52 |
0 |
0 |
T56 |
5804 |
2 |
0 |
0 |
T106 |
38441 |
255 |
0 |
0 |
T139 |
12494 |
12 |
0 |
0 |
T140 |
7114 |
28 |
0 |
0 |
T141 |
98916 |
50 |
0 |
0 |
T143 |
9655 |
14 |
0 |
0 |
T144 |
10033 |
7 |
0 |
0 |
T145 |
70686 |
86 |
0 |
0 |
T146 |
65789 |
68 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2231 |
0 |
0 |
T55 |
34825 |
78 |
0 |
0 |
T106 |
38441 |
204 |
0 |
0 |
T128 |
4775 |
12 |
0 |
0 |
T139 |
12494 |
24 |
0 |
0 |
T140 |
7114 |
32 |
0 |
0 |
T141 |
98916 |
93 |
0 |
0 |
T142 |
5701 |
9 |
0 |
0 |
T143 |
9655 |
27 |
0 |
0 |
T144 |
10033 |
23 |
0 |
0 |
T145 |
70686 |
146 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
10297 |
0 |
0 |
T55 |
34825 |
543 |
0 |
0 |
T106 |
38441 |
244 |
0 |
0 |
T128 |
4775 |
6 |
0 |
0 |
T139 |
12494 |
16 |
0 |
0 |
T141 |
98916 |
1361 |
0 |
0 |
T142 |
5701 |
59 |
0 |
0 |
T143 |
9655 |
126 |
0 |
0 |
T144 |
10033 |
127 |
0 |
0 |
T145 |
70686 |
1298 |
0 |
0 |
T146 |
65789 |
1192 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
10712 |
0 |
0 |
T55 |
34825 |
1124 |
0 |
0 |
T106 |
38441 |
196 |
0 |
0 |
T128 |
4775 |
68 |
0 |
0 |
T139 |
12494 |
68 |
0 |
0 |
T140 |
7114 |
42 |
0 |
0 |
T141 |
98916 |
1524 |
0 |
0 |
T142 |
5701 |
60 |
0 |
0 |
T143 |
9655 |
11 |
0 |
0 |
T144 |
10033 |
124 |
0 |
0 |
T145 |
70686 |
1362 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
8658 |
0 |
0 |
T55 |
34825 |
494 |
0 |
0 |
T106 |
38441 |
191 |
0 |
0 |
T128 |
4775 |
60 |
0 |
0 |
T140 |
7114 |
12 |
0 |
0 |
T141 |
98916 |
1076 |
0 |
0 |
T142 |
5701 |
54 |
0 |
0 |
T143 |
9655 |
17 |
0 |
0 |
T144 |
10033 |
229 |
0 |
0 |
T145 |
70686 |
742 |
0 |
0 |
T146 |
65789 |
1208 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
7940 |
0 |
0 |
T55 |
34825 |
593 |
0 |
0 |
T106 |
38441 |
200 |
0 |
0 |
T128 |
4775 |
51 |
0 |
0 |
T139 |
12494 |
54 |
0 |
0 |
T140 |
7114 |
10 |
0 |
0 |
T141 |
98916 |
707 |
0 |
0 |
T142 |
5701 |
50 |
0 |
0 |
T143 |
9655 |
160 |
0 |
0 |
T144 |
10033 |
126 |
0 |
0 |
T145 |
70686 |
872 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
9519 |
0 |
0 |
T55 |
34825 |
460 |
0 |
0 |
T106 |
38441 |
243 |
0 |
0 |
T128 |
4775 |
75 |
0 |
0 |
T139 |
12494 |
41 |
0 |
0 |
T140 |
7114 |
13 |
0 |
0 |
T141 |
98916 |
928 |
0 |
0 |
T143 |
9655 |
99 |
0 |
0 |
T144 |
10033 |
117 |
0 |
0 |
T145 |
70686 |
1551 |
0 |
0 |
T146 |
65789 |
1444 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
10043 |
0 |
0 |
T55 |
34825 |
489 |
0 |
0 |
T106 |
38441 |
233 |
0 |
0 |
T128 |
4775 |
92 |
0 |
0 |
T139 |
12494 |
55 |
0 |
0 |
T140 |
7114 |
9 |
0 |
0 |
T141 |
98916 |
1334 |
0 |
0 |
T142 |
5701 |
6 |
0 |
0 |
T143 |
9655 |
140 |
0 |
0 |
T144 |
10033 |
131 |
0 |
0 |
T145 |
70686 |
1443 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
9801 |
0 |
0 |
T55 |
34825 |
469 |
0 |
0 |
T106 |
38441 |
242 |
0 |
0 |
T128 |
4775 |
76 |
0 |
0 |
T139 |
12494 |
78 |
0 |
0 |
T140 |
7114 |
16 |
0 |
0 |
T141 |
98916 |
1247 |
0 |
0 |
T142 |
5701 |
2 |
0 |
0 |
T143 |
9655 |
149 |
0 |
0 |
T144 |
10033 |
246 |
0 |
0 |
T145 |
70686 |
1175 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
9879 |
0 |
0 |
T55 |
34825 |
505 |
0 |
0 |
T106 |
38441 |
240 |
0 |
0 |
T128 |
4775 |
40 |
0 |
0 |
T139 |
12494 |
53 |
0 |
0 |
T140 |
7114 |
19 |
0 |
0 |
T141 |
98916 |
889 |
0 |
0 |
T142 |
5701 |
41 |
0 |
0 |
T143 |
9655 |
228 |
0 |
0 |
T144 |
10033 |
152 |
0 |
0 |
T145 |
70686 |
1020 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4998 |
0 |
0 |
T55 |
34825 |
187 |
0 |
0 |
T106 |
38441 |
276 |
0 |
0 |
T128 |
4775 |
39 |
0 |
0 |
T139 |
12494 |
4 |
0 |
0 |
T140 |
7114 |
3 |
0 |
0 |
T141 |
98916 |
432 |
0 |
0 |
T143 |
9655 |
99 |
0 |
0 |
T144 |
10033 |
60 |
0 |
0 |
T145 |
70686 |
380 |
0 |
0 |
T146 |
65789 |
572 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5260 |
0 |
0 |
T55 |
34825 |
317 |
0 |
0 |
T106 |
38441 |
248 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
88 |
0 |
0 |
T140 |
7114 |
39 |
0 |
0 |
T141 |
98916 |
347 |
0 |
0 |
T142 |
5701 |
15 |
0 |
0 |
T143 |
9655 |
84 |
0 |
0 |
T144 |
10033 |
98 |
0 |
0 |
T145 |
70686 |
679 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4592 |
0 |
0 |
T55 |
34825 |
206 |
0 |
0 |
T106 |
38441 |
222 |
0 |
0 |
T128 |
4775 |
29 |
0 |
0 |
T139 |
12494 |
36 |
0 |
0 |
T140 |
7114 |
56 |
0 |
0 |
T141 |
98916 |
377 |
0 |
0 |
T142 |
5701 |
28 |
0 |
0 |
T143 |
9655 |
50 |
0 |
0 |
T144 |
10033 |
40 |
0 |
0 |
T145 |
70686 |
592 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4968 |
0 |
0 |
T55 |
34825 |
281 |
0 |
0 |
T106 |
38441 |
228 |
0 |
0 |
T128 |
4775 |
27 |
0 |
0 |
T139 |
12494 |
53 |
0 |
0 |
T140 |
7114 |
18 |
0 |
0 |
T141 |
98916 |
343 |
0 |
0 |
T142 |
5701 |
26 |
0 |
0 |
T143 |
9655 |
50 |
0 |
0 |
T144 |
10033 |
116 |
0 |
0 |
T145 |
70686 |
536 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5015 |
0 |
0 |
T55 |
34825 |
258 |
0 |
0 |
T106 |
38441 |
251 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
40 |
0 |
0 |
T140 |
7114 |
29 |
0 |
0 |
T141 |
98916 |
449 |
0 |
0 |
T142 |
5701 |
16 |
0 |
0 |
T143 |
9655 |
9 |
0 |
0 |
T144 |
10033 |
25 |
0 |
0 |
T145 |
70686 |
504 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4530 |
0 |
0 |
T55 |
34825 |
155 |
0 |
0 |
T106 |
38441 |
226 |
0 |
0 |
T128 |
4775 |
22 |
0 |
0 |
T139 |
12494 |
19 |
0 |
0 |
T140 |
7114 |
15 |
0 |
0 |
T141 |
98916 |
523 |
0 |
0 |
T142 |
5701 |
27 |
0 |
0 |
T143 |
9655 |
62 |
0 |
0 |
T144 |
10033 |
41 |
0 |
0 |
T145 |
70686 |
491 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4943 |
0 |
0 |
T55 |
34825 |
231 |
0 |
0 |
T106 |
38441 |
229 |
0 |
0 |
T139 |
12494 |
47 |
0 |
0 |
T140 |
7114 |
14 |
0 |
0 |
T141 |
98916 |
348 |
0 |
0 |
T142 |
5701 |
10 |
0 |
0 |
T143 |
9655 |
83 |
0 |
0 |
T144 |
10033 |
64 |
0 |
0 |
T145 |
70686 |
443 |
0 |
0 |
T146 |
65789 |
527 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5027 |
0 |
0 |
T55 |
34825 |
223 |
0 |
0 |
T106 |
38441 |
237 |
0 |
0 |
T128 |
4775 |
22 |
0 |
0 |
T139 |
12494 |
35 |
0 |
0 |
T140 |
7114 |
37 |
0 |
0 |
T141 |
98916 |
466 |
0 |
0 |
T142 |
5701 |
20 |
0 |
0 |
T143 |
9655 |
13 |
0 |
0 |
T144 |
10033 |
14 |
0 |
0 |
T145 |
70686 |
464 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4903 |
0 |
0 |
T55 |
34825 |
321 |
0 |
0 |
T106 |
38441 |
232 |
0 |
0 |
T139 |
12494 |
26 |
0 |
0 |
T140 |
7114 |
14 |
0 |
0 |
T141 |
98916 |
582 |
0 |
0 |
T142 |
5701 |
4 |
0 |
0 |
T143 |
9655 |
112 |
0 |
0 |
T144 |
10033 |
39 |
0 |
0 |
T145 |
70686 |
546 |
0 |
0 |
T146 |
65789 |
480 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4717 |
0 |
0 |
T55 |
34825 |
261 |
0 |
0 |
T106 |
38441 |
205 |
0 |
0 |
T139 |
12494 |
52 |
0 |
0 |
T141 |
98916 |
450 |
0 |
0 |
T142 |
5701 |
2 |
0 |
0 |
T143 |
9655 |
129 |
0 |
0 |
T144 |
10033 |
13 |
0 |
0 |
T145 |
70686 |
419 |
0 |
0 |
T146 |
65789 |
604 |
0 |
0 |
T147 |
39738 |
307 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4783 |
0 |
0 |
T55 |
34825 |
171 |
0 |
0 |
T106 |
38441 |
247 |
0 |
0 |
T128 |
4775 |
19 |
0 |
0 |
T139 |
12494 |
38 |
0 |
0 |
T140 |
7114 |
13 |
0 |
0 |
T141 |
98916 |
381 |
0 |
0 |
T142 |
5701 |
13 |
0 |
0 |
T143 |
9655 |
52 |
0 |
0 |
T144 |
10033 |
14 |
0 |
0 |
T145 |
70686 |
596 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4907 |
0 |
0 |
T55 |
34825 |
221 |
0 |
0 |
T106 |
38441 |
212 |
0 |
0 |
T128 |
4775 |
2 |
0 |
0 |
T139 |
12494 |
25 |
0 |
0 |
T140 |
7114 |
32 |
0 |
0 |
T141 |
98916 |
512 |
0 |
0 |
T143 |
9655 |
12 |
0 |
0 |
T144 |
10033 |
38 |
0 |
0 |
T145 |
70686 |
729 |
0 |
0 |
T146 |
65789 |
519 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4437 |
0 |
0 |
T55 |
34825 |
183 |
0 |
0 |
T56 |
5804 |
2 |
0 |
0 |
T88 |
18880 |
1 |
0 |
0 |
T106 |
38441 |
268 |
0 |
0 |
T128 |
4775 |
30 |
0 |
0 |
T139 |
12494 |
28 |
0 |
0 |
T140 |
7114 |
10 |
0 |
0 |
T141 |
98916 |
440 |
0 |
0 |
T142 |
5701 |
4 |
0 |
0 |
T143 |
9655 |
40 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5075 |
0 |
0 |
T55 |
34825 |
223 |
0 |
0 |
T106 |
38441 |
228 |
0 |
0 |
T139 |
12494 |
92 |
0 |
0 |
T140 |
7114 |
10 |
0 |
0 |
T141 |
98916 |
337 |
0 |
0 |
T142 |
5701 |
27 |
0 |
0 |
T143 |
9655 |
38 |
0 |
0 |
T144 |
10033 |
47 |
0 |
0 |
T145 |
70686 |
363 |
0 |
0 |
T146 |
65789 |
564 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4801 |
0 |
0 |
T55 |
34825 |
265 |
0 |
0 |
T106 |
38441 |
217 |
0 |
0 |
T139 |
12494 |
37 |
0 |
0 |
T140 |
7114 |
24 |
0 |
0 |
T141 |
98916 |
368 |
0 |
0 |
T142 |
5701 |
35 |
0 |
0 |
T143 |
9655 |
106 |
0 |
0 |
T144 |
10033 |
92 |
0 |
0 |
T145 |
70686 |
452 |
0 |
0 |
T146 |
65789 |
419 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5418 |
0 |
0 |
T55 |
34825 |
222 |
0 |
0 |
T106 |
38441 |
231 |
0 |
0 |
T128 |
4775 |
33 |
0 |
0 |
T139 |
12494 |
58 |
0 |
0 |
T140 |
7114 |
22 |
0 |
0 |
T141 |
98916 |
584 |
0 |
0 |
T143 |
9655 |
82 |
0 |
0 |
T144 |
10033 |
57 |
0 |
0 |
T145 |
70686 |
537 |
0 |
0 |
T146 |
65789 |
847 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4871 |
0 |
0 |
T55 |
34825 |
319 |
0 |
0 |
T106 |
38441 |
251 |
0 |
0 |
T128 |
4775 |
19 |
0 |
0 |
T139 |
12494 |
30 |
0 |
0 |
T140 |
7114 |
22 |
0 |
0 |
T141 |
98916 |
426 |
0 |
0 |
T142 |
5701 |
4 |
0 |
0 |
T143 |
9655 |
27 |
0 |
0 |
T144 |
10033 |
110 |
0 |
0 |
T145 |
70686 |
522 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4765 |
0 |
0 |
T55 |
34825 |
240 |
0 |
0 |
T106 |
38441 |
228 |
0 |
0 |
T128 |
4775 |
26 |
0 |
0 |
T139 |
12494 |
25 |
0 |
0 |
T140 |
7114 |
19 |
0 |
0 |
T141 |
98916 |
465 |
0 |
0 |
T142 |
5701 |
36 |
0 |
0 |
T143 |
9655 |
14 |
0 |
0 |
T144 |
10033 |
57 |
0 |
0 |
T145 |
70686 |
523 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4898 |
0 |
0 |
T55 |
34825 |
207 |
0 |
0 |
T106 |
38441 |
248 |
0 |
0 |
T139 |
12494 |
29 |
0 |
0 |
T140 |
7114 |
17 |
0 |
0 |
T141 |
98916 |
361 |
0 |
0 |
T142 |
5701 |
38 |
0 |
0 |
T143 |
9655 |
19 |
0 |
0 |
T144 |
10033 |
54 |
0 |
0 |
T145 |
70686 |
657 |
0 |
0 |
T146 |
65789 |
606 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4681 |
0 |
0 |
T55 |
34825 |
360 |
0 |
0 |
T106 |
38441 |
200 |
0 |
0 |
T128 |
4775 |
38 |
0 |
0 |
T139 |
12494 |
47 |
0 |
0 |
T140 |
7114 |
10 |
0 |
0 |
T141 |
98916 |
340 |
0 |
0 |
T142 |
5701 |
26 |
0 |
0 |
T143 |
9655 |
74 |
0 |
0 |
T144 |
10033 |
16 |
0 |
0 |
T145 |
70686 |
585 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5150 |
0 |
0 |
T55 |
34825 |
384 |
0 |
0 |
T106 |
38441 |
218 |
0 |
0 |
T139 |
12494 |
50 |
0 |
0 |
T140 |
7114 |
6 |
0 |
0 |
T141 |
98916 |
407 |
0 |
0 |
T142 |
5701 |
4 |
0 |
0 |
T143 |
9655 |
41 |
0 |
0 |
T144 |
10033 |
65 |
0 |
0 |
T145 |
70686 |
545 |
0 |
0 |
T146 |
65789 |
564 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4477 |
0 |
0 |
T55 |
34825 |
284 |
0 |
0 |
T106 |
38441 |
263 |
0 |
0 |
T128 |
4775 |
38 |
0 |
0 |
T139 |
12494 |
35 |
0 |
0 |
T140 |
7114 |
28 |
0 |
0 |
T141 |
98916 |
343 |
0 |
0 |
T143 |
9655 |
56 |
0 |
0 |
T144 |
10033 |
95 |
0 |
0 |
T145 |
70686 |
498 |
0 |
0 |
T146 |
65789 |
424 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4830 |
0 |
0 |
T55 |
34825 |
178 |
0 |
0 |
T106 |
38441 |
226 |
0 |
0 |
T128 |
4775 |
30 |
0 |
0 |
T139 |
12494 |
55 |
0 |
0 |
T140 |
7114 |
8 |
0 |
0 |
T141 |
98916 |
386 |
0 |
0 |
T142 |
5701 |
25 |
0 |
0 |
T143 |
9655 |
62 |
0 |
0 |
T144 |
10033 |
12 |
0 |
0 |
T145 |
70686 |
707 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
5354 |
0 |
0 |
T55 |
34825 |
348 |
0 |
0 |
T106 |
38441 |
246 |
0 |
0 |
T128 |
4775 |
21 |
0 |
0 |
T139 |
12494 |
86 |
0 |
0 |
T140 |
7114 |
7 |
0 |
0 |
T141 |
98916 |
502 |
0 |
0 |
T142 |
5701 |
8 |
0 |
0 |
T143 |
9655 |
18 |
0 |
0 |
T144 |
10033 |
86 |
0 |
0 |
T145 |
70686 |
662 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2205 |
0 |
0 |
T55 |
34825 |
68 |
0 |
0 |
T106 |
38441 |
227 |
0 |
0 |
T128 |
4775 |
3 |
0 |
0 |
T139 |
12494 |
50 |
0 |
0 |
T140 |
7114 |
24 |
0 |
0 |
T141 |
98916 |
93 |
0 |
0 |
T143 |
9655 |
20 |
0 |
0 |
T144 |
10033 |
7 |
0 |
0 |
T145 |
70686 |
109 |
0 |
0 |
T146 |
65789 |
116 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2228 |
0 |
0 |
T55 |
34825 |
64 |
0 |
0 |
T106 |
38441 |
230 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
7 |
0 |
0 |
T140 |
7114 |
1 |
0 |
0 |
T141 |
98916 |
116 |
0 |
0 |
T142 |
5701 |
9 |
0 |
0 |
T143 |
9655 |
36 |
0 |
0 |
T144 |
10033 |
24 |
0 |
0 |
T145 |
70686 |
121 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2150 |
0 |
0 |
T55 |
34825 |
46 |
0 |
0 |
T106 |
38441 |
248 |
0 |
0 |
T128 |
4775 |
9 |
0 |
0 |
T139 |
12494 |
36 |
0 |
0 |
T140 |
7114 |
34 |
0 |
0 |
T141 |
98916 |
71 |
0 |
0 |
T142 |
5701 |
16 |
0 |
0 |
T143 |
9655 |
17 |
0 |
0 |
T144 |
10033 |
19 |
0 |
0 |
T145 |
70686 |
115 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2194 |
0 |
0 |
T55 |
34825 |
49 |
0 |
0 |
T106 |
38441 |
233 |
0 |
0 |
T139 |
12494 |
37 |
0 |
0 |
T140 |
7114 |
3 |
0 |
0 |
T141 |
98916 |
103 |
0 |
0 |
T142 |
5701 |
2 |
0 |
0 |
T143 |
9655 |
21 |
0 |
0 |
T144 |
10033 |
13 |
0 |
0 |
T145 |
70686 |
94 |
0 |
0 |
T146 |
65789 |
131 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2571 |
0 |
0 |
T55 |
34825 |
123 |
0 |
0 |
T106 |
38441 |
223 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
20 |
0 |
0 |
T140 |
7114 |
16 |
0 |
0 |
T141 |
98916 |
186 |
0 |
0 |
T143 |
9655 |
15 |
0 |
0 |
T144 |
10033 |
25 |
0 |
0 |
T145 |
70686 |
158 |
0 |
0 |
T146 |
65789 |
162 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
4434 |
0 |
0 |
T27 |
466882 |
0 |
0 |
0 |
T36 |
24465 |
0 |
0 |
0 |
T51 |
1172 |
0 |
0 |
0 |
T52 |
1331 |
0 |
0 |
0 |
T53 |
29172 |
9 |
0 |
0 |
T57 |
0 |
31 |
0 |
0 |
T101 |
9851 |
0 |
0 |
0 |
T102 |
27157 |
0 |
0 |
0 |
T148 |
0 |
17 |
0 |
0 |
T149 |
0 |
15 |
0 |
0 |
T150 |
0 |
33 |
0 |
0 |
T151 |
0 |
14 |
0 |
0 |
T152 |
0 |
18 |
0 |
0 |
T153 |
0 |
19 |
0 |
0 |
T154 |
0 |
20 |
0 |
0 |
T155 |
0 |
38 |
0 |
0 |
T156 |
1003 |
0 |
0 |
0 |
T157 |
392204 |
0 |
0 |
0 |
T158 |
1282 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2058 |
0 |
0 |
T55 |
34825 |
51 |
0 |
0 |
T106 |
38441 |
197 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
42 |
0 |
0 |
T140 |
7114 |
27 |
0 |
0 |
T141 |
98916 |
91 |
0 |
0 |
T143 |
9655 |
23 |
0 |
0 |
T144 |
10033 |
12 |
0 |
0 |
T145 |
70686 |
129 |
0 |
0 |
T146 |
65789 |
93 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2040 |
0 |
0 |
T55 |
34825 |
65 |
0 |
0 |
T106 |
38441 |
187 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
30 |
0 |
0 |
T140 |
7114 |
29 |
0 |
0 |
T141 |
98916 |
82 |
0 |
0 |
T142 |
5701 |
1 |
0 |
0 |
T143 |
9655 |
23 |
0 |
0 |
T144 |
10033 |
23 |
0 |
0 |
T145 |
70686 |
105 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1807 |
0 |
0 |
T55 |
34825 |
38 |
0 |
0 |
T106 |
38441 |
255 |
0 |
0 |
T128 |
4775 |
8 |
0 |
0 |
T139 |
12494 |
29 |
0 |
0 |
T140 |
7114 |
30 |
0 |
0 |
T141 |
98916 |
17 |
0 |
0 |
T142 |
5701 |
3 |
0 |
0 |
T143 |
9655 |
19 |
0 |
0 |
T144 |
10033 |
19 |
0 |
0 |
T145 |
70686 |
81 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2004 |
0 |
0 |
T55 |
34825 |
48 |
0 |
0 |
T106 |
38441 |
232 |
0 |
0 |
T139 |
12494 |
102 |
0 |
0 |
T140 |
7114 |
8 |
0 |
0 |
T141 |
98916 |
88 |
0 |
0 |
T142 |
5701 |
8 |
0 |
0 |
T143 |
9655 |
17 |
0 |
0 |
T144 |
10033 |
10 |
0 |
0 |
T145 |
70686 |
62 |
0 |
0 |
T146 |
65789 |
75 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1915 |
0 |
0 |
T55 |
34825 |
34 |
0 |
0 |
T106 |
38441 |
209 |
0 |
0 |
T139 |
12494 |
19 |
0 |
0 |
T140 |
7114 |
32 |
0 |
0 |
T141 |
98916 |
63 |
0 |
0 |
T143 |
9655 |
17 |
0 |
0 |
T144 |
10033 |
20 |
0 |
0 |
T145 |
70686 |
69 |
0 |
0 |
T146 |
65789 |
90 |
0 |
0 |
T147 |
39738 |
241 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1827 |
0 |
0 |
T55 |
34825 |
34 |
0 |
0 |
T106 |
38441 |
238 |
0 |
0 |
T139 |
12494 |
28 |
0 |
0 |
T140 |
7114 |
27 |
0 |
0 |
T141 |
98916 |
89 |
0 |
0 |
T143 |
9655 |
12 |
0 |
0 |
T144 |
10033 |
19 |
0 |
0 |
T145 |
70686 |
55 |
0 |
0 |
T146 |
65789 |
85 |
0 |
0 |
T147 |
39738 |
277 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2534 |
0 |
0 |
T55 |
34825 |
89 |
0 |
0 |
T106 |
38441 |
267 |
0 |
0 |
T128 |
4775 |
11 |
0 |
0 |
T139 |
12494 |
8 |
0 |
0 |
T140 |
7114 |
22 |
0 |
0 |
T141 |
98916 |
126 |
0 |
0 |
T143 |
9655 |
21 |
0 |
0 |
T144 |
10033 |
32 |
0 |
0 |
T145 |
70686 |
207 |
0 |
0 |
T146 |
65789 |
131 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1841 |
0 |
0 |
T55 |
34825 |
46 |
0 |
0 |
T106 |
38441 |
240 |
0 |
0 |
T139 |
12494 |
55 |
0 |
0 |
T140 |
7114 |
38 |
0 |
0 |
T141 |
98916 |
44 |
0 |
0 |
T143 |
9655 |
18 |
0 |
0 |
T144 |
10033 |
9 |
0 |
0 |
T145 |
70686 |
81 |
0 |
0 |
T146 |
65789 |
69 |
0 |
0 |
T147 |
39738 |
214 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2969 |
0 |
0 |
T55 |
34825 |
122 |
0 |
0 |
T106 |
38441 |
226 |
0 |
0 |
T139 |
12494 |
25 |
0 |
0 |
T140 |
7114 |
17 |
0 |
0 |
T141 |
98916 |
194 |
0 |
0 |
T143 |
9655 |
24 |
0 |
0 |
T144 |
10033 |
54 |
0 |
0 |
T145 |
70686 |
234 |
0 |
0 |
T146 |
65789 |
239 |
0 |
0 |
T147 |
39738 |
269 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2102 |
0 |
0 |
T55 |
34825 |
44 |
0 |
0 |
T106 |
38441 |
226 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
51 |
0 |
0 |
T140 |
7114 |
16 |
0 |
0 |
T141 |
98916 |
117 |
0 |
0 |
T142 |
5701 |
9 |
0 |
0 |
T143 |
9655 |
20 |
0 |
0 |
T144 |
10033 |
6 |
0 |
0 |
T145 |
70686 |
105 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1905 |
0 |
0 |
T55 |
34825 |
31 |
0 |
0 |
T106 |
38441 |
249 |
0 |
0 |
T128 |
4775 |
1 |
0 |
0 |
T139 |
12494 |
91 |
0 |
0 |
T140 |
7114 |
17 |
0 |
0 |
T141 |
98916 |
63 |
0 |
0 |
T143 |
9655 |
3 |
0 |
0 |
T144 |
10033 |
7 |
0 |
0 |
T145 |
70686 |
72 |
0 |
0 |
T146 |
65789 |
63 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1869 |
0 |
0 |
T55 |
34825 |
33 |
0 |
0 |
T106 |
38441 |
253 |
0 |
0 |
T139 |
12494 |
22 |
0 |
0 |
T140 |
7114 |
33 |
0 |
0 |
T141 |
98916 |
81 |
0 |
0 |
T142 |
5701 |
4 |
0 |
0 |
T143 |
9655 |
12 |
0 |
0 |
T144 |
10033 |
16 |
0 |
0 |
T145 |
70686 |
67 |
0 |
0 |
T146 |
65789 |
96 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1831 |
0 |
0 |
T55 |
34825 |
44 |
0 |
0 |
T106 |
38441 |
202 |
0 |
0 |
T128 |
4775 |
8 |
0 |
0 |
T139 |
12494 |
50 |
0 |
0 |
T141 |
98916 |
58 |
0 |
0 |
T144 |
10033 |
6 |
0 |
0 |
T145 |
70686 |
76 |
0 |
0 |
T146 |
65789 |
53 |
0 |
0 |
T147 |
39738 |
240 |
0 |
0 |
T159 |
8559 |
9 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
2094 |
0 |
0 |
T55 |
34825 |
43 |
0 |
0 |
T106 |
38441 |
263 |
0 |
0 |
T139 |
12494 |
67 |
0 |
0 |
T140 |
7114 |
22 |
0 |
0 |
T141 |
98916 |
81 |
0 |
0 |
T142 |
5701 |
10 |
0 |
0 |
T143 |
9655 |
21 |
0 |
0 |
T144 |
10033 |
11 |
0 |
0 |
T145 |
70686 |
87 |
0 |
0 |
T146 |
65789 |
80 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1847 |
0 |
0 |
T55 |
34825 |
32 |
0 |
0 |
T106 |
38441 |
195 |
0 |
0 |
T128 |
4775 |
3 |
0 |
0 |
T139 |
12494 |
34 |
0 |
0 |
T140 |
7114 |
14 |
0 |
0 |
T141 |
98916 |
46 |
0 |
0 |
T142 |
5701 |
6 |
0 |
0 |
T143 |
9655 |
24 |
0 |
0 |
T144 |
10033 |
17 |
0 |
0 |
T145 |
70686 |
61 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405602196 |
1916 |
0 |
0 |
T55 |
34825 |
43 |
0 |
0 |
T106 |
38441 |
221 |
0 |
0 |
T139 |
12494 |
58 |
0 |
0 |
T140 |
7114 |
1 |
0 |
0 |
T141 |
98916 |
67 |
0 |
0 |
T143 |
9655 |
26 |
0 |
0 |
T144 |
10033 |
15 |
0 |
0 |
T145 |
70686 |
78 |
0 |
0 |
T146 |
65789 |
76 |
0 |
0 |
T147 |
39738 |
247 |
0 |
0 |