Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3590723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3835311

1

T1

8421

T2

1504

T3

6164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4235475	1			T1	5808		T2	1192		T3	1447
values[0x0]	1593829	1			T1	4102		T2	454		T3	2654
values[0x1]	1596730	1			T1	4016		T2	458		T3	2652

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2542439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4883595

1

T1

10004

T2

1625

T3

6295

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26583	1			T1	11		T2	10		T3	33
valid_sources[0x01]	30534	1			T1	21		T2	13		T3	29
valid_sources[0x02]	28074	1			T1	9		T2	7		T3	14
valid_sources[0x03]	30253	1			T2	7		T3	25		T4	37
valid_sources[0x04]	28146	1			T2	7		T3	19		T4	67
valid_sources[0x05]	27843	1			T2	20		T3	22		T4	51
valid_sources[0x06]	29523	1			T1	110		T2	4		T3	24
valid_sources[0x07]	26534	1			T1	3		T2	6		T3	18
valid_sources[0x08]	24684	1			T1	8		T2	7		T3	20
valid_sources[0x09]	26773	1			T2	9		T3	20		T4	60
valid_sources[0x0a]	27637	1			T1	26		T2	10		T3	26
valid_sources[0x0b]	28093	1			T1	102		T2	9		T3	51
valid_sources[0x0c]	25304	1			T1	3		T2	12		T3	22
valid_sources[0x0d]	26569	1			T1	17		T2	5		T3	16
valid_sources[0x0e]	25206	1			T1	214		T2	7		T3	36
valid_sources[0x0f]	30047	1			T1	1		T2	5		T3	23
valid_sources[0x10]	30091	1			T1	5		T2	7		T3	24
valid_sources[0x11]	31391	1			T1	38		T2	15		T3	20
valid_sources[0x12]	31823	1			T2	11		T3	27		T4	37
valid_sources[0x13]	33872	1			T1	140		T2	8		T3	22
valid_sources[0x14]	27334	1			T2	11		T3	32		T4	45
valid_sources[0x15]	28395	1			T2	3		T3	25		T4	41
valid_sources[0x16]	31821	1			T1	2		T2	8		T3	25
valid_sources[0x17]	25051	1			T2	15		T3	17		T4	43
valid_sources[0x18]	30293	1			T1	1		T2	6		T3	21
valid_sources[0x19]	29596	1			T1	38		T2	7		T3	17
valid_sources[0x1a]	30142	1			T1	1		T2	10		T3	24
valid_sources[0x1b]	77448	1			T1	3		T2	1		T3	31
valid_sources[0x1c]	26920	1			T1	20		T2	4		T3	23
valid_sources[0x1d]	33283	1			T1	87		T2	8		T3	35
valid_sources[0x1e]	26433	1			T2	4		T3	20		T4	53
valid_sources[0x1f]	29009	1			T2	11		T3	17		T4	42
valid_sources[0x20]	29284	1			T1	25		T2	7		T3	40
valid_sources[0x21]	38092	1			T1	2		T2	7		T3	28
valid_sources[0x22]	33904	1			T1	7		T2	8		T3	23
valid_sources[0x23]	28355	1			T1	1		T2	7		T3	18
valid_sources[0x24]	29683	1			T1	14		T2	18		T3	34
valid_sources[0x25]	28090	1			T1	1		T2	7		T3	36
valid_sources[0x26]	30443	1			T1	15		T2	3		T3	21
valid_sources[0x27]	29351	1			T1	1		T2	5		T3	27
valid_sources[0x28]	26518	1			T1	1		T2	11		T3	33
valid_sources[0x29]	28027	1			T1	4		T2	5		T3	30
valid_sources[0x2a]	28322	1			T1	77		T2	8		T3	29
valid_sources[0x2b]	29596	1			T1	78		T2	7		T3	30
valid_sources[0x2c]	28176	1			T1	3		T2	17		T3	33
valid_sources[0x2d]	27902	1			T1	84		T2	7		T3	14
valid_sources[0x2e]	60958	1			T1	447		T2	6		T3	18
valid_sources[0x2f]	28301	1			T1	3		T2	7		T3	25
valid_sources[0x30]	28271	1			T1	35		T2	11		T3	18
valid_sources[0x31]	30511	1			T2	8		T3	29		T4	61
valid_sources[0x32]	30183	1			T1	227		T2	8		T3	18
valid_sources[0x33]	29170	1			T1	93		T2	10		T3	35
valid_sources[0x34]	30478	1			T1	21		T2	7		T3	22
valid_sources[0x35]	26018	1			T1	116		T2	4		T3	19
valid_sources[0x36]	28642	1			T1	6		T2	7		T3	21
valid_sources[0x37]	25748	1			T2	9		T3	26		T4	46
valid_sources[0x38]	27956	1			T1	478		T2	14		T3	28
valid_sources[0x39]	29121	1			T1	11		T2	7		T3	19
valid_sources[0x3a]	28480	1			T2	5		T3	20		T4	38
valid_sources[0x3b]	28313	1			T1	21		T2	4		T3	32
valid_sources[0x3c]	33325	1			T1	1		T2	6		T3	22
valid_sources[0x3d]	28273	1			T1	18		T2	7		T3	23
valid_sources[0x3e]	28130	1			T1	1		T2	15		T3	35
valid_sources[0x3f]	25915	1			T1	109		T2	8		T3	32
valid_sources[0x40]	29584	1			T1	1		T2	5		T3	29
valid_sources[0x41]	29329	1			T2	8		T3	38		T4	49
valid_sources[0x42]	26951	1			T1	75		T2	9		T3	33
valid_sources[0x43]	27409	1			T1	28		T2	4		T3	20
valid_sources[0x44]	30320	1			T1	438		T2	11		T3	31
valid_sources[0x45]	30967	1			T1	423		T2	5		T3	25
valid_sources[0x46]	30476	1			T2	6		T3	26		T4	54
valid_sources[0x47]	28025	1			T2	5		T3	29		T4	51
valid_sources[0x48]	25487	1			T1	3		T2	7		T3	25
valid_sources[0x49]	28828	1			T1	1		T2	11		T3	40
valid_sources[0x4a]	28518	1			T1	22		T2	8		T3	20
valid_sources[0x4b]	26932	1			T1	4		T2	7		T3	31
valid_sources[0x4c]	28316	1			T2	12		T3	23		T4	47
valid_sources[0x4d]	29095	1			T1	292		T2	17		T3	33
valid_sources[0x4e]	27444	1			T1	541		T2	12		T3	22
valid_sources[0x4f]	39127	1			T2	5		T3	33		T4	58
valid_sources[0x50]	26358	1			T1	3		T2	6		T3	26
valid_sources[0x51]	28876	1			T1	30		T2	9		T3	27
valid_sources[0x52]	28115	1			T2	8		T3	25		T4	62
valid_sources[0x53]	33486	1			T1	2		T2	6		T3	26
valid_sources[0x54]	33056	1			T1	517		T2	7		T3	20
valid_sources[0x55]	28567	1			T2	9		T3	24		T4	39
valid_sources[0x56]	28130	1			T1	178		T2	6		T3	24
valid_sources[0x57]	28760	1			T1	13		T2	5		T3	18
valid_sources[0x58]	30145	1			T2	5		T3	34		T4	43
valid_sources[0x59]	32204	1			T1	6		T2	11		T3	37
valid_sources[0x5a]	28211	1			T1	137		T2	9		T3	30
valid_sources[0x5b]	29671	1			T1	67		T2	18		T3	38
valid_sources[0x5c]	29590	1			T2	12		T3	25		T4	37
valid_sources[0x5d]	26369	1			T2	12		T3	26		T4	46
valid_sources[0x5e]	30137	1			T1	492		T2	6		T3	12
valid_sources[0x5f]	28210	1			T2	7		T3	35		T4	59
valid_sources[0x60]	25325	1			T1	223		T2	4		T3	31
valid_sources[0x61]	25343	1			T1	1		T2	17		T3	23
valid_sources[0x62]	27393	1			T1	48		T2	6		T3	35
valid_sources[0x63]	32380	1			T1	460		T2	7		T3	21
valid_sources[0x64]	28345	1			T1	145		T2	13		T3	26
valid_sources[0x65]	27064	1			T1	52		T2	6		T3	27
valid_sources[0x66]	28503	1			T2	12		T3	24		T4	47
valid_sources[0x67]	34744	1			T1	38		T2	5		T3	24
valid_sources[0x68]	27411	1			T1	197		T2	15		T3	37
valid_sources[0x69]	29300	1			T1	14		T2	9		T3	41
valid_sources[0x6a]	30886	1			T2	9		T3	23		T4	53
valid_sources[0x6b]	32501	1			T1	1		T2	7		T3	19
valid_sources[0x6c]	25142	1			T1	23		T2	14		T3	21
valid_sources[0x6d]	28154	1			T2	6		T3	28		T4	54
valid_sources[0x6e]	29022	1			T2	6		T3	27		T4	41
valid_sources[0x6f]	26334	1			T2	4		T3	21		T4	32
valid_sources[0x70]	34917	1			T1	142		T2	4		T3	26
valid_sources[0x71]	27629	1			T1	428		T2	2		T3	30
valid_sources[0x72]	25321	1			T1	33		T2	13		T3	23
valid_sources[0x73]	26129	1			T1	1		T2	7		T3	25
valid_sources[0x74]	27274	1			T2	10		T3	28		T4	56
valid_sources[0x75]	29280	1			T1	133		T2	9		T3	39
valid_sources[0x76]	26590	1			T1	460		T2	4		T3	26
valid_sources[0x77]	30011	1			T2	7		T3	36		T4	53
valid_sources[0x78]	28552	1			T1	11		T2	3		T3	26
valid_sources[0x79]	25575	1			T1	2		T2	6		T3	27
valid_sources[0x7a]	33442	1			T1	1		T2	16		T3	28
valid_sources[0x7b]	29809	1			T1	1		T2	9		T3	24
valid_sources[0x7c]	27625	1			T1	270		T2	9		T3	25
valid_sources[0x7d]	27437	1			T1	8		T2	2		T3	23
valid_sources[0x7e]	28714	1			T1	22		T2	3		T3	25
valid_sources[0x7f]	35503	1			T1	8		T2	9		T3	37
valid_sources[0x80]	26975	1			T2	6		T3	24		T4	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

979405

1

T1

1338

T2

601

T3

886

values[0x0]

all_enables

biggest_size

1438553

1

T1

3612

T2

453

T3

2644

values[0x1]

all_enables

biggest_size

1417353

1

T1

3471

T2

450

T3

2634