Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3607928

1

T1

5505

T2

600

T3

589

full_word

3836176

1

T1

8421

T2

1504

T3

6164

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7443734	1			T1	13926		T2	2104		T3	6753
auto[TlIntgErrCmd]	122	1			T55	2		T56	7		T57	7
auto[TlIntgErrData]	121	1			T55	6		T56	4		T57	6
auto[TlIntgErrBoth]	127	1			T55	2		T56	9		T57	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4238086

1

T1

5808

T2

1192

T3

1447

auto[1]

3206018

1

T1

8118

T2

912

T3

5306

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3258310	1			T1	4470		T2	591		T3	561
auto[TlIntgErrNone]	partial	auto[1]	349281	1			T1	1035		T2	9		T3	28
auto[TlIntgErrNone]	full_word	auto[0]	979614	1			T1	1338		T2	601		T3	886
auto[TlIntgErrNone]	full_word	auto[1]	2856529	1			T1	7083		T2	903		T3	5278
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T55	1		T56	2		T57	2
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T56	4		T57	5		T105	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T98	1		T186	1		T183	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T55	1		T56	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T55	2		T56	3		T57	2
auto[TlIntgErrData]	partial	auto[1]	59	1			T55	4		T56	1		T57	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T57	1		T108	1		T98	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T182	2		T186	2		T187	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T56	3		T57	1		T105	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T55	1		T56	5		T57	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T55	1		T57	1		T105	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T56	1		T57	1		T105	1