Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	516492457	2710329	0	0
gen_wmask[1].MaskCheckPortA_A	516492457	2710329	0	0
gen_wmask[2].MaskCheckPortA_A	516492457	2710329	0	0
gen_wmask[3].MaskCheckPortA_A	516492457	2710329	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516492457	2710329	0	0
T1	789210	10011	0	0
T2	76638	832	0	0
T3	875089	10284	0	0
T4	841358	18257	0	0
T5	988	0	0	0
T6	378283	3376	0	0
T7	1614	0	0	0
T8	34964	832	0	0
T9	918143	15507	0	0
T10	495933	832	0	0
T11	16	832	0	0
T14	0	4175	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516492457	2710329	0	0
T1	789210	10011	0	0
T2	76638	832	0	0
T3	875089	10284	0	0
T4	841358	18257	0	0
T5	988	0	0	0
T6	378283	3376	0	0
T7	1614	0	0	0
T8	34964	832	0	0
T9	918143	15507	0	0
T10	495933	832	0	0
T11	16	832	0	0
T14	0	4175	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516492457	2710329	0	0
T1	789210	10011	0	0
T2	76638	832	0	0
T3	875089	10284	0	0
T4	841358	18257	0	0
T5	988	0	0	0
T6	378283	3376	0	0
T7	1614	0	0	0
T8	34964	832	0	0
T9	918143	15507	0	0
T10	495933	832	0	0
T11	16	832	0	0
T14	0	4175	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516492457	2710329	0	0
T1	789210	10011	0	0
T2	76638	832	0	0
T3	875089	10284	0	0
T4	841358	18257	0	0
T5	988	0	0	0
T6	378283	3376	0	0
T7	1614	0	0	0
T8	34964	832	0	0
T9	918143	15507	0	0
T10	495933	832	0	0
T11	16	832	0	0
T14	0	4175	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	393584500	1770764	0	0
gen_wmask[1].MaskCheckPortA_A	393584500	1770764	0	0
gen_wmask[2].MaskCheckPortA_A	393584500	1770764	0	0
gen_wmask[3].MaskCheckPortA_A	393584500	1770764	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1770764	0	0
T1	401975	5089	0	0
T2	43271	832	0	0
T3	609852	4992	0	0
T4	244711	10816	0	0
T5	988	0	0	0
T6	104124	1056	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	11327	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1009	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1770764	0	0
T1	401975	5089	0	0
T2	43271	832	0	0
T3	609852	4992	0	0
T4	244711	10816	0	0
T5	988	0	0	0
T6	104124	1056	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	11327	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1009	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1770764	0	0
T1	401975	5089	0	0
T2	43271	832	0	0
T3	609852	4992	0	0
T4	244711	10816	0	0
T5	988	0	0	0
T6	104124	1056	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	11327	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1009	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1770764	0	0
T1	401975	5089	0	0
T2	43271	832	0	0
T3	609852	4992	0	0
T4	244711	10816	0	0
T5	988	0	0	0
T6	104124	1056	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	11327	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1009	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	122907957	939565	0	0
gen_wmask[1].MaskCheckPortA_A	122907957	939565	0	0
gen_wmask[2].MaskCheckPortA_A	122907957	939565	0	0
gen_wmask[3].MaskCheckPortA_A	122907957	939565	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	939565	0	0
T1	387235	4922	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	2320	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4180	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	3166	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	939565	0	0
T1	387235	4922	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	2320	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4180	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	3166	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	939565	0	0
T1	387235	4922	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	2320	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4180	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	3166	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	939565	0	0
T1	387235	4922	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	2320	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4180	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	3166	0	0
T16	0	8258	0	0
T17	0	1787	0	0
T22	0	3752	0	0
T23	0	5815	0	0