Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395714596	2402636	0	0
DepthKnown_A	395714596	395587397	0	0
RvalidKnown_A	395714596	395587397	0	0
WreadyKnown_A	395714596	395587397	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	2402636	0	0
T1	401975	8320	0	0
T2	43271	832	0	0
T3	609852	5826	0	0
T4	244711	14991	0	0
T5	988	0	0	0
T6	104124	0	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	13311	0	0
T10	249920	1670	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395714596	2711179	0	0
DepthKnown_A	395714596	395587397	0	0
RvalidKnown_A	395714596	395587397	0	0
WreadyKnown_A	395714596	395587397	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	2711179	0	0
T1	401975	4165	0	0
T2	43271	2545	0	0
T3	609852	19732	0	0
T4	244711	25331	0	0
T5	988	0	0	0
T6	104124	0	0	0
T7	1398	0	0	0
T8	16757	3689	0	0
T9	797566	30760	0	0
T10	249920	839	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395714596	166539	0	0
DepthKnown_A	395714596	395587397	0	0
RvalidKnown_A	395714596	395587397	0	0
WreadyKnown_A	395714596	395587397	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	166539	0	0
T1	401975	985	0	0
T2	43271	0	0	0
T3	609852	352	0	0
T4	244711	524	0	0
T5	988	0	0	0
T6	104124	598	0	0
T7	1398	0	0	0
T8	16757	0	0	0
T9	797566	1027	0	0
T10	249920	0	0	0
T14	0	827	0	0
T16	0	1349	0	0
T17	0	426	0	0
T22	0	516	0	0
T23	0	622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395714596	396243	0	0
DepthKnown_A	395714596	395587397	0	0
RvalidKnown_A	395714596	395587397	0	0
WreadyKnown_A	395714596	395587397	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	396243	0	0
T1	401975	4283	0	0
T2	43271	0	0	0
T3	609852	1539	0	0
T4	244711	1905	0	0
T5	988	0	0	0
T6	104124	2712	0	0
T7	1398	0	0	0
T8	16757	0	0	0
T9	797566	3369	0	0
T10	249920	0	0	0
T14	0	827	0	0
T16	0	4180	0	0
T17	0	424	0	0
T22	0	516	0	0
T23	0	622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395714596	6147016	0	0
DepthKnown_A	395714596	395587397	0	0
RvalidKnown_A	395714596	395587397	0	0
WreadyKnown_A	395714596	395587397	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	6147016	0	0
T1	401975	10172	0	0
T2	43271	1272	0	0
T3	609852	1436	0	0
T4	244711	1226	0	0
T5	988	61	0	0
T6	104124	3941	0	0
T7	1398	11	0	0
T8	16757	322	0	0
T9	797566	13946	0	0
T10	249920	10180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395714596	14075404	0	0
DepthKnown_A	395714596	395587397	0	0
RvalidKnown_A	395714596	395587397	0	0
WreadyKnown_A	395714596	395587397	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	14075404	0	0
T1	401975	39217	0	0
T2	43271	3910	0	0
T3	609852	6167	0	0
T4	244711	4349	0	0
T5	988	61	0	0
T6	104124	16015	0	0
T7	1398	11	0	0
T8	16757	1269	0	0
T9	797566	43481	0	0
T10	249920	44279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395714596	395587397	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0