Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T6,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T1,T6,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	639400414	515072901	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	639400414	3095327	0	0
GntImpliesValid_A	639400414	3095327	0	0
GrantKnown_A	639400414	515072901	0	0
IdxKnown_A	639400414	515072901	0	0
IndexIsCorrect_A	639400414	3095327	0	0
LockArbDecision_A	639400414	0	0	0
NoReadyValidNoGrant_A	639400414	0	0	0
ReadyAndValidImplyGrant_A	639400414	3095327	0	0
ReqAndReadyImplyGrant_A	639400414	3095327	0	0
ReqImpliesValid_A	639400414	3095327	0	0
ReqStaysHighUntilGranted0_M	639400414	0	0	0
RoundRobin_A	639400414	1	0	906
ValidKnown_A	639400414	515072901	0	0
gen_data_port_assertion.DataFlow_A	639400414	3095327	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	515072901	0	0
T1	1176445	783383	0	0
T2	110005	76385	0	0
T3	1140326	872991	0	0
T4	1438005	837897	0	0
T5	988	898	0	0
T6	652442	374875	0	0
T7	1830	1558	0	0
T8	53171	34895	0	0
T9	1038720	1994865	0	0
T10	741946	495699	0	0
T11	32	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	515072901	0	0
T1	1176445	783383	0	0
T2	110005	76385	0	0
T3	1140326	872991	0	0
T4	1438005	837897	0	0
T5	988	898	0	0
T6	652442	374875	0	0
T7	1830	1558	0	0
T8	53171	34895	0	0
T9	1038720	1994865	0	0
T10	741946	495699	0	0
T11	32	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	515072901	0	0
T1	1176445	783383	0	0
T2	110005	76385	0	0
T3	1140326	872991	0	0
T4	1438005	837897	0	0
T5	988	898	0	0
T6	652442	374875	0	0
T7	1830	1558	0	0
T8	53171	34895	0	0
T9	1038720	1994865	0	0
T10	741946	495699	0	0
T11	32	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	1	0	906
T40	198022	1	0	1
T41	38752	0	0	1
T42	28510	0	0	1
T43	17759	0	0	1
T44	209653	0	0	1
T45	158664	0	0	1
T46	122094	0	0	1
T47	65247	0	0	1
T48	214122	0	0	1
T49	960836	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	515072901	0	0
T1	1176445	783383	0	0
T2	110005	76385	0	0
T3	1140326	872991	0	0
T4	1438005	837897	0	0
T5	988	898	0	0
T6	652442	374875	0	0
T7	1830	1558	0	0
T8	53171	34895	0	0
T9	1038720	1994865	0	0
T10	741946	495699	0	0
T11	32	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639400414	3095327	0	0
T1	1176445	12020	0	0
T2	110005	832	0	0
T3	1140326	10671	0	0
T4	1438005	18812	0	0
T5	988	0	0	0
T6	652442	5120	0	0
T7	1830	0	0	0
T8	53171	832	0	0
T9	1038720	18020	0	0
T10	741946	832	0	0
T11	32	832	0	0
T14	0	6114	0	0
T16	0	10409	0	0
T17	0	2070	0	0
T22	0	3752	0	0
T23	0	6383	0	0
T25	0	9422	0	0
T37	0	3030	0	0
T39	0	1707	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T6,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T1,T6,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	122907957	28042925	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	122907957	682600	0	0
GntImpliesValid_A	122907957	682600	0	0
GrantKnown_A	122907957	28042925	0	0
IdxKnown_A	122907957	28042925	0	0
IndexIsCorrect_A	122907957	682600	0	0
LockArbDecision_A	122907957	0	0	0
NoReadyValidNoGrant_A	122907957	0	0	0
ReadyAndValidImplyGrant_A	122907957	682600	0	0
ReqAndReadyImplyGrant_A	122907957	682600	0	0
ReqImpliesValid_A	122907957	682600	0	0
ReqStaysHighUntilGranted0_M	122907957	0	0	0
RoundRobin_A	122907957	0	0	0
ValidKnown_A	122907957	28042925	0	0
gen_data_port_assertion.DataFlow_A	122907957	682600	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	28042925	0	0
T1	387235	139376	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	270832	0	0
T7	216	216	0	0
T8	18207	0	0	0
T9	120577	253792	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	28042925	0	0
T1	387235	139376	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	270832	0	0
T7	216	216	0	0
T8	18207	0	0	0
T9	120577	253792	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	28042925	0	0
T1	387235	139376	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	270832	0	0
T7	216	216	0	0
T8	18207	0	0	0
T9	120577	253792	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	28042925	0	0
T1	387235	139376	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	270832	0	0
T7	216	216	0	0
T8	18207	0	0	0
T9	120577	253792	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	94920	0	0
T16	0	144656	0	0
T17	0	61088	0	0
T18	0	16152	0	0
T23	0	31176	0	0
T39	0	55312	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	682600	0	0
T1	387235	3512	0	0
T2	33367	0	0	0
T3	265237	0	0	0
T4	596647	0	0	0
T6	274159	3466	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	4755	0	0
T10	246013	0	0	0
T11	16	0	0	0
T14	0	4278	0	0
T16	0	6616	0	0
T17	0	809	0	0
T23	0	1365	0	0
T25	0	5452	0	0
T37	0	3030	0	0
T39	0	919	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	122907957	93529203	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	122907957	482121	0	0
GntImpliesValid_A	122907957	482121	0	0
GrantKnown_A	122907957	93529203	0	0
IdxKnown_A	122907957	93529203	0	0
IndexIsCorrect_A	122907957	482121	0	0
LockArbDecision_A	122907957	0	0	0
NoReadyValidNoGrant_A	122907957	0	0	0
ReadyAndValidImplyGrant_A	122907957	482121	0	0
ReqAndReadyImplyGrant_A	122907957	482121	0	0
ReqImpliesValid_A	122907957	482121	0	0
ReqStaysHighUntilGranted0_M	122907957	0	0	0
RoundRobin_A	122907957	0	0	0
ValidKnown_A	122907957	93529203	0	0
gen_data_port_assertion.DataFlow_A	122907957	482121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	93529203	0	0
T1	387235	242095	0	0
T2	33367	33180	0	0
T3	265237	263191	0	0
T4	596647	593286	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	18207	0	0
T9	120577	943813	0	0
T10	246013	245840	0	0
T11	16	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	93529203	0	0
T1	387235	242095	0	0
T2	33367	33180	0	0
T3	265237	263191	0	0
T4	596647	593286	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	18207	0	0
T9	120577	943813	0	0
T10	246013	245840	0	0
T11	16	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	93529203	0	0
T1	387235	242095	0	0
T2	33367	33180	0	0
T3	265237	263191	0	0
T4	596647	593286	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	18207	0	0
T9	120577	943813	0	0
T10	246013	245840	0	0
T11	16	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	93529203	0	0
T1	387235	242095	0	0
T2	33367	33180	0	0
T3	265237	263191	0	0
T4	596647	593286	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	18207	0	0
T9	120577	943813	0	0
T10	246013	245840	0	0
T11	16	16	0	0
T12	0	14598	0	0
T13	0	30624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122907957	482121	0	0
T1	387235	2444	0	0
T2	33367	0	0	0
T3	265237	5292	0	0
T4	596647	7441	0	0
T6	274159	0	0	0
T7	216	0	0	0
T8	18207	0	0	0
T9	120577	917	0	0
T10	246013	0	0	0
T11	16	0	0	0
T16	0	3793	0	0
T17	0	1261	0	0
T22	0	3752	0	0
T23	0	5018	0	0
T25	0	3970	0	0
T39	0	788	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393584500	393500773	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	393584500	1930606	0	0
GntImpliesValid_A	393584500	1930606	0	0
GrantKnown_A	393584500	393500773	0	0
IdxKnown_A	393584500	393500773	0	0
IndexIsCorrect_A	393584500	1930606	0	0
LockArbDecision_A	393584500	0	0	0
NoReadyValidNoGrant_A	393584500	0	0	0
ReadyAndValidImplyGrant_A	393584500	1930606	0	0
ReqAndReadyImplyGrant_A	393584500	1930606	0	0
ReqImpliesValid_A	393584500	1930606	0	0
ReqStaysHighUntilGranted0_M	393584500	0	0	0
RoundRobin_A	393584500	1	0	906
ValidKnown_A	393584500	393500773	0	0
gen_data_port_assertion.DataFlow_A	393584500	1930606	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	393500773	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	393500773	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	393500773	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1	0	906
T40	198022	1	0	1
T41	38752	0	0	1
T42	28510	0	0	1
T43	17759	0	0	1
T44	209653	0	0	1
T45	158664	0	0	1
T46	122094	0	0	1
T47	65247	0	0	1
T48	214122	0	0	1
T49	960836	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	393500773	0	0
T1	401975	401912	0	0
T2	43271	43205	0	0
T3	609852	609800	0	0
T4	244711	244611	0	0
T5	988	898	0	0
T6	104124	104043	0	0
T7	1398	1342	0	0
T8	16757	16688	0	0
T9	797566	797260	0	0
T10	249920	249859	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393584500	1930606	0	0
T1	401975	6064	0	0
T2	43271	832	0	0
T3	609852	5379	0	0
T4	244711	11371	0	0
T5	988	0	0	0
T6	104124	1654	0	0
T7	1398	0	0	0
T8	16757	832	0	0
T9	797566	12348	0	0
T10	249920	832	0	0
T11	0	832	0	0
T14	0	1836	0	0