Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
2704 |
0 |
0 |
T55 |
27136 |
1 |
0 |
0 |
T56 |
55405 |
2 |
0 |
0 |
T89 |
7171 |
240 |
0 |
0 |
T90 |
3852 |
104 |
0 |
0 |
T91 |
5612 |
18 |
0 |
0 |
T94 |
4646 |
244 |
0 |
0 |
T95 |
4969 |
222 |
0 |
0 |
T105 |
103557 |
7 |
0 |
0 |
T106 |
2457 |
3 |
0 |
0 |
T108 |
37195 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1313 |
0 |
0 |
T57 |
64896 |
72 |
0 |
0 |
T105 |
103557 |
105 |
0 |
0 |
T107 |
30125 |
21 |
0 |
0 |
T108 |
37195 |
28 |
0 |
0 |
T115 |
9691 |
9 |
0 |
0 |
T136 |
17555 |
32 |
0 |
0 |
T145 |
5081 |
9 |
0 |
0 |
T146 |
5180 |
9 |
0 |
0 |
T147 |
13956 |
40 |
0 |
0 |
T148 |
33593 |
37 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1322 |
0 |
0 |
T57 |
64896 |
87 |
0 |
0 |
T97 |
19520 |
2 |
0 |
0 |
T105 |
103557 |
87 |
0 |
0 |
T107 |
30125 |
27 |
0 |
0 |
T108 |
37195 |
42 |
0 |
0 |
T115 |
9691 |
6 |
0 |
0 |
T136 |
17555 |
20 |
0 |
0 |
T145 |
5081 |
5 |
0 |
0 |
T146 |
5180 |
6 |
0 |
0 |
T147 |
13956 |
61 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
2187 |
0 |
0 |
T57 |
64896 |
185 |
0 |
0 |
T105 |
103557 |
243 |
0 |
0 |
T107 |
30125 |
28 |
0 |
0 |
T108 |
37195 |
82 |
0 |
0 |
T115 |
9691 |
34 |
0 |
0 |
T136 |
17555 |
66 |
0 |
0 |
T145 |
5081 |
13 |
0 |
0 |
T146 |
5180 |
2 |
0 |
0 |
T147 |
13956 |
40 |
0 |
0 |
T148 |
33593 |
104 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
11073 |
0 |
0 |
T57 |
64896 |
882 |
0 |
0 |
T105 |
103557 |
1763 |
0 |
0 |
T107 |
30125 |
330 |
0 |
0 |
T108 |
37195 |
460 |
0 |
0 |
T115 |
9691 |
61 |
0 |
0 |
T136 |
17555 |
42 |
0 |
0 |
T145 |
5081 |
11 |
0 |
0 |
T146 |
5180 |
12 |
0 |
0 |
T147 |
13956 |
10 |
0 |
0 |
T148 |
33593 |
582 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
13200 |
0 |
0 |
T57 |
64896 |
1161 |
0 |
0 |
T105 |
103557 |
1844 |
0 |
0 |
T107 |
30125 |
232 |
0 |
0 |
T108 |
37195 |
831 |
0 |
0 |
T115 |
9691 |
127 |
0 |
0 |
T136 |
17555 |
75 |
0 |
0 |
T145 |
5081 |
130 |
0 |
0 |
T146 |
5180 |
7 |
0 |
0 |
T147 |
13956 |
35 |
0 |
0 |
T148 |
33593 |
269 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
12537 |
0 |
0 |
T57 |
64896 |
1188 |
0 |
0 |
T105 |
103557 |
1952 |
0 |
0 |
T107 |
30125 |
452 |
0 |
0 |
T108 |
37195 |
747 |
0 |
0 |
T115 |
9691 |
153 |
0 |
0 |
T136 |
17555 |
14 |
0 |
0 |
T145 |
5081 |
7 |
0 |
0 |
T146 |
5180 |
11 |
0 |
0 |
T147 |
13956 |
35 |
0 |
0 |
T148 |
33593 |
542 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
14587 |
0 |
0 |
T57 |
64896 |
1157 |
0 |
0 |
T105 |
103557 |
2516 |
0 |
0 |
T107 |
30125 |
370 |
0 |
0 |
T108 |
37195 |
699 |
0 |
0 |
T115 |
9691 |
211 |
0 |
0 |
T136 |
17555 |
28 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
4 |
0 |
0 |
T147 |
13956 |
40 |
0 |
0 |
T148 |
33593 |
856 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
12824 |
0 |
0 |
T57 |
64896 |
1187 |
0 |
0 |
T105 |
103557 |
1581 |
0 |
0 |
T107 |
30125 |
324 |
0 |
0 |
T108 |
37195 |
608 |
0 |
0 |
T115 |
9691 |
69 |
0 |
0 |
T136 |
17555 |
36 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
8 |
0 |
0 |
T147 |
13956 |
22 |
0 |
0 |
T148 |
33593 |
658 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
12331 |
0 |
0 |
T57 |
64896 |
1309 |
0 |
0 |
T97 |
19520 |
8 |
0 |
0 |
T105 |
103557 |
1087 |
0 |
0 |
T107 |
30125 |
363 |
0 |
0 |
T108 |
37195 |
386 |
0 |
0 |
T115 |
9691 |
87 |
0 |
0 |
T136 |
17555 |
7 |
0 |
0 |
T145 |
5081 |
110 |
0 |
0 |
T146 |
5180 |
137 |
0 |
0 |
T147 |
13956 |
74 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
13719 |
0 |
0 |
T57 |
64896 |
1358 |
0 |
0 |
T105 |
103557 |
1841 |
0 |
0 |
T107 |
30125 |
207 |
0 |
0 |
T108 |
37195 |
769 |
0 |
0 |
T115 |
9691 |
141 |
0 |
0 |
T136 |
17555 |
35 |
0 |
0 |
T145 |
5081 |
148 |
0 |
0 |
T146 |
5180 |
16 |
0 |
0 |
T147 |
13956 |
47 |
0 |
0 |
T148 |
33593 |
737 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
10533 |
0 |
0 |
T57 |
64896 |
1160 |
0 |
0 |
T105 |
103557 |
1244 |
0 |
0 |
T107 |
30125 |
339 |
0 |
0 |
T108 |
37195 |
704 |
0 |
0 |
T115 |
9691 |
163 |
0 |
0 |
T136 |
17555 |
24 |
0 |
0 |
T145 |
5081 |
113 |
0 |
0 |
T146 |
5180 |
117 |
0 |
0 |
T147 |
13956 |
22 |
0 |
0 |
T148 |
33593 |
528 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5752 |
0 |
0 |
T57 |
64896 |
597 |
0 |
0 |
T105 |
103557 |
879 |
0 |
0 |
T107 |
30125 |
128 |
0 |
0 |
T108 |
37195 |
294 |
0 |
0 |
T115 |
9691 |
5 |
0 |
0 |
T136 |
17555 |
41 |
0 |
0 |
T145 |
5081 |
7 |
0 |
0 |
T146 |
5180 |
6 |
0 |
0 |
T147 |
13956 |
47 |
0 |
0 |
T148 |
33593 |
260 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5225 |
0 |
0 |
T57 |
64896 |
450 |
0 |
0 |
T105 |
103557 |
824 |
0 |
0 |
T107 |
30125 |
124 |
0 |
0 |
T108 |
37195 |
339 |
0 |
0 |
T115 |
9691 |
27 |
0 |
0 |
T136 |
17555 |
23 |
0 |
0 |
T145 |
5081 |
54 |
0 |
0 |
T146 |
5180 |
7 |
0 |
0 |
T147 |
13956 |
45 |
0 |
0 |
T148 |
33593 |
136 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5680 |
0 |
0 |
T57 |
64896 |
577 |
0 |
0 |
T105 |
103557 |
916 |
0 |
0 |
T107 |
30125 |
131 |
0 |
0 |
T108 |
37195 |
232 |
0 |
0 |
T115 |
9691 |
18 |
0 |
0 |
T136 |
17555 |
50 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
49 |
0 |
0 |
T147 |
13956 |
57 |
0 |
0 |
T148 |
33593 |
324 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5493 |
0 |
0 |
T57 |
64896 |
500 |
0 |
0 |
T105 |
103557 |
681 |
0 |
0 |
T107 |
30125 |
167 |
0 |
0 |
T108 |
37195 |
249 |
0 |
0 |
T115 |
9691 |
44 |
0 |
0 |
T136 |
17555 |
10 |
0 |
0 |
T145 |
5081 |
13 |
0 |
0 |
T146 |
5180 |
6 |
0 |
0 |
T147 |
13956 |
18 |
0 |
0 |
T148 |
33593 |
276 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5575 |
0 |
0 |
T57 |
64896 |
675 |
0 |
0 |
T105 |
103557 |
698 |
0 |
0 |
T107 |
30125 |
140 |
0 |
0 |
T108 |
37195 |
183 |
0 |
0 |
T115 |
9691 |
31 |
0 |
0 |
T117 |
10688 |
160 |
0 |
0 |
T136 |
17555 |
27 |
0 |
0 |
T145 |
5081 |
9 |
0 |
0 |
T147 |
13956 |
10 |
0 |
0 |
T148 |
33593 |
289 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5804 |
0 |
0 |
T57 |
64896 |
463 |
0 |
0 |
T105 |
103557 |
795 |
0 |
0 |
T107 |
30125 |
123 |
0 |
0 |
T108 |
37195 |
288 |
0 |
0 |
T115 |
9691 |
96 |
0 |
0 |
T136 |
17555 |
10 |
0 |
0 |
T145 |
5081 |
7 |
0 |
0 |
T146 |
5180 |
48 |
0 |
0 |
T147 |
13956 |
27 |
0 |
0 |
T148 |
33593 |
369 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5168 |
0 |
0 |
T57 |
64896 |
312 |
0 |
0 |
T105 |
103557 |
802 |
0 |
0 |
T107 |
30125 |
184 |
0 |
0 |
T108 |
37195 |
337 |
0 |
0 |
T115 |
9691 |
30 |
0 |
0 |
T136 |
17555 |
47 |
0 |
0 |
T145 |
5081 |
63 |
0 |
0 |
T146 |
5180 |
12 |
0 |
0 |
T147 |
13956 |
49 |
0 |
0 |
T148 |
33593 |
325 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5902 |
0 |
0 |
T57 |
64896 |
571 |
0 |
0 |
T105 |
103557 |
1019 |
0 |
0 |
T107 |
30125 |
155 |
0 |
0 |
T108 |
37195 |
318 |
0 |
0 |
T115 |
9691 |
76 |
0 |
0 |
T136 |
17555 |
20 |
0 |
0 |
T145 |
5081 |
48 |
0 |
0 |
T146 |
5180 |
61 |
0 |
0 |
T147 |
13956 |
87 |
0 |
0 |
T148 |
33593 |
257 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5347 |
0 |
0 |
T57 |
64896 |
396 |
0 |
0 |
T105 |
103557 |
776 |
0 |
0 |
T107 |
30125 |
113 |
0 |
0 |
T108 |
37195 |
267 |
0 |
0 |
T115 |
9691 |
10 |
0 |
0 |
T136 |
17555 |
37 |
0 |
0 |
T145 |
5081 |
51 |
0 |
0 |
T146 |
5180 |
65 |
0 |
0 |
T147 |
13956 |
15 |
0 |
0 |
T148 |
33593 |
199 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5860 |
0 |
0 |
T57 |
64896 |
400 |
0 |
0 |
T105 |
103557 |
679 |
0 |
0 |
T107 |
30125 |
190 |
0 |
0 |
T108 |
37195 |
398 |
0 |
0 |
T115 |
9691 |
74 |
0 |
0 |
T136 |
17555 |
48 |
0 |
0 |
T145 |
5081 |
13 |
0 |
0 |
T146 |
5180 |
49 |
0 |
0 |
T147 |
13956 |
39 |
0 |
0 |
T148 |
33593 |
337 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
6193 |
0 |
0 |
T57 |
64896 |
699 |
0 |
0 |
T105 |
103557 |
756 |
0 |
0 |
T107 |
30125 |
163 |
0 |
0 |
T108 |
37195 |
412 |
0 |
0 |
T115 |
9691 |
61 |
0 |
0 |
T136 |
17555 |
44 |
0 |
0 |
T145 |
5081 |
60 |
0 |
0 |
T146 |
5180 |
57 |
0 |
0 |
T147 |
13956 |
59 |
0 |
0 |
T148 |
33593 |
310 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
4956 |
0 |
0 |
T57 |
64896 |
562 |
0 |
0 |
T105 |
103557 |
598 |
0 |
0 |
T107 |
30125 |
75 |
0 |
0 |
T108 |
37195 |
183 |
0 |
0 |
T115 |
9691 |
1 |
0 |
0 |
T136 |
17555 |
45 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
6 |
0 |
0 |
T148 |
33593 |
231 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5500 |
0 |
0 |
T57 |
64896 |
575 |
0 |
0 |
T105 |
103557 |
481 |
0 |
0 |
T107 |
30125 |
186 |
0 |
0 |
T108 |
37195 |
238 |
0 |
0 |
T115 |
9691 |
89 |
0 |
0 |
T136 |
17555 |
41 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
43 |
0 |
0 |
T147 |
13956 |
50 |
0 |
0 |
T148 |
33593 |
205 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5569 |
0 |
0 |
T57 |
64896 |
507 |
0 |
0 |
T105 |
103557 |
677 |
0 |
0 |
T107 |
30125 |
175 |
0 |
0 |
T108 |
37195 |
258 |
0 |
0 |
T115 |
9691 |
16 |
0 |
0 |
T136 |
17555 |
41 |
0 |
0 |
T145 |
5081 |
45 |
0 |
0 |
T146 |
5180 |
69 |
0 |
0 |
T147 |
13956 |
67 |
0 |
0 |
T148 |
33593 |
167 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5864 |
0 |
0 |
T57 |
64896 |
583 |
0 |
0 |
T105 |
103557 |
952 |
0 |
0 |
T107 |
30125 |
159 |
0 |
0 |
T108 |
37195 |
209 |
0 |
0 |
T115 |
9691 |
76 |
0 |
0 |
T136 |
17555 |
26 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
28 |
0 |
0 |
T148 |
33593 |
214 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5044 |
0 |
0 |
T57 |
64896 |
386 |
0 |
0 |
T105 |
103557 |
713 |
0 |
0 |
T107 |
30125 |
93 |
0 |
0 |
T108 |
37195 |
375 |
0 |
0 |
T115 |
9691 |
16 |
0 |
0 |
T136 |
17555 |
25 |
0 |
0 |
T145 |
5081 |
18 |
0 |
0 |
T146 |
5180 |
8 |
0 |
0 |
T147 |
13956 |
14 |
0 |
0 |
T148 |
33593 |
331 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
6128 |
0 |
0 |
T57 |
64896 |
753 |
0 |
0 |
T105 |
103557 |
751 |
0 |
0 |
T107 |
30125 |
142 |
0 |
0 |
T108 |
37195 |
258 |
0 |
0 |
T115 |
9691 |
51 |
0 |
0 |
T136 |
17555 |
40 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
7 |
0 |
0 |
T147 |
13956 |
37 |
0 |
0 |
T148 |
33593 |
394 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5313 |
0 |
0 |
T57 |
64896 |
632 |
0 |
0 |
T105 |
103557 |
846 |
0 |
0 |
T107 |
30125 |
103 |
0 |
0 |
T108 |
37195 |
269 |
0 |
0 |
T115 |
9691 |
5 |
0 |
0 |
T136 |
17555 |
43 |
0 |
0 |
T145 |
5081 |
36 |
0 |
0 |
T146 |
5180 |
8 |
0 |
0 |
T147 |
13956 |
30 |
0 |
0 |
T148 |
33593 |
306 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5434 |
0 |
0 |
T57 |
64896 |
470 |
0 |
0 |
T105 |
103557 |
536 |
0 |
0 |
T107 |
30125 |
192 |
0 |
0 |
T108 |
37195 |
326 |
0 |
0 |
T115 |
9691 |
4 |
0 |
0 |
T136 |
17555 |
18 |
0 |
0 |
T145 |
5081 |
10 |
0 |
0 |
T146 |
5180 |
47 |
0 |
0 |
T147 |
13956 |
7 |
0 |
0 |
T148 |
33593 |
354 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5985 |
0 |
0 |
T57 |
64896 |
584 |
0 |
0 |
T105 |
103557 |
706 |
0 |
0 |
T107 |
30125 |
166 |
0 |
0 |
T108 |
37195 |
401 |
0 |
0 |
T115 |
9691 |
8 |
0 |
0 |
T136 |
17555 |
80 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
18 |
0 |
0 |
T147 |
13956 |
31 |
0 |
0 |
T148 |
33593 |
306 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5732 |
0 |
0 |
T57 |
64896 |
544 |
0 |
0 |
T105 |
103557 |
863 |
0 |
0 |
T107 |
30125 |
105 |
0 |
0 |
T108 |
37195 |
332 |
0 |
0 |
T115 |
9691 |
85 |
0 |
0 |
T136 |
17555 |
19 |
0 |
0 |
T145 |
5081 |
60 |
0 |
0 |
T146 |
5180 |
63 |
0 |
0 |
T147 |
13956 |
52 |
0 |
0 |
T148 |
33593 |
271 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5634 |
0 |
0 |
T57 |
64896 |
387 |
0 |
0 |
T97 |
19520 |
5 |
0 |
0 |
T105 |
103557 |
1012 |
0 |
0 |
T107 |
30125 |
134 |
0 |
0 |
T108 |
37195 |
287 |
0 |
0 |
T115 |
9691 |
51 |
0 |
0 |
T136 |
17555 |
15 |
0 |
0 |
T145 |
5081 |
4 |
0 |
0 |
T146 |
5180 |
54 |
0 |
0 |
T147 |
13956 |
2 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5491 |
0 |
0 |
T57 |
64896 |
435 |
0 |
0 |
T105 |
103557 |
724 |
0 |
0 |
T107 |
30125 |
91 |
0 |
0 |
T108 |
37195 |
380 |
0 |
0 |
T115 |
9691 |
43 |
0 |
0 |
T136 |
17555 |
28 |
0 |
0 |
T145 |
5081 |
3 |
0 |
0 |
T146 |
5180 |
14 |
0 |
0 |
T147 |
13956 |
64 |
0 |
0 |
T148 |
33593 |
333 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
5215 |
0 |
0 |
T57 |
64896 |
457 |
0 |
0 |
T105 |
103557 |
879 |
0 |
0 |
T107 |
30125 |
143 |
0 |
0 |
T108 |
37195 |
76 |
0 |
0 |
T115 |
9691 |
28 |
0 |
0 |
T136 |
17555 |
53 |
0 |
0 |
T145 |
5081 |
14 |
0 |
0 |
T146 |
5180 |
11 |
0 |
0 |
T147 |
13956 |
44 |
0 |
0 |
T148 |
33593 |
305 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1602 |
0 |
0 |
T57 |
64896 |
122 |
0 |
0 |
T105 |
103557 |
160 |
0 |
0 |
T107 |
30125 |
29 |
0 |
0 |
T108 |
37195 |
38 |
0 |
0 |
T115 |
9691 |
16 |
0 |
0 |
T136 |
17555 |
37 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
7 |
0 |
0 |
T147 |
13956 |
46 |
0 |
0 |
T148 |
33593 |
62 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1692 |
0 |
0 |
T57 |
64896 |
153 |
0 |
0 |
T105 |
103557 |
141 |
0 |
0 |
T107 |
30125 |
21 |
0 |
0 |
T108 |
37195 |
49 |
0 |
0 |
T115 |
9691 |
14 |
0 |
0 |
T136 |
17555 |
45 |
0 |
0 |
T145 |
5081 |
10 |
0 |
0 |
T146 |
5180 |
11 |
0 |
0 |
T147 |
13956 |
66 |
0 |
0 |
T148 |
33593 |
60 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1722 |
0 |
0 |
T57 |
64896 |
126 |
0 |
0 |
T105 |
103557 |
174 |
0 |
0 |
T107 |
30125 |
33 |
0 |
0 |
T108 |
37195 |
58 |
0 |
0 |
T115 |
9691 |
4 |
0 |
0 |
T136 |
17555 |
36 |
0 |
0 |
T145 |
5081 |
11 |
0 |
0 |
T146 |
5180 |
14 |
0 |
0 |
T147 |
13956 |
44 |
0 |
0 |
T148 |
33593 |
65 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1572 |
0 |
0 |
T57 |
64896 |
105 |
0 |
0 |
T105 |
103557 |
204 |
0 |
0 |
T107 |
30125 |
37 |
0 |
0 |
T108 |
37195 |
49 |
0 |
0 |
T117 |
10688 |
24 |
0 |
0 |
T136 |
17555 |
37 |
0 |
0 |
T145 |
5081 |
16 |
0 |
0 |
T146 |
5180 |
3 |
0 |
0 |
T147 |
13956 |
20 |
0 |
0 |
T148 |
33593 |
36 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
2394 |
0 |
0 |
T57 |
64896 |
187 |
0 |
0 |
T105 |
103557 |
279 |
0 |
0 |
T107 |
30125 |
26 |
0 |
0 |
T108 |
37195 |
98 |
0 |
0 |
T115 |
9691 |
8 |
0 |
0 |
T136 |
17555 |
41 |
0 |
0 |
T145 |
5081 |
5 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
103 |
0 |
0 |
T148 |
33593 |
75 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
4396 |
0 |
0 |
T40 |
0 |
15 |
0 |
0 |
T79 |
804005 |
21 |
0 |
0 |
T149 |
0 |
6 |
0 |
0 |
T150 |
0 |
25 |
0 |
0 |
T151 |
0 |
7 |
0 |
0 |
T152 |
0 |
61 |
0 |
0 |
T153 |
0 |
14 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
20 |
0 |
0 |
T156 |
0 |
30 |
0 |
0 |
T157 |
211194 |
0 |
0 |
0 |
T158 |
176775 |
0 |
0 |
0 |
T159 |
735163 |
0 |
0 |
0 |
T160 |
216125 |
0 |
0 |
0 |
T161 |
105346 |
0 |
0 |
0 |
T162 |
66205 |
0 |
0 |
0 |
T163 |
27418 |
0 |
0 |
0 |
T164 |
622879 |
0 |
0 |
0 |
T165 |
830788 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1621 |
0 |
0 |
T57 |
64896 |
90 |
0 |
0 |
T97 |
19520 |
2 |
0 |
0 |
T105 |
103557 |
120 |
0 |
0 |
T107 |
30125 |
24 |
0 |
0 |
T108 |
37195 |
54 |
0 |
0 |
T115 |
9691 |
5 |
0 |
0 |
T136 |
17555 |
17 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
7 |
0 |
0 |
T147 |
13956 |
78 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1753 |
0 |
0 |
T57 |
64896 |
168 |
0 |
0 |
T105 |
103557 |
154 |
0 |
0 |
T107 |
30125 |
42 |
0 |
0 |
T108 |
37195 |
63 |
0 |
0 |
T115 |
9691 |
7 |
0 |
0 |
T136 |
17555 |
68 |
0 |
0 |
T145 |
5081 |
12 |
0 |
0 |
T146 |
5180 |
3 |
0 |
0 |
T147 |
13956 |
13 |
0 |
0 |
T148 |
33593 |
36 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1320 |
0 |
0 |
T57 |
64896 |
55 |
0 |
0 |
T105 |
103557 |
138 |
0 |
0 |
T107 |
30125 |
30 |
0 |
0 |
T108 |
37195 |
44 |
0 |
0 |
T117 |
10688 |
16 |
0 |
0 |
T136 |
17555 |
27 |
0 |
0 |
T145 |
5081 |
11 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
76 |
0 |
0 |
T148 |
33593 |
30 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1212 |
0 |
0 |
T57 |
64896 |
80 |
0 |
0 |
T105 |
103557 |
88 |
0 |
0 |
T107 |
30125 |
12 |
0 |
0 |
T108 |
37195 |
24 |
0 |
0 |
T115 |
9691 |
4 |
0 |
0 |
T136 |
17555 |
74 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
2 |
0 |
0 |
T147 |
13956 |
48 |
0 |
0 |
T148 |
33593 |
40 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1300 |
0 |
0 |
T57 |
64896 |
75 |
0 |
0 |
T97 |
19520 |
9 |
0 |
0 |
T105 |
103557 |
102 |
0 |
0 |
T107 |
30125 |
11 |
0 |
0 |
T108 |
37195 |
36 |
0 |
0 |
T136 |
17555 |
22 |
0 |
0 |
T145 |
5081 |
9 |
0 |
0 |
T146 |
5180 |
3 |
0 |
0 |
T147 |
13956 |
57 |
0 |
0 |
T148 |
33593 |
34 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1341 |
0 |
0 |
T57 |
64896 |
78 |
0 |
0 |
T97 |
19520 |
4 |
0 |
0 |
T105 |
103557 |
114 |
0 |
0 |
T107 |
30125 |
37 |
0 |
0 |
T108 |
37195 |
27 |
0 |
0 |
T136 |
17555 |
48 |
0 |
0 |
T145 |
5081 |
7 |
0 |
0 |
T146 |
5180 |
9 |
0 |
0 |
T147 |
13956 |
14 |
0 |
0 |
T148 |
33593 |
45 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
2354 |
0 |
0 |
T57 |
64896 |
217 |
0 |
0 |
T105 |
103557 |
320 |
0 |
0 |
T107 |
30125 |
57 |
0 |
0 |
T108 |
37195 |
87 |
0 |
0 |
T115 |
9691 |
18 |
0 |
0 |
T136 |
17555 |
33 |
0 |
0 |
T145 |
5081 |
4 |
0 |
0 |
T146 |
5180 |
5 |
0 |
0 |
T147 |
13956 |
39 |
0 |
0 |
T148 |
33593 |
94 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1188 |
0 |
0 |
T57 |
64896 |
81 |
0 |
0 |
T105 |
103557 |
130 |
0 |
0 |
T107 |
30125 |
15 |
0 |
0 |
T108 |
37195 |
23 |
0 |
0 |
T115 |
9691 |
6 |
0 |
0 |
T136 |
17555 |
26 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
11 |
0 |
0 |
T147 |
13956 |
28 |
0 |
0 |
T148 |
33593 |
40 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
2834 |
0 |
0 |
T57 |
64896 |
224 |
0 |
0 |
T105 |
103557 |
434 |
0 |
0 |
T107 |
30125 |
37 |
0 |
0 |
T108 |
37195 |
122 |
0 |
0 |
T115 |
9691 |
2 |
0 |
0 |
T136 |
17555 |
28 |
0 |
0 |
T145 |
5081 |
26 |
0 |
0 |
T146 |
5180 |
14 |
0 |
0 |
T147 |
13956 |
34 |
0 |
0 |
T148 |
33593 |
83 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1641 |
0 |
0 |
T57 |
64896 |
106 |
0 |
0 |
T105 |
103557 |
168 |
0 |
0 |
T107 |
30125 |
35 |
0 |
0 |
T108 |
37195 |
61 |
0 |
0 |
T115 |
9691 |
7 |
0 |
0 |
T136 |
17555 |
37 |
0 |
0 |
T145 |
5081 |
1 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
60 |
0 |
0 |
T148 |
33593 |
48 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1289 |
0 |
0 |
T57 |
64896 |
70 |
0 |
0 |
T105 |
103557 |
103 |
0 |
0 |
T107 |
30125 |
23 |
0 |
0 |
T108 |
37195 |
30 |
0 |
0 |
T115 |
9691 |
8 |
0 |
0 |
T136 |
17555 |
47 |
0 |
0 |
T145 |
5081 |
5 |
0 |
0 |
T146 |
5180 |
2 |
0 |
0 |
T147 |
13956 |
53 |
0 |
0 |
T148 |
33593 |
34 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1264 |
0 |
0 |
T57 |
64896 |
48 |
0 |
0 |
T105 |
103557 |
123 |
0 |
0 |
T107 |
30125 |
30 |
0 |
0 |
T108 |
37195 |
25 |
0 |
0 |
T115 |
9691 |
8 |
0 |
0 |
T136 |
17555 |
43 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
4 |
0 |
0 |
T147 |
13956 |
47 |
0 |
0 |
T148 |
33593 |
33 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1398 |
0 |
0 |
T57 |
64896 |
73 |
0 |
0 |
T105 |
103557 |
106 |
0 |
0 |
T107 |
30125 |
19 |
0 |
0 |
T108 |
37195 |
33 |
0 |
0 |
T115 |
9691 |
7 |
0 |
0 |
T136 |
17555 |
50 |
0 |
0 |
T145 |
5081 |
6 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
62 |
0 |
0 |
T148 |
33593 |
34 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1433 |
0 |
0 |
T57 |
64896 |
77 |
0 |
0 |
T105 |
103557 |
94 |
0 |
0 |
T107 |
30125 |
19 |
0 |
0 |
T108 |
37195 |
18 |
0 |
0 |
T115 |
9691 |
3 |
0 |
0 |
T136 |
17555 |
80 |
0 |
0 |
T145 |
5081 |
8 |
0 |
0 |
T146 |
5180 |
15 |
0 |
0 |
T147 |
13956 |
42 |
0 |
0 |
T148 |
33593 |
44 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1296 |
0 |
0 |
T57 |
64896 |
72 |
0 |
0 |
T105 |
103557 |
136 |
0 |
0 |
T107 |
30125 |
24 |
0 |
0 |
T108 |
37195 |
45 |
0 |
0 |
T115 |
9691 |
8 |
0 |
0 |
T136 |
17555 |
64 |
0 |
0 |
T145 |
5081 |
9 |
0 |
0 |
T146 |
5180 |
5 |
0 |
0 |
T147 |
13956 |
44 |
0 |
0 |
T148 |
33593 |
37 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395714596 |
1366 |
0 |
0 |
T57 |
64896 |
60 |
0 |
0 |
T97 |
19520 |
5 |
0 |
0 |
T105 |
103557 |
127 |
0 |
0 |
T107 |
30125 |
23 |
0 |
0 |
T108 |
37195 |
26 |
0 |
0 |
T136 |
17555 |
42 |
0 |
0 |
T145 |
5081 |
4 |
0 |
0 |
T146 |
5180 |
10 |
0 |
0 |
T147 |
13956 |
53 |
0 |
0 |
T148 |
33593 |
42 |
0 |
0 |