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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.93 98.30 94.12 98.61 89.36 97.06 95.83 98.22


Total test records in report: 1081
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T1012 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1053797057 May 19 12:50:37 PM PDT 24 May 19 12:50:44 PM PDT 24 2467852421 ps
T182 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4199045341 May 19 12:50:21 PM PDT 24 May 19 12:50:45 PM PDT 24 6620005270 ps
T1013 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2583766592 May 19 12:50:49 PM PDT 24 May 19 12:50:52 PM PDT 24 13802097 ps
T1014 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.176267174 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 18573737 ps
T1015 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3889843379 May 19 12:50:27 PM PDT 24 May 19 12:50:44 PM PDT 24 789604799 ps
T1016 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.515100270 May 19 12:50:33 PM PDT 24 May 19 12:50:38 PM PDT 24 81368577 ps
T1017 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2372294255 May 19 12:50:25 PM PDT 24 May 19 12:50:29 PM PDT 24 17974201 ps
T1018 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.216744780 May 19 12:50:43 PM PDT 24 May 19 12:50:45 PM PDT 24 14953912 ps
T1019 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3426453681 May 19 12:50:30 PM PDT 24 May 19 12:50:33 PM PDT 24 75477182 ps
T186 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1280989797 May 19 12:50:25 PM PDT 24 May 19 12:50:53 PM PDT 24 4441489883 ps
T1020 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3434796828 May 19 12:50:22 PM PDT 24 May 19 12:50:40 PM PDT 24 1256240135 ps
T1021 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2968224646 May 19 12:50:40 PM PDT 24 May 19 12:50:43 PM PDT 24 16109816 ps
T102 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1916479580 May 19 12:50:43 PM PDT 24 May 19 12:50:46 PM PDT 24 210973489 ps
T1022 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1282359141 May 19 12:50:25 PM PDT 24 May 19 12:50:35 PM PDT 24 352936777 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3631535836 May 19 12:50:28 PM PDT 24 May 19 12:50:31 PM PDT 24 12493203 ps
T1024 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.172197705 May 19 12:50:40 PM PDT 24 May 19 12:50:45 PM PDT 24 211713256 ps
T183 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.924963430 May 19 12:50:46 PM PDT 24 May 19 12:51:09 PM PDT 24 1238440588 ps
T1025 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3917284703 May 19 12:50:38 PM PDT 24 May 19 12:50:44 PM PDT 24 472909378 ps
T101 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.524724673 May 19 12:50:33 PM PDT 24 May 19 12:50:40 PM PDT 24 42651609 ps
T1026 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.678961953 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 44360020 ps
T1027 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.606027533 May 19 12:50:35 PM PDT 24 May 19 12:50:40 PM PDT 24 54618048 ps
T1028 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.571789161 May 19 12:50:42 PM PDT 24 May 19 12:50:44 PM PDT 24 13738099 ps
T1029 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4345808 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 29249866 ps
T78 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4085753369 May 19 12:50:31 PM PDT 24 May 19 12:50:34 PM PDT 24 134091260 ps
T103 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.971703245 May 19 12:50:32 PM PDT 24 May 19 12:50:37 PM PDT 24 261952646 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3562898991 May 19 12:50:27 PM PDT 24 May 19 12:50:32 PM PDT 24 152591673 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1422084846 May 19 12:50:26 PM PDT 24 May 19 12:50:32 PM PDT 24 619022093 ps
T187 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3732845979 May 19 12:50:39 PM PDT 24 May 19 12:50:47 PM PDT 24 311706453 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1922079228 May 19 12:50:29 PM PDT 24 May 19 12:50:33 PM PDT 24 322873637 ps
T1033 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3178998448 May 19 12:50:27 PM PDT 24 May 19 12:50:34 PM PDT 24 318520834 ps
T1034 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.35056698 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 19667826 ps
T1035 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1156591562 May 19 12:50:44 PM PDT 24 May 19 12:50:48 PM PDT 24 41639215 ps
T1036 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1220715392 May 19 12:50:37 PM PDT 24 May 19 12:50:42 PM PDT 24 29093220 ps
T1037 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.594895988 May 19 12:50:26 PM PDT 24 May 19 12:50:37 PM PDT 24 443942728 ps
T122 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2066123735 May 19 12:50:36 PM PDT 24 May 19 12:50:41 PM PDT 24 67348720 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4183800627 May 19 12:50:25 PM PDT 24 May 19 12:50:30 PM PDT 24 62537970 ps
T1039 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.54507893 May 19 12:50:32 PM PDT 24 May 19 12:50:36 PM PDT 24 63187336 ps
T1040 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.994955830 May 19 12:50:50 PM PDT 24 May 19 12:50:54 PM PDT 24 14298929 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1325796549 May 19 12:50:29 PM PDT 24 May 19 12:50:34 PM PDT 24 129588872 ps
T180 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1481792461 May 19 12:50:34 PM PDT 24 May 19 12:50:40 PM PDT 24 27197258 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1116081627 May 19 12:50:27 PM PDT 24 May 19 12:50:31 PM PDT 24 19700731 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1365420946 May 19 12:50:38 PM PDT 24 May 19 12:50:41 PM PDT 24 22359296 ps
T1044 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2854556730 May 19 12:50:48 PM PDT 24 May 19 12:50:51 PM PDT 24 15651816 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.254372698 May 19 12:50:28 PM PDT 24 May 19 12:50:33 PM PDT 24 330936841 ps
T1046 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2896156947 May 19 12:50:37 PM PDT 24 May 19 12:50:43 PM PDT 24 87020598 ps
T1047 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.112459607 May 19 12:50:29 PM PDT 24 May 19 12:50:34 PM PDT 24 61733441 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.397844515 May 19 12:50:26 PM PDT 24 May 19 12:50:43 PM PDT 24 1260654304 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3894553434 May 19 12:50:27 PM PDT 24 May 19 12:50:34 PM PDT 24 229382716 ps
T1050 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3179164345 May 19 12:50:44 PM PDT 24 May 19 12:50:47 PM PDT 24 61945059 ps
T1051 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2723362811 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 17311751 ps
T1052 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2950403055 May 19 12:50:33 PM PDT 24 May 19 12:50:37 PM PDT 24 84482817 ps
T1053 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4094152075 May 19 12:50:28 PM PDT 24 May 19 12:50:33 PM PDT 24 66863469 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3885808106 May 19 12:50:31 PM PDT 24 May 19 12:50:34 PM PDT 24 136431940 ps
T1055 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2972564637 May 19 12:50:25 PM PDT 24 May 19 12:50:30 PM PDT 24 238390495 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.187714930 May 19 12:50:27 PM PDT 24 May 19 12:50:32 PM PDT 24 329133024 ps
T1057 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1222609095 May 19 12:50:45 PM PDT 24 May 19 12:50:49 PM PDT 24 40351742 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2361408712 May 19 12:50:34 PM PDT 24 May 19 12:50:46 PM PDT 24 273735417 ps
T1059 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1901451409 May 19 12:50:48 PM PDT 24 May 19 12:50:51 PM PDT 24 140210288 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3004789728 May 19 12:50:30 PM PDT 24 May 19 12:50:37 PM PDT 24 278088594 ps
T1061 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1204110029 May 19 12:50:34 PM PDT 24 May 19 12:50:41 PM PDT 24 241349570 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4242146103 May 19 12:50:27 PM PDT 24 May 19 12:50:31 PM PDT 24 131090326 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2558832626 May 19 12:50:26 PM PDT 24 May 19 12:50:53 PM PDT 24 12046056950 ps
T1064 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4261564109 May 19 12:50:47 PM PDT 24 May 19 12:50:50 PM PDT 24 14780786 ps
T1065 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1096760786 May 19 12:50:33 PM PDT 24 May 19 12:50:44 PM PDT 24 808445953 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2496090975 May 19 12:50:26 PM PDT 24 May 19 12:50:32 PM PDT 24 1372809657 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2107988061 May 19 12:50:44 PM PDT 24 May 19 12:50:46 PM PDT 24 50290196 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2831310276 May 19 12:50:28 PM PDT 24 May 19 12:50:34 PM PDT 24 222130705 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3704815256 May 19 12:50:24 PM PDT 24 May 19 12:50:29 PM PDT 24 104800079 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2017314247 May 19 12:50:30 PM PDT 24 May 19 12:50:47 PM PDT 24 693315569 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4245188613 May 19 12:50:34 PM PDT 24 May 19 12:50:40 PM PDT 24 31681162 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1863295024 May 19 12:50:33 PM PDT 24 May 19 12:50:37 PM PDT 24 38153850 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3473472083 May 19 12:50:31 PM PDT 24 May 19 12:50:36 PM PDT 24 226065730 ps
T1074 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3651024429 May 19 12:50:43 PM PDT 24 May 19 12:50:47 PM PDT 24 114000734 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1167392215 May 19 12:50:24 PM PDT 24 May 19 12:50:28 PM PDT 24 35316106 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.258017838 May 19 12:50:30 PM PDT 24 May 19 12:50:33 PM PDT 24 69511998 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3737871727 May 19 12:50:34 PM PDT 24 May 19 12:50:38 PM PDT 24 20200994 ps
T181 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4255463954 May 19 12:50:26 PM PDT 24 May 19 12:50:33 PM PDT 24 162079693 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.488564029 May 19 12:50:40 PM PDT 24 May 19 12:50:55 PM PDT 24 194184360 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3800050272 May 19 12:50:34 PM PDT 24 May 19 12:51:02 PM PDT 24 4837997421 ps
T1080 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.812516105 May 19 12:50:31 PM PDT 24 May 19 12:50:35 PM PDT 24 31584630 ps
T1081 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2979298539 May 19 12:50:43 PM PDT 24 May 19 12:50:46 PM PDT 24 29944848 ps

Test location /workspace/coverage/default/36.spi_device_stress_all.2969235013
Short name T9
Test name
Test status
Simulation time 8056236624 ps
CPU time 140.58 seconds
Started May 19 12:52:43 PM PDT 24
Finished May 19 12:55:05 PM PDT 24
Peak memory 266332 kb
Host smart-22ea6cfe-b58a-4b52-8c48-ca7b5230a0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969235013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2969235013
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1450077493
Short name T16
Test name
Test status
Simulation time 70102641256 ps
CPU time 163.36 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 251376 kb
Host smart-f09f892a-0e74-4295-bd7c-b835e04128d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450077493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1450077493
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1100252997
Short name T32
Test name
Test status
Simulation time 38133847472 ps
CPU time 313.22 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:57:38 PM PDT 24
Peak memory 266612 kb
Host smart-88020f7a-3712-4255-a69a-3ed52109fe22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100252997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1100252997
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2453336095
Short name T105
Test name
Test status
Simulation time 4315013257 ps
CPU time 22.36 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:51:02 PM PDT 24
Peak memory 215152 kb
Host smart-c1246818-86ab-42a3-88d0-66c9f1df1846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453336095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2453336095
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4026045533
Short name T79
Test name
Test status
Simulation time 80400570887 ps
CPU time 813.61 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 01:05:51 PM PDT 24
Peak memory 265396 kb
Host smart-cb8a2605-7e62-4e62-974c-8a6dc2a99287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026045533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4026045533
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2499100860
Short name T167
Test name
Test status
Simulation time 97410999820 ps
CPU time 572.83 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 01:02:39 PM PDT 24
Peak memory 265504 kb
Host smart-ab95df4e-6277-40b3-9257-eaf89fcc1abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499100860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2499100860
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.310493224
Short name T59
Test name
Test status
Simulation time 31090606 ps
CPU time 0.76 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:15 PM PDT 24
Peak memory 215868 kb
Host smart-4747f299-10eb-4824-8dba-dbab62cf90eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310493224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.310493224
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3857296713
Short name T31
Test name
Test status
Simulation time 202481358263 ps
CPU time 443.05 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:59:32 PM PDT 24
Peak memory 272832 kb
Host smart-3e5c1f1f-41db-43ea-b9d4-fcbd8f03c2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857296713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3857296713
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3871256490
Short name T29
Test name
Test status
Simulation time 51416967719 ps
CPU time 434.47 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:59:34 PM PDT 24
Peak memory 251556 kb
Host smart-8ad684af-be22-466e-8959-52750192df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871256490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3871256490
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1168721123
Short name T150
Test name
Test status
Simulation time 93051478753 ps
CPU time 445.28 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:59:17 PM PDT 24
Peak memory 262536 kb
Host smart-223f9033-23e4-4451-89e5-a2b1be2149ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168721123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1168721123
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3076846570
Short name T141
Test name
Test status
Simulation time 5935100264 ps
CPU time 29.51 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:53:20 PM PDT 24
Peak memory 232452 kb
Host smart-fa0521dc-6486-404d-acd9-ce465a978cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076846570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3076846570
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1293456219
Short name T95
Test name
Test status
Simulation time 331409580 ps
CPU time 3.34 seconds
Started May 19 12:50:28 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 215308 kb
Host smart-8029278e-b684-47f6-a852-c68224cc4917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293456219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
293456219
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1322955507
Short name T133
Test name
Test status
Simulation time 160864651236 ps
CPU time 752.09 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 01:04:43 PM PDT 24
Peak memory 282060 kb
Host smart-69ab38c1-8c15-4929-8502-79776f7fb743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322955507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1322955507
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1952489182
Short name T53
Test name
Test status
Simulation time 24259133 ps
CPU time 0.73 seconds
Started May 19 12:51:35 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 205136 kb
Host smart-2ec80338-068e-44ef-b856-63dc2241bbf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952489182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1952489182
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3059864248
Short name T34
Test name
Test status
Simulation time 12811121259 ps
CPU time 165.46 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:54:55 PM PDT 24
Peak memory 252636 kb
Host smart-6cc58c8f-382d-49b8-be12-ecd37eb22779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059864248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3059864248
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3886269342
Short name T33
Test name
Test status
Simulation time 42547274448 ps
CPU time 383.6 seconds
Started May 19 12:51:50 PM PDT 24
Finished May 19 12:58:15 PM PDT 24
Peak memory 249072 kb
Host smart-0cf5b63f-16f7-4a61-a0d1-db4b0487e312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886269342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3886269342
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.632196090
Short name T115
Test name
Test status
Simulation time 96944582 ps
CPU time 2.44 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 214972 kb
Host smart-bbe8953b-2770-4082-b5ea-a853938db9a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632196090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.632196090
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3540538865
Short name T35
Test name
Test status
Simulation time 234595802006 ps
CPU time 429.86 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 01:00:11 PM PDT 24
Peak memory 255796 kb
Host smart-d0d7f6d0-e5e7-4c96-bb5a-1fbd7e618479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540538865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3540538865
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.491785030
Short name T26
Test name
Test status
Simulation time 554989441531 ps
CPU time 427.66 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 01:00:07 PM PDT 24
Peak memory 255544 kb
Host smart-55e5064e-9051-4556-9acc-c1cb1a6a7ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491785030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.491785030
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1673980188
Short name T170
Test name
Test status
Simulation time 57100008945 ps
CPU time 590.68 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 01:01:15 PM PDT 24
Peak memory 264752 kb
Host smart-8ea7b40e-e525-42e1-a1df-0057cfd22bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673980188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1673980188
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2371669318
Short name T270
Test name
Test status
Simulation time 456826495453 ps
CPU time 307.87 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:58:01 PM PDT 24
Peak memory 252824 kb
Host smart-87284146-36e4-44a6-aa7f-6e6ab7812713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371669318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2371669318
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3247819691
Short name T62
Test name
Test status
Simulation time 81856145 ps
CPU time 1.22 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:19 PM PDT 24
Peak memory 234564 kb
Host smart-f1eac06e-e6c4-4e17-82a9-fa8329d9d3b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247819691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3247819691
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2246743709
Short name T189
Test name
Test status
Simulation time 19675266216 ps
CPU time 163.85 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:55:45 PM PDT 24
Peak memory 257120 kb
Host smart-29619ba3-b241-4a88-97b9-8136384a4e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246743709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2246743709
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.381794821
Short name T25
Test name
Test status
Simulation time 15468742543 ps
CPU time 96.09 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 257040 kb
Host smart-878dcafd-666a-4362-9838-6ec2a848db23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381794821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.381794821
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2287437729
Short name T80
Test name
Test status
Simulation time 19981528973 ps
CPU time 215.65 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 12:55:57 PM PDT 24
Peak memory 250796 kb
Host smart-1e71afa4-26b8-4668-8473-f915c01d923f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287437729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2287437729
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4199045341
Short name T182
Test name
Test status
Simulation time 6620005270 ps
CPU time 21.45 seconds
Started May 19 12:50:21 PM PDT 24
Finished May 19 12:50:45 PM PDT 24
Peak memory 215436 kb
Host smart-3807d446-acc6-4a0a-8ddc-e02dae99514d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199045341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4199045341
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3977756169
Short name T191
Test name
Test status
Simulation time 13359764821 ps
CPU time 183.46 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:55:27 PM PDT 24
Peak memory 267960 kb
Host smart-b0e07caf-be63-43a3-ba11-64f6058652bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977756169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3977756169
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3258127805
Short name T100
Test name
Test status
Simulation time 94285474 ps
CPU time 2.52 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 216240 kb
Host smart-900e9059-a393-4752-bdbc-92c3703ffd90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258127805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
258127805
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3738943989
Short name T11
Test name
Test status
Simulation time 108855022 ps
CPU time 2.13 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:17 PM PDT 24
Peak memory 218472 kb
Host smart-d40f4128-dc50-4c97-b3f9-c3958f61967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738943989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3738943989
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1756797771
Short name T19
Test name
Test status
Simulation time 14065354314 ps
CPU time 138.42 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:54:46 PM PDT 24
Peak memory 249004 kb
Host smart-84a9b40b-de83-4875-8537-da49eda30c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756797771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1756797771
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2824379658
Short name T223
Test name
Test status
Simulation time 2919088529 ps
CPU time 24.08 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:41 PM PDT 24
Peak memory 233968 kb
Host smart-40c462af-43c9-4693-9bd1-135d3d04c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824379658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2824379658
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3025275521
Short name T134
Test name
Test status
Simulation time 30391520127 ps
CPU time 137.91 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:54:30 PM PDT 24
Peak memory 272704 kb
Host smart-b0543278-1a37-4f0e-8c83-45e42438f377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025275521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3025275521
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.682501666
Short name T269
Test name
Test status
Simulation time 108311525701 ps
CPU time 329.93 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:57:56 PM PDT 24
Peak memory 266636 kb
Host smart-d53338d9-9e35-4e48-9221-a26e81854df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682501666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.682501666
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.194998808
Short name T40
Test name
Test status
Simulation time 4125415305 ps
CPU time 51.03 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 251244 kb
Host smart-5afbe5cb-05bf-4419-bfe1-f51107a1b5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194998808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.194998808
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2871121924
Short name T98
Test name
Test status
Simulation time 935080339 ps
CPU time 22.29 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:51:01 PM PDT 24
Peak memory 215856 kb
Host smart-b7b7c1e7-057c-4cea-a7b7-2fe92c9759b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871121924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2871121924
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4099448325
Short name T68
Test name
Test status
Simulation time 7593977211 ps
CPU time 44.75 seconds
Started May 19 12:51:45 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 236608 kb
Host smart-92dd5a02-76fa-4a67-8f2f-2d848edda919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099448325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4099448325
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2688761085
Short name T291
Test name
Test status
Simulation time 13375474401 ps
CPU time 185.84 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:55:24 PM PDT 24
Peak memory 250380 kb
Host smart-abec6959-8715-4244-9bdb-d8810cb4f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688761085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2688761085
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2379021894
Short name T295
Test name
Test status
Simulation time 461369524325 ps
CPU time 206.84 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 12:55:49 PM PDT 24
Peak memory 254688 kb
Host smart-490426f0-f9ad-4c05-bf13-afdcaa35425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379021894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2379021894
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3939760814
Short name T260
Test name
Test status
Simulation time 47521138123 ps
CPU time 151.78 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:55:15 PM PDT 24
Peak memory 264812 kb
Host smart-41dc6875-a350-4fa4-a2f9-ef1daec8360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939760814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3939760814
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3529317840
Short name T69
Test name
Test status
Simulation time 52229639703 ps
CPU time 110.18 seconds
Started May 19 12:51:12 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 239396 kb
Host smart-689fd276-76b1-4d34-9eaa-00794e4a818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529317840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3529317840
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.653754672
Short name T209
Test name
Test status
Simulation time 236115341 ps
CPU time 5.29 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 218496 kb
Host smart-30e4fa1c-418b-45b8-a263-4c54775fc055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653754672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.653754672
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3811694623
Short name T304
Test name
Test status
Simulation time 59787500872 ps
CPU time 376.19 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:57:29 PM PDT 24
Peak memory 256896 kb
Host smart-476ba13e-f7c6-460d-9b50-36649328b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811694623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3811694623
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.56064690
Short name T834
Test name
Test status
Simulation time 1697232401 ps
CPU time 17.7 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:39 PM PDT 24
Peak memory 240564 kb
Host smart-a1d99410-f098-48a9-967e-cbbb211aa262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56064690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.56064690
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.168004093
Short name T17
Test name
Test status
Simulation time 4526259014 ps
CPU time 30.75 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:52:23 PM PDT 24
Peak memory 249500 kb
Host smart-a9e7b0af-28f5-47e3-ace7-1aac9ad87747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168004093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.168004093
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_intercept.510264288
Short name T456
Test name
Test status
Simulation time 3264343988 ps
CPU time 5.19 seconds
Started May 19 12:51:33 PM PDT 24
Finished May 19 12:51:39 PM PDT 24
Peak memory 233404 kb
Host smart-4b88bdfa-9f7b-4a82-a3b4-81125bc8b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510264288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.510264288
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.519527421
Short name T365
Test name
Test status
Simulation time 5220424614 ps
CPU time 6.45 seconds
Started May 19 12:51:50 PM PDT 24
Finished May 19 12:51:58 PM PDT 24
Peak memory 216080 kb
Host smart-d23289d0-76c7-4c9a-9aab-4dbd1f72d3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519527421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.519527421
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2215259520
Short name T305
Test name
Test status
Simulation time 93995846471 ps
CPU time 218.54 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:55:49 PM PDT 24
Peak memory 251752 kb
Host smart-b68bda18-bf96-4117-9de9-6dc93ac8ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215259520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2215259520
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.396094764
Short name T317
Test name
Test status
Simulation time 826257685 ps
CPU time 8.65 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 224172 kb
Host smart-a5031951-e99c-4fee-b1f5-9ef03c29b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396094764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.396094764
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2903016414
Short name T288
Test name
Test status
Simulation time 729778562005 ps
CPU time 511.68 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 01:00:53 PM PDT 24
Peak memory 270816 kb
Host smart-7b5551d3-8a84-4000-b250-13070bf0c274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903016414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2903016414
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4139072634
Short name T234
Test name
Test status
Simulation time 6542621981 ps
CPU time 47.37 seconds
Started May 19 12:52:46 PM PDT 24
Finished May 19 12:53:34 PM PDT 24
Peak memory 248888 kb
Host smart-f252d374-5401-4b84-8d15-40ca9d636440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139072634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4139072634
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2621844176
Short name T296
Test name
Test status
Simulation time 37665483003 ps
CPU time 469.12 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:59:11 PM PDT 24
Peak memory 283272 kb
Host smart-584fbc68-dfa0-499c-8ea6-213d35b7c850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621844176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2621844176
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3541013197
Short name T90
Test name
Test status
Simulation time 142699522 ps
CPU time 2.7 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 215256 kb
Host smart-cb280470-134f-48ce-b065-3e5083161414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541013197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3541013197
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1966786856
Short name T74
Test name
Test status
Simulation time 351222244 ps
CPU time 4.88 seconds
Started May 19 12:51:48 PM PDT 24
Finished May 19 12:51:55 PM PDT 24
Peak memory 234528 kb
Host smart-82e3cc92-2b4b-46c5-ae30-ab7317280b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966786856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1966786856
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2333334770
Short name T75
Test name
Test status
Simulation time 44860201 ps
CPU time 1.43 seconds
Started May 19 12:50:22 PM PDT 24
Finished May 19 12:50:26 PM PDT 24
Peak memory 206828 kb
Host smart-a922880f-aba6-44a9-afaf-0d0c9e188c49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333334770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2333334770
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3434796828
Short name T1020
Test name
Test status
Simulation time 1256240135 ps
CPU time 15.84 seconds
Started May 19 12:50:22 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 206720 kb
Host smart-9513d05f-d13d-47ac-8bff-3a8e9b913c36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434796828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3434796828
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.397844515
Short name T1048
Test name
Test status
Simulation time 1260654304 ps
CPU time 14.27 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 206704 kb
Host smart-702f56dc-56e1-4e3d-b8bf-b5e0089081c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397844515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.397844515
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3890694059
Short name T77
Test name
Test status
Simulation time 41246071 ps
CPU time 0.94 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:31 PM PDT 24
Peak memory 206568 kb
Host smart-1c8be5c1-1c77-4380-8190-560e2857f822
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890694059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3890694059
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2158391481
Short name T145
Test name
Test status
Simulation time 211798456 ps
CPU time 1.71 seconds
Started May 19 12:50:24 PM PDT 24
Finished May 19 12:50:28 PM PDT 24
Peak memory 215200 kb
Host smart-d6e0f18d-c566-47b6-b722-694461eaa282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158391481 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2158391481
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3443445685
Short name T111
Test name
Test status
Simulation time 91592410 ps
CPU time 3.05 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 206728 kb
Host smart-faefc448-7f7d-45f9-a715-ef3f51d27828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443445685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
443445685
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1167392215
Short name T1075
Test name
Test status
Simulation time 35316106 ps
CPU time 0.72 seconds
Started May 19 12:50:24 PM PDT 24
Finished May 19 12:50:28 PM PDT 24
Peak memory 203728 kb
Host smart-c2ee065d-ae67-43bc-96c1-b2298aed551c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167392215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
167392215
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4242146103
Short name T1062
Test name
Test status
Simulation time 131090326 ps
CPU time 1.28 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:31 PM PDT 24
Peak memory 215080 kb
Host smart-bfabd719-8973-414b-b1ad-4a9185bd3c9c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242146103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4242146103
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2164316981
Short name T960
Test name
Test status
Simulation time 15343268 ps
CPU time 0.66 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 203288 kb
Host smart-4819bdbe-7edc-4e3f-b3e2-f676251e9dec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164316981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2164316981
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2496090975
Short name T1066
Test name
Test status
Simulation time 1372809657 ps
CPU time 3.72 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 215076 kb
Host smart-149f1cb7-36df-43cd-8d5f-f5da6a3b118d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496090975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2496090975
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4183800627
Short name T1038
Test name
Test status
Simulation time 62537970 ps
CPU time 1.97 seconds
Started May 19 12:50:25 PM PDT 24
Finished May 19 12:50:30 PM PDT 24
Peak memory 215184 kb
Host smart-febcde7b-d845-401e-b9dc-6fdcb8bd2d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183800627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
183800627
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3269567493
Short name T991
Test name
Test status
Simulation time 583690742 ps
CPU time 16.93 seconds
Started May 19 12:50:28 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 215004 kb
Host smart-cbbb0b64-ad80-460c-8c95-916d40b75273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269567493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3269567493
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1282359141
Short name T1022
Test name
Test status
Simulation time 352936777 ps
CPU time 7.54 seconds
Started May 19 12:50:25 PM PDT 24
Finished May 19 12:50:35 PM PDT 24
Peak memory 206824 kb
Host smart-5670c26e-d895-4aaa-a83e-335b9e970304
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282359141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1282359141
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4252062584
Short name T1005
Test name
Test status
Simulation time 353861553 ps
CPU time 22.23 seconds
Started May 19 12:50:24 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 206864 kb
Host smart-94b4ed63-3090-4701-aa3e-be9418205ff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252062584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4252062584
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3894553434
Short name T1049
Test name
Test status
Simulation time 229382716 ps
CPU time 4.09 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 217044 kb
Host smart-b98ec451-5400-4214-8070-7eda9638fdce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894553434 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3894553434
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3562898991
Short name T1030
Test name
Test status
Simulation time 152591673 ps
CPU time 2.16 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 214968 kb
Host smart-932d047d-ba74-4abf-b68b-5169c52025a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562898991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
562898991
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2372294255
Short name T1017
Test name
Test status
Simulation time 17974201 ps
CPU time 0.69 seconds
Started May 19 12:50:25 PM PDT 24
Finished May 19 12:50:29 PM PDT 24
Peak memory 203720 kb
Host smart-98274531-5799-4527-b214-b6a1eb936ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372294255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
372294255
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1634558090
Short name T112
Test name
Test status
Simulation time 27240820 ps
CPU time 2.04 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 215032 kb
Host smart-e8ca9c0a-ad2a-4e0d-969a-171087f93fd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634558090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1634558090
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3631535836
Short name T1023
Test name
Test status
Simulation time 12493203 ps
CPU time 0.64 seconds
Started May 19 12:50:28 PM PDT 24
Finished May 19 12:50:31 PM PDT 24
Peak memory 203312 kb
Host smart-2c193d28-93c2-49fd-8f6e-9b15d67a4d66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631535836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3631535836
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3704815256
Short name T1069
Test name
Test status
Simulation time 104800079 ps
CPU time 2.84 seconds
Started May 19 12:50:24 PM PDT 24
Finished May 19 12:50:29 PM PDT 24
Peak memory 215008 kb
Host smart-601fbd0b-23be-4f19-b5d8-c39e761624f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704815256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3704815256
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1422084846
Short name T1031
Test name
Test status
Simulation time 619022093 ps
CPU time 3.16 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 215228 kb
Host smart-86373c3e-7908-4e05-94b4-98d1a2fc78d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422084846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
422084846
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1810837562
Short name T106
Test name
Test status
Simulation time 24602511 ps
CPU time 1.68 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 216160 kb
Host smart-91381ccf-be7d-442e-9b3f-e28b57e338aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810837562 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1810837562
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3213286523
Short name T962
Test name
Test status
Simulation time 234115136 ps
CPU time 0.73 seconds
Started May 19 12:50:42 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 203520 kb
Host smart-401a5890-caf9-474f-93bf-33b98058be79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213286523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3213286523
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4134765546
Short name T1007
Test name
Test status
Simulation time 211852860 ps
CPU time 4.37 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 215044 kb
Host smart-398a1d56-8b03-4ca7-8870-37af6aaf9d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134765546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4134765546
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2032033366
Short name T89
Test name
Test status
Simulation time 143469315 ps
CPU time 4.47 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 215164 kb
Host smart-98df0db5-8257-46ac-b692-7bc31fe6172b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032033366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2032033366
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3814141134
Short name T56
Test name
Test status
Simulation time 577184036 ps
CPU time 15.4 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:54 PM PDT 24
Peak memory 215132 kb
Host smart-08ab942e-5497-4ae8-95c8-0b23f79b0b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814141134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3814141134
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2564385331
Short name T96
Test name
Test status
Simulation time 416652996 ps
CPU time 3.93 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 216764 kb
Host smart-96ae3260-97d6-4722-bd30-6453778b20e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564385331 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2564385331
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2942375255
Short name T120
Test name
Test status
Simulation time 26253551 ps
CPU time 1.83 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 214960 kb
Host smart-294103de-66ed-44b6-8915-1f2d41b0628f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942375255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2942375255
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.851060077
Short name T966
Test name
Test status
Simulation time 33539955 ps
CPU time 0.75 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 203728 kb
Host smart-c09f3977-2b7f-41f8-b53a-3169c085b139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851060077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.851060077
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1204110029
Short name T1061
Test name
Test status
Simulation time 241349570 ps
CPU time 2.83 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 215128 kb
Host smart-bb90efe0-ea5d-47bf-bb94-34f47fbcdfab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204110029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1204110029
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2742319844
Short name T108
Test name
Test status
Simulation time 743946476 ps
CPU time 8.82 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 214964 kb
Host smart-bf4f7fb8-4209-46df-81c5-d7877f0f7b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742319844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2742319844
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2774005543
Short name T91
Test name
Test status
Simulation time 57871623 ps
CPU time 3.55 seconds
Started May 19 12:50:37 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 217180 kb
Host smart-76100907-31ea-43ec-b0e6-164a951cfeeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774005543 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2774005543
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3324422046
Short name T119
Test name
Test status
Simulation time 28806571 ps
CPU time 1.79 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 206788 kb
Host smart-6e8711b1-af96-4e9b-9e36-8784b97cdbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324422046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3324422046
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2706404909
Short name T1000
Test name
Test status
Simulation time 42938081 ps
CPU time 0.75 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:35 PM PDT 24
Peak memory 203824 kb
Host smart-563623b8-e686-44e2-bbf3-9c1705e389d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706404909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2706404909
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3348398685
Short name T997
Test name
Test status
Simulation time 221344531 ps
CPU time 3.02 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 215056 kb
Host smart-95d80358-7eda-4419-99fd-edb596225e20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348398685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3348398685
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.413017615
Short name T97
Test name
Test status
Simulation time 382782177 ps
CPU time 4.62 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 215224 kb
Host smart-6b91ef5f-23df-433f-8365-dfdefc22b685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413017615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.413017615
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1096760786
Short name T1065
Test name
Test status
Simulation time 808445953 ps
CPU time 7.17 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 215128 kb
Host smart-fe678844-bfe3-4b05-a652-c56a70413b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096760786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1096760786
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2786759012
Short name T104
Test name
Test status
Simulation time 143678243 ps
CPU time 2.84 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 216944 kb
Host smart-e1e2f68d-594a-4142-9c2f-0ec79166798a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786759012 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2786759012
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2479901659
Short name T1001
Test name
Test status
Simulation time 253846215 ps
CPU time 2.73 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:42 PM PDT 24
Peak memory 214844 kb
Host smart-a264878e-827c-430b-ac13-39c66edfca05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479901659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2479901659
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2024413768
Short name T969
Test name
Test status
Simulation time 18114075 ps
CPU time 0.75 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 203372 kb
Host smart-e4e00ba0-2fae-48fb-927a-73b2ef031cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024413768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2024413768
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3775863502
Short name T1003
Test name
Test status
Simulation time 244367291 ps
CPU time 1.82 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 214996 kb
Host smart-09114c99-c85c-43aa-8853-78378672223e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775863502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3775863502
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1481792461
Short name T180
Test name
Test status
Simulation time 27197258 ps
CPU time 1.75 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 215516 kb
Host smart-3b0d72f3-08ed-42fc-912b-72f3375310dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481792461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1481792461
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1734021112
Short name T109
Test name
Test status
Simulation time 104140266 ps
CPU time 2.07 seconds
Started May 19 12:50:37 PM PDT 24
Finished May 19 12:50:42 PM PDT 24
Peak memory 216064 kb
Host smart-798d419c-568f-4d40-8ccd-8368c799fb40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734021112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1734021112
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1863295024
Short name T1072
Test name
Test status
Simulation time 38153850 ps
CPU time 1.35 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 214988 kb
Host smart-e4da5a97-dc6f-4c86-8418-df14f6152d67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863295024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1863295024
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1293329980
Short name T1006
Test name
Test status
Simulation time 32130865 ps
CPU time 0.75 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 203376 kb
Host smart-ad09614f-20d7-41b1-be81-9dd3e73e88b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293329980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1293329980
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3943684078
Short name T963
Test name
Test status
Simulation time 66162345 ps
CPU time 1.92 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 215000 kb
Host smart-b26df336-345b-4122-be44-b9984efb6b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943684078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3943684078
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.606027533
Short name T1027
Test name
Test status
Simulation time 54618048 ps
CPU time 1.65 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 215192 kb
Host smart-7f359fc0-f07f-455c-ba9f-f6e3f987baca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606027533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.606027533
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1426935418
Short name T55
Test name
Test status
Simulation time 1809261262 ps
CPU time 7.52 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:47 PM PDT 24
Peak memory 214988 kb
Host smart-9dfa9bab-8db7-455b-9323-49b5bbe0177a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426935418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1426935418
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.983434977
Short name T995
Test name
Test status
Simulation time 94036277 ps
CPU time 1.73 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 216088 kb
Host smart-5b6008c7-a032-4edb-a8c1-c88c839dc366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983434977 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.983434977
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.360025120
Short name T964
Test name
Test status
Simulation time 208228115 ps
CPU time 2.7 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:42 PM PDT 24
Peak memory 214972 kb
Host smart-97109501-0edf-4277-a35e-8dcbd77e6a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360025120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.360025120
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1365420946
Short name T1043
Test name
Test status
Simulation time 22359296 ps
CPU time 0.79 seconds
Started May 19 12:50:38 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 203396 kb
Host smart-a9766593-bc3e-4404-8ff0-c502b3995d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365420946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1365420946
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.172197705
Short name T1024
Test name
Test status
Simulation time 211713256 ps
CPU time 3.49 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:45 PM PDT 24
Peak memory 215020 kb
Host smart-69572ad4-51e5-49cc-b458-48870c8ef00d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172197705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.172197705
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1220715392
Short name T1036
Test name
Test status
Simulation time 29093220 ps
CPU time 2.07 seconds
Started May 19 12:50:37 PM PDT 24
Finished May 19 12:50:42 PM PDT 24
Peak memory 215268 kb
Host smart-f64cce17-7ea7-4973-8340-6472cedbc1b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220715392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1220715392
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2361408712
Short name T1058
Test name
Test status
Simulation time 273735417 ps
CPU time 8.69 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 215100 kb
Host smart-66192597-9cf5-4725-8341-5fe9c632d8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361408712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2361408712
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1884870863
Short name T967
Test name
Test status
Simulation time 57989014 ps
CPU time 3.93 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 216340 kb
Host smart-d4aa5c77-d55b-41a5-b793-4d0a66090ef7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884870863 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1884870863
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.683624886
Short name T118
Test name
Test status
Simulation time 27245377 ps
CPU time 2.07 seconds
Started May 19 12:50:44 PM PDT 24
Finished May 19 12:50:47 PM PDT 24
Peak memory 214980 kb
Host smart-f46969be-56cc-4152-a4cb-3991f2c902c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683624886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.683624886
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.571789161
Short name T1028
Test name
Test status
Simulation time 13738099 ps
CPU time 0.78 seconds
Started May 19 12:50:42 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 203432 kb
Host smart-f8439354-ae2d-47bf-b502-70a54e775c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571789161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.571789161
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.541431052
Short name T147
Test name
Test status
Simulation time 581583957 ps
CPU time 3.22 seconds
Started May 19 12:50:39 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 215332 kb
Host smart-b463a79d-5a27-4168-9841-25eecd21c882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541431052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.541431052
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3002314322
Short name T99
Test name
Test status
Simulation time 228544245 ps
CPU time 1.54 seconds
Started May 19 12:50:46 PM PDT 24
Finished May 19 12:50:51 PM PDT 24
Peak memory 215192 kb
Host smart-fcbf65c9-2b1e-4b85-957c-05d0cf96b546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002314322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3002314322
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3732845979
Short name T187
Test name
Test status
Simulation time 311706453 ps
CPU time 6.36 seconds
Started May 19 12:50:39 PM PDT 24
Finished May 19 12:50:47 PM PDT 24
Peak memory 214980 kb
Host smart-32df77df-82fb-4d2b-bb45-64caaf0bccce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732845979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3732845979
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2583738964
Short name T992
Test name
Test status
Simulation time 58482461 ps
CPU time 1.86 seconds
Started May 19 12:50:46 PM PDT 24
Finished May 19 12:50:51 PM PDT 24
Peak memory 215232 kb
Host smart-1b38e523-3742-4105-9cb0-d7491b8bd2de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583738964 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2583738964
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3507805123
Short name T117
Test name
Test status
Simulation time 395921765 ps
CPU time 2.76 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:45 PM PDT 24
Peak memory 206712 kb
Host smart-b58691a9-86a4-4a1d-8344-41cb5bf57c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507805123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3507805123
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2013861004
Short name T981
Test name
Test status
Simulation time 23094046 ps
CPU time 0.72 seconds
Started May 19 12:50:39 PM PDT 24
Finished May 19 12:50:42 PM PDT 24
Peak memory 203392 kb
Host smart-1ae8c4c2-8ee4-49b8-aa49-fd002ee807a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013861004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2013861004
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.763018916
Short name T988
Test name
Test status
Simulation time 107129330 ps
CPU time 3.33 seconds
Started May 19 12:50:39 PM PDT 24
Finished May 19 12:50:45 PM PDT 24
Peak memory 215384 kb
Host smart-61d84ec9-7b19-4b21-8caf-096dfc9e64b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763018916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.763018916
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2583644166
Short name T94
Test name
Test status
Simulation time 92955957 ps
CPU time 3.07 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:45 PM PDT 24
Peak memory 216308 kb
Host smart-a1fecb04-982f-439a-ae2a-e89f13cae60e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583644166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2583644166
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.927765654
Short name T107
Test name
Test status
Simulation time 614817624 ps
CPU time 7.13 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 215064 kb
Host smart-8ce2c5ad-7ee5-4db3-9b25-f88fb0857b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927765654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.927765654
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3917284703
Short name T1025
Test name
Test status
Simulation time 472909378 ps
CPU time 3.78 seconds
Started May 19 12:50:38 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 216836 kb
Host smart-a1b3154e-3748-43bf-b4bd-42ffe961b263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917284703 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3917284703
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1487959745
Short name T114
Test name
Test status
Simulation time 35122916 ps
CPU time 1.25 seconds
Started May 19 12:50:41 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 214964 kb
Host smart-f7a3ae30-ad86-4984-b241-8b62e0aa8e74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487959745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1487959745
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4010313359
Short name T979
Test name
Test status
Simulation time 27400462 ps
CPU time 0.68 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203432 kb
Host smart-8404ee16-3967-4db6-9649-4bfd2430f280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010313359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4010313359
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2381041854
Short name T978
Test name
Test status
Simulation time 988101781 ps
CPU time 4.08 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 215040 kb
Host smart-4730934d-3bf8-432b-ae10-198c2da7ab3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381041854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2381041854
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3651024429
Short name T1074
Test name
Test status
Simulation time 114000734 ps
CPU time 2.49 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:47 PM PDT 24
Peak memory 215348 kb
Host smart-0c6a0671-b00e-4e93-9b5b-5f0765d2ee88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651024429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3651024429
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.924963430
Short name T183
Test name
Test status
Simulation time 1238440588 ps
CPU time 19.88 seconds
Started May 19 12:50:46 PM PDT 24
Finished May 19 12:51:09 PM PDT 24
Peak memory 215012 kb
Host smart-47d85a4e-c9c6-4119-9c71-2904a34d57a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924963430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.924963430
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1053797057
Short name T1012
Test name
Test status
Simulation time 2467852421 ps
CPU time 3.79 seconds
Started May 19 12:50:37 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 218352 kb
Host smart-daf61548-f7b4-43ac-9b35-65553129b6f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053797057 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1053797057
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3770632517
Short name T116
Test name
Test status
Simulation time 132290650 ps
CPU time 2.58 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 207176 kb
Host smart-357cacb0-c08b-4b47-80ac-3eac08a5f324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770632517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3770632517
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2107988061
Short name T1067
Test name
Test status
Simulation time 50290196 ps
CPU time 0.81 seconds
Started May 19 12:50:44 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 203716 kb
Host smart-ede6cb9d-2893-4544-98fa-5415e0a068eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107988061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2107988061
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2750602907
Short name T970
Test name
Test status
Simulation time 289920262 ps
CPU time 2.89 seconds
Started May 19 12:50:41 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 215352 kb
Host smart-1a9e6868-6e29-47cd-b5e8-cac8e94521d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750602907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2750602907
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1916479580
Short name T102
Test name
Test status
Simulation time 210973489 ps
CPU time 1.81 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 215228 kb
Host smart-d1d7e838-50b8-442d-bbda-a5f2b4a730a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916479580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1916479580
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.488564029
Short name T1078
Test name
Test status
Simulation time 194184360 ps
CPU time 12.8 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:55 PM PDT 24
Peak memory 214956 kb
Host smart-9053e6ba-d715-4516-9aee-1e747c0a91ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488564029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.488564029
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.594895988
Short name T1037
Test name
Test status
Simulation time 443942728 ps
CPU time 8.77 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 206760 kb
Host smart-be76d049-8872-4d07-88dd-7fc125cf2492
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594895988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.594895988
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.725935160
Short name T1004
Test name
Test status
Simulation time 360937501 ps
CPU time 10.9 seconds
Started May 19 12:50:23 PM PDT 24
Finished May 19 12:50:36 PM PDT 24
Peak memory 206804 kb
Host smart-91857716-5e56-4b5c-bf5a-79d9dd7a14ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725935160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.725935160
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3426453681
Short name T1019
Test name
Test status
Simulation time 75477182 ps
CPU time 1.12 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:33 PM PDT 24
Peak memory 216000 kb
Host smart-ada896c1-fa60-4325-b135-4efb39244f6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426453681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3426453681
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2831310276
Short name T1068
Test name
Test status
Simulation time 222130705 ps
CPU time 3.93 seconds
Started May 19 12:50:28 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 217640 kb
Host smart-4853c2cb-1e7a-4d5d-923a-42456f21e077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831310276 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2831310276
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1116081627
Short name T1042
Test name
Test status
Simulation time 19700731 ps
CPU time 1.17 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:31 PM PDT 24
Peak memory 206852 kb
Host smart-81c83b14-3ace-4e66-bd63-c352779a9f87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116081627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
116081627
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2360692909
Short name T965
Test name
Test status
Simulation time 51103499 ps
CPU time 0.74 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 203704 kb
Host smart-73f8b340-4092-4e20-b098-4333c6c2b8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360692909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
360692909
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2972564637
Short name T1055
Test name
Test status
Simulation time 238390495 ps
CPU time 2.14 seconds
Started May 19 12:50:25 PM PDT 24
Finished May 19 12:50:30 PM PDT 24
Peak memory 215228 kb
Host smart-3f9c060a-c6f3-48f2-a28d-ff69e9fac031
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972564637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2972564637
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.145651804
Short name T983
Test name
Test status
Simulation time 25549273 ps
CPU time 0.65 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:30 PM PDT 24
Peak memory 203288 kb
Host smart-0c596bc3-878c-4e38-bf94-184cbe449ddf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145651804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.145651804
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4049280386
Short name T1011
Test name
Test status
Simulation time 691637624 ps
CPU time 1.83 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 215032 kb
Host smart-ef87ac15-feb7-4918-a8c9-06b0da5c7a81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049280386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4049280386
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1280989797
Short name T186
Test name
Test status
Simulation time 4441489883 ps
CPU time 25.64 seconds
Started May 19 12:50:25 PM PDT 24
Finished May 19 12:50:53 PM PDT 24
Peak memory 215116 kb
Host smart-2e889e92-05da-477a-9bc2-449bfac11b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280989797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1280989797
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4345808
Short name T1029
Test name
Test status
Simulation time 29249866 ps
CPU time 0.68 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203440 kb
Host smart-37d6e439-efd4-4c3b-a155-2774b4ccf3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4345808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.4345808
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2968224646
Short name T1021
Test name
Test status
Simulation time 16109816 ps
CPU time 0.7 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 203472 kb
Host smart-e97e38ce-211c-466d-a6a7-8066770acd01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968224646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2968224646
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4017009929
Short name T1008
Test name
Test status
Simulation time 12179486 ps
CPU time 0.79 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 203820 kb
Host smart-1d829b91-49bc-43cd-a9d8-8820b2469a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017009929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4017009929
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2604645025
Short name T994
Test name
Test status
Simulation time 66825817 ps
CPU time 0.68 seconds
Started May 19 12:50:39 PM PDT 24
Finished May 19 12:50:42 PM PDT 24
Peak memory 203508 kb
Host smart-50a8f9a6-61ec-41e0-94c0-1292f92bcbc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604645025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2604645025
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.433012014
Short name T999
Test name
Test status
Simulation time 127589813 ps
CPU time 0.73 seconds
Started May 19 12:50:40 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 203492 kb
Host smart-4f82e944-71a2-425c-9091-fde5868bd34d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433012014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.433012014
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.219577351
Short name T974
Test name
Test status
Simulation time 12404155 ps
CPU time 0.71 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 204120 kb
Host smart-f94c8e83-e9a9-4bee-8856-221a8f91bd79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219577351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.219577351
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2029366171
Short name T984
Test name
Test status
Simulation time 45632934 ps
CPU time 0.69 seconds
Started May 19 12:50:42 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 203516 kb
Host smart-a3adb498-a86c-4aff-bdf2-b54b67fa09bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029366171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2029366171
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.216744780
Short name T1018
Test name
Test status
Simulation time 14953912 ps
CPU time 0.69 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:45 PM PDT 24
Peak memory 203692 kb
Host smart-1b4d6452-1ae7-40a0-ac93-b17825989224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216744780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.216744780
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3179164345
Short name T1050
Test name
Test status
Simulation time 61945059 ps
CPU time 0.72 seconds
Started May 19 12:50:44 PM PDT 24
Finished May 19 12:50:47 PM PDT 24
Peak memory 203800 kb
Host smart-386240d8-63e7-4005-b638-7ed6fdb05aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179164345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3179164345
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.35056698
Short name T1034
Test name
Test status
Simulation time 19667826 ps
CPU time 0.74 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203800 kb
Host smart-66aeabcf-21d3-4549-ae22-b6fe0f23f6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.35056698
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2017314247
Short name T1070
Test name
Test status
Simulation time 693315569 ps
CPU time 14.97 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:47 PM PDT 24
Peak memory 214948 kb
Host smart-a71e9617-b57f-478d-bb50-56f6dd42ca7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017314247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2017314247
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2558832626
Short name T1063
Test name
Test status
Simulation time 12046056950 ps
CPU time 23.75 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:53 PM PDT 24
Peak memory 206796 kb
Host smart-76cf3500-331e-4dfc-b753-ad5b87853c1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558832626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2558832626
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4085753369
Short name T78
Test name
Test status
Simulation time 134091260 ps
CPU time 1.27 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 206760 kb
Host smart-354e2a37-14cd-48b4-8338-e05aedaf9726
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085753369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4085753369
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4251670997
Short name T993
Test name
Test status
Simulation time 53557015 ps
CPU time 2.29 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:30 PM PDT 24
Peak memory 216268 kb
Host smart-11f04870-3b94-461a-b020-ea46b35a8777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251670997 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4251670997
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.254372698
Short name T1045
Test name
Test status
Simulation time 330936841 ps
CPU time 2.95 seconds
Started May 19 12:50:28 PM PDT 24
Finished May 19 12:50:33 PM PDT 24
Peak memory 206792 kb
Host smart-5b5e410d-3faf-4f06-b074-7e5bb9bfdbb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254372698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.254372698
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3885808106
Short name T1054
Test name
Test status
Simulation time 136431940 ps
CPU time 0.71 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 203416 kb
Host smart-6f231475-ce97-4acc-9b74-223d3a0d555c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885808106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
885808106
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.187714930
Short name T1056
Test name
Test status
Simulation time 329133024 ps
CPU time 1.91 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 215088 kb
Host smart-5a1c325b-ba37-4282-805b-6cb8dfaedf29
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187714930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.187714930
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2910573002
Short name T976
Test name
Test status
Simulation time 18662950 ps
CPU time 0.66 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 203292 kb
Host smart-e8f3e635-93bf-453b-ad11-554ef49e0ce9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910573002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2910573002
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3473472083
Short name T1073
Test name
Test status
Simulation time 226065730 ps
CPU time 3.04 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:36 PM PDT 24
Peak memory 215056 kb
Host smart-1e28014f-3878-48c6-9bad-ae86d2b179c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473472083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3473472083
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.971703245
Short name T103
Test name
Test status
Simulation time 261952646 ps
CPU time 2.08 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 215200 kb
Host smart-daf2212c-2896-4012-9013-8ec05a8b8af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971703245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.971703245
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3461843833
Short name T977
Test name
Test status
Simulation time 395452199 ps
CPU time 6.11 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 215264 kb
Host smart-22993c2e-b031-41d4-af56-b71297ae9d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461843833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3461843833
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4261564109
Short name T1064
Test name
Test status
Simulation time 14780786 ps
CPU time 0.79 seconds
Started May 19 12:50:47 PM PDT 24
Finished May 19 12:50:50 PM PDT 24
Peak memory 203700 kb
Host smart-02e2da16-d81e-45c1-a9c3-2a4bc5ac2b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261564109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4261564109
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.678961953
Short name T1026
Test name
Test status
Simulation time 44360020 ps
CPU time 0.73 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203392 kb
Host smart-3172bc92-0f9a-4047-8d6a-e51f29495fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678961953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.678961953
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3908503324
Short name T990
Test name
Test status
Simulation time 13239691 ps
CPU time 0.72 seconds
Started May 19 12:50:44 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 203692 kb
Host smart-eb63c819-31de-4eb6-b70a-6e2d98f35ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908503324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3908503324
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1901451409
Short name T1059
Test name
Test status
Simulation time 140210288 ps
CPU time 0.77 seconds
Started May 19 12:50:48 PM PDT 24
Finished May 19 12:50:51 PM PDT 24
Peak memory 203412 kb
Host smart-d2d4440d-65c9-4564-b340-296228ce5749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901451409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1901451409
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3028257710
Short name T961
Test name
Test status
Simulation time 187327245 ps
CPU time 0.73 seconds
Started May 19 12:50:56 PM PDT 24
Finished May 19 12:50:59 PM PDT 24
Peak memory 203384 kb
Host smart-56bcc7c6-acc5-4d56-9066-f6d4862c7791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028257710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3028257710
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.207688221
Short name T998
Test name
Test status
Simulation time 11500512 ps
CPU time 0.73 seconds
Started May 19 12:50:46 PM PDT 24
Finished May 19 12:50:50 PM PDT 24
Peak memory 203400 kb
Host smart-49cad1cd-5782-4792-a283-db31bcfa444e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207688221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.207688221
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3863394246
Short name T986
Test name
Test status
Simulation time 38304349 ps
CPU time 0.74 seconds
Started May 19 12:50:56 PM PDT 24
Finished May 19 12:51:00 PM PDT 24
Peak memory 203696 kb
Host smart-74f16f75-7fe4-4adf-aca2-575db2c3e35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863394246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3863394246
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2583766592
Short name T1013
Test name
Test status
Simulation time 13802097 ps
CPU time 0.73 seconds
Started May 19 12:50:49 PM PDT 24
Finished May 19 12:50:52 PM PDT 24
Peak memory 203388 kb
Host smart-a9c874b3-f769-499c-82ce-8fefc6e02a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583766592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2583766592
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1156591562
Short name T1035
Test name
Test status
Simulation time 41639215 ps
CPU time 0.74 seconds
Started May 19 12:50:44 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 203396 kb
Host smart-2dd639ec-e4d7-4089-b603-10af30615c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156591562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1156591562
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.176267174
Short name T1014
Test name
Test status
Simulation time 18573737 ps
CPU time 0.81 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203388 kb
Host smart-d2c5f589-19ad-44dd-884d-a78e1d72d4fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176267174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.176267174
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2707587836
Short name T1009
Test name
Test status
Simulation time 206546894 ps
CPU time 14.97 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 206700 kb
Host smart-9cb844ba-db9b-4420-a13a-56c6e8990e4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707587836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2707587836
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3800050272
Short name T1079
Test name
Test status
Simulation time 4837997421 ps
CPU time 24.42 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:51:02 PM PDT 24
Peak memory 206852 kb
Host smart-873694bb-39fa-48d9-a674-2cb20781f9ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800050272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3800050272
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3857734705
Short name T76
Test name
Test status
Simulation time 51488462 ps
CPU time 1.41 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 206748 kb
Host smart-574227f2-9408-4c0c-98bd-33abeab4dec5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857734705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3857734705
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3027717418
Short name T146
Test name
Test status
Simulation time 53990162 ps
CPU time 1.69 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 215168 kb
Host smart-4ee81a33-6034-4351-b014-c8e2ab828882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027717418 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3027717418
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.515100270
Short name T1016
Test name
Test status
Simulation time 81368577 ps
CPU time 1.37 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:38 PM PDT 24
Peak memory 215040 kb
Host smart-ff04a048-aed7-4e84-a86a-4b11605ba0c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515100270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.515100270
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2892466929
Short name T987
Test name
Test status
Simulation time 36693275 ps
CPU time 0.71 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 203436 kb
Host smart-e23919fb-35ba-4b77-8b7b-37f66fde79fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892466929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
892466929
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1325796549
Short name T1041
Test name
Test status
Simulation time 129588872 ps
CPU time 2.38 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 215220 kb
Host smart-ead4402d-58ab-4ffa-8485-dc548c175095
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325796549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1325796549
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3737871727
Short name T1077
Test name
Test status
Simulation time 20200994 ps
CPU time 0.65 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:38 PM PDT 24
Peak memory 203628 kb
Host smart-7477713e-bb93-49fb-a3ab-67d2d8b97077
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737871727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3737871727
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3004789728
Short name T1060
Test name
Test status
Simulation time 278088594 ps
CPU time 4.43 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 215076 kb
Host smart-6d9c49a6-6994-4392-a4ee-53630c1e33e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004789728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3004789728
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3178998448
Short name T1033
Test name
Test status
Simulation time 318520834 ps
CPU time 4.53 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 215140 kb
Host smart-a46af48a-480d-46ff-a29d-b4a258acd2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178998448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
178998448
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1401635238
Short name T148
Test name
Test status
Simulation time 685588749 ps
CPU time 7.84 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:36 PM PDT 24
Peak memory 215092 kb
Host smart-07973ec2-40f5-45be-b1a9-bdf471b06c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401635238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1401635238
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.794933306
Short name T972
Test name
Test status
Simulation time 134665377 ps
CPU time 0.74 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203396 kb
Host smart-c07dfdf0-bd0d-4c55-b6d8-52f2512dd9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794933306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.794933306
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3054763409
Short name T980
Test name
Test status
Simulation time 43234308 ps
CPU time 0.71 seconds
Started May 19 12:50:47 PM PDT 24
Finished May 19 12:50:51 PM PDT 24
Peak memory 203736 kb
Host smart-0ba8a05c-4279-46c6-954c-ace5a522f4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054763409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3054763409
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.994955830
Short name T1040
Test name
Test status
Simulation time 14298929 ps
CPU time 0.71 seconds
Started May 19 12:50:50 PM PDT 24
Finished May 19 12:50:54 PM PDT 24
Peak memory 203396 kb
Host smart-b812bf79-409e-4c25-82d2-f6c4edac3665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994955830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.994955830
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1222609095
Short name T1057
Test name
Test status
Simulation time 40351742 ps
CPU time 0.72 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203424 kb
Host smart-0896696d-4723-4e45-bfff-40765fcdb0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222609095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1222609095
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2723362811
Short name T1051
Test name
Test status
Simulation time 17311751 ps
CPU time 0.76 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203416 kb
Host smart-f11efa4d-7f80-48af-8919-f259f72c8ea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723362811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2723362811
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1495634856
Short name T968
Test name
Test status
Simulation time 34734967 ps
CPU time 0.71 seconds
Started May 19 12:50:45 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 203436 kb
Host smart-bb243275-528a-499f-9a1a-734c360cceed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495634856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1495634856
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2979298539
Short name T1081
Test name
Test status
Simulation time 29944848 ps
CPU time 0.79 seconds
Started May 19 12:50:43 PM PDT 24
Finished May 19 12:50:46 PM PDT 24
Peak memory 203520 kb
Host smart-ad99a7f2-bdce-4e44-b51c-ad423de9ad48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979298539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2979298539
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2854556730
Short name T1044
Test name
Test status
Simulation time 15651816 ps
CPU time 0.72 seconds
Started May 19 12:50:48 PM PDT 24
Finished May 19 12:50:51 PM PDT 24
Peak memory 203672 kb
Host smart-5502a0e2-214f-4191-9590-95feca42a4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854556730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2854556730
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2515155039
Short name T1010
Test name
Test status
Simulation time 35774068 ps
CPU time 0.73 seconds
Started May 19 12:50:48 PM PDT 24
Finished May 19 12:50:51 PM PDT 24
Peak memory 203672 kb
Host smart-f855884d-9f27-40b8-a35c-5658d71ded9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515155039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2515155039
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3127446753
Short name T985
Test name
Test status
Simulation time 14775695 ps
CPU time 0.73 seconds
Started May 19 12:50:55 PM PDT 24
Finished May 19 12:50:59 PM PDT 24
Peak memory 203392 kb
Host smart-59a2a700-d7c9-4704-97a5-9af2b74a93ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127446753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3127446753
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2896156947
Short name T1046
Test name
Test status
Simulation time 87020598 ps
CPU time 2.98 seconds
Started May 19 12:50:37 PM PDT 24
Finished May 19 12:50:43 PM PDT 24
Peak memory 217188 kb
Host smart-29afcc18-4fd5-4d94-abe2-9da1c8072f49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896156947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2896156947
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4094152075
Short name T1053
Test name
Test status
Simulation time 66863469 ps
CPU time 2.24 seconds
Started May 19 12:50:28 PM PDT 24
Finished May 19 12:50:33 PM PDT 24
Peak memory 214928 kb
Host smart-0bdb549d-112c-45fe-9e4a-837bc23ad459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094152075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
094152075
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3578357598
Short name T982
Test name
Test status
Simulation time 15876013 ps
CPU time 0.7 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 203668 kb
Host smart-ddf0e2d6-b339-4396-991f-e850005738bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578357598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
578357598
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2524654554
Short name T137
Test name
Test status
Simulation time 764392501 ps
CPU time 3.61 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:39 PM PDT 24
Peak memory 215032 kb
Host smart-7eb36e4c-1d78-4bbe-b072-bbff53421677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524654554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2524654554
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1922079228
Short name T1032
Test name
Test status
Simulation time 322873637 ps
CPU time 2.29 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:33 PM PDT 24
Peak memory 215332 kb
Host smart-bb90135a-7377-42f9-92e5-087b1e147f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922079228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
922079228
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1960791917
Short name T185
Test name
Test status
Simulation time 214076190 ps
CPU time 12.75 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 215040 kb
Host smart-be237ca6-2ac7-4254-ae55-9852173be1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960791917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1960791917
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.145401910
Short name T973
Test name
Test status
Simulation time 27962560 ps
CPU time 1.96 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:38 PM PDT 24
Peak memory 216044 kb
Host smart-c423112f-2f50-47e1-9ea6-6ddc8dfb8e96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145401910 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.145401910
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2066123735
Short name T122
Test name
Test status
Simulation time 67348720 ps
CPU time 2.11 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 214988 kb
Host smart-b7f89ac6-783c-450b-bdd5-5765c395b782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066123735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
066123735
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.258017838
Short name T1076
Test name
Test status
Simulation time 69511998 ps
CPU time 0.77 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:33 PM PDT 24
Peak memory 203500 kb
Host smart-0dcb2810-2bae-4fb5-8771-ea72e1b5e691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258017838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.258017838
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.812516105
Short name T1080
Test name
Test status
Simulation time 31584630 ps
CPU time 1.8 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:35 PM PDT 24
Peak memory 214964 kb
Host smart-708f8488-b686-4c1c-8c5d-fe9804659743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812516105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.812516105
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3889843379
Short name T1015
Test name
Test status
Simulation time 789604799 ps
CPU time 14.12 seconds
Started May 19 12:50:27 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 215132 kb
Host smart-9a513aec-c875-4fc0-bfcc-fa29f1bf65f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889843379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3889843379
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2918917839
Short name T996
Test name
Test status
Simulation time 712355996 ps
CPU time 1.79 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:35 PM PDT 24
Peak memory 214972 kb
Host smart-a47100a2-9d75-4018-8d15-a127e83bca21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918917839 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2918917839
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2988681652
Short name T121
Test name
Test status
Simulation time 70390230 ps
CPU time 2.57 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:35 PM PDT 24
Peak memory 214916 kb
Host smart-00f83563-8747-44c4-9dc9-2bcf754e7356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988681652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
988681652
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4261329937
Short name T989
Test name
Test status
Simulation time 47332851 ps
CPU time 0.74 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:35 PM PDT 24
Peak memory 203728 kb
Host smart-9198a167-a1df-4e4b-af0d-c0655f3e4380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261329937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
261329937
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4145808712
Short name T138
Test name
Test status
Simulation time 132791834 ps
CPU time 1.81 seconds
Started May 19 12:50:31 PM PDT 24
Finished May 19 12:50:36 PM PDT 24
Peak memory 214944 kb
Host smart-4ea8819c-d5a6-4509-8d55-95e46a00f7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145808712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4145808712
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.112459607
Short name T1047
Test name
Test status
Simulation time 61733441 ps
CPU time 1.75 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:34 PM PDT 24
Peak memory 215264 kb
Host smart-4fe6534d-4e46-43ca-a88d-c3d931c01012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112459607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.112459607
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.97870027
Short name T184
Test name
Test status
Simulation time 3643034981 ps
CPU time 16.07 seconds
Started May 19 12:50:36 PM PDT 24
Finished May 19 12:50:55 PM PDT 24
Peak memory 216644 kb
Host smart-2507ab88-9ebb-4b38-8ddd-7002c8516f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97870027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.97870027
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.54507893
Short name T1039
Test name
Test status
Simulation time 63187336 ps
CPU time 1.89 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:36 PM PDT 24
Peak memory 216124 kb
Host smart-bb28a177-b96f-4cd4-a1cf-3a2a2e2fd5bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54507893 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.54507893
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1765171019
Short name T113
Test name
Test status
Simulation time 40145231 ps
CPU time 1.94 seconds
Started May 19 12:50:32 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 215028 kb
Host smart-2e45c3be-2696-4249-9a8b-eec7c553d88f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765171019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
765171019
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1792689945
Short name T971
Test name
Test status
Simulation time 18457294 ps
CPU time 0.75 seconds
Started May 19 12:50:29 PM PDT 24
Finished May 19 12:50:32 PM PDT 24
Peak memory 203524 kb
Host smart-282362b7-a03b-4d0a-bb55-46fe24afd401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792689945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
792689945
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3650990728
Short name T136
Test name
Test status
Simulation time 351148919 ps
CPU time 3.98 seconds
Started May 19 12:50:37 PM PDT 24
Finished May 19 12:50:44 PM PDT 24
Peak memory 215052 kb
Host smart-35153c15-6cc7-450c-bbb0-94f543de3167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650990728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3650990728
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4255463954
Short name T181
Test name
Test status
Simulation time 162079693 ps
CPU time 4.55 seconds
Started May 19 12:50:26 PM PDT 24
Finished May 19 12:50:33 PM PDT 24
Peak memory 215288 kb
Host smart-589f1c80-8296-4efb-9c32-8fe496a5955f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255463954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
255463954
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.424112530
Short name T57
Test name
Test status
Simulation time 655531669 ps
CPU time 14.89 seconds
Started May 19 12:50:30 PM PDT 24
Finished May 19 12:50:48 PM PDT 24
Peak memory 215024 kb
Host smart-a4b973e1-7522-436c-b2bc-fbffd553ad71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424112530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.424112530
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2972937053
Short name T1002
Test name
Test status
Simulation time 474411804 ps
CPU time 3.68 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:41 PM PDT 24
Peak memory 217092 kb
Host smart-fc919fd5-315d-4e88-8298-9af4459e7fb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972937053 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2972937053
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3199036326
Short name T975
Test name
Test status
Simulation time 167002242 ps
CPU time 1.52 seconds
Started May 19 12:50:35 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 215088 kb
Host smart-80c41178-2d9a-4336-87e1-4f32a60f5a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199036326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
199036326
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2950403055
Short name T1052
Test name
Test status
Simulation time 84482817 ps
CPU time 0.77 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:37 PM PDT 24
Peak memory 203712 kb
Host smart-2153ca2f-0344-4113-96de-d9c1acbabfe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950403055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
950403055
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4245188613
Short name T1071
Test name
Test status
Simulation time 31681162 ps
CPU time 1.94 seconds
Started May 19 12:50:34 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 215024 kb
Host smart-eb2160ad-97e4-45df-bbd8-64c318628a6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245188613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4245188613
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.524724673
Short name T101
Test name
Test status
Simulation time 42651609 ps
CPU time 2.91 seconds
Started May 19 12:50:33 PM PDT 24
Finished May 19 12:50:40 PM PDT 24
Peak memory 215176 kb
Host smart-c23dc80f-1265-4602-a691-55b733a1b45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524724673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.524724673
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.751752351
Short name T677
Test name
Test status
Simulation time 14161326 ps
CPU time 0.76 seconds
Started May 19 12:51:09 PM PDT 24
Finished May 19 12:51:11 PM PDT 24
Peak memory 204720 kb
Host smart-10cac8a7-b2d4-408d-acca-cf80de414195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751752351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.751752351
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1441208003
Short name T256
Test name
Test status
Simulation time 624722810 ps
CPU time 2.99 seconds
Started May 19 12:51:12 PM PDT 24
Finished May 19 12:51:18 PM PDT 24
Peak memory 234640 kb
Host smart-6ed9986c-36cd-4f29-97d1-47052d6c2e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441208003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1441208003
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.675635093
Short name T823
Test name
Test status
Simulation time 57283933 ps
CPU time 0.81 seconds
Started May 19 12:51:12 PM PDT 24
Finished May 19 12:51:15 PM PDT 24
Peak memory 206312 kb
Host smart-000c87a7-98f0-40a2-a8b1-169c09a185e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675635093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.675635093
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3618066791
Short name T70
Test name
Test status
Simulation time 13103776 ps
CPU time 0.76 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:15 PM PDT 24
Peak memory 215780 kb
Host smart-7939d956-729f-4f11-8a65-d431525f213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618066791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3618066791
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.736579214
Short name T274
Test name
Test status
Simulation time 43903973469 ps
CPU time 24.21 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 224332 kb
Host smart-c091673a-a338-4afe-9075-16f9a70cd46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736579214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.736579214
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1032639186
Short name T206
Test name
Test status
Simulation time 158055856 ps
CPU time 2.63 seconds
Started May 19 12:51:10 PM PDT 24
Finished May 19 12:51:14 PM PDT 24
Peak memory 224088 kb
Host smart-cc9aebc6-58e9-4f4a-9cb6-e9e0f5834c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032639186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1032639186
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2121706163
Short name T251
Test name
Test status
Simulation time 2000433178 ps
CPU time 13.21 seconds
Started May 19 12:51:10 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 229664 kb
Host smart-afaed02c-b8e8-404e-a250-96b178175db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121706163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2121706163
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4087720175
Short name T532
Test name
Test status
Simulation time 19356767798 ps
CPU time 17 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 232404 kb
Host smart-e5146e4d-1ef2-4930-9f57-d723b92f8f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087720175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4087720175
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3848198708
Short name T284
Test name
Test status
Simulation time 10072421332 ps
CPU time 22.47 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 228064 kb
Host smart-b7a1830d-e675-4fa3-ac1e-cb26e661e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848198708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3848198708
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1055362692
Short name T547
Test name
Test status
Simulation time 895592478 ps
CPU time 4.35 seconds
Started May 19 12:51:13 PM PDT 24
Finished May 19 12:51:20 PM PDT 24
Peak memory 220144 kb
Host smart-05527d0f-138b-42d1-b669-5ee1942e18b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1055362692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1055362692
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2551756032
Short name T48
Test name
Test status
Simulation time 2141247439 ps
CPU time 38.01 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:55 PM PDT 24
Peak memory 251536 kb
Host smart-c92aa72d-1855-4ecd-b904-30261155e514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551756032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2551756032
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3445550397
Short name T66
Test name
Test status
Simulation time 30866235135 ps
CPU time 45.28 seconds
Started May 19 12:51:13 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 216060 kb
Host smart-6f4416ca-4fa4-4867-a1f7-3d139358b5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445550397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3445550397
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2623125182
Short name T712
Test name
Test status
Simulation time 4918268331 ps
CPU time 8.14 seconds
Started May 19 12:51:12 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 216068 kb
Host smart-69a02ed4-cefa-4edc-ba0c-62aaac1c9beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623125182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2623125182
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1789097666
Short name T425
Test name
Test status
Simulation time 195107292 ps
CPU time 2.67 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:20 PM PDT 24
Peak memory 216032 kb
Host smart-1387085c-7ec6-49d1-9533-2bf3c8b6a5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789097666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1789097666
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2173681355
Short name T846
Test name
Test status
Simulation time 401970952 ps
CPU time 1.01 seconds
Started May 19 12:51:08 PM PDT 24
Finished May 19 12:51:10 PM PDT 24
Peak memory 206596 kb
Host smart-e7f8da13-2b69-42d1-855e-a0bbea88a1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173681355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2173681355
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1520585826
Short name T612
Test name
Test status
Simulation time 1894442812 ps
CPU time 2.89 seconds
Started May 19 12:51:12 PM PDT 24
Finished May 19 12:51:17 PM PDT 24
Peak memory 224256 kb
Host smart-851c15a3-3f5c-4167-bce5-b3f3004684ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520585826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1520585826
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2567355933
Short name T788
Test name
Test status
Simulation time 14727901 ps
CPU time 0.77 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:14 PM PDT 24
Peak memory 205616 kb
Host smart-69cbabc4-07b1-4b25-a78e-a9c1011a6376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567355933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
567355933
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2284711634
Short name T937
Test name
Test status
Simulation time 186324014 ps
CPU time 4.7 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:32 PM PDT 24
Peak memory 233964 kb
Host smart-788927f9-b2e9-4d22-82b9-540778969b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284711634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2284711634
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.436822635
Short name T959
Test name
Test status
Simulation time 12433948 ps
CPU time 0.81 seconds
Started May 19 12:51:12 PM PDT 24
Finished May 19 12:51:15 PM PDT 24
Peak memory 205948 kb
Host smart-858517b5-ca73-43da-a481-1ca39e905bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436822635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.436822635
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.197344815
Short name T176
Test name
Test status
Simulation time 21874621525 ps
CPU time 170.89 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:54:09 PM PDT 24
Peak memory 248452 kb
Host smart-22585ddc-fafe-4390-a091-059bc8ee5612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197344815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.197344815
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3901467852
Short name T518
Test name
Test status
Simulation time 16954944182 ps
CPU time 163.36 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:54:02 PM PDT 24
Peak memory 249640 kb
Host smart-ee0d0139-c8ae-4d03-96a9-32fb5c0a5dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901467852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3901467852
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.949705787
Short name T258
Test name
Test status
Simulation time 342240900 ps
CPU time 3.89 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:16 PM PDT 24
Peak memory 233144 kb
Host smart-f1812912-cfae-4518-bb50-2a02d2eccf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949705787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.949705787
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2628970071
Short name T87
Test name
Test status
Simulation time 21698304955 ps
CPU time 39.26 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:52 PM PDT 24
Peak memory 226420 kb
Host smart-314193e5-631b-4acf-88fb-b8019d67949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628970071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2628970071
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.383364274
Short name T551
Test name
Test status
Simulation time 210736897 ps
CPU time 2.33 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:21 PM PDT 24
Peak memory 215900 kb
Host smart-378e8089-a1a7-42b0-acae-b5c0f5d29dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383364274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
383364274
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4201385826
Short name T546
Test name
Test status
Simulation time 10902272122 ps
CPU time 10.46 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:33 PM PDT 24
Peak memory 232856 kb
Host smart-09adc0c8-de14-44a8-867b-81a2c5fd200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201385826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4201385826
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1157446269
Short name T635
Test name
Test status
Simulation time 726866683 ps
CPU time 8.45 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:27 PM PDT 24
Peak memory 218316 kb
Host smart-f20ccaed-1570-479c-8953-0f07d4d88789
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1157446269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1157446269
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4047805143
Short name T64
Test name
Test status
Simulation time 73670462 ps
CPU time 0.96 seconds
Started May 19 12:51:13 PM PDT 24
Finished May 19 12:51:16 PM PDT 24
Peak memory 234448 kb
Host smart-a206f098-5b32-4347-a579-179863b8320d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047805143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4047805143
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.69574848
Short name T217
Test name
Test status
Simulation time 20982485536 ps
CPU time 183.4 seconds
Started May 19 12:51:13 PM PDT 24
Finished May 19 12:54:19 PM PDT 24
Peak memory 249928 kb
Host smart-47785754-c25e-4514-a396-d93b8b422f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69574848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_
all.69574848
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1192345902
Short name T368
Test name
Test status
Simulation time 14925950 ps
CPU time 0.78 seconds
Started May 19 12:51:13 PM PDT 24
Finished May 19 12:51:17 PM PDT 24
Peak memory 205744 kb
Host smart-25f50f08-b390-4af8-b691-8807517f4067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192345902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1192345902
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.568533709
Short name T614
Test name
Test status
Simulation time 604892048 ps
CPU time 4.07 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:21 PM PDT 24
Peak memory 215904 kb
Host smart-7edb4916-5928-44be-9fbd-a5f67c4ed1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568533709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.568533709
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2115818943
Short name T690
Test name
Test status
Simulation time 38541476 ps
CPU time 2.04 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:20 PM PDT 24
Peak memory 216132 kb
Host smart-0c10552c-1387-445f-828c-dab0f1d1a7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115818943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2115818943
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3892337274
Short name T433
Test name
Test status
Simulation time 97291492 ps
CPU time 0.75 seconds
Started May 19 12:51:10 PM PDT 24
Finished May 19 12:51:13 PM PDT 24
Peak memory 205500 kb
Host smart-12fd7b1e-a2a2-484e-8651-c5aa7eda857c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892337274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3892337274
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2462647672
Short name T470
Test name
Test status
Simulation time 1970089062 ps
CPU time 3.47 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:20 PM PDT 24
Peak memory 232488 kb
Host smart-dfff5cd3-6a97-43dc-ae3c-ce6d8b084317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462647672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2462647672
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1721994968
Short name T870
Test name
Test status
Simulation time 58613041 ps
CPU time 0.72 seconds
Started May 19 12:51:36 PM PDT 24
Finished May 19 12:51:38 PM PDT 24
Peak memory 204680 kb
Host smart-af3cf3cd-5548-4182-8e22-781b873f4935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721994968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1721994968
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3324307215
Short name T941
Test name
Test status
Simulation time 144371160 ps
CPU time 2.34 seconds
Started May 19 12:51:32 PM PDT 24
Finished May 19 12:51:36 PM PDT 24
Peak memory 221232 kb
Host smart-f812c3a9-6768-476f-95fe-67595a95395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324307215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3324307215
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2782375772
Short name T414
Test name
Test status
Simulation time 21476975 ps
CPU time 0.82 seconds
Started May 19 12:51:26 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 206440 kb
Host smart-a0f21643-74cc-4a3b-a083-cb10e5d03bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782375772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2782375772
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4165654831
Short name T244
Test name
Test status
Simulation time 6413164773 ps
CPU time 27.17 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 235496 kb
Host smart-b3f64cfd-bacf-4e9a-9ae6-ad7701ae3c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165654831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4165654831
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.274420265
Short name T207
Test name
Test status
Simulation time 133912763859 ps
CPU time 343.74 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:57:19 PM PDT 24
Peak memory 252736 kb
Host smart-9cb5b3ab-f33a-476c-9a71-55d177c671c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274420265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.274420265
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2917646500
Short name T46
Test name
Test status
Simulation time 19692586937 ps
CPU time 121.42 seconds
Started May 19 12:51:48 PM PDT 24
Finished May 19 12:53:51 PM PDT 24
Peak memory 240696 kb
Host smart-b101e653-d68e-4b63-a4fa-ef542de37ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917646500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2917646500
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2630165568
Short name T838
Test name
Test status
Simulation time 238486404 ps
CPU time 7.67 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:51:46 PM PDT 24
Peak memory 248832 kb
Host smart-28e25b8f-e221-4631-9842-0de8350f908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630165568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2630165568
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.800987913
Short name T411
Test name
Test status
Simulation time 394455989 ps
CPU time 2.21 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:51:34 PM PDT 24
Peak memory 215900 kb
Host smart-7ed78599-4706-437c-924e-c36243b0dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800987913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.800987913
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3168181236
Short name T946
Test name
Test status
Simulation time 16044989167 ps
CPU time 72.79 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:53:03 PM PDT 24
Peak memory 221616 kb
Host smart-6edc320e-7bd2-4eda-b1b5-e8a2677a2e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168181236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3168181236
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2440053602
Short name T857
Test name
Test status
Simulation time 614345642 ps
CPU time 2.48 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 232496 kb
Host smart-3fa3d357-4a38-4469-ba1a-882271e150cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440053602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2440053602
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2627474192
Short name T744
Test name
Test status
Simulation time 240621223 ps
CPU time 3.66 seconds
Started May 19 12:51:35 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 233216 kb
Host smart-0aa79f1d-c66d-49ea-87f6-aab8733714e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627474192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2627474192
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1257730835
Short name T501
Test name
Test status
Simulation time 2541286325 ps
CPU time 9.09 seconds
Started May 19 12:51:35 PM PDT 24
Finished May 19 12:51:46 PM PDT 24
Peak memory 218916 kb
Host smart-7da4821a-d932-48c6-80ff-2ca3a0491b19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1257730835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1257730835
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2895506815
Short name T728
Test name
Test status
Simulation time 29008692963 ps
CPU time 162.88 seconds
Started May 19 12:51:36 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 254048 kb
Host smart-7b4b94d9-5641-4a9a-a5c1-795e385c85cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895506815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2895506815
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1610605825
Short name T487
Test name
Test status
Simulation time 1028845656 ps
CPU time 10.93 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:51:46 PM PDT 24
Peak memory 215980 kb
Host smart-4ec7d8d0-fc72-4586-b14b-4c1f11dfcccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610605825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1610605825
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.959214738
Short name T406
Test name
Test status
Simulation time 9525036188 ps
CPU time 29.02 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:52:09 PM PDT 24
Peak memory 215988 kb
Host smart-d637c06e-b196-4fc8-8de7-8d54661cb219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959214738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.959214738
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2125838473
Short name T669
Test name
Test status
Simulation time 23604273 ps
CPU time 1.35 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 216112 kb
Host smart-539da8a5-eac1-4cea-ba99-7a774b7d110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125838473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2125838473
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.560451112
Short name T860
Test name
Test status
Simulation time 233935447 ps
CPU time 0.87 seconds
Started May 19 12:51:30 PM PDT 24
Finished May 19 12:51:34 PM PDT 24
Peak memory 205464 kb
Host smart-208187c5-c800-4e6b-8ee6-3db683653880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560451112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.560451112
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3952308376
Short name T957
Test name
Test status
Simulation time 31233127534 ps
CPU time 14.93 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:51:55 PM PDT 24
Peak memory 249524 kb
Host smart-6b3209cb-e1ac-477a-a71b-9272cd7adef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952308376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3952308376
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3249705340
Short name T508
Test name
Test status
Simulation time 19943111 ps
CPU time 0.7 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 205552 kb
Host smart-5653fecd-4296-49ee-b63c-29f8f71fbf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249705340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3249705340
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2370374000
Short name T679
Test name
Test status
Simulation time 63264482 ps
CPU time 2.9 seconds
Started May 19 12:51:50 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 234192 kb
Host smart-4402189b-ec70-4b7b-a10b-05af857ce140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370374000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2370374000
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3817003818
Short name T389
Test name
Test status
Simulation time 17043678 ps
CPU time 0.76 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 206408 kb
Host smart-dfe0fc77-ee30-48c5-91e1-9b0690575447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817003818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3817003818
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2322090068
Short name T617
Test name
Test status
Simulation time 10656918671 ps
CPU time 55.98 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 250172 kb
Host smart-d09c0b5a-c4cc-4a1a-9e77-1764c0a1b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322090068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2322090068
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3573844817
Short name T160
Test name
Test status
Simulation time 8645118452 ps
CPU time 40.4 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 240872 kb
Host smart-cd0ec341-b992-46b5-b793-77f7d27f0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573844817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3573844817
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.697961610
Short name T884
Test name
Test status
Simulation time 558591283 ps
CPU time 7.32 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:04 PM PDT 24
Peak memory 232448 kb
Host smart-bb23ee1d-48f6-457a-b81c-4c624a776e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697961610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.697961610
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2066867659
Short name T880
Test name
Test status
Simulation time 4447309984 ps
CPU time 12.42 seconds
Started May 19 12:51:41 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 231888 kb
Host smart-23e67dfe-937b-4a02-9f71-04ab80401f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066867659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2066867659
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2197220393
Short name T674
Test name
Test status
Simulation time 106466362 ps
CPU time 3.13 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:51:51 PM PDT 24
Peak memory 236028 kb
Host smart-8ca31495-1c96-4cb4-8679-c62d50be74b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197220393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2197220393
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3882956861
Short name T562
Test name
Test status
Simulation time 1314268441 ps
CPU time 7.41 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:51:44 PM PDT 24
Peak memory 240076 kb
Host smart-e798ab93-56e6-45cb-acfa-effe6f5d1599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882956861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3882956861
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1521572221
Short name T732
Test name
Test status
Simulation time 708995169 ps
CPU time 5.41 seconds
Started May 19 12:51:43 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 218988 kb
Host smart-e8e675b8-e60e-4e57-949d-5e4cfe0cc91c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521572221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1521572221
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.379292891
Short name T716
Test name
Test status
Simulation time 1774724063 ps
CPU time 27.14 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:57 PM PDT 24
Peak memory 219016 kb
Host smart-82d19519-46c4-4fc9-b19c-f0934bbd5ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379292891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.379292891
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1118547494
Short name T725
Test name
Test status
Simulation time 30718460 ps
CPU time 0.76 seconds
Started May 19 12:51:45 PM PDT 24
Finished May 19 12:51:46 PM PDT 24
Peak memory 205380 kb
Host smart-93a6737f-cb54-4ee2-b581-b871a21bb8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118547494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1118547494
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1183837199
Short name T127
Test name
Test status
Simulation time 129996801 ps
CPU time 1.08 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 206720 kb
Host smart-d6a12daf-37be-430b-a25a-1b2bd1ef216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183837199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1183837199
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.920537928
Short name T7
Test name
Test status
Simulation time 60793739 ps
CPU time 0.76 seconds
Started May 19 12:51:31 PM PDT 24
Finished May 19 12:51:34 PM PDT 24
Peak memory 205640 kb
Host smart-b12e29e7-2871-4abb-8dc7-b5561a71ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920537928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.920537928
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4020618106
Short name T171
Test name
Test status
Simulation time 472757730 ps
CPU time 3.31 seconds
Started May 19 12:51:35 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 233644 kb
Host smart-f6875c9c-687e-41da-bc2a-0b8d2a627965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020618106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4020618106
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1062151458
Short name T246
Test name
Test status
Simulation time 116249219 ps
CPU time 3.42 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 233216 kb
Host smart-fa129400-7732-4634-8c0d-91146a8290ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062151458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1062151458
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1947568171
Short name T710
Test name
Test status
Simulation time 89472920 ps
CPU time 0.81 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 206992 kb
Host smart-794a0f03-fede-4138-9e3d-4c70e0112c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947568171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1947568171
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3279168096
Short name T864
Test name
Test status
Simulation time 55061135301 ps
CPU time 126.96 seconds
Started May 19 12:51:48 PM PDT 24
Finished May 19 12:53:56 PM PDT 24
Peak memory 248988 kb
Host smart-e00ed465-9af9-45de-a26c-b06e05665639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279168096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3279168096
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1518075386
Short name T746
Test name
Test status
Simulation time 10638865649 ps
CPU time 31.75 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 218300 kb
Host smart-d605b695-bfa8-4f9b-a52a-25ca03fd51e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518075386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1518075386
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1790928626
Short name T49
Test name
Test status
Simulation time 40035220500 ps
CPU time 87.42 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 250988 kb
Host smart-d3e28643-9d4b-4114-af9a-d1a69b4ab4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790928626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1790928626
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2231672000
Short name T565
Test name
Test status
Simulation time 650762936 ps
CPU time 5.99 seconds
Started May 19 12:51:43 PM PDT 24
Finished May 19 12:51:50 PM PDT 24
Peak memory 248848 kb
Host smart-83fac336-1ee0-4002-80f0-e41fb466a147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231672000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2231672000
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.769386635
Short name T262
Test name
Test status
Simulation time 247682106 ps
CPU time 5.12 seconds
Started May 19 12:51:41 PM PDT 24
Finished May 19 12:51:48 PM PDT 24
Peak memory 233264 kb
Host smart-80fe5cb1-a67b-4ca8-b915-e9ad84753c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769386635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.769386635
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.635404698
Short name T311
Test name
Test status
Simulation time 1809010543 ps
CPU time 7.05 seconds
Started May 19 12:51:40 PM PDT 24
Finished May 19 12:51:48 PM PDT 24
Peak memory 234212 kb
Host smart-eaef6473-e60f-4878-bb91-2f57617a47f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635404698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.635404698
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2944884359
Short name T845
Test name
Test status
Simulation time 1431663180 ps
CPU time 4.66 seconds
Started May 19 12:51:45 PM PDT 24
Finished May 19 12:51:51 PM PDT 24
Peak memory 224332 kb
Host smart-7986c162-50bc-4093-8ff4-f876b80c9579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944884359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2944884359
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2271039237
Short name T354
Test name
Test status
Simulation time 1044492443 ps
CPU time 9.68 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:12 PM PDT 24
Peak memory 218960 kb
Host smart-6e406b58-34e5-4abc-9a77-a68518cc5c8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271039237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2271039237
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.183707220
Short name T859
Test name
Test status
Simulation time 54246874 ps
CPU time 1.01 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:52:00 PM PDT 24
Peak memory 206784 kb
Host smart-cdf29e7b-07b3-4555-83ad-0671777b90f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183707220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.183707220
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.799459845
Short name T333
Test name
Test status
Simulation time 3164287452 ps
CPU time 25.5 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 216280 kb
Host smart-67b7fb42-298b-4836-b253-dad897fb8b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799459845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.799459845
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.897019329
Short name T882
Test name
Test status
Simulation time 6921886107 ps
CPU time 18.12 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:51:57 PM PDT 24
Peak memory 216008 kb
Host smart-32e5fab4-f3f4-4d4a-853b-31aaed84f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897019329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.897019329
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.753290052
Short name T781
Test name
Test status
Simulation time 553675625 ps
CPU time 5.71 seconds
Started May 19 12:51:45 PM PDT 24
Finished May 19 12:51:52 PM PDT 24
Peak memory 215992 kb
Host smart-b39dfe5d-79d8-4820-a01a-90213f36d9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753290052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.753290052
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.625517503
Short name T388
Test name
Test status
Simulation time 128792229 ps
CPU time 0.82 seconds
Started May 19 12:51:44 PM PDT 24
Finished May 19 12:51:46 PM PDT 24
Peak memory 205540 kb
Host smart-0a30a60d-16a7-4a91-b9bb-e5b10b0bf8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625517503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.625517503
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1895226696
Short name T395
Test name
Test status
Simulation time 6291520606 ps
CPU time 15.18 seconds
Started May 19 12:51:44 PM PDT 24
Finished May 19 12:52:00 PM PDT 24
Peak memory 220768 kb
Host smart-c59e88a1-9235-48d4-b9dd-e1556123d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895226696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1895226696
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1033372895
Short name T353
Test name
Test status
Simulation time 28088669 ps
CPU time 0.77 seconds
Started May 19 12:51:40 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 205208 kb
Host smart-14acee36-a690-4bc6-8e9f-cb4810641c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033372895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1033372895
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1722050038
Short name T475
Test name
Test status
Simulation time 60713421 ps
CPU time 2.54 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:51:57 PM PDT 24
Peak memory 221308 kb
Host smart-60cffd7b-2634-415c-9c86-d96f62b74384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722050038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1722050038
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2290533959
Short name T615
Test name
Test status
Simulation time 193742206 ps
CPU time 0.75 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 206660 kb
Host smart-8c69860f-d36b-4701-9d9b-1d4fe9493e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290533959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2290533959
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1331135093
Short name T659
Test name
Test status
Simulation time 12544954322 ps
CPU time 125.06 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 252220 kb
Host smart-c4ba8f69-7735-437d-bac3-48e1fcb4e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331135093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1331135093
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2679148004
Short name T275
Test name
Test status
Simulation time 10376735970 ps
CPU time 48.45 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 233524 kb
Host smart-e6ce2541-1f86-47b5-9bfe-658ad9428527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679148004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2679148004
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1858238357
Short name T378
Test name
Test status
Simulation time 554377212 ps
CPU time 12.76 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:52:06 PM PDT 24
Peak memory 232496 kb
Host smart-8733db9c-3318-479b-a546-483aa8af49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858238357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1858238357
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3630253087
Short name T404
Test name
Test status
Simulation time 1773236374 ps
CPU time 14.67 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:52:03 PM PDT 24
Peak memory 235072 kb
Host smart-dbfbf421-2b63-4dd9-9b02-07cdd6336a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630253087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3630253087
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2251118186
Short name T646
Test name
Test status
Simulation time 109618768786 ps
CPU time 92.17 seconds
Started May 19 12:51:42 PM PDT 24
Finished May 19 12:53:16 PM PDT 24
Peak memory 239888 kb
Host smart-fc52b314-c37b-4744-ade0-0080a28a9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251118186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2251118186
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3071397191
Short name T409
Test name
Test status
Simulation time 154793393 ps
CPU time 2.26 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:51:41 PM PDT 24
Peak memory 221340 kb
Host smart-f36cd832-5bfd-48bb-8f7c-cf422a228d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071397191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3071397191
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3265405468
Short name T647
Test name
Test status
Simulation time 767411880 ps
CPU time 7.44 seconds
Started May 19 12:51:41 PM PDT 24
Finished May 19 12:51:50 PM PDT 24
Peak memory 219676 kb
Host smart-27663a24-ec5f-47a7-8759-aad67e3d9581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265405468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3265405468
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1810686872
Short name T745
Test name
Test status
Simulation time 1271886994 ps
CPU time 15.94 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:52:05 PM PDT 24
Peak memory 222088 kb
Host smart-db097856-7a4c-458e-a96e-b8d540242a40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1810686872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1810686872
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1683588604
Short name T711
Test name
Test status
Simulation time 2346570730 ps
CPU time 25.13 seconds
Started May 19 12:51:40 PM PDT 24
Finished May 19 12:52:07 PM PDT 24
Peak memory 216216 kb
Host smart-c543f784-f352-446b-994b-3bdc7be4b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683588604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1683588604
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2992201154
Short name T671
Test name
Test status
Simulation time 730047646 ps
CPU time 2.54 seconds
Started May 19 12:51:39 PM PDT 24
Finished May 19 12:51:43 PM PDT 24
Peak memory 207656 kb
Host smart-903a74e4-80c8-434e-b541-5e5b83ef7327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992201154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2992201154
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.94655777
Short name T938
Test name
Test status
Simulation time 60739741 ps
CPU time 1.31 seconds
Started May 19 12:51:42 PM PDT 24
Finished May 19 12:51:44 PM PDT 24
Peak memory 208072 kb
Host smart-742fb996-db51-48af-b8ab-fc01bcd0291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94655777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.94655777
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2375198505
Short name T664
Test name
Test status
Simulation time 99766337 ps
CPU time 1.08 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 206552 kb
Host smart-5f2e09d7-7a8d-447c-9113-a7930392da6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375198505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2375198505
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2096634612
Short name T336
Test name
Test status
Simulation time 44905562 ps
CPU time 2.5 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:51:50 PM PDT 24
Peak memory 212708 kb
Host smart-e1f851c2-ac2f-4335-bf1c-2fbabea941d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096634612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2096634612
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.666185762
Short name T650
Test name
Test status
Simulation time 12184734 ps
CPU time 0.71 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:51:55 PM PDT 24
Peak memory 204552 kb
Host smart-0c5dc993-279e-423e-b961-f767349451ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666185762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.666185762
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1776998998
Short name T722
Test name
Test status
Simulation time 227962024 ps
CPU time 5.31 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:06 PM PDT 24
Peak memory 218408 kb
Host smart-e860a3d1-657e-4333-ae8a-e26f182e52ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776998998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1776998998
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.374734162
Short name T576
Test name
Test status
Simulation time 50291655 ps
CPU time 0.76 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:51:48 PM PDT 24
Peak memory 206356 kb
Host smart-6e9d3772-4023-42f8-9e83-881e1e729e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374734162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.374734162
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3722914521
Short name T871
Test name
Test status
Simulation time 38458496 ps
CPU time 0.86 seconds
Started May 19 12:51:45 PM PDT 24
Finished May 19 12:51:48 PM PDT 24
Peak memory 215960 kb
Host smart-33ef4c68-6aee-4d14-a4ce-386f7e84951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722914521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3722914521
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4133948088
Short name T227
Test name
Test status
Simulation time 4658198938 ps
CPU time 99.41 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:53:41 PM PDT 24
Peak memory 254464 kb
Host smart-3c925a9c-04c8-41dd-88bf-9dd461d6d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133948088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4133948088
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2296301733
Short name T752
Test name
Test status
Simulation time 54958346700 ps
CPU time 279.49 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:56:50 PM PDT 24
Peak memory 248904 kb
Host smart-2728d75d-5843-4f98-b7ba-395054357a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296301733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2296301733
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3365787917
Short name T222
Test name
Test status
Simulation time 1228421928 ps
CPU time 9.97 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:07 PM PDT 24
Peak memory 219172 kb
Host smart-9fec627e-9cce-4753-a6a1-4b63f9cbd4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365787917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3365787917
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1973234467
Short name T410
Test name
Test status
Simulation time 2281945023 ps
CPU time 26.84 seconds
Started May 19 12:52:00 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 237196 kb
Host smart-0325b066-c707-45ed-9a64-285371059956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973234467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1973234467
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2964980005
Short name T529
Test name
Test status
Simulation time 21096791220 ps
CPU time 7.35 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:51:47 PM PDT 24
Peak memory 233728 kb
Host smart-f1f21a6f-5b12-4c4e-a62f-6185e689c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964980005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2964980005
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.383666936
Short name T817
Test name
Test status
Simulation time 1124202556 ps
CPU time 5.5 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 233000 kb
Host smart-79f9916b-27a9-4e98-acfd-aeeea6afe754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383666936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.383666936
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.588497591
Short name T736
Test name
Test status
Simulation time 1270404601 ps
CPU time 7.22 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:51:57 PM PDT 24
Peak memory 222416 kb
Host smart-2a95d6c5-6a1a-450f-8246-d2c0d90d417d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=588497591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.588497591
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2795128241
Short name T457
Test name
Test status
Simulation time 64766606672 ps
CPU time 683.59 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 01:03:14 PM PDT 24
Peak memory 272236 kb
Host smart-987c98dc-8c19-4cc7-8ad4-69e86181fc53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795128241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2795128241
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.571848926
Short name T610
Test name
Test status
Simulation time 10134392100 ps
CPU time 50.76 seconds
Started May 19 12:51:40 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 216196 kb
Host smart-17f18ef5-e5da-47b7-b937-bd928786507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571848926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.571848926
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1283386925
Short name T901
Test name
Test status
Simulation time 16471856860 ps
CPU time 24.02 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:52:13 PM PDT 24
Peak memory 216104 kb
Host smart-635de23a-b63a-4242-bfe9-9eaead3a8410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283386925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1283386925
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2951054533
Short name T509
Test name
Test status
Simulation time 33529082 ps
CPU time 1.03 seconds
Started May 19 12:51:48 PM PDT 24
Finished May 19 12:51:51 PM PDT 24
Peak memory 207756 kb
Host smart-48597afb-80b1-4ab2-9b9e-68a77e48196c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951054533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2951054533
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3085436150
Short name T538
Test name
Test status
Simulation time 83436167 ps
CPU time 1.01 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:51:51 PM PDT 24
Peak memory 205956 kb
Host smart-73fafdca-88f1-44e1-8cff-5b105921bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085436150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3085436150
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.907387075
Short name T727
Test name
Test status
Simulation time 900194495 ps
CPU time 8.18 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 233932 kb
Host smart-14ad5828-3f68-457b-a44c-5278eeb8db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907387075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.907387075
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.936346403
Short name T460
Test name
Test status
Simulation time 13442530 ps
CPU time 0.74 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:51:56 PM PDT 24
Peak memory 204552 kb
Host smart-65bc83b3-fac2-4b2e-8e0f-fc5e528d4fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936346403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.936346403
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1367457558
Short name T678
Test name
Test status
Simulation time 72621708 ps
CPU time 2.92 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:00 PM PDT 24
Peak memory 233504 kb
Host smart-98e9b724-0543-4c8f-890a-a87b8fb3864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367457558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1367457558
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3655044053
Short name T755
Test name
Test status
Simulation time 18567067 ps
CPU time 0.8 seconds
Started May 19 12:51:45 PM PDT 24
Finished May 19 12:51:46 PM PDT 24
Peak memory 206336 kb
Host smart-0e66d47d-fbbf-4980-a9fc-de40c4432876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655044053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3655044053
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2440497946
Short name T81
Test name
Test status
Simulation time 87308311851 ps
CPU time 145.84 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:54:23 PM PDT 24
Peak memory 238196 kb
Host smart-358ce1eb-6b60-4bc0-a244-41044f6b9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440497946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2440497946
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.652249906
Short name T132
Test name
Test status
Simulation time 332285356155 ps
CPU time 377.02 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:58:28 PM PDT 24
Peak memory 256324 kb
Host smart-dc40423e-d1fe-46e8-aca7-de815f2ff9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652249906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.652249906
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.228599229
Short name T323
Test name
Test status
Simulation time 1646331143 ps
CPU time 11.33 seconds
Started May 19 12:51:43 PM PDT 24
Finished May 19 12:51:55 PM PDT 24
Peak memory 224236 kb
Host smart-c6820ce3-dcc5-4b2a-885a-04b3524472b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228599229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.228599229
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.961148745
Short name T842
Test name
Test status
Simulation time 1339354317 ps
CPU time 5.63 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:02 PM PDT 24
Peak memory 234440 kb
Host smart-c802e2ec-cb18-4611-84f9-5889ae3a4459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961148745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.961148745
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.962541591
Short name T210
Test name
Test status
Simulation time 12689704197 ps
CPU time 83.57 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:53:22 PM PDT 24
Peak memory 236484 kb
Host smart-fb0e3536-ef1f-486d-ae58-592136903fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962541591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.962541591
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2025174951
Short name T706
Test name
Test status
Simulation time 10849106392 ps
CPU time 33.67 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 248900 kb
Host smart-7116e765-926c-4ba7-924c-527d64a14307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025174951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2025174951
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.533903827
Short name T922
Test name
Test status
Simulation time 1095509780 ps
CPU time 6.85 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:10 PM PDT 24
Peak memory 233460 kb
Host smart-da9acf47-4a14-4490-b285-0d080f8782fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533903827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.533903827
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2171193611
Short name T720
Test name
Test status
Simulation time 318669139 ps
CPU time 3.88 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 219580 kb
Host smart-b2a3a6fd-f1fd-48b0-885f-430fa805d0f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2171193611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2171193611
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2401314616
Short name T151
Test name
Test status
Simulation time 10463067555 ps
CPU time 93.96 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 254516 kb
Host smart-46c3a39a-0b48-4990-9114-bfa81d221ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401314616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2401314616
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1976327247
Short name T82
Test name
Test status
Simulation time 5563615618 ps
CPU time 12.29 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:10 PM PDT 24
Peak memory 216172 kb
Host smart-eef9ad76-a419-4315-ac77-9bdd724bd53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976327247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1976327247
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2994191118
Short name T915
Test name
Test status
Simulation time 189168784 ps
CPU time 2.83 seconds
Started May 19 12:52:00 PM PDT 24
Finished May 19 12:52:08 PM PDT 24
Peak memory 216220 kb
Host smart-a25b416c-c4f7-4826-b78e-b829ee628b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994191118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2994191118
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2561801112
Short name T928
Test name
Test status
Simulation time 91512916 ps
CPU time 0.96 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:10 PM PDT 24
Peak memory 205572 kb
Host smart-9747fddc-e0ff-4e74-aee2-34b032c4df9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561801112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2561801112
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4270751643
Short name T853
Test name
Test status
Simulation time 41676039 ps
CPU time 2.5 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:04 PM PDT 24
Peak memory 224248 kb
Host smart-8c0aecfa-4cf9-4f04-ad32-d9d9177c17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270751643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4270751643
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4059455291
Short name T51
Test name
Test status
Simulation time 23243448 ps
CPU time 0.76 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 204684 kb
Host smart-9309814b-22e2-4bb5-8a40-8510672875ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059455291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4059455291
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3313504117
Short name T739
Test name
Test status
Simulation time 299860523 ps
CPU time 3.35 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:51:56 PM PDT 24
Peak memory 235824 kb
Host smart-82f37c5c-39bc-4b97-8ca8-5bf1889a2345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313504117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3313504117
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3872441204
Short name T620
Test name
Test status
Simulation time 18161713 ps
CPU time 0.8 seconds
Started May 19 12:51:46 PM PDT 24
Finished May 19 12:51:48 PM PDT 24
Peak memory 206664 kb
Host smart-d5eb5f68-9b6f-461e-a722-b666f7708650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872441204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3872441204
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4069468374
Short name T831
Test name
Test status
Simulation time 111243848857 ps
CPU time 188.95 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 248816 kb
Host smart-1d4fbc2f-60d1-4147-8a67-02cc18174c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069468374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4069468374
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3580163072
Short name T205
Test name
Test status
Simulation time 17866077255 ps
CPU time 78.7 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 236192 kb
Host smart-f19147d3-df62-45aa-981d-fd2b8de381f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580163072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3580163072
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3015562818
Short name T391
Test name
Test status
Simulation time 515401500 ps
CPU time 3.04 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 217056 kb
Host smart-5c63a340-ce7c-4814-9c76-10f45bae6682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015562818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3015562818
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1699494632
Short name T346
Test name
Test status
Simulation time 2255105257 ps
CPU time 4.72 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:04 PM PDT 24
Peak memory 224320 kb
Host smart-d5313771-dfc8-4297-95c5-808fb75640d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699494632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1699494632
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4548763
Short name T211
Test name
Test status
Simulation time 446706845 ps
CPU time 5.88 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:06 PM PDT 24
Peak memory 217128 kb
Host smart-9f957027-d253-4022-9f34-b8097b0b9ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4548763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4548763
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1608255743
Short name T684
Test name
Test status
Simulation time 4286906556 ps
CPU time 17.78 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 236296 kb
Host smart-f6cc7ea9-0888-4e91-91ff-8a375cb16145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608255743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1608255743
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2703404157
Short name T956
Test name
Test status
Simulation time 70144249840 ps
CPU time 18.34 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:52:23 PM PDT 24
Peak memory 233552 kb
Host smart-e459fc35-7dd2-4fa5-842f-94f3a8356c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703404157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2703404157
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2692501535
Short name T809
Test name
Test status
Simulation time 445407320 ps
CPU time 3.84 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 232900 kb
Host smart-93eaaaaa-8b30-4bb8-8a78-588ab431aacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692501535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2692501535
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.170023688
Short name T628
Test name
Test status
Simulation time 1218587258 ps
CPU time 7.38 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 220380 kb
Host smart-4f37246a-76ef-4397-a934-e7864967bc7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170023688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.170023688
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.288326798
Short name T156
Test name
Test status
Simulation time 7592303787 ps
CPU time 41.54 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 223592 kb
Host smart-bc9273ce-7c8f-4897-8031-e3302f20f066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288326798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.288326798
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.615172505
Short name T124
Test name
Test status
Simulation time 2317814695 ps
CPU time 22.02 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 216280 kb
Host smart-33c100f3-537b-414b-969a-a85b3bde4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615172505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.615172505
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2395194112
Short name T914
Test name
Test status
Simulation time 1882373723 ps
CPU time 9.46 seconds
Started May 19 12:51:48 PM PDT 24
Finished May 19 12:51:59 PM PDT 24
Peak memory 215856 kb
Host smart-5be6dfd0-f3f6-4fc1-9487-e1824f88806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395194112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2395194112
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.964934674
Short name T771
Test name
Test status
Simulation time 117288368 ps
CPU time 3.38 seconds
Started May 19 12:51:51 PM PDT 24
Finished May 19 12:51:56 PM PDT 24
Peak memory 216080 kb
Host smart-53ccac03-1855-4751-9a82-33a2e135828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964934674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.964934674
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2923574200
Short name T764
Test name
Test status
Simulation time 74985691 ps
CPU time 0.78 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:03 PM PDT 24
Peak memory 205652 kb
Host smart-3bd3ec4d-ae42-4003-b708-db98294a17bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923574200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2923574200
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4083873708
Short name T836
Test name
Test status
Simulation time 10779474551 ps
CPU time 9.35 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:52:05 PM PDT 24
Peak memory 235780 kb
Host smart-040a9e3f-daab-4010-97b2-0bd8cc9f07d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083873708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4083873708
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3492845089
Short name T821
Test name
Test status
Simulation time 11639084 ps
CPU time 0.71 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:51:59 PM PDT 24
Peak memory 205252 kb
Host smart-5261a775-e3af-4408-bb61-f4981b721601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492845089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3492845089
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1289650952
Short name T253
Test name
Test status
Simulation time 391016387 ps
CPU time 5.59 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:14 PM PDT 24
Peak memory 218324 kb
Host smart-1d567035-3e2f-482f-8af4-b7553f70ac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289650952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1289650952
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2519235101
Short name T417
Test name
Test status
Simulation time 37620286 ps
CPU time 0.76 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:51:58 PM PDT 24
Peak memory 206336 kb
Host smart-7cbb946a-25cb-4212-a372-0368f2069314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519235101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2519235101
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3824473594
Short name T273
Test name
Test status
Simulation time 1731702399 ps
CPU time 15.46 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 240672 kb
Host smart-abf7ec0b-c2ba-4a21-8e28-91dbb44ef84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824473594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3824473594
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.269291696
Short name T290
Test name
Test status
Simulation time 46169107615 ps
CPU time 442.46 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:59:34 PM PDT 24
Peak memory 254936 kb
Host smart-fcbc93b7-ebb0-4a0b-947a-fef474532dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269291696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.269291696
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3330068406
Short name T717
Test name
Test status
Simulation time 10627879779 ps
CPU time 40.6 seconds
Started May 19 12:52:03 PM PDT 24
Finished May 19 12:52:47 PM PDT 24
Peak memory 248920 kb
Host smart-91178fc2-af6d-407e-b540-10d3592da419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330068406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3330068406
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3700959916
Short name T321
Test name
Test status
Simulation time 1359565738 ps
CPU time 13.92 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 232512 kb
Host smart-84202f83-b436-45ba-9a4b-0f2aa0aca2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700959916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3700959916
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1645723268
Short name T815
Test name
Test status
Simulation time 640344795 ps
CPU time 4.61 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:51:58 PM PDT 24
Peak memory 233396 kb
Host smart-dd13a107-c2af-41d9-a25e-031fabc06133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645723268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1645723268
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1834172479
Short name T71
Test name
Test status
Simulation time 47162455136 ps
CPU time 113.44 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 12:54:08 PM PDT 24
Peak memory 231832 kb
Host smart-84301053-8e51-4cd3-871e-999534c6c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834172479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1834172479
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2868886344
Short name T550
Test name
Test status
Simulation time 2263042648 ps
CPU time 4.96 seconds
Started May 19 12:52:02 PM PDT 24
Finished May 19 12:52:11 PM PDT 24
Peak memory 220420 kb
Host smart-5c944e1b-ea21-43f8-93e4-e885c97fbc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868886344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2868886344
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2934001284
Short name T619
Test name
Test status
Simulation time 1284909651 ps
CPU time 7.55 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:08 PM PDT 24
Peak memory 233392 kb
Host smart-2b139b46-f36e-479a-a71c-b267df2f03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934001284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2934001284
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3199788401
Short name T139
Test name
Test status
Simulation time 599434839 ps
CPU time 6.93 seconds
Started May 19 12:52:02 PM PDT 24
Finished May 19 12:52:13 PM PDT 24
Peak memory 219092 kb
Host smart-0598e585-a6d4-4c86-87e9-e05e2d8f323d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3199788401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3199788401
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2582334184
Short name T238
Test name
Test status
Simulation time 87942174036 ps
CPU time 186.85 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:55:11 PM PDT 24
Peak memory 249056 kb
Host smart-9b3e4d27-3994-4ac0-b2f4-ea703b5ea4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582334184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2582334184
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3073816533
Short name T721
Test name
Test status
Simulation time 6199135067 ps
CPU time 18.17 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 216088 kb
Host smart-07ba91f8-2937-4807-8740-9485a546dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073816533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3073816533
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2882105924
Short name T371
Test name
Test status
Simulation time 6064698928 ps
CPU time 5.66 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:10 PM PDT 24
Peak memory 216108 kb
Host smart-65175a93-7ea4-4971-a48e-bb383d638bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882105924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2882105924
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3191975892
Short name T730
Test name
Test status
Simulation time 43366045 ps
CPU time 1.34 seconds
Started May 19 12:51:49 PM PDT 24
Finished May 19 12:51:51 PM PDT 24
Peak memory 216112 kb
Host smart-c713910c-089e-444b-b1fe-759fbbdc81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191975892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3191975892
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3743083223
Short name T377
Test name
Test status
Simulation time 95862861 ps
CPU time 0.88 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:04 PM PDT 24
Peak memory 205644 kb
Host smart-51085753-08e5-4a31-8e17-213a59b9d621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743083223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3743083223
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.461339296
Short name T250
Test name
Test status
Simulation time 5069861495 ps
CPU time 17.01 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:17 PM PDT 24
Peak memory 219640 kb
Host smart-4ccfc840-69d7-4e55-9a7a-135296cfc506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461339296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.461339296
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3318312623
Short name T421
Test name
Test status
Simulation time 30807913 ps
CPU time 0.68 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:05 PM PDT 24
Peak memory 205120 kb
Host smart-0446cf2d-5311-45d0-9fbe-41288264dfbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318312623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3318312623
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.398183598
Short name T285
Test name
Test status
Simulation time 1396210573 ps
CPU time 5.11 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:52:04 PM PDT 24
Peak memory 235488 kb
Host smart-49bf5846-f8dd-4695-ac1e-76221198ed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398183598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.398183598
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3064458525
Short name T729
Test name
Test status
Simulation time 57586923 ps
CPU time 0.82 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:02 PM PDT 24
Peak memory 206596 kb
Host smart-2cbd6cce-1983-415e-b296-2d50180bd41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064458525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3064458525
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.416005415
Short name T578
Test name
Test status
Simulation time 81292649436 ps
CPU time 120.9 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:54:05 PM PDT 24
Peak memory 248892 kb
Host smart-ec3d21f0-cc80-4140-a7c7-300cbc8920a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416005415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.416005415
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3061865226
Short name T791
Test name
Test status
Simulation time 24911374998 ps
CPU time 210.29 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:55:33 PM PDT 24
Peak memory 252936 kb
Host smart-1297357d-a84f-4113-81ba-ce5456b390e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061865226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3061865226
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1520946010
Short name T20
Test name
Test status
Simulation time 41986767664 ps
CPU time 449.98 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:59:28 PM PDT 24
Peak memory 259668 kb
Host smart-36f6720a-2ed1-47b0-8451-d15821e98db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520946010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1520946010
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2234536459
Short name T750
Test name
Test status
Simulation time 3347081938 ps
CPU time 16.33 seconds
Started May 19 12:51:55 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 237820 kb
Host smart-24e9cf97-0864-4446-a6bb-f3c8aa87aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234536459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2234536459
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.820548651
Short name T276
Test name
Test status
Simulation time 4907859828 ps
CPU time 21.23 seconds
Started May 19 12:52:00 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 234672 kb
Host smart-5e3e706c-1847-4ac0-aa98-302eaccd950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820548651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.820548651
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3486405960
Short name T88
Test name
Test status
Simulation time 133241822 ps
CPU time 2.31 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:51:59 PM PDT 24
Peak memory 224324 kb
Host smart-115cdbd3-c9fc-4690-9520-63ff9aa04aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486405960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3486405960
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3109547122
Short name T351
Test name
Test status
Simulation time 105841848 ps
CPU time 2.2 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:02 PM PDT 24
Peak memory 215980 kb
Host smart-732a0705-630e-4533-99e5-f1f9e0f45f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109547122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3109547122
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2229055001
Short name T760
Test name
Test status
Simulation time 6740427248 ps
CPU time 7.44 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 234120 kb
Host smart-5a8fd61d-960a-4911-9dda-10c866ba5cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229055001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2229055001
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.231488951
Short name T651
Test name
Test status
Simulation time 3559300484 ps
CPU time 9.41 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:11 PM PDT 24
Peak memory 219808 kb
Host smart-cfc090db-c08f-42bd-8f43-0b8dadef487e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231488951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.231488951
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1978580532
Short name T37
Test name
Test status
Simulation time 13067055908 ps
CPU time 156.31 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 259076 kb
Host smart-8b881faa-d6d1-435f-aad7-4a12f1993fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978580532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1978580532
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3892121464
Short name T329
Test name
Test status
Simulation time 2572210180 ps
CPU time 26.38 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:30 PM PDT 24
Peak memory 216160 kb
Host smart-032639e9-4648-4dcc-892b-6f32dc10b72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892121464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3892121464
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.844255065
Short name T618
Test name
Test status
Simulation time 6088798172 ps
CPU time 11.22 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:12 PM PDT 24
Peak memory 216028 kb
Host smart-64bb0c79-1326-4f9e-913c-91cb0441ecd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844255065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.844255065
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1533625839
Short name T555
Test name
Test status
Simulation time 134072361 ps
CPU time 1.1 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:02 PM PDT 24
Peak memory 206888 kb
Host smart-213b5612-c695-4658-a467-cb1d2a58c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533625839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1533625839
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2749733374
Short name T495
Test name
Test status
Simulation time 162698414 ps
CPU time 0.81 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:04 PM PDT 24
Peak memory 205464 kb
Host smart-1e8151df-bca9-4dec-ae8f-ab9a9a1966f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749733374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2749733374
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4147074078
Short name T917
Test name
Test status
Simulation time 5352174147 ps
CPU time 12.67 seconds
Started May 19 12:52:03 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 238992 kb
Host smart-40ee1d3a-e43a-411c-a881-a36e3ee61006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147074078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4147074078
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4274553218
Short name T462
Test name
Test status
Simulation time 24744962 ps
CPU time 0.73 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:03 PM PDT 24
Peak memory 205584 kb
Host smart-47ca1ac6-5cbf-4b7d-a339-1198a1cac454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274553218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4274553218
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2356371965
Short name T753
Test name
Test status
Simulation time 1227267038 ps
CPU time 5.51 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:07 PM PDT 24
Peak memory 218908 kb
Host smart-f512e01c-8454-478f-8e6f-40687c94e469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356371965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2356371965
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.215878208
Short name T900
Test name
Test status
Simulation time 12728393 ps
CPU time 0.81 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:02 PM PDT 24
Peak memory 206648 kb
Host smart-da04784e-567f-4947-abc3-6942a0643d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215878208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.215878208
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1694507548
Short name T403
Test name
Test status
Simulation time 112117082104 ps
CPU time 120.77 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:53:56 PM PDT 24
Peak memory 248956 kb
Host smart-020b9e3c-94d9-44d3-a4e3-ac37ac5c5ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694507548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1694507548
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2343442143
Short name T39
Test name
Test status
Simulation time 14832233151 ps
CPU time 31.05 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 240728 kb
Host smart-b8fb1f13-53e2-4695-a98a-ad4825593981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343442143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2343442143
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1723075101
Short name T623
Test name
Test status
Simulation time 1708876108 ps
CPU time 16.58 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 233700 kb
Host smart-a4a0ae27-b051-40c8-bc47-61bee360c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723075101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1723075101
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3188409529
Short name T314
Test name
Test status
Simulation time 3098318377 ps
CPU time 26.77 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:28 PM PDT 24
Peak memory 234284 kb
Host smart-8538e3ad-b968-4d25-b2f8-2a0e85f8ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188409529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3188409529
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1385238948
Short name T715
Test name
Test status
Simulation time 1668994092 ps
CPU time 15.95 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:52:17 PM PDT 24
Peak memory 235256 kb
Host smart-7aa8b48b-f340-4d7d-abff-e3b0413b6602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385238948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1385238948
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2453534730
Short name T451
Test name
Test status
Simulation time 59640327451 ps
CPU time 58.56 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 239972 kb
Host smart-e2132796-c5f8-4ea8-8edb-32193b42a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453534730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2453534730
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2043831971
Short name T438
Test name
Test status
Simulation time 128909480 ps
CPU time 4.06 seconds
Started May 19 12:52:00 PM PDT 24
Finished May 19 12:52:09 PM PDT 24
Peak memory 217072 kb
Host smart-e36127cb-7a4b-46f7-ab81-ea1f2577dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043831971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2043831971
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2024638000
Short name T943
Test name
Test status
Simulation time 1006230746 ps
CPU time 4.98 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 233460 kb
Host smart-3994313c-64f4-42f1-bf3e-8572b620617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024638000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2024638000
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4284931186
Short name T548
Test name
Test status
Simulation time 537135879 ps
CPU time 3.58 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:07 PM PDT 24
Peak memory 220052 kb
Host smart-5859390e-4091-4482-980a-5b45bf175f92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284931186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4284931186
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2700751730
Short name T154
Test name
Test status
Simulation time 31011004898 ps
CPU time 147.24 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 253300 kb
Host smart-247b14ff-da68-466d-b039-e9f941e8587d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700751730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2700751730
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3976348657
Short name T331
Test name
Test status
Simulation time 4880838244 ps
CPU time 27.45 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 216192 kb
Host smart-cc29a659-b098-4174-a594-856708dc4817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976348657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3976348657
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3100158709
Short name T816
Test name
Test status
Simulation time 30628344610 ps
CPU time 14.8 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:52:09 PM PDT 24
Peak memory 216200 kb
Host smart-ccfb001b-19c9-4922-8323-4d45b550a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100158709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3100158709
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3348931390
Short name T453
Test name
Test status
Simulation time 405359965 ps
CPU time 2.58 seconds
Started May 19 12:51:53 PM PDT 24
Finished May 19 12:51:58 PM PDT 24
Peak memory 216104 kb
Host smart-ea1e9c4e-7cb1-40e9-814f-a2db6ea6070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348931390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3348931390
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3078174695
Short name T704
Test name
Test status
Simulation time 59537183 ps
CPU time 0.78 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 205700 kb
Host smart-599ad65d-f8dd-4f52-bfdf-96d07420881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078174695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3078174695
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.380259595
Short name T835
Test name
Test status
Simulation time 330700784 ps
CPU time 3.24 seconds
Started May 19 12:51:52 PM PDT 24
Finished May 19 12:51:57 PM PDT 24
Peak memory 218156 kb
Host smart-c2f87b57-9127-4b9b-886b-03c59349703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380259595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.380259595
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3623899148
Short name T590
Test name
Test status
Simulation time 41130129 ps
CPU time 0.7 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:22 PM PDT 24
Peak memory 204572 kb
Host smart-c36b8bdc-e129-492d-8924-695a64437e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623899148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
623899148
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.102076856
Short name T912
Test name
Test status
Simulation time 132681128 ps
CPU time 4.1 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:27 PM PDT 24
Peak memory 236420 kb
Host smart-14978947-f1b0-4c45-aee5-5f5b18fc6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102076856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.102076856
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2549825202
Short name T543
Test name
Test status
Simulation time 43997103 ps
CPU time 0.79 seconds
Started May 19 12:51:13 PM PDT 24
Finished May 19 12:51:17 PM PDT 24
Peak memory 206432 kb
Host smart-5e531187-9f73-4565-9456-2fca98d977fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549825202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2549825202
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.4166559472
Short name T374
Test name
Test status
Simulation time 15580653 ps
CPU time 0.73 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:19 PM PDT 24
Peak memory 215776 kb
Host smart-0a5d3ec6-9ce4-48f0-aba8-45587ec26cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166559472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.4166559472
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.728912348
Short name T597
Test name
Test status
Simulation time 203921820281 ps
CPU time 226.79 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:55:10 PM PDT 24
Peak memory 252300 kb
Host smart-bc72b296-2f65-48de-9a8f-db7fedcb70ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728912348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
728912348
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2209125110
Short name T322
Test name
Test status
Simulation time 192884022 ps
CPU time 8.24 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:29 PM PDT 24
Peak memory 232488 kb
Host smart-e3f130a0-790c-45e9-bc57-56845274c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209125110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2209125110
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1529994586
Short name T630
Test name
Test status
Simulation time 3361211339 ps
CPU time 13.48 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 233920 kb
Host smart-716444a6-484d-4228-8072-0942f6098469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529994586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1529994586
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2163844034
Short name T213
Test name
Test status
Simulation time 632281145 ps
CPU time 5.09 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 234108 kb
Host smart-7edcf1f5-5eca-43ed-a837-a9b14a77b9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163844034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2163844034
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1606217967
Short name T272
Test name
Test status
Simulation time 563229294 ps
CPU time 3.16 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 218428 kb
Host smart-be764bdd-5d73-479f-9b0e-9fccc2241731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606217967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1606217967
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4159023790
Short name T507
Test name
Test status
Simulation time 2610615268 ps
CPU time 7.02 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:29 PM PDT 24
Peak memory 233412 kb
Host smart-7475031a-1939-4fc6-a612-a8cb7e5ca417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159023790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4159023790
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2705183970
Short name T490
Test name
Test status
Simulation time 1506440937 ps
CPU time 10.72 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 222784 kb
Host smart-03c7b0f9-1d8f-4c5e-88cb-64723783a171
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2705183970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2705183970
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1239937293
Short name T63
Test name
Test status
Simulation time 147473339 ps
CPU time 1.02 seconds
Started May 19 12:51:20 PM PDT 24
Finished May 19 12:51:27 PM PDT 24
Peak memory 234528 kb
Host smart-0177e23b-fbf0-4201-9a56-50d1e4c24308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239937293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1239937293
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1283571399
Short name T519
Test name
Test status
Simulation time 14806821099 ps
CPU time 54.06 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 254828 kb
Host smart-d615ae54-7be4-4d9b-bfa9-7547b1db0f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283571399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1283571399
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3835530863
Short name T639
Test name
Test status
Simulation time 11375672268 ps
CPU time 18.28 seconds
Started May 19 12:51:11 PM PDT 24
Finished May 19 12:51:32 PM PDT 24
Peak memory 216128 kb
Host smart-8fe5834b-17fd-4a61-921e-d6aa37312cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835530863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3835530863
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.47836539
Short name T793
Test name
Test status
Simulation time 10102955757 ps
CPU time 10.88 seconds
Started May 19 12:51:10 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 215940 kb
Host smart-d3c1fb09-1323-4686-b80a-4cccd0b841be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47836539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.47836539
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.448772903
Short name T825
Test name
Test status
Simulation time 97417688 ps
CPU time 4.48 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 216136 kb
Host smart-6926b5b4-4254-43f2-9440-b92c6ebc95af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448772903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.448772903
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3160799080
Short name T652
Test name
Test status
Simulation time 298671486 ps
CPU time 0.84 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:22 PM PDT 24
Peak memory 205520 kb
Host smart-7c6fee00-b1ca-41bd-8bd7-a44b4f1c0ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160799080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3160799080
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3225964633
Short name T255
Test name
Test status
Simulation time 164346045 ps
CPU time 3.61 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:26 PM PDT 24
Peak memory 237496 kb
Host smart-e16b31e3-49ee-4829-8905-7016d7ea3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225964633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3225964633
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1868064550
Short name T444
Test name
Test status
Simulation time 45125127 ps
CPU time 0.79 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:52:06 PM PDT 24
Peak memory 205168 kb
Host smart-bafcebb2-6685-45af-8ccc-9c681d4f5199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868064550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1868064550
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.559423767
Short name T13
Test name
Test status
Simulation time 394384562 ps
CPU time 6.82 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 233448 kb
Host smart-50d437ec-85ad-4b35-ba78-d3ce6bd5ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559423767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.559423767
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3903985283
Short name T624
Test name
Test status
Simulation time 171830254 ps
CPU time 0.77 seconds
Started May 19 12:51:54 PM PDT 24
Finished May 19 12:51:59 PM PDT 24
Peak memory 206416 kb
Host smart-24e6f914-e87d-421b-b216-b6e87478cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903985283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3903985283
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3905244151
Short name T496
Test name
Test status
Simulation time 21732848955 ps
CPU time 96.15 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:53:44 PM PDT 24
Peak memory 241064 kb
Host smart-5e389ba8-ed89-4506-8cca-6d1fb67c4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905244151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3905244151
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3211899777
Short name T512
Test name
Test status
Simulation time 45223019460 ps
CPU time 107.81 seconds
Started May 19 12:52:02 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 223252 kb
Host smart-0d9eec5b-345c-4e09-af57-c209606f7003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211899777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3211899777
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1062920095
Short name T886
Test name
Test status
Simulation time 594734115 ps
CPU time 8.04 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 240704 kb
Host smart-14397fd5-c0db-4fe7-aca2-11739f183016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062920095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1062920095
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.452445186
Short name T837
Test name
Test status
Simulation time 334935549 ps
CPU time 2.62 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:52:13 PM PDT 24
Peak memory 218248 kb
Host smart-8f5df2cf-0cbf-411e-a849-879b96f48a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452445186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.452445186
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3818342652
Short name T642
Test name
Test status
Simulation time 13320198603 ps
CPU time 33.64 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:37 PM PDT 24
Peak memory 237492 kb
Host smart-7635b25e-a4ea-4ec6-9751-97e8d1abc9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818342652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3818342652
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3535304873
Short name T598
Test name
Test status
Simulation time 15837283327 ps
CPU time 28.25 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 224348 kb
Host smart-f35892f3-1818-457b-9caf-6b45caccea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535304873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3535304873
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.379239662
Short name T887
Test name
Test status
Simulation time 10709243732 ps
CPU time 12.19 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 216516 kb
Host smart-540e3852-fb69-455c-83f1-30a5a055ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379239662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.379239662
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.931851491
Short name T863
Test name
Test status
Simulation time 817940615 ps
CPU time 9.29 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 222268 kb
Host smart-ae23ead0-1d30-4c1d-9975-84d9ebeb1305
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931851491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.931851491
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2467713645
Short name T448
Test name
Test status
Simulation time 10515597429 ps
CPU time 31.03 seconds
Started May 19 12:52:03 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 216452 kb
Host smart-6985ddb9-67d2-49f3-b5e1-d66a14247b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467713645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2467713645
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3911805154
Short name T455
Test name
Test status
Simulation time 3948717673 ps
CPU time 10.78 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 216096 kb
Host smart-ea000b23-403a-4ddf-9241-6d9e3a90f851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911805154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3911805154
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.452299024
Short name T554
Test name
Test status
Simulation time 244010575 ps
CPU time 3.53 seconds
Started May 19 12:51:56 PM PDT 24
Finished May 19 12:52:03 PM PDT 24
Peak memory 216408 kb
Host smart-ccda671e-1b85-434f-9d10-78104b261e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452299024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.452299024
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.178784513
Short name T707
Test name
Test status
Simulation time 48271875 ps
CPU time 0.9 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:12 PM PDT 24
Peak memory 205820 kb
Host smart-a9c1cd67-e59c-4d8d-ad39-08ee292e726c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178784513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.178784513
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.773546289
Short name T907
Test name
Test status
Simulation time 250327109 ps
CPU time 5.21 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:30 PM PDT 24
Peak memory 232524 kb
Host smart-e00ce5be-c730-4490-a2ef-e8d0c1323c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773546289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.773546289
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3929872592
Short name T807
Test name
Test status
Simulation time 83594536 ps
CPU time 0.73 seconds
Started May 19 12:52:00 PM PDT 24
Finished May 19 12:52:05 PM PDT 24
Peak memory 204664 kb
Host smart-1b350629-e121-4452-a264-3ab1831e12be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929872592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3929872592
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2785274967
Short name T936
Test name
Test status
Simulation time 211119257 ps
CPU time 3.13 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:14 PM PDT 24
Peak memory 219280 kb
Host smart-f94d838d-bb89-4b3b-916a-e522ab355538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785274967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2785274967
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2506713844
Short name T693
Test name
Test status
Simulation time 40732908 ps
CPU time 0.75 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 205236 kb
Host smart-b3fc916c-ff74-4aca-b44f-7a871e3f67a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506713844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2506713844
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3715462120
Short name T300
Test name
Test status
Simulation time 111991050338 ps
CPU time 253.98 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:56:22 PM PDT 24
Peak memory 264732 kb
Host smart-8a07e79b-369a-4e61-a8e2-a1cae0b9b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715462120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3715462120
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1041189575
Short name T586
Test name
Test status
Simulation time 39137457218 ps
CPU time 162.83 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 240260 kb
Host smart-5485a138-e5fd-4cf4-931e-f678001a55b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041189575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1041189575
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2510018426
Short name T574
Test name
Test status
Simulation time 18397451761 ps
CPU time 166.03 seconds
Started May 19 12:51:57 PM PDT 24
Finished May 19 12:54:47 PM PDT 24
Peak memory 238016 kb
Host smart-97c95847-5a9d-4cc2-9431-0658e85ba3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510018426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2510018426
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.850641994
Short name T44
Test name
Test status
Simulation time 2183982628 ps
CPU time 27.87 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:37 PM PDT 24
Peak memory 232540 kb
Host smart-a97ee764-7935-4200-af84-ec1c4bdda464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850641994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.850641994
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1780196370
Short name T778
Test name
Test status
Simulation time 210295147 ps
CPU time 4.98 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:17 PM PDT 24
Peak memory 219452 kb
Host smart-48fabc28-ef9d-434d-9262-09c3a0681ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780196370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1780196370
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4052817448
Short name T248
Test name
Test status
Simulation time 203693605548 ps
CPU time 112.66 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 256184 kb
Host smart-823a80aa-050b-43d8-bbcc-ab69077c4d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052817448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4052817448
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2144872014
Short name T525
Test name
Test status
Simulation time 7114689728 ps
CPU time 20.53 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 218380 kb
Host smart-e22dff6f-5d36-4176-b8ed-ee63107b2304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144872014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2144872014
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.615714063
Short name T866
Test name
Test status
Simulation time 3265828241 ps
CPU time 6.58 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:22 PM PDT 24
Peak memory 233280 kb
Host smart-060c8761-6a44-4636-ae3a-d35d85b56552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615714063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.615714063
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1504067531
Short name T731
Test name
Test status
Simulation time 855641403 ps
CPU time 4.16 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:13 PM PDT 24
Peak memory 219960 kb
Host smart-8fcdc647-d556-4321-81dd-d95094b4caa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504067531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1504067531
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3865175616
Short name T486
Test name
Test status
Simulation time 845791440 ps
CPU time 4.14 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 215932 kb
Host smart-ded506a8-ac70-4cc0-bdc9-82c0c25e288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865175616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3865175616
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3223448212
Short name T594
Test name
Test status
Simulation time 249308354 ps
CPU time 1.58 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:52:07 PM PDT 24
Peak memory 207564 kb
Host smart-97514881-b31d-4d15-a2e5-612d0d5661b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223448212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3223448212
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3759134819
Short name T851
Test name
Test status
Simulation time 32623199 ps
CPU time 0.84 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 205584 kb
Host smart-be25e74c-6ed1-4774-9440-a0f5f0178655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759134819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3759134819
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1506189579
Short name T373
Test name
Test status
Simulation time 12793459 ps
CPU time 0.7 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 12:52:14 PM PDT 24
Peak memory 205496 kb
Host smart-e2db4871-1dee-420a-9a52-0a2d908e6e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506189579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1506189579
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4086378161
Short name T556
Test name
Test status
Simulation time 6895148761 ps
CPU time 26.21 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 236556 kb
Host smart-0379028e-6ee4-4b1b-91b9-b18f7bf131fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086378161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4086378161
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1748798858
Short name T382
Test name
Test status
Simulation time 15120329 ps
CPU time 0.71 seconds
Started May 19 12:52:14 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 205248 kb
Host smart-9fb30929-46ea-43cf-90be-9a8520a2d8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748798858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1748798858
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.816952555
Short name T648
Test name
Test status
Simulation time 60630116 ps
CPU time 2.16 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 220784 kb
Host smart-409e22ef-37e5-43d8-a05a-a3b82c8feda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816952555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.816952555
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1974642245
Short name T384
Test name
Test status
Simulation time 68773355 ps
CPU time 0.76 seconds
Started May 19 12:52:02 PM PDT 24
Finished May 19 12:52:07 PM PDT 24
Peak memory 206348 kb
Host smart-c89d141d-b931-4f20-b821-fd0759e23ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974642245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1974642245
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3744993321
Short name T22
Test name
Test status
Simulation time 11331007772 ps
CPU time 59.07 seconds
Started May 19 12:52:01 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 248972 kb
Host smart-2d080aea-b385-4d27-b46c-ac1c50754cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744993321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3744993321
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2617718212
Short name T310
Test name
Test status
Simulation time 536651178158 ps
CPU time 488.67 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 01:00:22 PM PDT 24
Peak memory 239408 kb
Host smart-48ef7ef6-5faf-4513-bdc9-e85d83270f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617718212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2617718212
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1422858568
Short name T638
Test name
Test status
Simulation time 2953816512 ps
CPU time 13.46 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 232492 kb
Host smart-e3b693fa-2329-49a7-8486-0473c4d58340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422858568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1422858568
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.131766258
Short name T506
Test name
Test status
Simulation time 1134237134 ps
CPU time 11.89 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 218524 kb
Host smart-7e0beba2-65ed-4051-80cf-4e97fc12bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131766258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.131766258
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.109788760
Short name T541
Test name
Test status
Simulation time 10566447796 ps
CPU time 23.12 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 240164 kb
Host smart-31cbacb4-af04-47db-880a-cc7ddf6200f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109788760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.109788760
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1007103870
Short name T271
Test name
Test status
Simulation time 575773024 ps
CPU time 3.46 seconds
Started May 19 12:51:58 PM PDT 24
Finished May 19 12:52:06 PM PDT 24
Peak memory 216656 kb
Host smart-12d33863-cb56-4498-9784-e17e02df48eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007103870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1007103870
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3713675877
Short name T763
Test name
Test status
Simulation time 107719567 ps
CPU time 2.22 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:52:10 PM PDT 24
Peak memory 215896 kb
Host smart-ba4d8fdb-7254-4834-a2dc-337248a395ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713675877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3713675877
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2119643605
Short name T820
Test name
Test status
Simulation time 815291924 ps
CPU time 4.83 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:22 PM PDT 24
Peak memory 218612 kb
Host smart-f07dc098-f9f8-4902-95ee-1a384c380464
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2119643605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2119643605
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1605784115
Short name T631
Test name
Test status
Simulation time 43919161 ps
CPU time 0.94 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:14 PM PDT 24
Peak memory 205440 kb
Host smart-1f0b2d3a-813a-4c34-9bc9-93e7d8c2a718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605784115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1605784115
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1387507518
Short name T85
Test name
Test status
Simulation time 14512538333 ps
CPU time 31.52 seconds
Started May 19 12:52:03 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 216308 kb
Host smart-afe1d5a7-e9ba-43da-add6-991d3f4c250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387507518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1387507518
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4075854859
Short name T393
Test name
Test status
Simulation time 1793714379 ps
CPU time 2.94 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 216292 kb
Host smart-6860c327-bb93-444f-a2a3-8cc439ffabab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075854859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4075854859
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3229339414
Short name T544
Test name
Test status
Simulation time 243753798 ps
CPU time 1.28 seconds
Started May 19 12:51:59 PM PDT 24
Finished May 19 12:52:05 PM PDT 24
Peak memory 207716 kb
Host smart-d5a1df05-6618-47e0-a39a-3ff194719086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229339414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3229339414
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3335476760
Short name T830
Test name
Test status
Simulation time 76257599 ps
CPU time 0.88 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:18 PM PDT 24
Peak memory 205580 kb
Host smart-67c23747-cac0-436b-84fc-e8826d54ddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335476760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3335476760
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2885736656
Short name T482
Test name
Test status
Simulation time 4452373438 ps
CPU time 6.74 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 234040 kb
Host smart-4f5192d2-dd69-4448-8d34-f9c3414f43c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885736656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2885736656
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4259600409
Short name T737
Test name
Test status
Simulation time 24645729 ps
CPU time 0.73 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:52:11 PM PDT 24
Peak memory 205228 kb
Host smart-af6d6277-091a-4bf4-b8a0-8d5f2f579b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259600409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4259600409
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.842580718
Short name T242
Test name
Test status
Simulation time 2702438469 ps
CPU time 17.59 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 220132 kb
Host smart-bc2631d9-3037-4099-bccb-d1a15ad8f49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842580718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.842580718
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.455699830
Short name T513
Test name
Test status
Simulation time 68513320 ps
CPU time 0.73 seconds
Started May 19 12:52:14 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 206656 kb
Host smart-dd79b4db-4590-40d2-9006-9123174ed28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455699830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.455699830
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.545365265
Short name T309
Test name
Test status
Simulation time 1384361590 ps
CPU time 16.8 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 232388 kb
Host smart-07407f86-e822-46a1-8311-b8e7b65358a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545365265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.545365265
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3266038812
Short name T214
Test name
Test status
Simulation time 82997829691 ps
CPU time 161.11 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:54:59 PM PDT 24
Peak memory 237800 kb
Host smart-8c9d699b-0e8e-432b-9a28-d3715877fad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266038812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3266038812
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.620521521
Short name T232
Test name
Test status
Simulation time 42429071348 ps
CPU time 118.91 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 249004 kb
Host smart-c1b80f17-e69d-4e6e-959e-e39c994cfdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620521521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.620521521
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.845093401
Short name T843
Test name
Test status
Simulation time 276451401 ps
CPU time 8.17 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:23 PM PDT 24
Peak memory 232464 kb
Host smart-034f6c05-8cae-4033-80d6-543c454ccbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845093401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.845093401
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3254404826
Short name T224
Test name
Test status
Simulation time 1969665345 ps
CPU time 11.76 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 233776 kb
Host smart-682ca30f-e791-43df-8f9f-7f2ef57de660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254404826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3254404826
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.314054674
Short name T800
Test name
Test status
Simulation time 289253946 ps
CPU time 2.71 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 235696 kb
Host smart-46ae5194-e25f-4c5a-99ab-973088b0127b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314054674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.314054674
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2855429580
Short name T926
Test name
Test status
Simulation time 1853308013 ps
CPU time 8.16 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 224580 kb
Host smart-d0d9232d-3df6-4fa2-9758-c097665da832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855429580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2855429580
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3062868477
Short name T27
Test name
Test status
Simulation time 854717982 ps
CPU time 4.95 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 227168 kb
Host smart-39e7be95-1f5f-455d-82b5-c9e33a562bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062868477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3062868477
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2641087566
Short name T8
Test name
Test status
Simulation time 2793132330 ps
CPU time 3.97 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 220092 kb
Host smart-1d825ffc-966a-4dc0-a86c-a74480834b10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2641087566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2641087566
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.845064142
Short name T261
Test name
Test status
Simulation time 24913962529 ps
CPU time 199.24 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:55:44 PM PDT 24
Peak memory 248968 kb
Host smart-564b7318-4d24-4324-9d93-0718e462e7a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845064142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.845064142
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.73009097
Short name T334
Test name
Test status
Simulation time 1076073319 ps
CPU time 8.47 seconds
Started May 19 12:52:03 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 216040 kb
Host smart-9f87d75b-52cd-4b67-a21c-4113deefb06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73009097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.73009097
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4279364298
Short name T537
Test name
Test status
Simulation time 5052982986 ps
CPU time 14.96 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 216096 kb
Host smart-44d6dd09-c44f-453a-b5db-01161a6e5c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279364298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4279364298
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2060115380
Short name T478
Test name
Test status
Simulation time 1016507115 ps
CPU time 6.01 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 216048 kb
Host smart-47cf8f39-5fcb-4b5c-9c0c-1a47dfd28378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060115380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2060115380
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1205513018
Short name T511
Test name
Test status
Simulation time 65747669 ps
CPU time 0.81 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 205648 kb
Host smart-34ff1231-0c7c-410b-a806-1ebc3956c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205513018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1205513018
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2952381361
Short name T558
Test name
Test status
Simulation time 15192133776 ps
CPU time 15.74 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 239548 kb
Host smart-971a8f63-e3b6-4854-bcdf-80dccf71f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952381361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2952381361
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.182271581
Short name T572
Test name
Test status
Simulation time 32058092 ps
CPU time 0.72 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 205064 kb
Host smart-ff02a9e4-5a25-44c5-8bef-94e7ca65d2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182271581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.182271581
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1685883598
Short name T239
Test name
Test status
Simulation time 910310468 ps
CPU time 12.38 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 219524 kb
Host smart-510930c5-7f51-4fc8-b9de-6c04b5bac67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685883598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1685883598
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.47251082
Short name T897
Test name
Test status
Simulation time 26966077 ps
CPU time 0.8 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:18 PM PDT 24
Peak memory 206636 kb
Host smart-7675bc6e-dd11-4dc4-aeb0-03246346373e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47251082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.47251082
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4054543762
Short name T306
Test name
Test status
Simulation time 580211292408 ps
CPU time 249.93 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:56:28 PM PDT 24
Peak memory 256360 kb
Host smart-26e3c2a4-5813-4952-905c-37ca648f5504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054543762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4054543762
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2703695907
Short name T869
Test name
Test status
Simulation time 4239340572 ps
CPU time 45.51 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:52:56 PM PDT 24
Peak memory 240724 kb
Host smart-8b146fe6-1680-46f7-8fa7-dad4023a06e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703695907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2703695907
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_intercept.166921440
Short name T190
Test name
Test status
Simulation time 565133472 ps
CPU time 4.26 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:17 PM PDT 24
Peak memory 219524 kb
Host smart-c5d2d659-219a-4e8c-8c91-8f9fdb029aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166921440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.166921440
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1429446726
Short name T849
Test name
Test status
Simulation time 23933376615 ps
CPU time 74.06 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 238256 kb
Host smart-6052cee0-4419-4161-be22-2a8a025652e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429446726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1429446726
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3559366863
Short name T218
Test name
Test status
Simulation time 18227883983 ps
CPU time 51.11 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 240312 kb
Host smart-af3ece25-4cf9-491d-a1b8-8cdb36013151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559366863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3559366863
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.588074460
Short name T215
Test name
Test status
Simulation time 225518688 ps
CPU time 2.39 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 218120 kb
Host smart-60f90d60-4749-4dbd-ad6a-9bd78b753523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588074460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.588074460
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3457306232
Short name T891
Test name
Test status
Simulation time 461637174 ps
CPU time 5.2 seconds
Started May 19 12:52:06 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 222660 kb
Host smart-1341f2fe-f911-4d21-bdb5-12415fd4385e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3457306232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3457306232
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1658957794
Short name T328
Test name
Test status
Simulation time 1397294046 ps
CPU time 7.16 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 218800 kb
Host smart-de479b2f-3ff9-4be8-8a80-39f8b4ec989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658957794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1658957794
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1817649924
Short name T595
Test name
Test status
Simulation time 1165179019 ps
CPU time 5.07 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:18 PM PDT 24
Peak memory 216036 kb
Host smart-f21e435e-1e80-4a8d-946d-0b2ea18f1e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817649924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1817649924
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2171596498
Short name T332
Test name
Test status
Simulation time 130448595 ps
CPU time 1.07 seconds
Started May 19 12:52:14 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 207008 kb
Host smart-94ac555e-f229-434d-af87-57e497ed7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171596498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2171596498
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.449727318
Short name T349
Test name
Test status
Simulation time 59693238 ps
CPU time 0.81 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:12 PM PDT 24
Peak memory 205660 kb
Host smart-767f1afb-b3dc-4f14-9018-c16bd51cf389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449727318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.449727318
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.512486714
Short name T28
Test name
Test status
Simulation time 6431961134 ps
CPU time 18.5 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 229588 kb
Host smart-5b80d8e8-ba78-4646-b101-cf5d08e340dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512486714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.512486714
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3100974257
Short name T813
Test name
Test status
Simulation time 30171649 ps
CPU time 0.66 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 205260 kb
Host smart-3a6ff7bc-aeda-4b7e-91bb-4fdeed5a2df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100974257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3100974257
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1988188324
Short name T695
Test name
Test status
Simulation time 559041449 ps
CPU time 2.83 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:28 PM PDT 24
Peak memory 224124 kb
Host smart-4538be85-50d6-445d-849a-d9b771e779b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988188324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1988188324
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.344090809
Short name T405
Test name
Test status
Simulation time 14000780 ps
CPU time 0.75 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 206656 kb
Host smart-fca61a09-80ec-4cbe-b2c7-8c00656d5418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344090809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.344090809
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2395631912
Short name T308
Test name
Test status
Simulation time 62256274500 ps
CPU time 132.62 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:54:41 PM PDT 24
Peak memory 257152 kb
Host smart-4604e2c6-e4d7-4213-830f-60bc5943b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395631912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2395631912
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.886176164
Short name T599
Test name
Test status
Simulation time 7061539941 ps
CPU time 27.39 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 237444 kb
Host smart-e09f411c-a3ed-440f-8985-77439f72f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886176164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.886176164
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.980784626
Short name T397
Test name
Test status
Simulation time 968213549 ps
CPU time 3.92 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:22 PM PDT 24
Peak memory 219328 kb
Host smart-1c6feb36-1018-4572-805e-f3ca2c9a226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980784626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.980784626
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4218156987
Short name T528
Test name
Test status
Simulation time 937488642 ps
CPU time 5.22 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 218252 kb
Host smart-2c44ee2d-aff9-43e4-85ef-608ce000261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218156987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4218156987
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3108469957
Short name T230
Test name
Test status
Simulation time 5010356245 ps
CPU time 8.74 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 227984 kb
Host smart-eb48a9a6-aa6c-4c84-8ca9-0c124e869e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108469957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3108469957
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2164907465
Short name T629
Test name
Test status
Simulation time 29804951222 ps
CPU time 24.15 seconds
Started May 19 12:52:04 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 218324 kb
Host smart-22d937a0-d6eb-4cb2-b245-9d23e2413227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164907465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2164907465
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1709129679
Short name T516
Test name
Test status
Simulation time 801298165 ps
CPU time 8.05 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:23 PM PDT 24
Peak memory 219968 kb
Host smart-4bcaa2de-7eed-45db-aef0-8c8c6405e721
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709129679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1709129679
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3478744978
Short name T463
Test name
Test status
Simulation time 637144828797 ps
CPU time 382.92 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:58:35 PM PDT 24
Peak memory 254664 kb
Host smart-f778e786-44b5-4274-a0b5-323b933a7f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478744978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3478744978
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1600366767
Short name T616
Test name
Test status
Simulation time 28873599800 ps
CPU time 38.72 seconds
Started May 19 12:52:05 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 216092 kb
Host smart-3a3e4157-b89e-4e35-9902-38c2524fcf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600366767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1600366767
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1823335606
Short name T484
Test name
Test status
Simulation time 2114083296 ps
CPU time 6.46 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:18 PM PDT 24
Peak memory 215876 kb
Host smart-f90f080c-bf9e-4b7e-87ba-2b144dc35e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823335606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1823335606
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3083336860
Short name T178
Test name
Test status
Simulation time 35779540 ps
CPU time 1.28 seconds
Started May 19 12:52:07 PM PDT 24
Finished May 19 12:52:13 PM PDT 24
Peak memory 207920 kb
Host smart-d51a1bde-52e3-4f2b-9098-d060edacdc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083336860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3083336860
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2028261883
Short name T464
Test name
Test status
Simulation time 109170909 ps
CPU time 0.82 seconds
Started May 19 12:52:14 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 205580 kb
Host smart-96b27e39-a312-4dfd-ab0b-3ca0e7e3b9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028261883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2028261883
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2009222195
Short name T521
Test name
Test status
Simulation time 1433618948 ps
CPU time 4.04 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:29 PM PDT 24
Peak memory 233160 kb
Host smart-e79381cd-8e53-4d34-a00e-d07eb7eabd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009222195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2009222195
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3770058649
Short name T553
Test name
Test status
Simulation time 12658428 ps
CPU time 0.68 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 205076 kb
Host smart-2bbcbe5a-2b67-4978-a6ce-ebfd2ef9aef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770058649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3770058649
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1903621098
Short name T245
Test name
Test status
Simulation time 124387595 ps
CPU time 4.08 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 234672 kb
Host smart-68f4aaa7-f41e-4f7d-87d4-ca7898c46ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903621098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1903621098
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4038760854
Short name T385
Test name
Test status
Simulation time 50200952 ps
CPU time 0.76 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 206276 kb
Host smart-4c3f8038-0a02-4f51-8a33-4a263b0a73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038760854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4038760854
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.371078926
Short name T341
Test name
Test status
Simulation time 805169575 ps
CPU time 11.3 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 224284 kb
Host smart-c00de1b3-b88f-4e0e-9e7a-3bf50c7b12ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371078926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.371078926
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3960368984
Short name T226
Test name
Test status
Simulation time 165532565924 ps
CPU time 112.72 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:54:20 PM PDT 24
Peak memory 256860 kb
Host smart-bec7a516-e588-4e87-9633-a4116d39d541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960368984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3960368984
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1397340072
Short name T337
Test name
Test status
Simulation time 118353705 ps
CPU time 2.43 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:29 PM PDT 24
Peak memory 224172 kb
Host smart-a34c62e9-c7fa-436d-ade6-e71b801cef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397340072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1397340072
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1811177101
Short name T430
Test name
Test status
Simulation time 4677955071 ps
CPU time 13.57 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:42 PM PDT 24
Peak memory 221692 kb
Host smart-975e065f-4a7d-4323-8775-470c1897b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811177101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1811177101
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2403401140
Short name T219
Test name
Test status
Simulation time 15477634273 ps
CPU time 54.66 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:53:21 PM PDT 24
Peak memory 246296 kb
Host smart-cc3c69e5-ab91-4144-8bee-e868334af754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403401140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2403401140
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.799359501
Short name T505
Test name
Test status
Simulation time 1617372056 ps
CPU time 6.66 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 218600 kb
Host smart-9b1234e3-863f-464f-8d77-503d3f0fa7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799359501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.799359501
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1236247810
Short name T777
Test name
Test status
Simulation time 175228281 ps
CPU time 3.45 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:52:40 PM PDT 24
Peak memory 219688 kb
Host smart-b310ef6c-9ac8-405d-8f7d-63ccf83f86a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236247810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1236247810
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3142633603
Short name T520
Test name
Test status
Simulation time 3178951254 ps
CPU time 5.76 seconds
Started May 19 12:52:14 PM PDT 24
Finished May 19 12:52:24 PM PDT 24
Peak memory 222976 kb
Host smart-3c4abc61-70cf-475d-88c6-33848a908150
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3142633603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3142633603
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.788941877
Short name T58
Test name
Test status
Simulation time 90121108783 ps
CPU time 160.28 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 224336 kb
Host smart-57474b38-7f09-4545-9b4c-c94b838d72d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788941877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.788941877
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3775756690
Short name T539
Test name
Test status
Simulation time 29650200 ps
CPU time 0.71 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 205584 kb
Host smart-d664f710-a7a8-4bfd-9374-3005a4c063a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775756690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3775756690
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3652454202
Short name T622
Test name
Test status
Simulation time 841602126 ps
CPU time 4.89 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 215912 kb
Host smart-4fc677e2-5ef1-431e-bdf2-4b6dac518898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652454202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3652454202
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3972912486
Short name T343
Test name
Test status
Simulation time 398613254 ps
CPU time 1.8 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 216016 kb
Host smart-0c6f9129-5254-4320-a20e-8976d8908031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972912486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3972912486
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3107363865
Short name T605
Test name
Test status
Simulation time 30474256 ps
CPU time 0.73 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 12:52:23 PM PDT 24
Peak memory 205632 kb
Host smart-913184de-63bf-4b6d-9966-0e5b88c14fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107363865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3107363865
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2357486443
Short name T249
Test name
Test status
Simulation time 3577292400 ps
CPU time 5.11 seconds
Started May 19 12:52:08 PM PDT 24
Finished May 19 12:52:17 PM PDT 24
Peak memory 219632 kb
Host smart-acd99e3a-a10d-4ada-9620-989064e9c28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357486443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2357486443
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.791028978
Short name T933
Test name
Test status
Simulation time 20775412 ps
CPU time 0.68 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 205088 kb
Host smart-40d173f3-3401-430d-8bc4-eff701d6e00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791028978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.791028978
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.281493037
Short name T738
Test name
Test status
Simulation time 159610044 ps
CPU time 2.99 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 218316 kb
Host smart-4504a316-ef6d-413f-8fc5-ea0d0cbccdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281493037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.281493037
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1231303873
Short name T930
Test name
Test status
Simulation time 17748642 ps
CPU time 0.76 seconds
Started May 19 12:52:23 PM PDT 24
Finished May 19 12:52:30 PM PDT 24
Peak memory 205584 kb
Host smart-24da11b6-9237-4859-b166-59b151dda265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231303873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1231303873
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1048213455
Short name T301
Test name
Test status
Simulation time 52469326529 ps
CPU time 363.59 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:58:21 PM PDT 24
Peak memory 270700 kb
Host smart-f05bb140-6e70-43b8-a8b5-9f5f0b150adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048213455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1048213455
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1993296227
Short name T514
Test name
Test status
Simulation time 2132429024 ps
CPU time 8.27 seconds
Started May 19 12:52:15 PM PDT 24
Finished May 19 12:52:28 PM PDT 24
Peak memory 217044 kb
Host smart-854e873b-1211-4891-8a64-a1300efc8d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993296227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1993296227
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2294330875
Short name T726
Test name
Test status
Simulation time 63686871072 ps
CPU time 139.08 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:54:39 PM PDT 24
Peak memory 240840 kb
Host smart-1d55dee0-9d03-4e45-8a98-999c4c86c386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294330875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2294330875
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3981923465
Short name T312
Test name
Test status
Simulation time 3357893650 ps
CPU time 38.48 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 236380 kb
Host smart-43df2e6b-ec0d-4dd2-b3df-ad0662ca425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981923465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3981923465
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3221143423
Short name T473
Test name
Test status
Simulation time 8005259377 ps
CPU time 16.55 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:45 PM PDT 24
Peak memory 235084 kb
Host smart-f26e0593-bb19-4e5b-9023-aa1ebef7b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221143423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3221143423
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1581683651
Short name T632
Test name
Test status
Simulation time 11237151666 ps
CPU time 76.36 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:53:40 PM PDT 24
Peak memory 234892 kb
Host smart-177d0772-2512-4dfc-9a51-04c383ec10af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581683651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1581683651
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.434660880
Short name T892
Test name
Test status
Simulation time 168278278 ps
CPU time 3.18 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 233456 kb
Host smart-f6833ce5-89f9-4762-b5a5-8d020f069502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434660880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.434660880
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2167825460
Short name T169
Test name
Test status
Simulation time 976595228 ps
CPU time 8.2 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 240568 kb
Host smart-ea1f744d-d07c-4670-99ad-946793d83921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167825460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2167825460
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1346074563
Short name T429
Test name
Test status
Simulation time 384943906 ps
CPU time 6.81 seconds
Started May 19 12:52:24 PM PDT 24
Finished May 19 12:52:37 PM PDT 24
Peak memory 221208 kb
Host smart-41f02daa-547f-4be9-a9d3-2d77eb1b820a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1346074563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1346074563
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4065838849
Short name T889
Test name
Test status
Simulation time 5789696855 ps
CPU time 35.79 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 240676 kb
Host smart-b1024c12-9f75-47a6-8b54-9fdf32e37bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065838849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4065838849
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1835491762
Short name T325
Test name
Test status
Simulation time 6731396702 ps
CPU time 17.72 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 216112 kb
Host smart-26a611f1-c28c-47b7-a227-6a7b60d314c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835491762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1835491762
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2744733246
Short name T919
Test name
Test status
Simulation time 9835997866 ps
CPU time 14.03 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 216032 kb
Host smart-243337b9-2eb7-4654-bf01-537ed32acd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744733246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2744733246
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.825575879
Short name T832
Test name
Test status
Simulation time 948812271 ps
CPU time 8.57 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 215936 kb
Host smart-250f600d-125e-4d64-b692-0c9e76074953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825575879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.825575879
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1543534226
Short name T913
Test name
Test status
Simulation time 125375228 ps
CPU time 0.81 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:52:22 PM PDT 24
Peak memory 205492 kb
Host smart-2db5751b-4dca-43ec-9d6d-7dc64cbb9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543534226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1543534226
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.858878686
Short name T905
Test name
Test status
Simulation time 7264176935 ps
CPU time 13.24 seconds
Started May 19 12:52:32 PM PDT 24
Finished May 19 12:52:49 PM PDT 24
Peak memory 218360 kb
Host smart-102b8cb0-0c4b-47bc-87f8-2f389651dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858878686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.858878686
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.703715550
Short name T689
Test name
Test status
Simulation time 11422191 ps
CPU time 0.69 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 205496 kb
Host smart-cb7af669-c7e2-484f-b485-eb6e2a62d7f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703715550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.703715550
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1027604824
Short name T812
Test name
Test status
Simulation time 2695738432 ps
CPU time 7.47 seconds
Started May 19 12:52:15 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 220344 kb
Host smart-55217438-f7a8-4820-9296-686de6c39968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027604824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1027604824
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2964035774
Short name T795
Test name
Test status
Simulation time 17296470 ps
CPU time 0.81 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:28 PM PDT 24
Peak memory 206260 kb
Host smart-b36939b1-906f-4b48-910e-bf475ccbda1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964035774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2964035774
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3404692142
Short name T299
Test name
Test status
Simulation time 75429140359 ps
CPU time 531.53 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 01:01:08 PM PDT 24
Peak memory 250196 kb
Host smart-96c816ab-341d-49bf-a72e-71e03153ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404692142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3404692142
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.911234441
Short name T21
Test name
Test status
Simulation time 7773238623 ps
CPU time 99.83 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:54:12 PM PDT 24
Peak memory 247332 kb
Host smart-38728367-7b9d-4be0-ab5b-7bcebbc0948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911234441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.911234441
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2559494944
Short name T194
Test name
Test status
Simulation time 15886933567 ps
CPU time 121.51 seconds
Started May 19 12:52:09 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 240848 kb
Host smart-37a46f37-ee2a-45fe-8445-e2c19ec05e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559494944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2559494944
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1081764437
Short name T315
Test name
Test status
Simulation time 2213049796 ps
CPU time 13.49 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 232548 kb
Host smart-d03cc748-fa3e-4d77-be5b-0b669080f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081764437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1081764437
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.670507139
Short name T474
Test name
Test status
Simulation time 271966326 ps
CPU time 3 seconds
Started May 19 12:52:13 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 233992 kb
Host smart-684c41da-a62a-45ad-93bf-62715a680ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670507139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.670507139
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1991776854
Short name T157
Test name
Test status
Simulation time 3579539797 ps
CPU time 20.94 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:54 PM PDT 24
Peak memory 238308 kb
Host smart-fd719b14-cf90-4b72-b40c-3ad0f116657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991776854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1991776854
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1167551826
Short name T571
Test name
Test status
Simulation time 4266114173 ps
CPU time 10.6 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 238812 kb
Host smart-3bd1a14a-d944-44ab-b185-3cd8284b9768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167551826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1167551826
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.922214688
Short name T159
Test name
Test status
Simulation time 45947739626 ps
CPU time 18.19 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:44 PM PDT 24
Peak memory 219308 kb
Host smart-453258c3-5a7a-42a0-90ae-857c3e1c1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922214688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.922214688
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4090410389
Short name T363
Test name
Test status
Simulation time 794975854 ps
CPU time 4.46 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 222488 kb
Host smart-ac1cdffc-fd5f-4b3c-a9fa-a97f78ee950c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4090410389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4090410389
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.570618873
Short name T748
Test name
Test status
Simulation time 22500086874 ps
CPU time 26.91 seconds
Started May 19 12:52:15 PM PDT 24
Finished May 19 12:52:46 PM PDT 24
Peak memory 216128 kb
Host smart-2ed94dfb-5f95-44d3-92e5-86d91ae51a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570618873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.570618873
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3449467558
Short name T557
Test name
Test status
Simulation time 3058178787 ps
CPU time 8.35 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 215928 kb
Host smart-47a0d173-2258-44ad-aa78-b0bdd0d77533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449467558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3449467558
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2879484496
Short name T126
Test name
Test status
Simulation time 383779548 ps
CPU time 5.06 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 215952 kb
Host smart-6bf24225-ea3a-4c0a-9bce-e9cf8d27b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879484496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2879484496
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1767802627
Short name T427
Test name
Test status
Simulation time 108364822 ps
CPU time 0.78 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 205516 kb
Host smart-471fadbc-6487-426e-bec5-0dbab8f7c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767802627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1767802627
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.436024205
Short name T416
Test name
Test status
Simulation time 17561245418 ps
CPU time 20.65 seconds
Started May 19 12:52:36 PM PDT 24
Finished May 19 12:52:59 PM PDT 24
Peak memory 234792 kb
Host smart-051f8d0f-b8ec-45bf-9996-beb405bd9633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436024205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.436024205
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1502194345
Short name T743
Test name
Test status
Simulation time 14662773 ps
CPU time 0.74 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:16 PM PDT 24
Peak memory 205504 kb
Host smart-05ff6475-e010-4de0-9502-4eb588d39590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502194345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1502194345
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.13224142
Short name T568
Test name
Test status
Simulation time 131267951 ps
CPU time 2.49 seconds
Started May 19 12:52:31 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 218232 kb
Host smart-8ccd1d2c-5a51-4b4b-8715-f331edcadd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13224142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.13224142
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3507485695
Short name T500
Test name
Test status
Simulation time 41474195 ps
CPU time 0.79 seconds
Started May 19 12:52:10 PM PDT 24
Finished May 19 12:52:15 PM PDT 24
Peak memory 206264 kb
Host smart-eea2b955-badb-47e7-a11e-f60f55ff3bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507485695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3507485695
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3115161322
Short name T792
Test name
Test status
Simulation time 4732043803 ps
CPU time 48.34 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 248956 kb
Host smart-5b8eaafb-657b-4892-a31d-488a11a8c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115161322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3115161322
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2767244013
Short name T742
Test name
Test status
Simulation time 617540734 ps
CPU time 8.08 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 233472 kb
Host smart-fff7c8e1-df8c-4fe6-8227-8844b93f3dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767244013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2767244013
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1641358858
Short name T826
Test name
Test status
Simulation time 1045883130 ps
CPU time 7.9 seconds
Started May 19 12:52:15 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 232372 kb
Host smart-0257ec2a-1634-45e4-833c-708281c93f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641358858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1641358858
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3356769757
Short name T782
Test name
Test status
Simulation time 2213013130 ps
CPU time 27.53 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:52:47 PM PDT 24
Peak memory 233824 kb
Host smart-67191798-20ad-4ba9-8240-07bb67ece902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356769757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3356769757
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3025411433
Short name T278
Test name
Test status
Simulation time 762290978 ps
CPU time 4.77 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 218476 kb
Host smart-3f81a840-c59c-4651-831a-ef3e0d6440f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025411433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3025411433
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2981467835
Short name T283
Test name
Test status
Simulation time 813839950 ps
CPU time 2.87 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 232388 kb
Host smart-313b9e3e-b96b-418a-a02a-7910bdbcc9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981467835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2981467835
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2446176974
Short name T140
Test name
Test status
Simulation time 473808407 ps
CPU time 3.83 seconds
Started May 19 12:52:24 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 219116 kb
Host smart-9605f8b9-12fe-4e6a-b058-b2d5e6928cb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2446176974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2446176974
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1644384401
Short name T481
Test name
Test status
Simulation time 3008970378 ps
CPU time 26.46 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:51 PM PDT 24
Peak memory 216304 kb
Host smart-886ebd9d-b2cd-4045-bb81-fbb0cb9d28ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644384401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1644384401
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2166332926
Short name T324
Test name
Test status
Simulation time 405200569 ps
CPU time 1.96 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 206708 kb
Host smart-b27f128a-73ba-4bcb-afa4-48744ba3cf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166332926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2166332926
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2819593010
Short name T465
Test name
Test status
Simulation time 161616826 ps
CPU time 1.11 seconds
Started May 19 12:52:32 PM PDT 24
Finished May 19 12:52:37 PM PDT 24
Peak memory 215844 kb
Host smart-046a2b8f-7270-43bb-91f7-6b55771eeea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819593010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2819593010
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3223977432
Short name T694
Test name
Test status
Simulation time 121773205 ps
CPU time 0.93 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 205952 kb
Host smart-d241f2bc-8f5b-4202-9013-85844214eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223977432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3223977432
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2025940818
Short name T703
Test name
Test status
Simulation time 1492557813 ps
CPU time 4.37 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:29 PM PDT 24
Peak memory 224344 kb
Host smart-3f1b552e-7fed-4278-8bc5-8d5ebc831036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025940818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2025940818
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3049398925
Short name T776
Test name
Test status
Simulation time 36446142 ps
CPU time 0.69 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 205148 kb
Host smart-bfdbc841-d2bd-462b-ade5-c901131d2ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049398925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
049398925
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.131727638
Short name T431
Test name
Test status
Simulation time 7632742352 ps
CPU time 18.04 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:51:47 PM PDT 24
Peak memory 234312 kb
Host smart-7c1954e3-1962-48a7-9d68-2c059555e39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131727638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.131727638
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.804939272
Short name T718
Test name
Test status
Simulation time 206067729 ps
CPU time 0.8 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:22 PM PDT 24
Peak memory 206664 kb
Host smart-81f198b4-dda5-4cd2-afee-8348b4e3e85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804939272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.804939272
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.648965161
Short name T192
Test name
Test status
Simulation time 37830815001 ps
CPU time 124 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 251632 kb
Host smart-bb49a151-d0ae-4b1b-a05e-b8c8ca1df9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648965161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.648965161
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.357783223
Short name T894
Test name
Test status
Simulation time 9596321872 ps
CPU time 47.96 seconds
Started May 19 12:51:21 PM PDT 24
Finished May 19 12:52:13 PM PDT 24
Peak memory 217040 kb
Host smart-602616a8-45ef-4769-a9e6-c80454795243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357783223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.357783223
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4109648017
Short name T293
Test name
Test status
Simulation time 12103339863 ps
CPU time 192.84 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 263808 kb
Host smart-c1239d5b-d3fe-4e08-93e0-2c7efb5b345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109648017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4109648017
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2748978927
Short name T924
Test name
Test status
Simulation time 223561593 ps
CPU time 2.79 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 232528 kb
Host smart-41f61245-b055-4e09-bbc3-8a870da285d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748978927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2748978927
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1056981402
Short name T668
Test name
Test status
Simulation time 4028736539 ps
CPU time 7.13 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 235120 kb
Host smart-b59c41d9-5ec4-4460-b32a-4139d8fe4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056981402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1056981402
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2065922472
Short name T780
Test name
Test status
Simulation time 2569091768 ps
CPU time 31.14 seconds
Started May 19 12:51:23 PM PDT 24
Finished May 19 12:51:59 PM PDT 24
Peak memory 239776 kb
Host smart-8c25df32-45c4-41fc-b289-6652b33ca300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065922472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2065922472
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1151938566
Short name T266
Test name
Test status
Simulation time 11012712997 ps
CPU time 16.59 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:35 PM PDT 24
Peak memory 233528 kb
Host smart-ba340993-28f4-47f6-9570-5c2f9fa6a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151938566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1151938566
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4208696174
Short name T773
Test name
Test status
Simulation time 1220033545 ps
CPU time 6.25 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:28 PM PDT 24
Peak memory 232796 kb
Host smart-14fe84fc-d77c-43cd-bea2-d856cfc9f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208696174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4208696174
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.900553666
Short name T604
Test name
Test status
Simulation time 229249988 ps
CPU time 3.93 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:26 PM PDT 24
Peak memory 222632 kb
Host smart-8ad10a78-b22b-4fb9-94db-6712922b23fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=900553666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.900553666
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3023092507
Short name T61
Test name
Test status
Simulation time 319364575 ps
CPU time 1.2 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:24 PM PDT 24
Peak memory 234536 kb
Host smart-6a7eae6a-3c88-4569-8ae7-062df13254b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023092507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3023092507
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2640409398
Short name T865
Test name
Test status
Simulation time 7023399521 ps
CPU time 30.97 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:53 PM PDT 24
Peak memory 216396 kb
Host smart-17907190-47ef-4bd8-be6f-78283b7be06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640409398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2640409398
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.12941166
Short name T477
Test name
Test status
Simulation time 4994144205 ps
CPU time 17.57 seconds
Started May 19 12:51:23 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 216080 kb
Host smart-f3386bae-87ec-4fe1-969d-afaa9590ba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12941166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.12941166
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1829476952
Short name T767
Test name
Test status
Simulation time 71194161 ps
CPU time 1.15 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:22 PM PDT 24
Peak memory 207716 kb
Host smart-bdfdfc58-bd11-40db-987b-e6ce23053623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829476952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1829476952
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3100368115
Short name T432
Test name
Test status
Simulation time 114821679 ps
CPU time 0.71 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 205516 kb
Host smart-ebef5c6a-b419-4362-939a-d2a07b043f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100368115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3100368115
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2814590422
Short name T233
Test name
Test status
Simulation time 399314427 ps
CPU time 3.1 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:21 PM PDT 24
Peak memory 218504 kb
Host smart-4a1b50cd-5eec-4514-97aa-7e3d7c3ebe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814590422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2814590422
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2355413395
Short name T756
Test name
Test status
Simulation time 12533296 ps
CPU time 0.71 seconds
Started May 19 12:52:16 PM PDT 24
Finished May 19 12:52:21 PM PDT 24
Peak memory 205160 kb
Host smart-dcb2d15c-19d9-4249-8c24-645a3e072e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355413395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2355413395
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1238131802
Short name T441
Test name
Test status
Simulation time 913396556 ps
CPU time 3.69 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:20 PM PDT 24
Peak memory 233812 kb
Host smart-4796e189-0331-4d70-a78e-c19e94f7d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238131802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1238131802
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2072800152
Short name T394
Test name
Test status
Simulation time 19865290 ps
CPU time 0.75 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:17 PM PDT 24
Peak memory 206664 kb
Host smart-d1dfb72d-750a-47b3-8d85-ebc2459c2f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072800152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2072800152
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.742783
Short name T3
Test name
Test status
Simulation time 8470269275 ps
CPU time 64.58 seconds
Started May 19 12:52:15 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 256048 kb
Host smart-d454b669-3558-41c9-b84f-1f907bd2fe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.742783
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.205913428
Short name T600
Test name
Test status
Simulation time 2486782448 ps
CPU time 28.3 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:53:00 PM PDT 24
Peak memory 221784 kb
Host smart-65db6671-6743-40d0-94c0-d0d26fd36349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205913428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.205913428
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3027818872
Short name T390
Test name
Test status
Simulation time 19932919864 ps
CPU time 73.86 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:53:38 PM PDT 24
Peak memory 255772 kb
Host smart-5c9a1582-509d-45eb-98b2-87f39d3bd451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027818872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3027818872
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2829270111
Short name T754
Test name
Test status
Simulation time 435064616 ps
CPU time 6.11 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:37 PM PDT 24
Peak memory 248904 kb
Host smart-74de87c1-a366-4333-ab68-d65c2573c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829270111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2829270111
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3212482034
Short name T216
Test name
Test status
Simulation time 261182359 ps
CPU time 2.57 seconds
Started May 19 12:52:24 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 232868 kb
Host smart-0a2940cb-5a47-4152-9ddb-16aa11f940cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212482034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3212482034
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2258581594
Short name T858
Test name
Test status
Simulation time 330732057 ps
CPU time 5.54 seconds
Started May 19 12:52:32 PM PDT 24
Finished May 19 12:52:42 PM PDT 24
Peak memory 219372 kb
Host smart-3d478a32-56e3-4da7-8680-d6693031de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258581594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2258581594
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1644539893
Short name T292
Test name
Test status
Simulation time 3986236360 ps
CPU time 14.95 seconds
Started May 19 12:52:11 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 233192 kb
Host smart-19bfc2f8-e598-4263-92d7-014fcf1c5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644539893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1644539893
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1508049835
Short name T128
Test name
Test status
Simulation time 3506217308 ps
CPU time 12.13 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:40 PM PDT 24
Peak memory 218348 kb
Host smart-9bdc7760-9fa3-47ae-a5f9-5516dec4dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508049835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1508049835
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3754982735
Short name T143
Test name
Test status
Simulation time 430923511 ps
CPU time 3.78 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 222612 kb
Host smart-39d2df4b-5676-4535-9c8c-753d39ab13da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754982735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3754982735
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1927120909
Short name T621
Test name
Test status
Simulation time 8547693507 ps
CPU time 53.38 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:53:26 PM PDT 24
Peak memory 250120 kb
Host smart-4c8c567c-fbbb-4b3e-b7f5-9851a91f5e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927120909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1927120909
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4032018788
Short name T161
Test name
Test status
Simulation time 4580300251 ps
CPU time 17.19 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 216100 kb
Host smart-8fdbe67b-cda4-4a16-b86a-6bdc9b6fb860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032018788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4032018788
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1218895709
Short name T645
Test name
Test status
Simulation time 4617331371 ps
CPU time 5.23 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 216084 kb
Host smart-7ab3a170-f6df-4ce3-9f24-d37da936015f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218895709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1218895709
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.874459574
Short name T179
Test name
Test status
Simulation time 301537809 ps
CPU time 3.11 seconds
Started May 19 12:52:12 PM PDT 24
Finished May 19 12:52:19 PM PDT 24
Peak memory 216164 kb
Host smart-a92ea3f7-6bef-44c3-be97-55ce23ac0644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874459574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.874459574
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.775731964
Short name T625
Test name
Test status
Simulation time 25095801 ps
CPU time 0.68 seconds
Started May 19 12:52:40 PM PDT 24
Finished May 19 12:52:41 PM PDT 24
Peak memory 205296 kb
Host smart-fca42215-89fb-4582-9706-84af9a3ad376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775731964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.775731964
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3121805293
Short name T627
Test name
Test status
Simulation time 108379053 ps
CPU time 3.46 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:52:27 PM PDT 24
Peak memory 233116 kb
Host smart-b001171e-9a5a-41c8-8ae0-c36723ffca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121805293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3121805293
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.993020440
Short name T52
Test name
Test status
Simulation time 12515093 ps
CPU time 0.7 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:28 PM PDT 24
Peak memory 204660 kb
Host smart-2b11d99c-ee39-4643-b04b-f0caf4c25406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993020440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.993020440
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3153911328
Short name T252
Test name
Test status
Simulation time 232800894 ps
CPU time 2.55 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 218632 kb
Host smart-c9411621-47c5-41cc-8dfb-3ac54055829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153911328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3153911328
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1928906367
Short name T751
Test name
Test status
Simulation time 36595241 ps
CPU time 0.76 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 205220 kb
Host smart-c733f46a-1d0b-4f91-90ab-c4f7b3f02561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928906367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1928906367
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2760094557
Short name T279
Test name
Test status
Simulation time 439937722 ps
CPU time 10.64 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 224304 kb
Host smart-9034c9bf-759e-4fa5-a14c-09916b63aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760094557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2760094557
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3817908573
Short name T267
Test name
Test status
Simulation time 6176459506 ps
CPU time 102.8 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 250440 kb
Host smart-6ab966e4-d887-4c1d-b48a-41430aad3b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817908573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3817908573
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.604522240
Short name T467
Test name
Test status
Simulation time 221124588 ps
CPU time 6.64 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 232340 kb
Host smart-db7a658e-1f9f-4958-8b6c-378d438e1fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604522240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.604522240
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.577525205
Short name T666
Test name
Test status
Simulation time 1563763513 ps
CPU time 8.05 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:52:45 PM PDT 24
Peak memory 223508 kb
Host smart-97f1185f-d36a-46d5-932e-1889a27eeba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577525205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.577525205
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2699051309
Short name T534
Test name
Test status
Simulation time 18642392962 ps
CPU time 33.25 seconds
Started May 19 12:52:40 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 234404 kb
Host smart-3a94fefd-c33f-4de1-852e-a81572293929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699051309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2699051309
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.951723675
Short name T163
Test name
Test status
Simulation time 1142526395 ps
CPU time 6.91 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:52:30 PM PDT 24
Peak memory 240140 kb
Host smart-55690086-7b73-4c53-9812-e7f60aad8428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951723675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.951723675
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2946782457
Short name T921
Test name
Test status
Simulation time 1694168725 ps
CPU time 9.28 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 219728 kb
Host smart-7dc7d4ca-3917-437c-a0b9-b9262908bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946782457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2946782457
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1321807941
Short name T413
Test name
Test status
Simulation time 329949358 ps
CPU time 4.25 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 222152 kb
Host smart-bb03bcfc-7eba-469a-ba6b-96f7f6375f5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1321807941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1321807941
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2767606859
Short name T152
Test name
Test status
Simulation time 73492793282 ps
CPU time 560.56 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 01:01:52 PM PDT 24
Peak memory 265440 kb
Host smart-2b8353ad-8422-41c3-8e2a-048eec10583a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767606859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2767606859
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4140244389
Short name T899
Test name
Test status
Simulation time 2956107422 ps
CPU time 15.77 seconds
Started May 19 12:52:17 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 216436 kb
Host smart-ed774f95-1e80-4dd1-93df-5cf80a0d3cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140244389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4140244389
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.450985418
Short name T783
Test name
Test status
Simulation time 745729214 ps
CPU time 4.52 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:52:28 PM PDT 24
Peak memory 215960 kb
Host smart-b323f12b-9e9e-4258-ac02-94b1b3339bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450985418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.450985418
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3712838037
Short name T418
Test name
Test status
Simulation time 58829754 ps
CPU time 1.29 seconds
Started May 19 12:52:28 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 215944 kb
Host smart-2391f2f0-e8b7-433e-a0bf-a7a70ddced0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712838037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3712838037
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3821342855
Short name T401
Test name
Test status
Simulation time 50792562 ps
CPU time 0.77 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 205956 kb
Host smart-0bbc581f-fa4e-490b-ac9e-965633f2bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821342855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3821342855
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.279695415
Short name T705
Test name
Test status
Simulation time 675357521 ps
CPU time 3.2 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 232496 kb
Host smart-3073c48f-8234-4254-af8f-ebcd8ebec1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279695415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.279695415
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.465270551
Short name T903
Test name
Test status
Simulation time 59275547 ps
CPU time 0.72 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 205048 kb
Host smart-a0ac144f-5d91-47c9-88fe-aec6042fa4f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465270551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.465270551
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.804381944
Short name T829
Test name
Test status
Simulation time 5565488212 ps
CPU time 7.52 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 218532 kb
Host smart-60d4afe4-a451-4023-9a41-38fab4f8cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804381944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.804381944
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2811135874
Short name T535
Test name
Test status
Simulation time 39429074 ps
CPU time 0.79 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 206260 kb
Host smart-41d702fb-a051-423e-bdb5-c86972ba4e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811135874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2811135874
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.645897772
Short name T700
Test name
Test status
Simulation time 2052625461 ps
CPU time 41.75 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 240472 kb
Host smart-375fce7b-8a7b-4d1a-8642-52381b507e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645897772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.645897772
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2423375434
Short name T443
Test name
Test status
Simulation time 136943392305 ps
CPU time 251.26 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:56:38 PM PDT 24
Peak memory 240760 kb
Host smart-9a0755a6-bef0-487a-b851-d365a4e619e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423375434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2423375434
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3336945864
Short name T135
Test name
Test status
Simulation time 6123174177 ps
CPU time 120.61 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 255364 kb
Host smart-cc2cebf6-e49b-45dd-b672-99420ed99ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336945864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3336945864
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3334051282
Short name T399
Test name
Test status
Simulation time 32483844 ps
CPU time 2.55 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:30 PM PDT 24
Peak memory 232464 kb
Host smart-a10fd5e9-bb1b-41d2-82b4-a29ae1f5a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334051282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3334051282
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4261845540
Short name T691
Test name
Test status
Simulation time 5688860907 ps
CPU time 16.93 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 219628 kb
Host smart-d8eae5f0-d6c0-41d8-bf20-00c5152627d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261845540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4261845540
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1549565560
Short name T847
Test name
Test status
Simulation time 77329349 ps
CPU time 2.82 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 233496 kb
Host smart-8ecc9a43-75c2-4083-bf9d-a8ec5fe956a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549565560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1549565560
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.597506524
Short name T875
Test name
Test status
Simulation time 45437876910 ps
CPU time 30.7 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 228428 kb
Host smart-e9db697c-b05b-4559-b551-fac15d060e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597506524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.597506524
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3852243695
Short name T125
Test name
Test status
Simulation time 554608838 ps
CPU time 5.67 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 226840 kb
Host smart-119384d8-a23d-458f-ab6d-357cc20b49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852243695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3852243695
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1758730554
Short name T436
Test name
Test status
Simulation time 602304063 ps
CPU time 6.02 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 220180 kb
Host smart-9175b6f6-a741-4682-be7d-6e9be36d1ebf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1758730554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1758730554
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3920861892
Short name T153
Test name
Test status
Simulation time 5188581844 ps
CPU time 34.87 seconds
Started May 19 12:52:24 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 237644 kb
Host smart-f26cadaf-78df-4698-8201-ea19a27bd044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920861892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3920861892
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3161740681
Short name T653
Test name
Test status
Simulation time 37969439 ps
CPU time 0.68 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:29 PM PDT 24
Peak memory 205792 kb
Host smart-04174e4c-cc74-4344-8416-0a3e11eb01ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161740681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3161740681
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2290914316
Short name T491
Test name
Test status
Simulation time 28462077358 ps
CPU time 13.31 seconds
Started May 19 12:52:19 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 216116 kb
Host smart-987d8464-6b88-4d4a-9ff0-f55eee85f784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290914316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2290914316
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.93267140
Short name T340
Test name
Test status
Simulation time 19353330 ps
CPU time 0.95 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 206724 kb
Host smart-81ccb5b3-b24b-4c1a-a4b1-f107f39d5d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93267140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.93267140
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3745083305
Short name T580
Test name
Test status
Simulation time 166490841 ps
CPU time 0.92 seconds
Started May 19 12:52:23 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 205612 kb
Host smart-9ab1f8a1-3d1c-4012-9c59-efb39e2d90c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745083305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3745083305
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3349767790
Short name T530
Test name
Test status
Simulation time 10631498303 ps
CPU time 8.53 seconds
Started May 19 12:52:18 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 219764 kb
Host smart-d6724fbd-c1e3-4982-abaa-0b9c4af9e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349767790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3349767790
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.384769558
Short name T494
Test name
Test status
Simulation time 120523780 ps
CPU time 0.71 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:29 PM PDT 24
Peak memory 205236 kb
Host smart-e9067ae2-9557-47ef-ab27-d8279b086c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384769558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.384769558
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.993513609
Short name T524
Test name
Test status
Simulation time 2088973034 ps
CPU time 5.89 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 218480 kb
Host smart-ebddec83-84e0-429d-b327-245b0b9a5d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993513609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.993513609
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.897699661
Short name T422
Test name
Test status
Simulation time 19994386 ps
CPU time 0.81 seconds
Started May 19 12:52:23 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 206400 kb
Host smart-ac9146ca-cc65-42b2-96ec-5ad7558b62b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897699661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.897699661
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1560033638
Short name T165
Test name
Test status
Simulation time 8307910107 ps
CPU time 61 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:53:38 PM PDT 24
Peak memory 248268 kb
Host smart-6b22d357-9279-4656-aa6a-bd9921e3298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560033638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1560033638
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1546111720
Short name T461
Test name
Test status
Simulation time 27674661195 ps
CPU time 52.53 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:53:42 PM PDT 24
Peak memory 240812 kb
Host smart-a41779b3-eee8-479c-91b6-86cc8695abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546111720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1546111720
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2918453462
Short name T587
Test name
Test status
Simulation time 26961548047 ps
CPU time 282.53 seconds
Started May 19 12:52:21 PM PDT 24
Finished May 19 12:57:10 PM PDT 24
Peak memory 266644 kb
Host smart-ca11236d-76dd-40a4-bebd-661a146cc572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918453462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2918453462
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.744543851
Short name T319
Test name
Test status
Simulation time 699670557 ps
CPU time 8.89 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:41 PM PDT 24
Peak memory 232436 kb
Host smart-8dfe18ad-b680-4508-9173-95a4af7a01bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744543851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.744543851
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1615849633
Short name T356
Test name
Test status
Simulation time 57384060 ps
CPU time 1.96 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 215808 kb
Host smart-d5cf19bf-a538-4a6e-905f-395a1194a9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615849633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1615849633
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1024477033
Short name T948
Test name
Test status
Simulation time 5425344993 ps
CPU time 15.37 seconds
Started May 19 12:52:32 PM PDT 24
Finished May 19 12:52:52 PM PDT 24
Peak memory 239748 kb
Host smart-7672c383-1bf7-4d04-8374-978dbfd4130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024477033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1024477033
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.512019292
Short name T503
Test name
Test status
Simulation time 1781210814 ps
CPU time 10.54 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:42 PM PDT 24
Peak memory 236560 kb
Host smart-ec6202db-d99e-48ba-b6e1-14e88e9cfbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512019292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.512019292
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2137149108
Short name T881
Test name
Test status
Simulation time 7433013945 ps
CPU time 12.88 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:46 PM PDT 24
Peak memory 217856 kb
Host smart-222c9ebe-489e-4a1c-8fcb-c20e201ca386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137149108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2137149108
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.886589917
Short name T42
Test name
Test status
Simulation time 293928616 ps
CPU time 5.72 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:52:34 PM PDT 24
Peak memory 218932 kb
Host smart-eb3d7a59-8585-4c43-a560-0767e379900c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886589917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.886589917
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.839786238
Short name T303
Test name
Test status
Simulation time 24569757142 ps
CPU time 240.5 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:56:31 PM PDT 24
Peak memory 272592 kb
Host smart-863e0c19-d1db-4ec7-ab5d-f3006dcf864d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839786238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.839786238
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1772250383
Short name T376
Test name
Test status
Simulation time 1862435081 ps
CPU time 6.32 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 216120 kb
Host smart-6558fdb6-59ec-4fc2-8a1c-e9a5de9ef448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772250383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1772250383
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1201850934
Short name T687
Test name
Test status
Simulation time 1989805001 ps
CPU time 3.74 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 215884 kb
Host smart-fab71ac2-264c-4aa0-a086-08ab2b8d9c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201850934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1201850934
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2952836527
Short name T872
Test name
Test status
Simulation time 335033989 ps
CPU time 3.01 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 216152 kb
Host smart-f3bb322e-80bf-4464-9dc1-7d6d176f8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952836527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2952836527
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1071726982
Short name T381
Test name
Test status
Simulation time 16707854 ps
CPU time 0.73 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 205584 kb
Host smart-b6699a90-c5ba-45d6-a735-d681d2db4973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071726982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1071726982
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.546396346
Short name T596
Test name
Test status
Simulation time 966192211 ps
CPU time 6.77 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 233536 kb
Host smart-bf55f1df-02ef-49a6-b6ad-30f44ec1590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546396346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.546396346
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.991924869
Short name T415
Test name
Test status
Simulation time 32230010 ps
CPU time 0.73 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 204660 kb
Host smart-feb5dbcf-2b06-4c7f-939c-9ba51950d559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991924869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.991924869
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4125335639
Short name T877
Test name
Test status
Simulation time 552019237 ps
CPU time 5.89 seconds
Started May 19 12:52:23 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 218284 kb
Host smart-a2452cc4-3f88-4e0b-910f-8cccd6982cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125335639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4125335639
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.771798563
Short name T445
Test name
Test status
Simulation time 25108579 ps
CPU time 0.74 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 205548 kb
Host smart-1be65850-cf1b-4a72-a0dc-18dbcf1ac10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771798563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.771798563
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3966881117
Short name T581
Test name
Test status
Simulation time 4554537716 ps
CPU time 62.78 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 253572 kb
Host smart-c4697f1a-adc8-46ad-b8ba-661d2a53d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966881117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3966881117
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2982210056
Short name T927
Test name
Test status
Simulation time 7337488797 ps
CPU time 58.69 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 240792 kb
Host smart-97fe6345-8eed-4caa-836f-f8cffd886387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982210056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2982210056
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.301601662
Short name T265
Test name
Test status
Simulation time 25339554246 ps
CPU time 66.98 seconds
Started May 19 12:52:32 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 236840 kb
Host smart-29d137a7-1a4f-4a4f-9def-4b7eef6d3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301601662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.301601662
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4077449692
Short name T110
Test name
Test status
Simulation time 616698850 ps
CPU time 18.32 seconds
Started May 19 12:52:20 PM PDT 24
Finished May 19 12:52:45 PM PDT 24
Peak memory 237252 kb
Host smart-950450f7-bd14-4a6f-89bb-c80e44c36e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077449692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4077449692
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2160637850
Short name T766
Test name
Test status
Simulation time 2149576789 ps
CPU time 19.97 seconds
Started May 19 12:52:28 PM PDT 24
Finished May 19 12:52:54 PM PDT 24
Peak memory 219672 kb
Host smart-f8d315f8-abcd-408f-91db-9948655763a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160637850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2160637850
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4216634839
Short name T805
Test name
Test status
Simulation time 10455728124 ps
CPU time 102.78 seconds
Started May 19 12:52:22 PM PDT 24
Finished May 19 12:54:11 PM PDT 24
Peak memory 247924 kb
Host smart-7fd258d8-1830-4478-a289-fa78a0c67525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216634839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4216634839
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4229095243
Short name T685
Test name
Test status
Simulation time 3006803394 ps
CPU time 20.07 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:52 PM PDT 24
Peak memory 244980 kb
Host smart-1d56894a-0f44-4c4d-bf15-418c3a73350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229095243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4229095243
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.302031434
Short name T878
Test name
Test status
Simulation time 595477623 ps
CPU time 3.97 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 218452 kb
Host smart-2afad6ad-0af5-47f6-9d2b-b5419153342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302031434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.302031434
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1256692366
Short name T592
Test name
Test status
Simulation time 1239879008 ps
CPU time 6.21 seconds
Started May 19 12:52:28 PM PDT 24
Finished May 19 12:52:39 PM PDT 24
Peak memory 222704 kb
Host smart-398d4a40-9aeb-4ee6-961d-b60117e7db27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1256692366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1256692366
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1194699026
Short name T734
Test name
Test status
Simulation time 15965660185 ps
CPU time 49.19 seconds
Started May 19 12:52:36 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 216076 kb
Host smart-beec2566-5914-4a41-8daf-5e2dee1c0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194699026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1194699026
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.373762981
Short name T485
Test name
Test status
Simulation time 944607074 ps
CPU time 1.88 seconds
Started May 19 12:52:32 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 208024 kb
Host smart-70e2a678-f320-4131-b6fc-ef6c3b9c6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373762981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.373762981
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2397131095
Short name T663
Test name
Test status
Simulation time 138526104 ps
CPU time 2.36 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:35 PM PDT 24
Peak memory 216468 kb
Host smart-e03839c9-d7e9-4ded-a50d-75d9efb3d68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397131095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2397131095
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1357922709
Short name T515
Test name
Test status
Simulation time 242412760 ps
CPU time 0.91 seconds
Started May 19 12:52:25 PM PDT 24
Finished May 19 12:52:32 PM PDT 24
Peak memory 205448 kb
Host smart-7eb5e7fe-7e86-4262-bff8-5b1dd785f832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357922709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1357922709
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2603482747
Short name T828
Test name
Test status
Simulation time 42965446908 ps
CPU time 13.02 seconds
Started May 19 12:52:23 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 222536 kb
Host smart-e0bf5f93-d81b-463c-9fb3-c9501fe4821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603482747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2603482747
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3381954357
Short name T552
Test name
Test status
Simulation time 20908975 ps
CPU time 0.71 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:52:44 PM PDT 24
Peak memory 204648 kb
Host smart-5ac3ed1b-272a-432b-8c7d-5a452f45059a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381954357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3381954357
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2268259796
Short name T765
Test name
Test status
Simulation time 2164787962 ps
CPU time 14.11 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:53:02 PM PDT 24
Peak memory 219540 kb
Host smart-3cc9eeb7-563d-4c01-9cd0-db89845361d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268259796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2268259796
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1426079514
Short name T908
Test name
Test status
Simulation time 83350858 ps
CPU time 0.81 seconds
Started May 19 12:52:23 PM PDT 24
Finished May 19 12:52:31 PM PDT 24
Peak memory 206244 kb
Host smart-57252a18-cddf-4218-a297-be6f7bb1d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426079514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1426079514
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.643407261
Short name T45
Test name
Test status
Simulation time 15866489101 ps
CPU time 112.59 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 232828 kb
Host smart-993799fe-8864-42cb-814f-0583fc6c2fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643407261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.643407261
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2608238770
Short name T682
Test name
Test status
Simulation time 44734073912 ps
CPU time 61.79 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:53:45 PM PDT 24
Peak memory 257212 kb
Host smart-14e3cdd8-6e22-43fb-b42c-b25c9107874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608238770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2608238770
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3810516514
Short name T1
Test name
Test status
Simulation time 17477137339 ps
CPU time 65.24 seconds
Started May 19 12:52:39 PM PDT 24
Finished May 19 12:53:45 PM PDT 24
Peak memory 249332 kb
Host smart-ffea4d8e-6051-4273-9cd5-9a0a9e24d3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810516514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3810516514
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1437266189
Short name T130
Test name
Test status
Simulation time 4619832464 ps
CPU time 12.98 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:52:57 PM PDT 24
Peak memory 236532 kb
Host smart-478e1133-af39-40e8-a277-aeecc3de6c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437266189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1437266189
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3666498504
Short name T768
Test name
Test status
Simulation time 104345621 ps
CPU time 3.59 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 218172 kb
Host smart-3567382e-5cb8-4a5d-a9c7-9338f9598a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666498504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3666498504
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1842010972
Short name T636
Test name
Test status
Simulation time 2747381053 ps
CPU time 10.92 seconds
Started May 19 12:52:41 PM PDT 24
Finished May 19 12:52:53 PM PDT 24
Peak memory 234664 kb
Host smart-16f84286-b4dc-44e3-b1b5-c10bf9dc0818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842010972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1842010972
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1528900204
Short name T201
Test name
Test status
Simulation time 15476221399 ps
CPU time 23.77 seconds
Started May 19 12:52:45 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 232024 kb
Host smart-7d078ae2-4683-4431-8e43-ab0c220eb113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528900204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1528900204
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3023032383
Short name T362
Test name
Test status
Simulation time 4868348292 ps
CPU time 14.21 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:52:51 PM PDT 24
Peak memory 234028 kb
Host smart-66cf2327-6449-41f3-8327-19de5a8afcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023032383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3023032383
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.684022317
Short name T352
Test name
Test status
Simulation time 1105468744 ps
CPU time 8 seconds
Started May 19 12:52:28 PM PDT 24
Finished May 19 12:52:42 PM PDT 24
Peak memory 218560 kb
Host smart-fbd0bdbe-c193-455a-8b6f-366754a9ad2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=684022317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.684022317
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.561174893
Short name T808
Test name
Test status
Simulation time 8765808820 ps
CPU time 59.33 seconds
Started May 19 12:52:37 PM PDT 24
Finished May 19 12:53:38 PM PDT 24
Peak memory 248540 kb
Host smart-d7952b4a-a8fd-4a9d-a15c-7ecd72e83a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561174893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.561174893
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2759917159
Short name T326
Test name
Test status
Simulation time 1573807470 ps
CPU time 10.89 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 216020 kb
Host smart-df694c7f-7090-41e2-b271-37f2c7abf115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759917159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2759917159
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.760737817
Short name T350
Test name
Test status
Simulation time 768426190 ps
CPU time 2.25 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:52:39 PM PDT 24
Peak memory 215720 kb
Host smart-86af354d-abe8-407e-aa74-66fa646d26b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760737817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.760737817
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1045869071
Short name T910
Test name
Test status
Simulation time 130418311 ps
CPU time 1.23 seconds
Started May 19 12:52:35 PM PDT 24
Finished May 19 12:52:39 PM PDT 24
Peak memory 207772 kb
Host smart-c6e3b63e-68dd-401d-bbba-e55e93b27410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045869071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1045869071
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3749740495
Short name T488
Test name
Test status
Simulation time 412792205 ps
CPU time 0.99 seconds
Started May 19 12:52:26 PM PDT 24
Finished May 19 12:52:33 PM PDT 24
Peak memory 205868 kb
Host smart-49613e09-848e-4e73-88fa-b464d47ee806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749740495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3749740495
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.593481120
Short name T240
Test name
Test status
Simulation time 234544037 ps
CPU time 2.26 seconds
Started May 19 12:52:31 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 218620 kb
Host smart-1276fa25-755c-444b-91c9-f4d4c5e8991b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593481120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.593481120
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2468653590
Short name T355
Test name
Test status
Simulation time 45471788 ps
CPU time 0.73 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 205832 kb
Host smart-9063cd5d-6cab-4677-b640-0f7af8ebbcd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468653590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2468653590
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2693641729
Short name T43
Test name
Test status
Simulation time 710401352 ps
CPU time 4.21 seconds
Started May 19 12:52:27 PM PDT 24
Finished May 19 12:52:37 PM PDT 24
Peak memory 219488 kb
Host smart-db08dd4f-8ba1-4a58-8098-3e11f3c56098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693641729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2693641729
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.996039870
Short name T790
Test name
Test status
Simulation time 21083770 ps
CPU time 0.79 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:52:53 PM PDT 24
Peak memory 206640 kb
Host smart-2906236d-426c-48e1-b58b-e3a7f961de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996039870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.996039870
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.750125014
Short name T701
Test name
Test status
Simulation time 434207921 ps
CPU time 5.67 seconds
Started May 19 12:52:36 PM PDT 24
Finished May 19 12:52:44 PM PDT 24
Peak memory 224276 kb
Host smart-68bfae3f-a8ab-4bd5-86a9-44f135e12b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750125014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.750125014
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.884759462
Short name T560
Test name
Test status
Simulation time 6752380535 ps
CPU time 41.15 seconds
Started May 19 12:52:41 PM PDT 24
Finished May 19 12:53:23 PM PDT 24
Peak memory 217180 kb
Host smart-ec0d9bbe-22a5-487e-8f25-f623fff74c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884759462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.884759462
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.451009032
Short name T582
Test name
Test status
Simulation time 409051654 ps
CPU time 6.44 seconds
Started May 19 12:52:38 PM PDT 24
Finished May 19 12:52:45 PM PDT 24
Peak memory 232456 kb
Host smart-d22c115e-c598-4d9e-8f44-18fb82e3bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451009032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.451009032
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.602686964
Short name T36
Test name
Test status
Simulation time 176291762 ps
CPU time 2.94 seconds
Started May 19 12:52:44 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 224228 kb
Host smart-b2ab4f9b-f0af-4aee-bcb6-8cc3725d11c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602686964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.602686964
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.195724618
Short name T950
Test name
Test status
Simulation time 450073702 ps
CPU time 9.56 seconds
Started May 19 12:52:36 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 233740 kb
Host smart-549e7684-ca34-4710-bfcb-57bdb15f02b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195724618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.195724618
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1291789842
Short name T298
Test name
Test status
Simulation time 592606826 ps
CPU time 3.6 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 217480 kb
Host smart-e9c52e3d-c3b1-4b47-9331-6608e1396992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291789842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1291789842
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1966577075
Short name T247
Test name
Test status
Simulation time 78797966 ps
CPU time 2.25 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:52:46 PM PDT 24
Peak memory 218412 kb
Host smart-f9760411-a4b0-40e0-b644-eab9acb41218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966577075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1966577075
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1885440733
Short name T688
Test name
Test status
Simulation time 214642919 ps
CPU time 5.46 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:52:42 PM PDT 24
Peak memory 219768 kb
Host smart-71695ea8-f9c1-485a-94bc-97fc1a30cb44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1885440733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1885440733
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3421866462
Short name T702
Test name
Test status
Simulation time 8445452144 ps
CPU time 20.53 seconds
Started May 19 12:52:35 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 216212 kb
Host smart-f07c2227-fd4e-464e-a726-4b20daf8a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421866462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3421866462
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3875122131
Short name T435
Test name
Test status
Simulation time 2653002977 ps
CPU time 7.97 seconds
Started May 19 12:52:37 PM PDT 24
Finished May 19 12:52:47 PM PDT 24
Peak memory 215952 kb
Host smart-e41ad64a-d9f0-46dd-8e44-1d3ffa37c4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875122131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3875122131
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1310277269
Short name T911
Test name
Test status
Simulation time 678419946 ps
CPU time 2.17 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:52:45 PM PDT 24
Peak memory 215960 kb
Host smart-4e0ababd-e2c5-48bd-9433-9005351f0cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310277269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1310277269
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3568287675
Short name T386
Test name
Test status
Simulation time 94775989 ps
CPU time 0.86 seconds
Started May 19 12:52:45 PM PDT 24
Finished May 19 12:52:47 PM PDT 24
Peak memory 206596 kb
Host smart-20390207-2d12-4c8e-9893-a14d09b0741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568287675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3568287675
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2974597568
Short name T749
Test name
Test status
Simulation time 945425383 ps
CPU time 8.35 seconds
Started May 19 12:52:35 PM PDT 24
Finished May 19 12:52:46 PM PDT 24
Peak memory 232488 kb
Host smart-26383853-17c2-4b5e-9c44-51f8c9d93087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974597568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2974597568
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4025429329
Short name T526
Test name
Test status
Simulation time 20052500 ps
CPU time 0.69 seconds
Started May 19 12:52:48 PM PDT 24
Finished May 19 12:52:50 PM PDT 24
Peak memory 205216 kb
Host smart-d3932a1a-1cd6-4ab9-978e-6c540a551bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025429329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4025429329
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1419971210
Short name T93
Test name
Test status
Simulation time 2915387798 ps
CPU time 14.96 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 232936 kb
Host smart-f17a3743-73f0-49c0-8f2f-e6b6f2b09d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419971210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1419971210
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3695176186
Short name T392
Test name
Test status
Simulation time 43974392 ps
CPU time 0.8 seconds
Started May 19 12:52:30 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 206368 kb
Host smart-0bd7bc27-8f1d-46a7-a5e6-a293ed48ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695176186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3695176186
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4067754659
Short name T4
Test name
Test status
Simulation time 10639585720 ps
CPU time 55.09 seconds
Started May 19 12:52:48 PM PDT 24
Finished May 19 12:53:44 PM PDT 24
Peak memory 254988 kb
Host smart-754a7732-7851-406d-a0d7-e22e47c3b1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067754659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4067754659
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1332232002
Short name T286
Test name
Test status
Simulation time 1960223041 ps
CPU time 32.89 seconds
Started May 19 12:52:41 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 248900 kb
Host smart-34b1dcfa-a568-45ad-9b31-fb33e17b305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332232002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1332232002
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1768070569
Short name T504
Test name
Test status
Simulation time 1840130669 ps
CPU time 40.83 seconds
Started May 19 12:52:45 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 252264 kb
Host smart-6cd453a3-521b-46eb-9c0a-bfa5fa7e6272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768070569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1768070569
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3040942033
Short name T531
Test name
Test status
Simulation time 7845051270 ps
CPU time 47.47 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 239472 kb
Host smart-2e3785be-5c35-481b-8fdb-e1a4582a69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040942033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3040942033
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1480415798
Short name T2
Test name
Test status
Simulation time 1803074630 ps
CPU time 6.87 seconds
Started May 19 12:52:53 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 219744 kb
Host smart-e3ab0fab-245f-484d-a44a-87b7a28d03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480415798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1480415798
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3751073531
Short name T434
Test name
Test status
Simulation time 39254052156 ps
CPU time 62.15 seconds
Started May 19 12:52:40 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 246120 kb
Host smart-3480049d-6342-4fca-b836-e859d6aa7b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751073531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3751073531
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2396741182
Short name T280
Test name
Test status
Simulation time 13307956894 ps
CPU time 15.3 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 226356 kb
Host smart-71153029-3b14-46fc-a09a-b4f39fc1600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396741182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2396741182
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1326998923
Short name T951
Test name
Test status
Simulation time 13451334681 ps
CPU time 12.19 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:52:56 PM PDT 24
Peak memory 235828 kb
Host smart-4d9da448-a8cb-4858-84b6-455794a4fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326998923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1326998923
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2965488291
Short name T360
Test name
Test status
Simulation time 168988543 ps
CPU time 4.62 seconds
Started May 19 12:52:43 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 218596 kb
Host smart-ebce098d-1427-4e05-84fd-8fe7d682fcd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2965488291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2965488291
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2793349218
Short name T447
Test name
Test status
Simulation time 345631904 ps
CPU time 1.06 seconds
Started May 19 12:52:44 PM PDT 24
Finished May 19 12:52:46 PM PDT 24
Peak memory 206484 kb
Host smart-12c8dd3e-305b-45cc-94bd-87abfb40e32a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793349218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2793349218
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2923376694
Short name T330
Test name
Test status
Simulation time 9292559314 ps
CPU time 45.86 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:53:37 PM PDT 24
Peak memory 216108 kb
Host smart-638d9410-9ad5-4d6c-85ba-7493bd6e6a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923376694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2923376694
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2344676880
Short name T840
Test name
Test status
Simulation time 16918315170 ps
CPU time 13.59 seconds
Started May 19 12:52:29 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 216048 kb
Host smart-2e63a55c-3afb-4541-b248-1874b02b8372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344676880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2344676880
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3531246733
Short name T692
Test name
Test status
Simulation time 17213198 ps
CPU time 0.9 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:52:52 PM PDT 24
Peak memory 207104 kb
Host smart-b2e6ce05-14b0-4594-9f37-87b6cf3d56c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531246733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3531246733
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3210018951
Short name T861
Test name
Test status
Simulation time 353845631 ps
CPU time 1 seconds
Started May 19 12:52:53 PM PDT 24
Finished May 19 12:52:56 PM PDT 24
Peak memory 205564 kb
Host smart-5c6100c5-6db7-4fac-8275-3e6aa4da4793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210018951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3210018951
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.199448091
Short name T339
Test name
Test status
Simulation time 35507837 ps
CPU time 2.26 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:52:50 PM PDT 24
Peak memory 212756 kb
Host smart-641c23ab-8d30-411a-9145-35714235b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199448091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.199448091
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1173089013
Short name T931
Test name
Test status
Simulation time 14665872 ps
CPU time 0.71 seconds
Started May 19 12:52:34 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 205144 kb
Host smart-0a4e9184-cc48-4639-a109-aff1474f145b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173089013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1173089013
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1869929325
Short name T466
Test name
Test status
Simulation time 3407692940 ps
CPU time 11.77 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 219600 kb
Host smart-c1b27992-2e1e-4606-90aa-5ea336f3705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869929325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1869929325
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1763185737
Short name T407
Test name
Test status
Simulation time 13846387 ps
CPU time 0.75 seconds
Started May 19 12:52:40 PM PDT 24
Finished May 19 12:52:42 PM PDT 24
Peak memory 206412 kb
Host smart-c2bc2a82-71e0-424f-ba2b-c9035748c79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763185737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1763185737
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.859359
Short name T672
Test name
Test status
Simulation time 20890523083 ps
CPU time 49.15 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:53:37 PM PDT 24
Peak memory 217252 kb
Host smart-dce070d4-9ef7-4c09-9082-5b19f301a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.859359
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1617879268
Short name T469
Test name
Test status
Simulation time 52283731265 ps
CPU time 133.31 seconds
Started May 19 12:52:42 PM PDT 24
Finished May 19 12:54:57 PM PDT 24
Peak memory 248956 kb
Host smart-45fadd4d-0ea1-4968-bb85-55644e687d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617879268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1617879268
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3745969014
Short name T932
Test name
Test status
Simulation time 2148964149 ps
CPU time 8.57 seconds
Started May 19 12:52:39 PM PDT 24
Finished May 19 12:52:49 PM PDT 24
Peak memory 234928 kb
Host smart-f0eceec5-7f14-45fe-842d-15cc596e686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745969014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3745969014
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2241026914
Short name T452
Test name
Test status
Simulation time 1984224273 ps
CPU time 15.45 seconds
Started May 19 12:52:33 PM PDT 24
Finished May 19 12:52:52 PM PDT 24
Peak memory 227844 kb
Host smart-9589c57d-fbd2-46eb-94b6-d56b64e67523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241026914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2241026914
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2646359798
Short name T200
Test name
Test status
Simulation time 580017919 ps
CPU time 4.15 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:02 PM PDT 24
Peak memory 233508 kb
Host smart-37cda4bf-012f-4e47-859a-4e1cb47a9217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646359798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2646359798
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1055355405
Short name T24
Test name
Test status
Simulation time 1663786717 ps
CPU time 7.31 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 217596 kb
Host smart-a7ae9f9b-b2fa-45b6-a6b7-0eb7108ff96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055355405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1055355405
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3849889762
Short name T142
Test name
Test status
Simulation time 3985181524 ps
CPU time 8.97 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:52:59 PM PDT 24
Peak memory 219960 kb
Host smart-010a6083-7e15-4241-a95d-f3c9ab145ef5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3849889762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3849889762
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4094041783
Short name T758
Test name
Test status
Simulation time 112583450 ps
CPU time 1.06 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:52:49 PM PDT 24
Peak memory 206880 kb
Host smart-907cd4bc-6c2f-449d-b94f-5722cf13581a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094041783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4094041783
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2802533117
Short name T6
Test name
Test status
Simulation time 4338586440 ps
CPU time 18.5 seconds
Started May 19 12:52:46 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 216188 kb
Host smart-87fa4623-f445-463a-a6c3-5dfccfe078cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802533117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2802533117
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3375303780
Short name T713
Test name
Test status
Simulation time 795988802 ps
CPU time 3.17 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:52:56 PM PDT 24
Peak memory 215928 kb
Host smart-acbe7329-77d6-4b42-95eb-67c7bb4f38e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375303780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3375303780
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2023823136
Short name T588
Test name
Test status
Simulation time 13292829 ps
CPU time 0.69 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 12:52:57 PM PDT 24
Peak memory 205324 kb
Host smart-64b0972a-a598-448f-ad62-f83001a84d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023823136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2023823136
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4006442851
Short name T498
Test name
Test status
Simulation time 67456239 ps
CPU time 0.8 seconds
Started May 19 12:52:46 PM PDT 24
Finished May 19 12:52:47 PM PDT 24
Peak memory 205596 kb
Host smart-155ab0a9-7f90-41cc-b719-eed8e4fa4313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006442851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4006442851
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.488574331
Short name T662
Test name
Test status
Simulation time 7102997823 ps
CPU time 13.99 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 232428 kb
Host smart-c13a5295-498d-457e-a781-259219075163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488574331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.488574331
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1804254370
Short name T641
Test name
Test status
Simulation time 45063508 ps
CPU time 0.72 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 204652 kb
Host smart-cda0cf13-c354-41e5-940f-28dc3805a9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804254370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1804254370
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1867295180
Short name T940
Test name
Test status
Simulation time 132277333 ps
CPU time 3.32 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:53:02 PM PDT 24
Peak memory 234540 kb
Host smart-a5138719-0c38-47fd-b81d-7c9ecda9af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867295180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1867295180
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1476682077
Short name T925
Test name
Test status
Simulation time 39401981 ps
CPU time 0.73 seconds
Started May 19 12:52:41 PM PDT 24
Finished May 19 12:52:43 PM PDT 24
Peak memory 205396 kb
Host smart-769c1142-5848-4bed-b9ef-342513ac70c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476682077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1476682077
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4260424999
Short name T30
Test name
Test status
Simulation time 46553904697 ps
CPU time 160.36 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:55:43 PM PDT 24
Peak memory 249868 kb
Host smart-5b505a28-876c-4c6e-a0a8-41c92058d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260424999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4260424999
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.902498708
Short name T204
Test name
Test status
Simulation time 19725880467 ps
CPU time 159.02 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:55:33 PM PDT 24
Peak memory 238556 kb
Host smart-7584cfe4-d068-4d2c-af68-0fb93cc509fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902498708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.902498708
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4166452856
Short name T193
Test name
Test status
Simulation time 215270422710 ps
CPU time 445.13 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 01:00:21 PM PDT 24
Peak memory 249004 kb
Host smart-27d787c6-6b2d-4760-9d08-bafad819d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166452856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4166452856
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3271097409
Short name T316
Test name
Test status
Simulation time 2265172482 ps
CPU time 12.71 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:11 PM PDT 24
Peak memory 232924 kb
Host smart-e4bb4309-924a-43e0-aa9a-689b3f85ccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271097409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3271097409
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3347204567
Short name T665
Test name
Test status
Simulation time 1155950653 ps
CPU time 9.7 seconds
Started May 19 12:52:55 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 219316 kb
Host smart-8658e8b9-bd59-4059-9eb2-f15a52c9a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347204567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3347204567
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3631148988
Short name T338
Test name
Test status
Simulation time 372725390 ps
CPU time 2.15 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 215860 kb
Host smart-db91dcf2-06b1-401c-bfc0-e2db557d899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631148988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3631148988
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2808948796
Short name T263
Test name
Test status
Simulation time 2289795778 ps
CPU time 3.63 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:52:54 PM PDT 24
Peak memory 218560 kb
Host smart-fd2b3f14-ad0d-4583-b5a1-dc0544c29c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808948796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2808948796
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3663159828
Short name T540
Test name
Test status
Simulation time 7258704402 ps
CPU time 16.48 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 234004 kb
Host smart-a283833b-f998-4b64-af82-0cbc84b4262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663159828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3663159828
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1604629324
Short name T848
Test name
Test status
Simulation time 930036059 ps
CPU time 11.1 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:53:03 PM PDT 24
Peak memory 219464 kb
Host smart-cf090be4-2208-481d-95af-655c30155205
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1604629324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1604629324
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3942923605
Short name T54
Test name
Test status
Simulation time 4646004412 ps
CPU time 93.77 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 248996 kb
Host smart-8cb39803-47ca-4b04-ad39-ef6607ca9c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942923605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3942923605
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.480413653
Short name T844
Test name
Test status
Simulation time 13069874082 ps
CPU time 38.83 seconds
Started May 19 12:52:45 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 216080 kb
Host smart-870d115e-9197-4760-bbca-ae92959bce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480413653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.480413653
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3802732057
Short name T801
Test name
Test status
Simulation time 35636089 ps
CPU time 0.98 seconds
Started May 19 12:52:44 PM PDT 24
Finished May 19 12:52:46 PM PDT 24
Peak memory 205612 kb
Host smart-943f1925-e48c-4591-9f1b-b439940c1c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802732057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3802732057
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2367193691
Short name T479
Test name
Test status
Simulation time 416113297 ps
CPU time 1.42 seconds
Started May 19 12:52:55 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 216124 kb
Host smart-a51f416e-85f3-4bc6-b135-f7e2fe92a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367193691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2367193691
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2175422154
Short name T335
Test name
Test status
Simulation time 155018033 ps
CPU time 0.87 seconds
Started May 19 12:52:48 PM PDT 24
Finished May 19 12:52:50 PM PDT 24
Peak memory 205648 kb
Host smart-12d43828-dac4-40f2-9bf0-ab9fa385f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175422154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2175422154
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1769661627
Short name T442
Test name
Test status
Simulation time 271055416 ps
CPU time 3.76 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 234388 kb
Host smart-71a94852-fc44-4042-b17b-33fc7d4f8f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769661627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1769661627
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2009151776
Short name T367
Test name
Test status
Simulation time 44684158 ps
CPU time 0.71 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:51:24 PM PDT 24
Peak memory 205532 kb
Host smart-b9a8d2cf-65c3-4b55-81b8-8c4f6c60da7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009151776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
009151776
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2473543551
Short name T577
Test name
Test status
Simulation time 173383327 ps
CPU time 2.89 seconds
Started May 19 12:51:14 PM PDT 24
Finished May 19 12:51:19 PM PDT 24
Peak memory 218232 kb
Host smart-0cf453ef-434d-4271-bc82-462516b9c0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473543551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2473543551
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2404813539
Short name T626
Test name
Test status
Simulation time 34148587 ps
CPU time 0.75 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:21 PM PDT 24
Peak memory 205240 kb
Host smart-a0caf52c-3c25-4050-9b04-b290a08d622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404813539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2404813539
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.817576576
Short name T173
Test name
Test status
Simulation time 19120385771 ps
CPU time 62.23 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:52:25 PM PDT 24
Peak memory 224304 kb
Host smart-df90f876-fbb6-4477-a14b-8f0da9cb7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817576576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.817576576
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2765161933
Short name T254
Test name
Test status
Simulation time 109251988608 ps
CPU time 257.85 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:55:40 PM PDT 24
Peak memory 247328 kb
Host smart-31c6b730-2339-43f9-87d5-4d72b76e18ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765161933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2765161933
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1144980527
Short name T172
Test name
Test status
Simulation time 19059632701 ps
CPU time 64.65 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:52:26 PM PDT 24
Peak memory 237244 kb
Host smart-501dd1b2-b48b-4f36-ba9f-826c9c7842e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144980527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1144980527
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1890225120
Short name T72
Test name
Test status
Simulation time 195801784 ps
CPU time 2.87 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 232364 kb
Host smart-1bb45ac3-a5b5-43c9-86f8-3b57b7fababf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890225120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1890225120
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2103586128
Short name T855
Test name
Test status
Simulation time 253153620 ps
CPU time 2.3 seconds
Started May 19 12:51:17 PM PDT 24
Finished May 19 12:51:24 PM PDT 24
Peak memory 218092 kb
Host smart-bb9a44fd-2a15-4a93-b68d-9882ee9dacd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103586128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2103586128
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1571653688
Short name T379
Test name
Test status
Simulation time 10571373507 ps
CPU time 22.22 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 218292 kb
Host smart-5d523ff9-1921-471b-ab97-0b6c6f35f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571653688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1571653688
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.377550990
Short name T797
Test name
Test status
Simulation time 337353105 ps
CPU time 2.98 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:30 PM PDT 24
Peak memory 219252 kb
Host smart-7e4cf27a-7f4f-4bdd-837f-806733eb0129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377550990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
377550990
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4045266597
Short name T675
Test name
Test status
Simulation time 235389565 ps
CPU time 3.89 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 233124 kb
Host smart-0518967e-4378-4988-a15e-f5f043c2eff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045266597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4045266597
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2338898542
Short name T656
Test name
Test status
Simulation time 965515529 ps
CPU time 5.65 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:51:30 PM PDT 24
Peak memory 222552 kb
Host smart-1407b173-daf3-4e1e-b7a1-c70976059db8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2338898542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2338898542
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.636741299
Short name T60
Test name
Test status
Simulation time 203002034 ps
CPU time 1.2 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:20 PM PDT 24
Peak memory 236140 kb
Host smart-b06dfb1d-eb08-4084-847a-f196ee6a3f57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636741299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.636741299
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1010310836
Short name T876
Test name
Test status
Simulation time 10324136847 ps
CPU time 39.85 seconds
Started May 19 12:51:16 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 216144 kb
Host smart-4fd46150-28dc-4452-ba3b-298dcaec08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010310836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1010310836
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3724073199
Short name T708
Test name
Test status
Simulation time 698039296 ps
CPU time 3.74 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:23 PM PDT 24
Peak memory 215960 kb
Host smart-4e214b68-7162-4174-a3c9-10d1f7b30668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724073199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3724073199
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3269992350
Short name T569
Test name
Test status
Simulation time 45013893 ps
CPU time 0.71 seconds
Started May 19 12:51:15 PM PDT 24
Finished May 19 12:51:20 PM PDT 24
Peak memory 205600 kb
Host smart-6e17affe-b06e-4f74-85b4-7678d1a1291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269992350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3269992350
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.43281298
Short name T670
Test name
Test status
Simulation time 59009979 ps
CPU time 0.74 seconds
Started May 19 12:51:20 PM PDT 24
Finished May 19 12:51:25 PM PDT 24
Peak memory 205624 kb
Host smart-7a8c9194-f14b-423e-bc54-591507b497ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43281298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.43281298
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1968966321
Short name T259
Test name
Test status
Simulation time 6608327956 ps
CPU time 14.02 seconds
Started May 19 12:51:18 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 221452 kb
Host smart-159f5170-8617-40a1-88c1-e6f8eb1558d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968966321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1968966321
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.431529884
Short name T342
Test name
Test status
Simulation time 26917243 ps
CPU time 0.74 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 205236 kb
Host smart-f319f7ba-e84f-45e3-92aa-98b409b2800b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431529884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.431529884
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1029330409
Short name T257
Test name
Test status
Simulation time 187605862 ps
CPU time 2.54 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 232772 kb
Host smart-f3ee80f1-2803-4df5-bf24-cc00e1574feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029330409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1029330409
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1210091250
Short name T5
Test name
Test status
Simulation time 82440540 ps
CPU time 0.8 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 12:52:57 PM PDT 24
Peak memory 206360 kb
Host smart-60740257-790b-42df-b024-f5155337fb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210091250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1210091250
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2923472165
Short name T603
Test name
Test status
Simulation time 4862391672 ps
CPU time 26.38 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 217228 kb
Host smart-dff3f85c-4bb9-4372-b93c-81c1f077b3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923472165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2923472165
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1816349910
Short name T375
Test name
Test status
Simulation time 648016471 ps
CPU time 13.43 seconds
Started May 19 12:52:53 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 240568 kb
Host smart-2c36831d-af4d-4d3e-9a4c-e17474def6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816349910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1816349910
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2789264449
Short name T660
Test name
Test status
Simulation time 3119486842 ps
CPU time 12.15 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 238380 kb
Host smart-004479d9-0f2e-4df2-bc8e-0ada9af028fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789264449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2789264449
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2641529697
Short name T212
Test name
Test status
Simulation time 11335685487 ps
CPU time 79.7 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 246200 kb
Host smart-f272ed0b-0ea1-42fc-be50-dd39f0628ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641529697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2641529697
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3554063354
Short name T819
Test name
Test status
Simulation time 226844425 ps
CPU time 5.12 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:52:57 PM PDT 24
Peak memory 240564 kb
Host smart-bb6d9f3d-2337-4a7b-827c-a935635c0b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554063354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3554063354
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.589639853
Short name T497
Test name
Test status
Simulation time 551735814 ps
CPU time 6.3 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:52:59 PM PDT 24
Peak memory 233944 kb
Host smart-7d44027a-3b15-4e48-81aa-ff5bd3b47720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589639853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.589639853
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.96121442
Short name T158
Test name
Test status
Simulation time 7071086006 ps
CPU time 16.18 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 219664 kb
Host smart-024cee51-5dd0-4004-b38b-4339b7399d8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=96121442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direc
t.96121442
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3084834263
Short name T155
Test name
Test status
Simulation time 256845304 ps
CPU time 1.08 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 12:52:57 PM PDT 24
Peak memory 206968 kb
Host smart-7ff8ce3e-0784-4649-a582-25256093677f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084834263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3084834263
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.768686926
Short name T918
Test name
Test status
Simulation time 2165530785 ps
CPU time 19.93 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 12:53:16 PM PDT 24
Peak memory 216336 kb
Host smart-8c5394bb-1c58-4ddd-bd0e-51f27ce408c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768686926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.768686926
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1907708971
Short name T852
Test name
Test status
Simulation time 780161948 ps
CPU time 5.75 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:52:57 PM PDT 24
Peak memory 216000 kb
Host smart-d4346346-ca8a-48ae-97b2-e1d9c53ab7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907708971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1907708971
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.768409207
Short name T366
Test name
Test status
Simulation time 189081693 ps
CPU time 2.84 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:00 PM PDT 24
Peak memory 215992 kb
Host smart-d6bba514-3c13-4497-85df-8ec436400511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768409207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.768409207
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3713873027
Short name T879
Test name
Test status
Simulation time 27599795 ps
CPU time 0.82 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 205540 kb
Host smart-49288877-7f7d-4b58-b742-0152a3867d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713873027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3713873027
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1828254194
Short name T714
Test name
Test status
Simulation time 861761380 ps
CPU time 8.26 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 218856 kb
Host smart-394df83f-cc2e-493a-9e8c-5d123037793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828254194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1828254194
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1112534769
Short name T50
Test name
Test status
Simulation time 26704925 ps
CPU time 0.69 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:03 PM PDT 24
Peak memory 205480 kb
Host smart-c63090a8-397c-4b29-87b2-ad94989a3948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112534769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1112534769
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1535889651
Short name T369
Test name
Test status
Simulation time 626264041 ps
CPU time 9.6 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 218304 kb
Host smart-db432e52-fc92-476d-96aa-e4702a175a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535889651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1535889651
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2669577044
Short name T359
Test name
Test status
Simulation time 56856908 ps
CPU time 0.8 seconds
Started May 19 12:52:50 PM PDT 24
Finished May 19 12:52:53 PM PDT 24
Peak memory 206436 kb
Host smart-6d0c367d-61b5-4f30-8c83-c8c6255a5786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669577044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2669577044
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4014526214
Short name T643
Test name
Test status
Simulation time 10026591387 ps
CPU time 18.08 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 234624 kb
Host smart-0b5ba98e-2d88-4c1c-908d-101075757110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014526214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4014526214
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4230332766
Short name T784
Test name
Test status
Simulation time 2977203730 ps
CPU time 73.3 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 256640 kb
Host smart-88581749-542b-49bb-8f91-e7661b288433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230332766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4230332766
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1506951408
Short name T759
Test name
Test status
Simulation time 4959162557 ps
CPU time 71.16 seconds
Started May 19 12:52:53 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 236212 kb
Host smart-b6038fe9-302b-4831-835b-a8f0d4267f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506951408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1506951408
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2502791648
Short name T741
Test name
Test status
Simulation time 8203415094 ps
CPU time 17.09 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:19 PM PDT 24
Peak memory 232592 kb
Host smart-a0741c6c-1443-4663-a377-fbff3380e96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502791648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2502791648
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3862411387
Short name T162
Test name
Test status
Simulation time 719681421 ps
CPU time 7 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 235284 kb
Host smart-616a34eb-7472-45a6-9853-a450a32be22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862411387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3862411387
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.143425295
Short name T197
Test name
Test status
Simulation time 145252919 ps
CPU time 2.73 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:52:53 PM PDT 24
Peak memory 218296 kb
Host smart-40dfc98d-0e3b-40eb-b4ca-e7fa6be83bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143425295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.143425295
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2125302744
Short name T796
Test name
Test status
Simulation time 636758959 ps
CPU time 4.24 seconds
Started May 19 12:52:54 PM PDT 24
Finished May 19 12:53:00 PM PDT 24
Peak memory 233092 kb
Host smart-86ea4420-c4cc-49ca-97e3-4fc88f0858c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125302744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2125302744
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3284729537
Short name T761
Test name
Test status
Simulation time 83823113 ps
CPU time 2.35 seconds
Started May 19 12:52:55 PM PDT 24
Finished May 19 12:52:59 PM PDT 24
Peak memory 218220 kb
Host smart-a4d9dd59-69a2-431b-8147-d30ad8ab618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284729537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3284729537
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.838122532
Short name T696
Test name
Test status
Simulation time 408382440 ps
CPU time 5.32 seconds
Started May 19 12:52:47 PM PDT 24
Finished May 19 12:52:53 PM PDT 24
Peak memory 222152 kb
Host smart-9772ab82-6f04-490e-96a5-600e7338950c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=838122532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.838122532
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.830576794
Short name T166
Test name
Test status
Simulation time 25859297089 ps
CPU time 114.86 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 265396 kb
Host smart-5ff821da-3886-4ead-9ccf-a94dd0bc48f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830576794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.830576794
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.838017500
Short name T920
Test name
Test status
Simulation time 3963633678 ps
CPU time 13.14 seconds
Started May 19 12:52:51 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 216552 kb
Host smart-b75a6d51-c040-4b38-a157-a6e468027144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838017500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.838017500
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.152707447
Short name T601
Test name
Test status
Simulation time 5377996449 ps
CPU time 4.32 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 216080 kb
Host smart-4298cdf1-7a71-4433-b867-36c7a7f08adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152707447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.152707447
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1413692379
Short name T772
Test name
Test status
Simulation time 54216945 ps
CPU time 0.79 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:52:51 PM PDT 24
Peak memory 205584 kb
Host smart-5811cf00-8b19-4e8e-ab63-645fae5a2bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413692379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1413692379
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1009537625
Short name T454
Test name
Test status
Simulation time 96212522 ps
CPU time 0.78 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:52:55 PM PDT 24
Peak memory 205632 kb
Host smart-65c753c0-ae90-4266-9566-ba3c4981b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009537625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1009537625
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1232140932
Short name T890
Test name
Test status
Simulation time 689535528 ps
CPU time 4.04 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 217112 kb
Host smart-ce9557c0-e000-4467-9634-0f88632e6a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232140932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1232140932
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3585147875
Short name T372
Test name
Test status
Simulation time 42420792 ps
CPU time 0.77 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 205268 kb
Host smart-79f67dfc-1ff8-4ffd-ac76-e8e239043239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585147875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3585147875
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.733973506
Short name T243
Test name
Test status
Simulation time 565813335 ps
CPU time 3.71 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 233236 kb
Host smart-8c99a0ed-7b4e-45b6-bac6-bdf518c5c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733973506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.733973506
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.393652116
Short name T798
Test name
Test status
Simulation time 21986300 ps
CPU time 0.76 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 206716 kb
Host smart-37486e02-77f3-4e67-a30e-3df17afa9a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393652116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.393652116
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2025597638
Short name T237
Test name
Test status
Simulation time 8410526494 ps
CPU time 63.35 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:54:08 PM PDT 24
Peak memory 240780 kb
Host smart-c23e504d-a45f-40ef-8d7c-b5e08d3380b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025597638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2025597638
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1326562937
Short name T199
Test name
Test status
Simulation time 36622375414 ps
CPU time 113.09 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:54:54 PM PDT 24
Peak memory 249060 kb
Host smart-5c442e7b-3730-4f6a-b346-4e3cdfbcfbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326562937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1326562937
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3783956081
Short name T794
Test name
Test status
Simulation time 43233303421 ps
CPU time 366.76 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:59:14 PM PDT 24
Peak memory 252356 kb
Host smart-2a84c2e4-049c-4004-a935-fb1537c11496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783956081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3783956081
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3008760613
Short name T769
Test name
Test status
Simulation time 315039755 ps
CPU time 4.37 seconds
Started May 19 12:52:49 PM PDT 24
Finished May 19 12:52:54 PM PDT 24
Peak memory 232568 kb
Host smart-0d75b4c1-646e-4d19-81da-06c416e3a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008760613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3008760613
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3747345994
Short name T575
Test name
Test status
Simulation time 63794449 ps
CPU time 2.63 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:04 PM PDT 24
Peak memory 232468 kb
Host smart-4d29bb98-115e-4e78-b51f-85217c0997dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747345994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3747345994
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3554322315
Short name T203
Test name
Test status
Simulation time 825566871 ps
CPU time 3.24 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 233236 kb
Host smart-c086697b-f167-4e0d-88ff-60b5648fb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554322315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3554322315
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3891148001
Short name T188
Test name
Test status
Simulation time 2651329552 ps
CPU time 7.23 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:12 PM PDT 24
Peak memory 217520 kb
Host smart-97cb843c-ac34-4e5c-9e03-25b7a201ec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891148001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3891148001
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1636699774
Short name T803
Test name
Test status
Simulation time 144292755 ps
CPU time 2.47 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 220836 kb
Host smart-5df66cad-e2dc-4501-a775-4ca745fafdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636699774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1636699774
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3543546963
Short name T144
Test name
Test status
Simulation time 1832239916 ps
CPU time 4.23 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 218500 kb
Host smart-5d846efb-96dd-449f-b406-2510d20377f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3543546963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3543546963
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1836838399
Short name T289
Test name
Test status
Simulation time 71742339149 ps
CPU time 367.74 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:59:16 PM PDT 24
Peak memory 255832 kb
Host smart-0c92ada6-d686-4b53-b975-f87ca82e8a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836838399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1836838399
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1779366901
Short name T468
Test name
Test status
Simulation time 8089744700 ps
CPU time 26.5 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 216340 kb
Host smart-0932484d-62c3-423c-bb3d-234a3e4e6105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779366901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1779366901
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3173445622
Short name T489
Test name
Test status
Simulation time 5028983392 ps
CPU time 6.33 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 216084 kb
Host smart-b7d0ce45-49e0-4fe8-8935-bc6a191b0722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173445622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3173445622
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1884042935
Short name T698
Test name
Test status
Simulation time 36943605 ps
CPU time 0.86 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 206396 kb
Host smart-9fbc1551-ad1f-4eb8-84ea-253a383c272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884042935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1884042935
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2622101847
Short name T510
Test name
Test status
Simulation time 340197061 ps
CPU time 0.97 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 205544 kb
Host smart-d8d63ccc-f731-4bfc-a7a1-e17934c86947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622101847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2622101847
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.241089398
Short name T747
Test name
Test status
Simulation time 325531409 ps
CPU time 4.21 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:11 PM PDT 24
Peak memory 234156 kb
Host smart-dae84074-86d8-4a59-84e4-82871a363f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241089398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.241089398
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3882298728
Short name T841
Test name
Test status
Simulation time 54341867 ps
CPU time 0.69 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:02 PM PDT 24
Peak memory 205148 kb
Host smart-03009a8a-6c99-42b9-8f6f-061473944ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882298728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3882298728
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2453402060
Short name T439
Test name
Test status
Simulation time 293473096 ps
CPU time 4.03 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 218756 kb
Host smart-d20e6f60-81e1-480f-b0f1-f0945dcaa7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453402060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2453402060
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2175417552
Short name T929
Test name
Test status
Simulation time 23422859 ps
CPU time 0.81 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 206576 kb
Host smart-79881902-1632-4f9d-87bc-1f8b585b7e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175417552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2175417552
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3078092633
Short name T523
Test name
Test status
Simulation time 883811567 ps
CPU time 15.68 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:20 PM PDT 24
Peak memory 240744 kb
Host smart-56f4b73b-76ee-4294-a41d-f55926645539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078092633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3078092633
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4114796800
Short name T195
Test name
Test status
Simulation time 82597567467 ps
CPU time 214.61 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:56:39 PM PDT 24
Peak memory 251064 kb
Host smart-36e00a32-a8d9-46ee-8006-7511d9949ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114796800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4114796800
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3247603294
Short name T313
Test name
Test status
Simulation time 561509316 ps
CPU time 10.56 seconds
Started May 19 12:52:55 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 224308 kb
Host smart-08cec73f-eece-4386-be92-078c82d06fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247603294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3247603294
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2413118161
Short name T818
Test name
Test status
Simulation time 5577651077 ps
CPU time 12.69 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 219672 kb
Host smart-7bdbdf8a-ef9c-4dfc-b1f7-1c3ab70f5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413118161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2413118161
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1405197626
Short name T757
Test name
Test status
Simulation time 1703822383 ps
CPU time 7.19 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:18 PM PDT 24
Peak memory 240296 kb
Host smart-a07ba89f-516a-4593-9b40-8edcf2d8f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405197626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1405197626
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.695086474
Short name T282
Test name
Test status
Simulation time 427292527 ps
CPU time 5.43 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 233552 kb
Host smart-e0235f61-beba-48de-be86-2a91501b2aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695086474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.695086474
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2463459627
Short name T850
Test name
Test status
Simulation time 580905484 ps
CPU time 2.23 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 215808 kb
Host smart-93995c18-97aa-4499-9c00-bec964fbab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463459627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2463459627
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.693570082
Short name T499
Test name
Test status
Simulation time 1609892979 ps
CPU time 9.57 seconds
Started May 19 12:53:15 PM PDT 24
Finished May 19 12:53:30 PM PDT 24
Peak memory 218824 kb
Host smart-1fb59ad5-53f0-4936-b026-9b7ba185e2f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693570082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.693570082
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4018870061
Short name T775
Test name
Test status
Simulation time 14200398223 ps
CPU time 29.85 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:53:30 PM PDT 24
Peak memory 216052 kb
Host smart-a85a873d-7008-4187-86ab-777cad957e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018870061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4018870061
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2303472989
Short name T934
Test name
Test status
Simulation time 5412342279 ps
CPU time 6.37 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:12 PM PDT 24
Peak memory 216028 kb
Host smart-d91e3de0-1558-4e24-bb87-b2a6abfed9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303472989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2303472989
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2603350787
Short name T483
Test name
Test status
Simulation time 56321683 ps
CPU time 0.82 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 205600 kb
Host smart-3b0fc2d2-e22f-4b15-9944-1bb1179b4e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603350787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2603350787
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3999273410
Short name T955
Test name
Test status
Simulation time 22397581 ps
CPU time 0.7 seconds
Started May 19 12:52:55 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 205336 kb
Host smart-32cf8ad5-9ed5-48e5-ba04-2914d281cd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999273410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3999273410
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3468935383
Short name T686
Test name
Test status
Simulation time 12674569897 ps
CPU time 11.44 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:18 PM PDT 24
Peak memory 234036 kb
Host smart-de116e61-233b-4ccf-a10f-5424ebe99117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468935383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3468935383
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3804962912
Short name T681
Test name
Test status
Simulation time 33332341 ps
CPU time 0.74 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 205260 kb
Host smart-aa3794a5-5ad4-431c-ae47-a2346a5899a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804962912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3804962912
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1571651486
Short name T236
Test name
Test status
Simulation time 328394986 ps
CPU time 3.15 seconds
Started May 19 12:52:53 PM PDT 24
Finished May 19 12:52:58 PM PDT 24
Peak memory 218400 kb
Host smart-37bbdd21-0a71-42e4-a371-c704aa7a614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571651486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1571651486
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.900532925
Short name T15
Test name
Test status
Simulation time 72010837 ps
CPU time 0.75 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:03 PM PDT 24
Peak memory 206656 kb
Host smart-a73f3e17-f63c-465b-99bb-80e51cb6d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900532925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.900532925
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1794540649
Short name T387
Test name
Test status
Simulation time 5058311717 ps
CPU time 34.48 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:41 PM PDT 24
Peak memory 237892 kb
Host smart-6cb28aea-d176-44ae-b2d5-0627096a21fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794540649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1794540649
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3674706384
Short name T888
Test name
Test status
Simulation time 14855476277 ps
CPU time 90.28 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 250236 kb
Host smart-04005cf8-97eb-4683-860a-7c8679e9c52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674706384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3674706384
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3072858154
Short name T370
Test name
Test status
Simulation time 1598387782 ps
CPU time 7.05 seconds
Started May 19 12:52:52 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 224232 kb
Host smart-3611a7fc-f087-4108-b9ed-719dfa96fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072858154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3072858154
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.951683060
Short name T522
Test name
Test status
Simulation time 1652803371 ps
CPU time 13.6 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 232988 kb
Host smart-98aebd67-e7ad-45e9-af2e-e1a586015f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951683060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.951683060
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2537801424
Short name T47
Test name
Test status
Simulation time 672654378 ps
CPU time 9.91 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 233396 kb
Host smart-90154a68-894c-4605-9f50-341481f14c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537801424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2537801424
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1643351832
Short name T437
Test name
Test status
Simulation time 6746225571 ps
CPU time 21.89 seconds
Started May 19 12:53:11 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 233528 kb
Host smart-47f3767f-1aa0-4f1f-8cc4-cb626570e40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643351832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1643351832
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.89592075
Short name T637
Test name
Test status
Simulation time 760358088 ps
CPU time 3.28 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:11 PM PDT 24
Peak memory 218668 kb
Host smart-3896d99c-7fc9-4c75-8a2e-49e86e67ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89592075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.89592075
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3522855460
Short name T38
Test name
Test status
Simulation time 1073895517 ps
CPU time 8.74 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:19 PM PDT 24
Peak memory 222732 kb
Host smart-b9058474-a14c-444c-9b25-1dea41fefbeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522855460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3522855460
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2523736638
Short name T802
Test name
Test status
Simulation time 15936147685 ps
CPU time 132.89 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:55:25 PM PDT 24
Peak memory 250880 kb
Host smart-047307fc-e70e-4940-84e8-bc6cb874afd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523736638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2523736638
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1615327283
Short name T883
Test name
Test status
Simulation time 4226224808 ps
CPU time 19 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 216368 kb
Host smart-3402278e-9cb5-4a77-bac2-3d013d94609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615327283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1615327283
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2305788803
Short name T854
Test name
Test status
Simulation time 3739099169 ps
CPU time 10.03 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 216096 kb
Host smart-d4201656-3220-4208-9b4a-a327f60ec562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305788803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2305788803
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1893718660
Short name T400
Test name
Test status
Simulation time 13460512 ps
CPU time 0.69 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:53:00 PM PDT 24
Peak memory 205412 kb
Host smart-99d803cd-f594-47cf-9a7e-a74082386b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893718660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1893718660
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3171270886
Short name T567
Test name
Test status
Simulation time 81621817 ps
CPU time 0.85 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:53:04 PM PDT 24
Peak memory 205952 kb
Host smart-2e82e375-c2dc-4bfd-8552-4f2bc82ce7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171270886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3171270886
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.405043587
Short name T168
Test name
Test status
Simulation time 598145205 ps
CPU time 6.85 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 239828 kb
Host smart-806f839d-710f-4f29-be2c-9106ba6589e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405043587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.405043587
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3596342768
Short name T129
Test name
Test status
Simulation time 17888357 ps
CPU time 0.78 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 205580 kb
Host smart-b61364e6-15f8-4b06-8914-8ad83cde8b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596342768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3596342768
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3297571345
Short name T241
Test name
Test status
Simulation time 822505755 ps
CPU time 3.37 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 219328 kb
Host smart-7d665da6-36b1-47fb-96e1-43b105a54a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297571345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3297571345
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.464457650
Short name T640
Test name
Test status
Simulation time 29686854 ps
CPU time 0.76 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:53:01 PM PDT 24
Peak memory 206592 kb
Host smart-554dbd1e-e1ba-45be-8dbd-9e0e1119a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464457650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.464457650
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3209497132
Short name T175
Test name
Test status
Simulation time 2545708087 ps
CPU time 17.82 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:53:18 PM PDT 24
Peak memory 237600 kb
Host smart-1e4d7443-8436-4a8a-9a18-10f587d70042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209497132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3209497132
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3936244632
Short name T131
Test name
Test status
Simulation time 13925174115 ps
CPU time 74.19 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:54:28 PM PDT 24
Peak memory 240732 kb
Host smart-6b79281a-fd42-492d-b9f5-ee316950b38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936244632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3936244632
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3904678155
Short name T423
Test name
Test status
Simulation time 5287609844 ps
CPU time 11.41 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:22 PM PDT 24
Peak memory 217240 kb
Host smart-5e870ba9-b035-45e6-8650-0e9a67809903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904678155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3904678155
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3968620179
Short name T954
Test name
Test status
Simulation time 179229889 ps
CPU time 5.2 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 232524 kb
Host smart-1c26a467-0110-47bd-a053-c2a5802a1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968620179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3968620179
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3077085522
Short name T893
Test name
Test status
Simulation time 1345236464 ps
CPU time 6.41 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 233572 kb
Host smart-3962e8de-e3a4-4e07-958f-fb29b2dd7cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077085522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3077085522
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2476235549
Short name T579
Test name
Test status
Simulation time 2784105135 ps
CPU time 34.44 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:41 PM PDT 24
Peak memory 249972 kb
Host smart-38d5ca80-a231-4083-8dfd-c0a5077180a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476235549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2476235549
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3105236102
Short name T294
Test name
Test status
Simulation time 1834664241 ps
CPU time 5.72 seconds
Started May 19 12:52:57 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 218528 kb
Host smart-9f4fd385-776b-49f5-9da2-89bf7d4d1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105236102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3105236102
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2366798313
Short name T424
Test name
Test status
Simulation time 362831375 ps
CPU time 4.24 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 233968 kb
Host smart-161ee76e-fda7-4cbe-8da2-3f528909f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366798313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2366798313
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3614735524
Short name T449
Test name
Test status
Simulation time 169244360 ps
CPU time 3.88 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 218792 kb
Host smart-3fc68e27-28c9-4b09-8ae3-27d38f1c235b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3614735524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3614735524
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2328081226
Short name T149
Test name
Test status
Simulation time 166161726 ps
CPU time 0.93 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:05 PM PDT 24
Peak memory 206728 kb
Host smart-2898bbc1-571e-49f6-bdd7-44026cd5ce4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328081226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2328081226
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1430521750
Short name T661
Test name
Test status
Simulation time 11614277290 ps
CPU time 32.67 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:37 PM PDT 24
Peak memory 219688 kb
Host smart-27c0bb77-861b-4125-b938-e2cf0104667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430521750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1430521750
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.346122948
Short name T868
Test name
Test status
Simulation time 154075773 ps
CPU time 1.61 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:03 PM PDT 24
Peak memory 207528 kb
Host smart-762ee6c1-36c1-4b8a-a48a-e93617ed227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346122948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.346122948
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4218329796
Short name T396
Test name
Test status
Simulation time 276490449 ps
CPU time 2.16 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 216096 kb
Host smart-b2842833-c93f-47a5-8a55-4b175442c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218329796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4218329796
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3083366174
Short name T348
Test name
Test status
Simulation time 77257852 ps
CPU time 0.87 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:52:59 PM PDT 24
Peak memory 205644 kb
Host smart-831d41ae-89d2-46c0-8dc8-82828c60ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083366174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3083366174
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1065426023
Short name T947
Test name
Test status
Simulation time 10349094489 ps
CPU time 30.14 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:49 PM PDT 24
Peak memory 232580 kb
Host smart-81ed2cef-c856-4d59-9bf2-5d85ce381b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065426023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1065426023
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1950845383
Short name T944
Test name
Test status
Simulation time 17188065 ps
CPU time 0.7 seconds
Started May 19 12:53:26 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 204680 kb
Host smart-b6eca9c8-23c7-4130-9aa8-ff52df0ed2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950845383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1950845383
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3113625547
Short name T723
Test name
Test status
Simulation time 2700094403 ps
CPU time 7.45 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 219232 kb
Host smart-57a1f52f-c2c9-4c9d-85d5-817a1ddb960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113625547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3113625547
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1112255116
Short name T380
Test name
Test status
Simulation time 15647020 ps
CPU time 0.77 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 205304 kb
Host smart-190870fb-04a1-440a-9c79-09c0b0b35af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112255116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1112255116
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3722624567
Short name T208
Test name
Test status
Simulation time 362972182819 ps
CPU time 204.54 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:56:26 PM PDT 24
Peak memory 252156 kb
Host smart-a433d7e8-8892-41b2-a50c-571a4ec9170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722624567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3722624567
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2140271932
Short name T952
Test name
Test status
Simulation time 58204598593 ps
CPU time 98.94 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 224300 kb
Host smart-c8638750-8266-48c1-a119-0b6346dbc1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140271932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2140271932
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.36664043
Short name T789
Test name
Test status
Simulation time 3496312426 ps
CPU time 46.42 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:54:01 PM PDT 24
Peak memory 238088 kb
Host smart-83159422-401d-422c-bc01-6ad2bff8ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36664043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.36664043
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1058981872
Short name T839
Test name
Test status
Simulation time 4157104820 ps
CPU time 6.9 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 224396 kb
Host smart-6b79f034-cfd9-4ec2-a86e-79a5d1911dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058981872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1058981872
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.970584022
Short name T92
Test name
Test status
Simulation time 2854098168 ps
CPU time 10.51 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 233456 kb
Host smart-0e5b758d-3d8c-4056-a335-9f430ded43d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970584022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.970584022
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.752107036
Short name T225
Test name
Test status
Simulation time 8352357816 ps
CPU time 27.64 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 246128 kb
Host smart-0ebd6ca1-71b4-4575-80e8-069e43035b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752107036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.752107036
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.194820165
Short name T667
Test name
Test status
Simulation time 6952086848 ps
CPU time 17.5 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 232572 kb
Host smart-cd5a4462-3fd9-477a-989e-ba10fa12a80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194820165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.194820165
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.600899658
Short name T945
Test name
Test status
Simulation time 6872631060 ps
CPU time 13.07 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:19 PM PDT 24
Peak memory 227712 kb
Host smart-888c8262-7f87-409d-933c-a09c174cfbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600899658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.600899658
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3467269843
Short name T799
Test name
Test status
Simulation time 903174049 ps
CPU time 6.36 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 219920 kb
Host smart-2b9df660-7243-40ba-9acf-f01af5688f1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467269843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3467269843
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.49170247
Short name T493
Test name
Test status
Simulation time 13930170847 ps
CPU time 149.85 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:55:42 PM PDT 24
Peak memory 251604 kb
Host smart-b2c3eb84-530f-4f49-8b37-4f28dc4b4f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49170247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress
_all.49170247
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3008107399
Short name T440
Test name
Test status
Simulation time 1468645973 ps
CPU time 3.35 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:17 PM PDT 24
Peak memory 216020 kb
Host smart-8cdf2b12-ae0b-4c49-8669-8154d96360c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008107399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3008107399
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4112307359
Short name T673
Test name
Test status
Simulation time 21595167847 ps
CPU time 16.9 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 216376 kb
Host smart-20d727fe-7c1f-4a6d-9019-bd7374af49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112307359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4112307359
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3344029449
Short name T676
Test name
Test status
Simulation time 153490980 ps
CPU time 2.34 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:11 PM PDT 24
Peak memory 216352 kb
Host smart-d271c1c4-1f57-4863-bd80-e1a9d26354a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344029449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3344029449
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2400220807
Short name T607
Test name
Test status
Simulation time 19056466 ps
CPU time 0.79 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 205656 kb
Host smart-217a3d3a-c8b4-40a2-b9c9-402dec0014e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400220807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2400220807
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4082919985
Short name T735
Test name
Test status
Simulation time 264670821 ps
CPU time 4.21 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:16 PM PDT 24
Peak memory 236036 kb
Host smart-64fd7384-5298-4997-9291-a850fb8e098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082919985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4082919985
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3542751848
Short name T398
Test name
Test status
Simulation time 144815672 ps
CPU time 0.69 seconds
Started May 19 12:53:11 PM PDT 24
Finished May 19 12:53:17 PM PDT 24
Peak memory 205116 kb
Host smart-ff60ef2a-64b1-413c-a90b-d16ee30fcf12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542751848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3542751848
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2575184026
Short name T231
Test name
Test status
Simulation time 169902053 ps
CPU time 3.46 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 218876 kb
Host smart-e1aa5831-d769-4db1-8554-177e58e3076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575184026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2575184026
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1737309892
Short name T649
Test name
Test status
Simulation time 16832685 ps
CPU time 0.77 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 205244 kb
Host smart-e8dc6323-9e02-443a-9ff0-f0771248f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737309892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1737309892
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3574811566
Short name T904
Test name
Test status
Simulation time 2024194337 ps
CPU time 35.95 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:47 PM PDT 24
Peak memory 249816 kb
Host smart-c0bcd8c5-0c7b-45fa-b980-d08615b20586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574811566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3574811566
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.143256766
Short name T307
Test name
Test status
Simulation time 50901441085 ps
CPU time 175.53 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:56:06 PM PDT 24
Peak memory 255600 kb
Host smart-cac5f253-559b-463a-b199-508ece26c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143256766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.143256766
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2183987461
Short name T611
Test name
Test status
Simulation time 13357270118 ps
CPU time 146.74 seconds
Started May 19 12:52:58 PM PDT 24
Finished May 19 12:55:27 PM PDT 24
Peak memory 251800 kb
Host smart-87f016ec-d54d-4aef-9a6d-0994acba93e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183987461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2183987461
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1724836785
Short name T898
Test name
Test status
Simulation time 3271741683 ps
CPU time 26.98 seconds
Started May 19 12:52:56 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 232508 kb
Host smart-d0041e58-1840-4858-9839-bdbcb0807546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724836785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1724836785
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2038819759
Short name T573
Test name
Test status
Simulation time 559256547 ps
CPU time 2.52 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 218176 kb
Host smart-b6ed00be-9fe7-4210-8245-052949dc8754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038819759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2038819759
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2462224662
Short name T953
Test name
Test status
Simulation time 412115048 ps
CPU time 2.27 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 215852 kb
Host smart-7979c700-073e-41d1-a4d9-22bd4a5608d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462224662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2462224662
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2630591844
Short name T268
Test name
Test status
Simulation time 3260649905 ps
CPU time 5.7 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 235932 kb
Host smart-f123015b-db64-49bf-9b8f-9087624a9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630591844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2630591844
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1867384760
Short name T277
Test name
Test status
Simulation time 563940475 ps
CPU time 5.38 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:07 PM PDT 24
Peak memory 227652 kb
Host smart-5b7b6f2b-fa77-4f5c-b337-25a8ec076e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867384760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1867384760
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2296987437
Short name T12
Test name
Test status
Simulation time 1835350590 ps
CPU time 8.61 seconds
Started May 19 12:52:59 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 219768 kb
Host smart-277941c9-747a-4d04-9c79-546bc2e61613
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2296987437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2296987437
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3105651531
Short name T287
Test name
Test status
Simulation time 1971669550 ps
CPU time 51.84 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 248920 kb
Host smart-a9d50179-2298-4446-ac2b-fdb963bba3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105651531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3105651531
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1329627637
Short name T561
Test name
Test status
Simulation time 6288098822 ps
CPU time 20.2 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 217764 kb
Host smart-33fc3021-4b01-4a89-86b0-dcd55add9c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329627637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1329627637
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1671015471
Short name T606
Test name
Test status
Simulation time 9800059378 ps
CPU time 9.01 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:23 PM PDT 24
Peak memory 216408 kb
Host smart-b6cc9242-e7b2-4586-be53-78cfbc58283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671015471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1671015471
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.675103889
Short name T383
Test name
Test status
Simulation time 39365679 ps
CPU time 0.85 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 206448 kb
Host smart-f192e5ec-21d7-4890-aab8-6de1dbb6a606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675103889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.675103889
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.753452536
Short name T593
Test name
Test status
Simulation time 143463181 ps
CPU time 0.84 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 12:53:04 PM PDT 24
Peak memory 205656 kb
Host smart-3b6c0887-9b5f-4367-a6ac-ff2f62d87d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753452536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.753452536
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.425453591
Short name T123
Test name
Test status
Simulation time 2702124768 ps
CPU time 11.02 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 218860 kb
Host smart-1f5b0ada-0f0a-4d37-a797-f6034fd31d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425453591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.425453591
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1578493430
Short name T633
Test name
Test status
Simulation time 20456459 ps
CPU time 0.7 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 204924 kb
Host smart-dd653b0f-52ea-40df-b7cb-38b4651e7966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578493430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1578493430
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2259889069
Short name T235
Test name
Test status
Simulation time 335087715 ps
CPU time 2.68 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:16 PM PDT 24
Peak memory 233196 kb
Host smart-f898c193-3442-4f80-84a5-1174f07f5b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259889069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2259889069
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2005470994
Short name T923
Test name
Test status
Simulation time 27668230 ps
CPU time 0.79 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:06 PM PDT 24
Peak memory 206696 kb
Host smart-fc9bd21e-c595-4a61-b742-c1abb3430e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005470994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2005470994
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.430766096
Short name T533
Test name
Test status
Simulation time 30928317064 ps
CPU time 77.43 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:54:23 PM PDT 24
Peak memory 235552 kb
Host smart-f0195f62-29b1-4407-aa1d-1b4f6fb39cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430766096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.430766096
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2690561672
Short name T719
Test name
Test status
Simulation time 13351970934 ps
CPU time 28.16 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:47 PM PDT 24
Peak memory 232500 kb
Host smart-ca0e6c2a-e197-4e0b-8dbd-ba3288c935fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690561672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2690561672
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.993307361
Short name T196
Test name
Test status
Simulation time 268347311574 ps
CPU time 662.24 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 253964 kb
Host smart-349e024e-3810-48b1-8786-25d94292b4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993307361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.993307361
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2721981618
Short name T644
Test name
Test status
Simulation time 2745692593 ps
CPU time 13.13 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:30 PM PDT 24
Peak memory 240760 kb
Host smart-e0d06a4a-9aa0-43f4-9bef-34b982e122cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721981618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2721981618
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.703835600
Short name T740
Test name
Test status
Simulation time 1291050753 ps
CPU time 4.9 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 218568 kb
Host smart-37c27a00-7bdf-480c-9788-f77e65d8195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703835600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.703835600
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3965872980
Short name T822
Test name
Test status
Simulation time 40094457881 ps
CPU time 84.2 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 233864 kb
Host smart-eae10176-04ee-4647-afc2-7ef8b8ec402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965872980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3965872980
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3789010957
Short name T264
Test name
Test status
Simulation time 1543068777 ps
CPU time 8.59 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:18 PM PDT 24
Peak memory 233584 kb
Host smart-02d88f01-dbcb-49c9-952d-1adcbe1b8bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789010957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3789010957
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3607164234
Short name T608
Test name
Test status
Simulation time 1605437816 ps
CPU time 3.46 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:21 PM PDT 24
Peak memory 218588 kb
Host smart-dffa30d4-423a-41a1-a9b7-48aa066c0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607164234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3607164234
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3594874680
Short name T609
Test name
Test status
Simulation time 291371967 ps
CPU time 4.78 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:15 PM PDT 24
Peak memory 222340 kb
Host smart-fe80f024-9c06-4ab1-ae98-524f11ad16fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3594874680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3594874680
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3938978760
Short name T811
Test name
Test status
Simulation time 126099644 ps
CPU time 1.14 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:19 PM PDT 24
Peak memory 206504 kb
Host smart-740cde89-6ee9-4e05-a750-b9c090624d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938978760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3938978760
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4032676756
Short name T420
Test name
Test status
Simulation time 8191685252 ps
CPU time 22.19 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 216080 kb
Host smart-a8719f8a-7e88-4237-b071-856a6490d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032676756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4032676756
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3947281696
Short name T18
Test name
Test status
Simulation time 920862033 ps
CPU time 1.72 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 207736 kb
Host smart-f13f96ac-d5f0-4831-ad5d-a4ce0d43c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947281696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3947281696
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2737915508
Short name T885
Test name
Test status
Simulation time 1510241852 ps
CPU time 6.87 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 215996 kb
Host smart-73bac700-b65f-45f2-9fde-38edc1036bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737915508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2737915508
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2027777605
Short name T345
Test name
Test status
Simulation time 162001118 ps
CPU time 0.78 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 205900 kb
Host smart-7aa0cb84-e084-4f41-89bb-056faceb2079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027777605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2027777605
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1459075936
Short name T895
Test name
Test status
Simulation time 219988316 ps
CPU time 4.21 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:17 PM PDT 24
Peak memory 218308 kb
Host smart-ee39634b-f46f-4b44-8f50-8249673bb49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459075936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1459075936
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1765286019
Short name T589
Test name
Test status
Simulation time 150702340 ps
CPU time 0.73 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:12 PM PDT 24
Peak memory 205240 kb
Host smart-daa6fb14-f8de-4dce-acb6-29c7b9de9256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765286019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1765286019
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.593509900
Short name T428
Test name
Test status
Simulation time 41554727 ps
CPU time 0.73 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:18 PM PDT 24
Peak memory 205344 kb
Host smart-d5295fe3-4687-494f-bb82-6ea5abe52156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593509900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.593509900
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4203092636
Short name T570
Test name
Test status
Simulation time 1742990740 ps
CPU time 14.03 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 233456 kb
Host smart-95b503ff-b634-48db-877e-82c7ca727005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203092636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4203092636
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.559970742
Short name T221
Test name
Test status
Simulation time 60294118598 ps
CPU time 528.35 seconds
Started May 19 12:53:00 PM PDT 24
Finished May 19 01:01:51 PM PDT 24
Peak memory 272788 kb
Host smart-4d8c0e01-7756-4e8f-9f90-f58a0f382f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559970742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.559970742
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.646175131
Short name T502
Test name
Test status
Simulation time 5644713114 ps
CPU time 68.84 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:54:14 PM PDT 24
Peak memory 251932 kb
Host smart-194a44b5-72da-4aa9-9d5b-ec8ae4c73ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646175131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.646175131
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2508327321
Short name T634
Test name
Test status
Simulation time 206917381 ps
CPU time 5.72 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:11 PM PDT 24
Peak memory 232368 kb
Host smart-b1b9de34-221b-4500-97ad-2498cb86f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508327321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2508327321
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.997443447
Short name T202
Test name
Test status
Simulation time 1493214841 ps
CPU time 8.42 seconds
Started May 19 12:53:16 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 233524 kb
Host smart-5a770b79-2731-42b9-b958-7062dcfd785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997443447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.997443447
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1272007628
Short name T906
Test name
Test status
Simulation time 584750139 ps
CPU time 8.67 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:26 PM PDT 24
Peak memory 234732 kb
Host smart-7521ecea-f216-4e20-9a29-47fc175312c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272007628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1272007628
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3112308584
Short name T281
Test name
Test status
Simulation time 440351075 ps
CPU time 3.99 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:10 PM PDT 24
Peak memory 233404 kb
Host smart-6e094086-745a-4998-8dac-b1acdfd975c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112308584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3112308584
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1538342126
Short name T229
Test name
Test status
Simulation time 226052912 ps
CPU time 4.48 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 240680 kb
Host smart-7b894b72-0acd-4c6e-80ed-575b637e9c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538342126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1538342126
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1515427502
Short name T786
Test name
Test status
Simulation time 293185599 ps
CPU time 5.19 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:17 PM PDT 24
Peak memory 218776 kb
Host smart-3992a211-943a-4869-a4da-8ff08637cea2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1515427502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1515427502
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.141589847
Short name T559
Test name
Test status
Simulation time 59208013 ps
CPU time 1.19 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 207480 kb
Host smart-a41d128a-d98b-47cf-a93c-949ad77c3793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141589847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.141589847
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.17456039
Short name T65
Test name
Test status
Simulation time 58378467 ps
CPU time 0.77 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:19 PM PDT 24
Peak memory 205716 kb
Host smart-8e3921bc-cc56-45b0-838f-3f0ed1470161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17456039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.17456039
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.945785414
Short name T699
Test name
Test status
Simulation time 5378630358 ps
CPU time 16.03 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 216048 kb
Host smart-87a5b212-dcf4-4ea3-bc15-e84825482f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945785414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.945785414
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1229854008
Short name T709
Test name
Test status
Simulation time 377209844 ps
CPU time 2.5 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:18 PM PDT 24
Peak memory 216064 kb
Host smart-fba701b3-bccf-4b76-97cc-43be78a36e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229854008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1229854008
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2650688869
Short name T542
Test name
Test status
Simulation time 20613721 ps
CPU time 0.72 seconds
Started May 19 12:53:07 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 205348 kb
Host smart-9c2fef9c-e62f-416f-b0e8-8fe0ebeee999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650688869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2650688869
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.440349721
Short name T549
Test name
Test status
Simulation time 26664838961 ps
CPU time 42.07 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:49 PM PDT 24
Peak memory 240188 kb
Host smart-eeb7f8e6-0d93-4277-935f-b96cb271cffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440349721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.440349721
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3467877358
Short name T458
Test name
Test status
Simulation time 10908044 ps
CPU time 0.77 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:28 PM PDT 24
Peak memory 205572 kb
Host smart-ff96f924-04ab-4cd6-9c30-e23d4078bacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467877358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
467877358
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2948650784
Short name T563
Test name
Test status
Simulation time 1114306651 ps
CPU time 12.14 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 218344 kb
Host smart-71a6011d-c386-45af-a697-bfe1dc2ddd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948650784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2948650784
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2376095773
Short name T697
Test name
Test status
Simulation time 36999339 ps
CPU time 0.74 seconds
Started May 19 12:51:19 PM PDT 24
Finished May 19 12:51:24 PM PDT 24
Peak memory 206592 kb
Host smart-190bbaea-9e3b-40cb-b0e6-43e069ca5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376095773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2376095773
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1966606520
Short name T67
Test name
Test status
Simulation time 263867504593 ps
CPU time 101.39 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:53:08 PM PDT 24
Peak memory 248872 kb
Host smart-1d9868a3-23ef-4919-b53b-796d2359af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966606520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1966606520
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3820385285
Short name T327
Test name
Test status
Simulation time 6575698099 ps
CPU time 24.69 seconds
Started May 19 12:51:23 PM PDT 24
Finished May 19 12:51:53 PM PDT 24
Peak memory 233492 kb
Host smart-6211a2ed-2e30-4f3a-ba70-6d63200409f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820385285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3820385285
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.973289538
Short name T228
Test name
Test status
Simulation time 7883811166 ps
CPU time 64.17 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 249044 kb
Host smart-704c12ab-1835-4824-8956-44073cf64f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973289538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
973289538
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2858648953
Short name T814
Test name
Test status
Simulation time 1096600618 ps
CPU time 7.47 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 240664 kb
Host smart-20320824-d564-433d-9c38-a7fc6edb6e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858648953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2858648953
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1610180753
Short name T220
Test name
Test status
Simulation time 399629643 ps
CPU time 3.4 seconds
Started May 19 12:51:21 PM PDT 24
Finished May 19 12:51:29 PM PDT 24
Peak memory 232376 kb
Host smart-e3497cda-df65-484a-b198-42eea2b95ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610180753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1610180753
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2418978655
Short name T939
Test name
Test status
Simulation time 1562653640 ps
CPU time 8.61 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:36 PM PDT 24
Peak memory 228832 kb
Host smart-fcc428c5-b63c-4575-aaa2-2a4d4e3a50ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418978655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2418978655
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1084541586
Short name T810
Test name
Test status
Simulation time 385765853 ps
CPU time 4.98 seconds
Started May 19 12:51:21 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 232944 kb
Host smart-4e38cea8-b476-4bc0-a168-3f7f75bc14c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084541586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1084541586
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.824337651
Short name T909
Test name
Test status
Simulation time 360750957 ps
CPU time 2.42 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:30 PM PDT 24
Peak memory 215808 kb
Host smart-bb0d6baa-a71f-4be3-9f3a-7489632e6421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824337651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.824337651
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.696932844
Short name T680
Test name
Test status
Simulation time 417324428 ps
CPU time 3.45 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:51:35 PM PDT 24
Peak memory 220076 kb
Host smart-8532b12c-3d04-4ea6-9d08-508ed1e1150c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696932844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.696932844
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.241030389
Short name T762
Test name
Test status
Simulation time 179119071 ps
CPU time 1.07 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 215048 kb
Host smart-d2a6c59d-b21a-4c68-94b6-9a368fd98fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241030389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.241030389
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3001803082
Short name T566
Test name
Test status
Simulation time 20866250292 ps
CPU time 27.94 seconds
Started May 19 12:51:23 PM PDT 24
Finished May 19 12:51:56 PM PDT 24
Peak memory 216096 kb
Host smart-60e727cc-ee8a-4a9e-8d82-e3d070a79360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001803082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3001803082
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.314616135
Short name T935
Test name
Test status
Simulation time 2342761238 ps
CPU time 2.57 seconds
Started May 19 12:51:20 PM PDT 24
Finished May 19 12:51:28 PM PDT 24
Peak memory 207692 kb
Host smart-da100e30-895a-4cb0-8124-1bf939bb5f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314616135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.314616135
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1181020764
Short name T862
Test name
Test status
Simulation time 34378788 ps
CPU time 0.89 seconds
Started May 19 12:51:32 PM PDT 24
Finished May 19 12:51:35 PM PDT 24
Peak memory 206268 kb
Host smart-9b462100-1c5a-4ec9-8723-5ebd969b6402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181020764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1181020764
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1068923963
Short name T84
Test name
Test status
Simulation time 274177250 ps
CPU time 0.96 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 206608 kb
Host smart-829020e4-61b0-4e7f-b64c-a26166b95dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068923963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1068923963
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2684783038
Short name T896
Test name
Test status
Simulation time 2675583420 ps
CPU time 10.15 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 224360 kb
Host smart-18303e94-8932-4496-81e5-35ffeb00836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684783038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2684783038
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1239650201
Short name T408
Test name
Test status
Simulation time 13268277 ps
CPU time 0.71 seconds
Started May 19 12:51:26 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 205556 kb
Host smart-59158d82-feaa-4ee9-83bd-b8de341ff9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239650201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
239650201
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3686408592
Short name T86
Test name
Test status
Simulation time 351405231 ps
CPU time 2.66 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:35 PM PDT 24
Peak memory 218596 kb
Host smart-c326c7eb-8019-4fc5-b6fb-36902ab7473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686408592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3686408592
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2515936490
Short name T412
Test name
Test status
Simulation time 77866404 ps
CPU time 0.8 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:51:33 PM PDT 24
Peak memory 206268 kb
Host smart-eaf66cb1-2c84-4f37-893c-bbbb0059ce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515936490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2515936490
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1429895071
Short name T916
Test name
Test status
Simulation time 62058233290 ps
CPU time 121.33 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 240068 kb
Host smart-d7b64484-6f24-4829-ad63-ca2a7671e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429895071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1429895071
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2129350922
Short name T654
Test name
Test status
Simulation time 13854243831 ps
CPU time 119.74 seconds
Started May 19 12:51:27 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 252868 kb
Host smart-dd0b65cf-b708-4aa5-9456-3566dd15e32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129350922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2129350922
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.447810053
Short name T297
Test name
Test status
Simulation time 16075232688 ps
CPU time 91.88 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:52:59 PM PDT 24
Peak memory 267184 kb
Host smart-7815fe15-97e7-4bc4-b949-3a451502852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447810053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
447810053
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2882322079
Short name T320
Test name
Test status
Simulation time 19379378001 ps
CPU time 19.46 seconds
Started May 19 12:51:31 PM PDT 24
Finished May 19 12:51:53 PM PDT 24
Peak memory 234248 kb
Host smart-5c895479-74bd-4fba-ba79-f4b8bfecddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882322079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2882322079
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3828842365
Short name T613
Test name
Test status
Simulation time 60012297 ps
CPU time 2.58 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:29 PM PDT 24
Peak memory 221324 kb
Host smart-e2248d24-d38a-432e-8ced-6f822000c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828842365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3828842365
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2458333259
Short name T10
Test name
Test status
Simulation time 10413473069 ps
CPU time 32.51 seconds
Started May 19 12:51:26 PM PDT 24
Finished May 19 12:52:03 PM PDT 24
Peak memory 240456 kb
Host smart-bdc9cccf-7d02-4486-b9ec-ffbc8af2d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458333259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2458333259
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.361754929
Short name T824
Test name
Test status
Simulation time 1539068410 ps
CPU time 6.74 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:39 PM PDT 24
Peak memory 233432 kb
Host smart-986fd094-f6ca-4198-8a58-6ba4cec6d7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361754929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
361754929
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2507757642
Short name T517
Test name
Test status
Simulation time 131488673 ps
CPU time 2.46 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 221324 kb
Host smart-2ac1fd4d-91be-43d5-bf9f-0fe8da13b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507757642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2507757642
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2764380191
Short name T476
Test name
Test status
Simulation time 237309092 ps
CPU time 3.93 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 222716 kb
Host smart-7fd40f66-632b-4a25-ab58-01c622209382
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2764380191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2764380191
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.378440465
Short name T770
Test name
Test status
Simulation time 41920326245 ps
CPU time 145.43 seconds
Started May 19 12:51:39 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 255756 kb
Host smart-b0d67bdc-1dc0-4af6-bc3a-1d2884d51a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378440465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.378440465
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.101054313
Short name T583
Test name
Test status
Simulation time 19081853426 ps
CPU time 20.09 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:50 PM PDT 24
Peak memory 216040 kb
Host smart-5f327405-5264-4919-a43b-ce79acc74045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101054313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.101054313
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2722149192
Short name T958
Test name
Test status
Simulation time 23943680415 ps
CPU time 12.19 seconds
Started May 19 12:51:21 PM PDT 24
Finished May 19 12:51:38 PM PDT 24
Peak memory 217124 kb
Host smart-6a9409f7-1dc5-4eae-8b59-68ecb1b71f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722149192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2722149192
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2951428041
Short name T402
Test name
Test status
Simulation time 346413302 ps
CPU time 1.67 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 216104 kb
Host smart-fb3e5de1-65be-4ace-9817-ee46ecfd6982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951428041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2951428041
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2746856840
Short name T785
Test name
Test status
Simulation time 76803745 ps
CPU time 0.76 seconds
Started May 19 12:51:27 PM PDT 24
Finished May 19 12:51:32 PM PDT 24
Peak memory 205544 kb
Host smart-3481f901-1f0c-4f2e-b576-748b5f4f7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746856840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2746856840
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.652842950
Short name T41
Test name
Test status
Simulation time 399513961 ps
CPU time 4.41 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:33 PM PDT 24
Peak memory 236488 kb
Host smart-30fbcaee-fac7-46a5-a153-76fc36221439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652842950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.652842950
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2033082164
Short name T658
Test name
Test status
Simulation time 12755664 ps
CPU time 0.71 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 204992 kb
Host smart-2d32705a-2f81-48a6-97b4-0302599fc0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033082164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
033082164
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2006767493
Short name T527
Test name
Test status
Simulation time 7597093704 ps
CPU time 18.1 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:47 PM PDT 24
Peak memory 234192 kb
Host smart-c16aa61a-d052-4ef5-aaf3-9fd21c233920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006767493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2006767493
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1549337940
Short name T480
Test name
Test status
Simulation time 19990758 ps
CPU time 0.84 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:51:33 PM PDT 24
Peak memory 206328 kb
Host smart-2cfbc985-fa11-40a5-812b-a3b7603a5934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549337940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1549337940
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1986025200
Short name T302
Test name
Test status
Simulation time 83761190988 ps
CPU time 180.03 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 240628 kb
Host smart-937eace3-7875-4494-9634-e577d8566031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986025200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1986025200
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1658767325
Short name T23
Test name
Test status
Simulation time 40353489067 ps
CPU time 316.51 seconds
Started May 19 12:51:26 PM PDT 24
Finished May 19 12:56:47 PM PDT 24
Peak memory 253772 kb
Host smart-5023447d-6741-4ea4-8e75-aacf8d7df2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658767325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1658767325
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1543622013
Short name T733
Test name
Test status
Simulation time 609274357 ps
CPU time 5.06 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:32 PM PDT 24
Peak memory 232452 kb
Host smart-f8062f81-1c25-4ca9-afa2-20f53c15bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543622013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1543622013
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2218812285
Short name T564
Test name
Test status
Simulation time 548798081 ps
CPU time 5.24 seconds
Started May 19 12:51:26 PM PDT 24
Finished May 19 12:51:36 PM PDT 24
Peak memory 233404 kb
Host smart-5146810f-e398-468e-b199-15de57ba818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218812285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2218812285
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.586436129
Short name T856
Test name
Test status
Simulation time 28276119465 ps
CPU time 48.66 seconds
Started May 19 12:51:50 PM PDT 24
Finished May 19 12:52:40 PM PDT 24
Peak memory 228064 kb
Host smart-2da24c4d-c9b2-45c4-ac7f-ef5e5b66aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586436129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.586436129
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3416587922
Short name T827
Test name
Test status
Simulation time 2287629829 ps
CPU time 11 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:41 PM PDT 24
Peak memory 233612 kb
Host smart-97913dfc-eb7e-4a75-8818-85f8738e1877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416587922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3416587922
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1302302679
Short name T655
Test name
Test status
Simulation time 598892725 ps
CPU time 3.45 seconds
Started May 19 12:51:22 PM PDT 24
Finished May 19 12:51:31 PM PDT 24
Peak memory 224280 kb
Host smart-d378f913-aa12-41a4-ae0f-5e88f2df0060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302302679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1302302679
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.391618171
Short name T683
Test name
Test status
Simulation time 240226522 ps
CPU time 5.2 seconds
Started May 19 12:51:27 PM PDT 24
Finished May 19 12:51:36 PM PDT 24
Peak memory 222200 kb
Host smart-2345c5d6-e3a5-4708-b0a4-04fac39cd351
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=391618171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.391618171
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3732950024
Short name T779
Test name
Test status
Simulation time 2384482151 ps
CPU time 63.11 seconds
Started May 19 12:51:30 PM PDT 24
Finished May 19 12:52:36 PM PDT 24
Peak memory 250328 kb
Host smart-d3188ff6-4601-485e-ac9e-b874c6603534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732950024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3732950024
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3525079790
Short name T14
Test name
Test status
Simulation time 5364957555 ps
CPU time 32.37 seconds
Started May 19 12:51:30 PM PDT 24
Finished May 19 12:52:06 PM PDT 24
Peak memory 216160 kb
Host smart-17f032f0-f47b-4f6f-a1d4-7190485cef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525079790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3525079790
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.518691063
Short name T833
Test name
Test status
Simulation time 5343490135 ps
CPU time 7.74 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:36 PM PDT 24
Peak memory 215952 kb
Host smart-4473a141-0ddd-4ff8-867b-756683e64854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518691063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.518691063
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4094386996
Short name T426
Test name
Test status
Simulation time 19962471 ps
CPU time 0.95 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:30 PM PDT 24
Peak memory 207140 kb
Host smart-cd8b1c54-c95f-475c-8569-acd02c1b5ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094386996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4094386996
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2759840612
Short name T471
Test name
Test status
Simulation time 105841492 ps
CPU time 0.92 seconds
Started May 19 12:51:23 PM PDT 24
Finished May 19 12:51:29 PM PDT 24
Peak memory 205572 kb
Host smart-b94c6dfb-03fd-4857-9478-525c35a55770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759840612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2759840612
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.697596167
Short name T867
Test name
Test status
Simulation time 1793876514 ps
CPU time 5.38 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:38 PM PDT 24
Peak memory 216396 kb
Host smart-a0cb49bc-339c-4d2a-ad88-c112d561df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697596167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.697596167
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3752208735
Short name T358
Test name
Test status
Simulation time 29602171 ps
CPU time 0.72 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 205104 kb
Host smart-5760fecf-35ef-44fa-87f5-592401a56e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752208735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
752208735
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2023393116
Short name T873
Test name
Test status
Simulation time 3060006342 ps
CPU time 16.36 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 233704 kb
Host smart-3aca2032-1096-4e6b-b4fd-5d8f34cf12f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023393116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2023393116
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1020874638
Short name T536
Test name
Test status
Simulation time 79904034 ps
CPU time 0.83 seconds
Started May 19 12:51:41 PM PDT 24
Finished May 19 12:51:43 PM PDT 24
Peak memory 206612 kb
Host smart-7a177387-f60e-41e6-9a47-4d3d4cea1d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020874638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1020874638
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.836773681
Short name T198
Test name
Test status
Simulation time 1659717758 ps
CPU time 15.58 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:45 PM PDT 24
Peak memory 224616 kb
Host smart-962b0563-9767-4944-be85-4effc84ed61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836773681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.836773681
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3647569011
Short name T874
Test name
Test status
Simulation time 4365186098 ps
CPU time 22.3 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:51 PM PDT 24
Peak memory 217560 kb
Host smart-c375f00d-1cb2-4804-b07d-27e06d53c162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647569011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3647569011
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.385292756
Short name T73
Test name
Test status
Simulation time 4477839740 ps
CPU time 58.89 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:52:38 PM PDT 24
Peak memory 251296 kb
Host smart-67605f7b-9e9e-4082-a328-2f392e8d540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385292756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
385292756
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2018736750
Short name T657
Test name
Test status
Simulation time 1760594488 ps
CPU time 8.79 seconds
Started May 19 12:51:44 PM PDT 24
Finished May 19 12:51:53 PM PDT 24
Peak memory 240572 kb
Host smart-747a4432-3c09-492f-ad60-22735f522b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018736750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2018736750
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1583954657
Short name T902
Test name
Test status
Simulation time 1084045925 ps
CPU time 16.01 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:49 PM PDT 24
Peak memory 234916 kb
Host smart-aa981a63-e4d1-47e7-aa22-813dff5d19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583954657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1583954657
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.54101928
Short name T446
Test name
Test status
Simulation time 6338623061 ps
CPU time 10.05 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:43 PM PDT 24
Peak memory 234796 kb
Host smart-3e89ba30-2233-43af-b82a-9b20ab3ebd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54101928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.54101928
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.615794363
Short name T949
Test name
Test status
Simulation time 2333717812 ps
CPU time 8.15 seconds
Started May 19 12:51:47 PM PDT 24
Finished May 19 12:51:56 PM PDT 24
Peak memory 219608 kb
Host smart-f43d6923-2aa8-4e6c-9be0-9409ae18a272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615794363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
615794363
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2300937181
Short name T344
Test name
Test status
Simulation time 31871518 ps
CPU time 2.34 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:32 PM PDT 24
Peak memory 221184 kb
Host smart-7939d523-9406-40c1-bb4b-72d518e7c31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300937181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2300937181
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4055551228
Short name T804
Test name
Test status
Simulation time 604989298 ps
CPU time 9.19 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 218768 kb
Host smart-93c53f05-3c82-4b64-aa39-a7f89c7d74fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055551228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4055551228
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4042955387
Short name T787
Test name
Test status
Simulation time 1594062514 ps
CPU time 27.04 seconds
Started May 19 12:51:32 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 237880 kb
Host smart-8881d294-3156-405f-811d-15db48aa3808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042955387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4042955387
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1479574561
Short name T459
Test name
Test status
Simulation time 3440905786 ps
CPU time 19.17 seconds
Started May 19 12:51:31 PM PDT 24
Finished May 19 12:51:53 PM PDT 24
Peak memory 216068 kb
Host smart-90a9a21b-37d3-47f7-8ce9-8b9fb2d5ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479574561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1479574561
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.262664146
Short name T361
Test name
Test status
Simulation time 1292701276 ps
CPU time 5.19 seconds
Started May 19 12:51:25 PM PDT 24
Finished May 19 12:51:35 PM PDT 24
Peak memory 216028 kb
Host smart-cd00f665-3e83-46d8-85b3-2ef8ce2a6c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262664146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.262664146
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1735241675
Short name T357
Test name
Test status
Simulation time 11990980 ps
CPU time 0.68 seconds
Started May 19 12:51:28 PM PDT 24
Finished May 19 12:51:35 PM PDT 24
Peak memory 205456 kb
Host smart-452dfaca-4a4f-40a8-9877-6b6dddcd4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735241675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1735241675
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1376757448
Short name T83
Test name
Test status
Simulation time 23994233 ps
CPU time 0.79 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:34 PM PDT 24
Peak memory 205628 kb
Host smart-3f4d9222-9ec4-4bec-b20e-87e80e8e6480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376757448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1376757448
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3567258491
Short name T942
Test name
Test status
Simulation time 2743047848 ps
CPU time 11.39 seconds
Started May 19 12:51:24 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 237052 kb
Host smart-cbf31370-9d46-44a4-a0fb-406c951820eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567258491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3567258491
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4017901603
Short name T472
Test name
Test status
Simulation time 13129737 ps
CPU time 0.69 seconds
Started May 19 12:51:40 PM PDT 24
Finished May 19 12:51:42 PM PDT 24
Peak memory 204572 kb
Host smart-cddd0e28-de03-4561-9efd-118628c9beb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017901603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
017901603
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1224426697
Short name T724
Test name
Test status
Simulation time 631715814 ps
CPU time 3.88 seconds
Started May 19 12:51:26 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 219824 kb
Host smart-2cf833d2-03f7-4a28-8c0c-751c53e77da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224426697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1224426697
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2886075974
Short name T419
Test name
Test status
Simulation time 30250399 ps
CPU time 0.78 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 206636 kb
Host smart-efb83f76-97f2-46fc-902a-f351733eae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886075974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2886075974
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3055647475
Short name T585
Test name
Test status
Simulation time 1378437154 ps
CPU time 22.12 seconds
Started May 19 12:51:27 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 240548 kb
Host smart-e259d4b9-5746-43ff-9bed-abcbed8b0d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055647475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3055647475
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.881512407
Short name T806
Test name
Test status
Simulation time 4311963831 ps
CPU time 21.8 seconds
Started May 19 12:51:36 PM PDT 24
Finished May 19 12:51:59 PM PDT 24
Peak memory 217308 kb
Host smart-1f503506-cd73-4724-91be-677ac52e5ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881512407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.881512407
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4233898421
Short name T174
Test name
Test status
Simulation time 34666524378 ps
CPU time 307.48 seconds
Started May 19 12:51:40 PM PDT 24
Finished May 19 12:56:49 PM PDT 24
Peak memory 256344 kb
Host smart-e06086ff-fa1c-4c58-a736-45280fb27b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233898421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4233898421
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1383525875
Short name T318
Test name
Test status
Simulation time 31219775440 ps
CPU time 94.95 seconds
Started May 19 12:51:35 PM PDT 24
Finished May 19 12:53:12 PM PDT 24
Peak memory 248880 kb
Host smart-7b04a552-8d74-49f0-9644-c21610868f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383525875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1383525875
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2896548085
Short name T450
Test name
Test status
Simulation time 1446917760 ps
CPU time 15.23 seconds
Started May 19 12:51:30 PM PDT 24
Finished May 19 12:51:48 PM PDT 24
Peak memory 234168 kb
Host smart-883f6fd8-d28f-485f-a89c-a914ac981590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896548085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2896548085
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1772201679
Short name T774
Test name
Test status
Simulation time 2382961534 ps
CPU time 12.62 seconds
Started May 19 12:51:38 PM PDT 24
Finished May 19 12:51:52 PM PDT 24
Peak memory 234160 kb
Host smart-2f8077c7-38e1-4ca7-a51b-b3d99fc9b87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772201679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1772201679
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2291096259
Short name T164
Test name
Test status
Simulation time 6556439497 ps
CPU time 25.11 seconds
Started May 19 12:51:30 PM PDT 24
Finished May 19 12:51:58 PM PDT 24
Peak memory 246624 kb
Host smart-b9ca0488-865c-49d7-a71a-efd8f63e01fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291096259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2291096259
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.716646460
Short name T584
Test name
Test status
Simulation time 195426881 ps
CPU time 3.86 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:51:47 PM PDT 24
Peak memory 233244 kb
Host smart-5376e960-7a31-4b95-aeb8-9c7f3054e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716646460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.716646460
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3906205786
Short name T347
Test name
Test status
Simulation time 467028599 ps
CPU time 5.36 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:38 PM PDT 24
Peak memory 222520 kb
Host smart-fc85e967-a338-41bf-8040-7d9b675821d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906205786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3906205786
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1153415464
Short name T545
Test name
Test status
Simulation time 17961470598 ps
CPU time 111.3 seconds
Started May 19 12:51:27 PM PDT 24
Finished May 19 12:53:23 PM PDT 24
Peak memory 250076 kb
Host smart-ae1838f0-64c4-4d60-a6e5-55f6eb5141f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153415464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1153415464
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.608423197
Short name T591
Test name
Test status
Simulation time 7821338058 ps
CPU time 15.9 seconds
Started May 19 12:51:37 PM PDT 24
Finished May 19 12:51:54 PM PDT 24
Peak memory 216192 kb
Host smart-7b7e0b2e-34c5-413d-819f-22798c910f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608423197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.608423197
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2574562656
Short name T492
Test name
Test status
Simulation time 1074635392 ps
CPU time 5.99 seconds
Started May 19 12:51:29 PM PDT 24
Finished May 19 12:51:38 PM PDT 24
Peak memory 215936 kb
Host smart-aa21c6fe-a300-41b1-88b6-8c052b307c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574562656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2574562656
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4004256263
Short name T177
Test name
Test status
Simulation time 334946828 ps
CPU time 3.38 seconds
Started May 19 12:51:43 PM PDT 24
Finished May 19 12:51:47 PM PDT 24
Peak memory 216220 kb
Host smart-7059d504-c2bc-49f0-9d2a-3cb431958d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004256263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4004256263
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.462133275
Short name T602
Test name
Test status
Simulation time 145343116 ps
CPU time 0.88 seconds
Started May 19 12:51:35 PM PDT 24
Finished May 19 12:51:37 PM PDT 24
Peak memory 205568 kb
Host smart-89c6d69d-b60c-4b2b-a41c-86933dfdcbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462133275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.462133275
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2080104889
Short name T364
Test name
Test status
Simulation time 1639646563 ps
CPU time 5.01 seconds
Started May 19 12:51:34 PM PDT 24
Finished May 19 12:51:41 PM PDT 24
Peak memory 232956 kb
Host smart-80a88481-d1c8-4d8f-8620-8972455f5526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080104889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2080104889
Directory /workspace/9.spi_device_upload/latest
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