Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3370293 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 3797714 1 T1 882 T2 11263 T3 1177



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 4004734 1 T1 5 T2 19292 T3 521
values[0x0] 1580977 1 T1 438 T2 5844 T3 457
values[0x1] 1582296 1 T1 445 T2 5848 T3 466



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2388982 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 4779025 1 T1 886 T2 17446 T3 1236



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25662 1 T1 10 T2 158 T3 8
valid_sources[0x01] 29826 1 T1 7 T2 182 T3 1
valid_sources[0x02] 26888 1 T1 6 T2 139 T3 12
valid_sources[0x03] 30658 1 T2 138 T5 1 T6 2
valid_sources[0x04] 25500 1 T1 3 T2 70 T5 5
valid_sources[0x05] 25974 1 T1 1 T2 38 T3 3
valid_sources[0x06] 29659 1 T1 13 T2 181 T3 1
valid_sources[0x07] 31075 1 T2 202 T3 11 T5 4
valid_sources[0x08] 32246 1 T1 5 T2 187 T3 1
valid_sources[0x09] 29542 1 T1 8 T2 152 T3 25
valid_sources[0x0a] 29652 1 T2 83 T3 10 T5 3
valid_sources[0x0b] 26859 1 T1 8 T2 120 T3 8
valid_sources[0x0c] 25703 1 T2 113 T3 20 T5 5
valid_sources[0x0d] 35748 1 T2 66 T3 4 T5 26
valid_sources[0x0e] 25436 1 T1 2 T2 166 T3 6
valid_sources[0x0f] 35059 1 T1 16 T2 94 T3 22
valid_sources[0x10] 27209 1 T1 4 T2 127 T5 1
valid_sources[0x11] 23430 1 T2 111 T3 2 T5 17
valid_sources[0x12] 24642 1 T2 92 T3 1 T5 11
valid_sources[0x13] 26625 1 T1 1 T2 121 T3 31
valid_sources[0x14] 25201 1 T2 167 T3 10 T5 1
valid_sources[0x15] 26328 1 T1 2 T2 41 T3 1
valid_sources[0x16] 25351 1 T1 4 T2 84 T3 5
valid_sources[0x17] 29875 1 T2 162 T3 1 T5 4
valid_sources[0x18] 24608 1 T1 1 T2 75 T3 7
valid_sources[0x19] 25012 1 T1 6 T2 163 T3 2
valid_sources[0x1a] 26767 1 T2 72 T5 2 T6 3
valid_sources[0x1b] 31443 1 T1 4 T2 191 T5 4
valid_sources[0x1c] 30289 1 T2 94 T3 8 T5 3
valid_sources[0x1d] 27306 1 T2 55 T3 8 T5 2
valid_sources[0x1e] 26330 1 T2 67 T3 2 T5 3
valid_sources[0x1f] 27766 1 T2 147 T5 15 T6 3
valid_sources[0x20] 26142 1 T2 186 T3 14 T5 4
valid_sources[0x21] 26524 1 T2 104 T5 2 T6 8
valid_sources[0x22] 25937 1 T2 108 T5 6 T6 4
valid_sources[0x23] 28029 1 T2 108 T3 8 T5 7
valid_sources[0x24] 27700 1 T2 89 T3 2 T5 14
valid_sources[0x25] 27674 1 T1 28 T2 146 T3 8
valid_sources[0x26] 24529 1 T1 1 T2 140 T5 1
valid_sources[0x27] 27904 1 T1 4 T2 48 T3 1
valid_sources[0x28] 31863 1 T2 178 T3 8 T5 8
valid_sources[0x29] 26236 1 T2 102 T5 4 T6 5
valid_sources[0x2a] 31434 1 T1 12 T2 115 T3 4
valid_sources[0x2b] 26812 1 T1 9 T2 123 T3 3
valid_sources[0x2c] 32162 1 T2 130 T3 20 T5 18
valid_sources[0x2d] 27706 1 T2 141 T3 7 T5 4
valid_sources[0x2e] 25333 1 T1 6 T2 73 T3 4
valid_sources[0x2f] 26421 1 T1 25 T2 136 T3 11
valid_sources[0x30] 28930 1 T1 17 T2 217 T3 13
valid_sources[0x31] 31373 1 T2 172 T3 4 T5 5
valid_sources[0x32] 28920 1 T1 7 T2 99 T3 4
valid_sources[0x33] 26552 1 T2 146 T3 6 T5 5
valid_sources[0x34] 35169 1 T2 116 T3 3 T5 21
valid_sources[0x35] 26306 1 T1 2 T2 163 T3 30
valid_sources[0x36] 25828 1 T1 2 T2 144 T5 6
valid_sources[0x37] 27170 1 T1 9 T2 164 T5 7
valid_sources[0x38] 28564 1 T2 45 T3 7 T6 7
valid_sources[0x39] 23944 1 T1 1 T2 32 T5 14
valid_sources[0x3a] 34661 1 T2 110 T3 2 T6 5
valid_sources[0x3b] 29414 1 T2 91 T3 3 T5 3
valid_sources[0x3c] 25610 1 T1 35 T2 155 T5 3
valid_sources[0x3d] 26120 1 T2 73 T3 8 T5 2
valid_sources[0x3e] 25875 1 T2 151 T3 1 T5 5
valid_sources[0x3f] 25190 1 T2 101 T3 26 T5 6
valid_sources[0x40] 29164 1 T2 242 T3 3 T5 7
valid_sources[0x41] 25580 1 T1 2 T2 36 T3 2
valid_sources[0x42] 25483 1 T1 2 T2 215 T5 2
valid_sources[0x43] 36159 1 T2 199 T5 6 T6 2
valid_sources[0x44] 25698 1 T1 3 T2 52 T5 2
valid_sources[0x45] 29335 1 T1 2 T2 122 T3 36
valid_sources[0x46] 25059 1 T1 1 T2 159 T3 2
valid_sources[0x47] 25222 1 T1 1 T2 241 T3 1
valid_sources[0x48] 28228 1 T1 1 T2 97 T5 5
valid_sources[0x49] 34472 1 T1 1 T2 110 T5 16
valid_sources[0x4a] 28380 1 T2 37 T5 2 T6 3
valid_sources[0x4b] 25632 1 T1 33 T2 107 T3 7
valid_sources[0x4c] 25677 1 T2 93 T3 9 T5 3
valid_sources[0x4d] 27042 1 T2 116 T3 2 T7 6
valid_sources[0x4e] 25622 1 T2 123 T3 6 T5 1
valid_sources[0x4f] 25864 1 T2 153 T5 7 T6 2
valid_sources[0x50] 26425 1 T1 12 T2 103 T3 3
valid_sources[0x51] 24974 1 T2 144 T5 6 T6 5
valid_sources[0x52] 26159 1 T2 193 T3 6 T5 3
valid_sources[0x53] 29710 1 T1 2 T2 73 T3 17
valid_sources[0x54] 28607 1 T2 151 T3 10 T5 1
valid_sources[0x55] 54398 1 T1 5 T2 57 T5 3
valid_sources[0x56] 32152 1 T1 14 T2 197 T5 7
valid_sources[0x57] 27557 1 T2 125 T3 12 T6 4
valid_sources[0x58] 29411 1 T1 1 T2 126 T3 7
valid_sources[0x59] 26095 1 T2 115 T3 2 T5 5
valid_sources[0x5a] 27865 1 T1 3 T2 146 T3 9
valid_sources[0x5b] 25961 1 T1 6 T2 217 T6 1
valid_sources[0x5c] 26376 1 T1 15 T2 105 T3 3
valid_sources[0x5d] 26652 1 T2 55 T3 7 T6 2
valid_sources[0x5e] 27573 1 T1 1 T2 102 T5 2
valid_sources[0x5f] 29102 1 T2 181 T3 16 T6 3
valid_sources[0x60] 26430 1 T1 1 T2 130 T4 603
valid_sources[0x61] 24756 1 T1 7 T2 91 T3 3
valid_sources[0x62] 24677 1 T1 6 T2 195 T3 3
valid_sources[0x63] 24788 1 T1 1 T2 107 T3 7
valid_sources[0x64] 25736 1 T1 8 T2 148 T5 6
valid_sources[0x65] 27371 1 T1 22 T2 102 T3 1
valid_sources[0x66] 25824 1 T2 122 T5 7 T6 2
valid_sources[0x67] 26372 1 T1 6 T2 38 T3 9
valid_sources[0x68] 26299 1 T2 150 T5 5 T6 4
valid_sources[0x69] 28198 1 T1 18 T2 74 T5 6
valid_sources[0x6a] 27292 1 T1 11 T2 139 T3 6
valid_sources[0x6b] 27565 1 T2 101 T5 5 T6 2
valid_sources[0x6c] 26313 1 T2 183 T3 9 T5 9
valid_sources[0x6d] 24728 1 T1 3 T2 172 T5 3
valid_sources[0x6e] 25733 1 T2 210 T3 2 T5 5
valid_sources[0x6f] 26863 1 T1 6 T2 137 T3 2
valid_sources[0x70] 27363 1 T1 4 T2 125 T6 4
valid_sources[0x71] 26291 1 T2 116 T5 1 T6 3
valid_sources[0x72] 26590 1 T2 139 T3 4 T5 7
valid_sources[0x73] 37728 1 T2 220 T3 6 T5 1
valid_sources[0x74] 30263 1 T2 94 T5 5 T6 3
valid_sources[0x75] 27571 1 T1 7 T2 105 T3 20
valid_sources[0x76] 28270 1 T2 62 T3 4 T5 4
valid_sources[0x77] 24697 1 T2 65 T3 4 T5 8
valid_sources[0x78] 28932 1 T1 15 T2 130 T5 5
valid_sources[0x79] 28229 1 T2 87 T3 2 T5 3
valid_sources[0x7a] 24051 1 T2 62 T5 2 T6 6
valid_sources[0x7b] 30404 1 T2 114 T3 19 T5 7
valid_sources[0x7c] 25975 1 T2 117 T5 7 T6 3
valid_sources[0x7d] 47107 1 T1 17 T2 91 T3 10
valid_sources[0x7e] 74135 1 T1 26 T2 173 T3 3
valid_sources[0x7f] 25309 1 T1 6 T2 49 T5 10
valid_sources[0x80] 26139 1 T2 136 T3 11 T5 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 941978 1 T1 3 T2 1573 T3 261
values[0x0] all_enables biggest_size 1438404 1 T1 437 T2 4857 T3 455
values[0x1] all_enables biggest_size 1417332 1 T1 442 T2 4833 T3 461

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%