Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3390094

1

T1

6

T2

19721

T3

267

full_word

3798931

1

T1

882

T2

11263

T3

1177

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7188625	1			T1	888		T2	30984		T3	1444
auto[TlIntgErrCmd]	144	1			T114	3		T115	10		T116	8
auto[TlIntgErrData]	131	1			T114	3		T115	8		T116	7
auto[TlIntgErrBoth]	125	1			T114	4		T115	12		T116	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4007856

1

T1

5

T2

19292

T3

521

auto[1]

3181169

1

T1

883

T2

11692

T3

923

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3065486	1			T1	2		T2	17719		T3	260
auto[TlIntgErrNone]	partial	auto[1]	324242	1			T1	4		T2	2002		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	942198	1			T1	3		T2	1573		T3	261
auto[TlIntgErrNone]	full_word	auto[1]	2856699	1			T1	879		T2	9690		T3	916
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T114	2		T115	5		T116	3
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T114	1		T115	3		T116	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T115	2		T165	1		T275	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T116	2		T165	1		T274	2
auto[TlIntgErrData]	partial	auto[0]	43	1			T114	2		T115	3		T116	2
auto[TlIntgErrData]	partial	auto[1]	75	1			T114	1		T115	5		T116	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T274	1		T278	1		T279	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T165	1		T273	1		T280	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T114	1		T115	8		T116	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T114	3		T115	3		T116	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T281	1		T165	1		T277	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T115	1		T274	1		T275	1