Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	527506291	2721766	0	0
gen_wmask[1].MaskCheckPortA_A	527506291	2721766	0	0
gen_wmask[2].MaskCheckPortA_A	527506291	2721766	0	0
gen_wmask[3].MaskCheckPortA_A	527506291	2721766	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527506291	2721766	0	0
T1	63085	832	0	0
T2	383464	7192	0	0
T3	60806	832	0	0
T4	8611	77	0	0
T5	63782	832	0	0
T6	3091	832	0	0
T7	45080	832	0	0
T8	1361	0	0	0
T9	362696	832	0	0
T10	178700	832	0	0
T11	38866	1088	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527506291	2721766	0	0
T1	63085	832	0	0
T2	383464	7192	0	0
T3	60806	832	0	0
T4	8611	77	0	0
T5	63782	832	0	0
T6	3091	832	0	0
T7	45080	832	0	0
T8	1361	0	0	0
T9	362696	832	0	0
T10	178700	832	0	0
T11	38866	1088	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527506291	2721766	0	0
T1	63085	832	0	0
T2	383464	7192	0	0
T3	60806	832	0	0
T4	8611	77	0	0
T5	63782	832	0	0
T6	3091	832	0	0
T7	45080	832	0	0
T8	1361	0	0	0
T9	362696	832	0	0
T10	178700	832	0	0
T11	38866	1088	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527506291	2721766	0	0
T1	63085	832	0	0
T2	383464	7192	0	0
T3	60806	832	0	0
T4	8611	77	0	0
T5	63782	832	0	0
T6	3091	832	0	0
T7	45080	832	0	0
T8	1361	0	0	0
T9	362696	832	0	0
T10	178700	832	0	0
T11	38866	1088	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	394330459	1839850	0	0
gen_wmask[1].MaskCheckPortA_A	394330459	1839850	0	0
gen_wmask[2].MaskCheckPortA_A	394330459	1839850	0	0
gen_wmask[3].MaskCheckPortA_A	394330459	1839850	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1839850	0	0
T1	63085	832	0	0
T2	157570	3702	0	0
T3	19407	832	0	0
T4	7330	6	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1839850	0	0
T1	63085	832	0	0
T2	157570	3702	0	0
T3	19407	832	0	0
T4	7330	6	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1839850	0	0
T1	63085	832	0	0
T2	157570	3702	0	0
T3	19407	832	0	0
T4	7330	6	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1839850	0	0
T1	63085	832	0	0
T2	157570	3702	0	0
T3	19407	832	0	0
T4	7330	6	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	133175832	881916	0	0
gen_wmask[1].MaskCheckPortA_A	133175832	881916	0	0
gen_wmask[2].MaskCheckPortA_A	133175832	881916	0	0
gen_wmask[3].MaskCheckPortA_A	133175832	881916	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	881916	0	0
T2	225894	3490	0	0
T3	41399	0	0	0
T4	1281	71	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	881916	0	0
T2	225894	3490	0	0
T3	41399	0	0	0
T4	1281	71	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	881916	0	0
T2	225894	3490	0	0
T3	41399	0	0	0
T4	1281	71	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	881916	0	0
T2	225894	3490	0	0
T3	41399	0	0	0
T4	1281	71	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	10132	0	0
T15	0	1778	0	0
T17	0	90	0	0
T19	0	325	0	0
T26	0	99	0	0
T27	0	2	0	0
T28	0	6	0	0