Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Covered	T2,T11,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T12
1	0	Covered	T2,T11,T12
1	1	Covered	T2,T11,T12

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1182991377	2271	0	0
SrcPulseCheck_M	399527496	2271	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182991377	2271	0	0
T2	157570	4	0	0
T3	19407	0	0	0
T4	7330	0	0	0
T5	17830	0	0	0
T6	3059	0	0	0
T7	21553	0	0	0
T8	1361	0	0	0
T9	290860	0	0	0
T10	61736	0	0	0
T11	628968	3	0	0
T12	326964	10	0	0
T13	825	0	0	0
T14	211670	11	0	0
T15	696626	0	0	0
T16	10088	0	0	0
T17	5090	0	0	0
T18	6880	0	0	0
T19	74156	0	0	0
T20	10714	0	0	0
T21	0	8	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	2	0	0
T31	0	10	0	0
T38	13978	0	0	0
T40	0	7	0	0
T41	0	7	0	0
T42	0	26	0	0
T62	0	2	0	0
T143	0	7	0	0
T155	0	7	0	0
T156	0	16	0	0
T157	0	7	0	0
T158	0	7	0	0
T159	0	7	0	0
T160	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399527496	2271	0	0
T2	225894	4	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	116598	3	0	0
T12	896217	10	0	0
T14	203640	11	0	0
T15	170154	0	0	0
T16	3266	0	0	0
T17	2368	0	0	0
T18	1880	0	0	0
T19	10192	0	0	0
T20	1136	0	0	0
T21	0	8	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	2	0	0
T31	0	10	0	0
T38	4320	0	0	0
T40	0	7	0	0
T41	0	7	0	0
T42	0	26	0	0
T62	0	2	0	0
T143	0	7	0	0
T155	0	7	0	0
T156	0	16	0	0
T157	0	7	0	0
T158	0	7	0	0
T159	0	7	0	0
T160	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T40,T41
1	0	Covered	T11,T40,T41
1	1	Covered	T11,T40,T41

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T40,T41
1	0	Covered	T11,T40,T41
1	1	Covered	T11,T40,T41

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	394330459	175	0	0
SrcPulseCheck_M	133175832	175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	175	0	0
T11	314484	2	0	0
T12	163482	0	0	0
T14	105835	0	0	0
T15	348313	0	0	0
T16	5044	0	0	0
T17	2545	0	0	0
T18	3440	0	0	0
T19	37078	0	0	0
T20	5357	0	0	0
T38	6989	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T143	0	2	0	0
T155	0	2	0	0
T156	0	8	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	175	0	0
T11	38866	2	0	0
T12	298739	0	0	0
T14	101820	0	0	0
T15	85077	0	0	0
T16	1633	0	0	0
T17	1184	0	0	0
T18	940	0	0	0
T19	5096	0	0	0
T20	568	0	0	0
T38	2160	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T143	0	2	0	0
T155	0	2	0	0
T156	0	8	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T40,T41
1	0	Covered	T11,T40,T41
1	1	Covered	T40,T41,T155

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T40,T41
1	0	Covered	T40,T41,T155
1	1	Covered	T11,T40,T41

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	394330459	332	0	0
SrcPulseCheck_M	133175832	332	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	332	0	0
T11	314484	1	0	0
T12	163482	0	0	0
T14	105835	0	0	0
T15	348313	0	0	0
T16	5044	0	0	0
T17	2545	0	0	0
T18	3440	0	0	0
T19	37078	0	0	0
T20	5357	0	0	0
T38	6989	0	0	0
T40	0	5	0	0
T41	0	5	0	0
T143	0	5	0	0
T155	0	5	0	0
T156	0	8	0	0
T157	0	5	0	0
T158	0	5	0	0
T159	0	5	0	0
T160	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	332	0	0
T11	38866	1	0	0
T12	298739	0	0	0
T14	101820	0	0	0
T15	85077	0	0	0
T16	1633	0	0	0
T17	1184	0	0	0
T18	940	0	0	0
T19	5096	0	0	0
T20	568	0	0	0
T38	2160	0	0	0
T40	0	5	0	0
T41	0	5	0	0
T143	0	5	0	0
T155	0	5	0	0
T156	0	8	0	0
T157	0	5	0	0
T158	0	5	0	0
T159	0	5	0	0
T160	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14
1	1	Covered	T2,T12,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14
1	1	Covered	T2,T12,T14

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	394330459	1764	0	0
SrcPulseCheck_M	133175832	1764	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1764	0	0
T2	157570	4	0	0
T3	19407	0	0	0
T4	7330	0	0	0
T5	17830	0	0	0
T6	3059	0	0	0
T7	21553	0	0	0
T8	1361	0	0	0
T9	290860	0	0	0
T10	61736	0	0	0
T12	0	10	0	0
T13	825	0	0	0
T14	0	11	0	0
T21	0	8	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	2	0	0
T31	0	10	0	0
T42	0	26	0	0
T62	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	1764	0	0
T2	225894	4	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	10	0	0
T14	0	11	0	0
T21	0	8	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	2	0	0
T31	0	10	0	0
T42	0	26	0	0
T62	0	2	0	0