Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Unreachable
1	1	Covered	T2,T4,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	660682123	526132774	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	660682123	3080255	0	0
GntImpliesValid_A	660682123	3080255	0	0
GrantKnown_A	660682123	526132774	0	0
IdxKnown_A	660682123	526132774	0	0
IndexIsCorrect_A	660682123	3080255	0	0
LockArbDecision_A	660682123	0	0	0
NoReadyValidNoGrant_A	660682123	0	0	0
ReadyAndValidImplyGrant_A	660682123	3080255	0	0
ReqAndReadyImplyGrant_A	660682123	3080255	0	0
ReqImpliesValid_A	660682123	3080255	0	0
ReqStaysHighUntilGranted0_M	660682123	0	0	0
RoundRobin_A	660682123	8	0	906
ValidKnown_A	660682123	526132774	0	0
gen_data_port_assertion.DataFlow_A	660682123	3080255	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	526132774	0	0
T1	115103	115033	0	0
T2	609358	378311	0	0
T3	102205	60302	0	0
T4	9892	8293	0	0
T5	109734	63711	0	0
T6	3123	3017	0	0
T7	68607	44329	0	0
T8	1361	1290	0	0
T9	434532	362635	0	0
T10	295664	178630	0	0
T11	77732	38866	0	0
T12	298739	295780	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	526132774	0	0
T1	115103	115033	0	0
T2	609358	378311	0	0
T3	102205	60302	0	0
T4	9892	8293	0	0
T5	109734	63711	0	0
T6	3123	3017	0	0
T7	68607	44329	0	0
T8	1361	1290	0	0
T9	434532	362635	0	0
T10	295664	178630	0	0
T11	77732	38866	0	0
T12	298739	295780	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	526132774	0	0
T1	115103	115033	0	0
T2	609358	378311	0	0
T3	102205	60302	0	0
T4	9892	8293	0	0
T5	109734	63711	0	0
T6	3123	3017	0	0
T7	68607	44329	0	0
T8	1361	1290	0	0
T9	434532	362635	0	0
T10	295664	178630	0	0
T11	77732	38866	0	0
T12	298739	295780	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	8	0	906
T22	677246	0	0	1
T46	349612	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	1820	0	0	1
T55	225016	0	0	1
T56	2761	0	0	1
T57	194892	0	0	1
T58	10824	0	0	1
T59	101723	0	0	1
T60	545517	0	0	1
T61	19916	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	526132774	0	0
T1	115103	115033	0	0
T2	609358	378311	0	0
T3	102205	60302	0	0
T4	9892	8293	0	0
T5	109734	63711	0	0
T6	3123	3017	0	0
T7	68607	44329	0	0
T8	1361	1290	0	0
T9	434532	362635	0	0
T10	295664	178630	0	0
T11	77732	38866	0	0
T12	298739	295780	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660682123	3080255	0	0
T1	63085	832	0	0
T2	609358	9191	0	0
T3	102205	832	0	0
T4	9892	104	0	0
T5	109734	832	0	0
T6	3123	832	0	0
T7	68607	832	0	0
T8	1361	0	0	0
T9	434532	832	0	0
T10	295664	832	0	0
T11	77732	1088	0	0
T12	597478	705	0	0
T14	0	11135	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T21	0	7523	0	0
T26	0	106	0	0
T27	0	5	0	0
T28	0	6	0	0
T45	0	55	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T14
1	0	Covered	T2,T4,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Unreachable
1	1	Covered	T2,T4,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133175832	28129721	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	133175832	620190	0	0
GntImpliesValid_A	133175832	620190	0	0
GrantKnown_A	133175832	28129721	0	0
IdxKnown_A	133175832	28129721	0	0
IndexIsCorrect_A	133175832	620190	0	0
LockArbDecision_A	133175832	0	0	0
NoReadyValidNoGrant_A	133175832	0	0	0
ReadyAndValidImplyGrant_A	133175832	620190	0	0
ReqAndReadyImplyGrant_A	133175832	620190	0	0
ReqImpliesValid_A	133175832	620190	0	0
ReqStaysHighUntilGranted0_M	133175832	0	0	0
RoundRobin_A	133175832	0	0	0
ValidKnown_A	133175832	28129721	0	0
gen_data_port_assertion.DataFlow_A	133175832	620190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	28129721	0	0
T2	225894	78392	0	0
T3	41399	0	0	0
T4	1281	1024	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	28129721	0	0
T2	225894	78392	0	0
T3	41399	0	0	0
T4	1281	1024	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	28129721	0	0
T2	225894	78392	0	0
T3	41399	0	0	0
T4	1281	1024	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	28129721	0	0
T2	225894	78392	0	0
T3	41399	0	0	0
T4	1281	1024	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	108664	0	0
T15	0	82184	0	0
T16	0	936	0	0
T17	0	1184	0	0
T18	0	504	0	0
T19	0	5096	0	0
T20	0	568	0	0
T26	0	1136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	620190	0	0
T2	225894	3444	0	0
T3	41399	0	0	0
T4	1281	79	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	0	0	0
T14	0	2977	0	0
T15	0	3142	0	0
T17	0	95	0	0
T19	0	390	0	0
T20	0	17	0	0
T26	0	106	0	0
T27	0	5	0	0
T45	0	55	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T12,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133175832	103757846	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	133175832	472271	0	0
GntImpliesValid_A	133175832	472271	0	0
GrantKnown_A	133175832	103757846	0	0
IdxKnown_A	133175832	103757846	0	0
IndexIsCorrect_A	133175832	472271	0	0
LockArbDecision_A	133175832	0	0	0
NoReadyValidNoGrant_A	133175832	0	0	0
ReadyAndValidImplyGrant_A	133175832	472271	0	0
ReqAndReadyImplyGrant_A	133175832	472271	0	0
ReqImpliesValid_A	133175832	472271	0	0
ReqStaysHighUntilGranted0_M	133175832	0	0	0
RoundRobin_A	133175832	0	0	0
ValidKnown_A	133175832	103757846	0	0
gen_data_port_assertion.DataFlow_A	133175832	472271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	103757846	0	0
T1	52018	52000	0	0
T2	225894	142383	0	0
T3	41399	40976	0	0
T4	1281	0	0	0
T5	45952	45952	0	0
T6	32	32	0	0
T7	23527	22860	0	0
T9	71836	71836	0	0
T10	116964	116964	0	0
T11	38866	38866	0	0
T12	0	295780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	103757846	0	0
T1	52018	52000	0	0
T2	225894	142383	0	0
T3	41399	40976	0	0
T4	1281	0	0	0
T5	45952	45952	0	0
T6	32	32	0	0
T7	23527	22860	0	0
T9	71836	71836	0	0
T10	116964	116964	0	0
T11	38866	38866	0	0
T12	0	295780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	103757846	0	0
T1	52018	52000	0	0
T2	225894	142383	0	0
T3	41399	40976	0	0
T4	1281	0	0	0
T5	45952	45952	0	0
T6	32	32	0	0
T7	23527	22860	0	0
T9	71836	71836	0	0
T10	116964	116964	0	0
T11	38866	38866	0	0
T12	0	295780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	103757846	0	0
T1	52018	52000	0	0
T2	225894	142383	0	0
T3	41399	40976	0	0
T4	1281	0	0	0
T5	45952	45952	0	0
T6	32	32	0	0
T7	23527	22860	0	0
T9	71836	71836	0	0
T10	116964	116964	0	0
T11	38866	38866	0	0
T12	0	295780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133175832	472271	0	0
T2	225894	1361	0	0
T3	41399	0	0	0
T4	1281	0	0	0
T5	45952	0	0	0
T6	32	0	0	0
T7	23527	0	0	0
T9	71836	0	0	0
T10	116964	0	0	0
T11	38866	0	0	0
T12	298739	705	0	0
T14	0	8158	0	0
T21	0	7523	0	0
T25	0	1942	0	0
T28	0	6	0	0
T30	0	2	0	0
T31	0	5984	0	0
T42	0	807	0	0
T62	0	3148	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394330459	394245207	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	394330459	1987794	0	0
GntImpliesValid_A	394330459	1987794	0	0
GrantKnown_A	394330459	394245207	0	0
IdxKnown_A	394330459	394245207	0	0
IndexIsCorrect_A	394330459	1987794	0	0
LockArbDecision_A	394330459	0	0	0
NoReadyValidNoGrant_A	394330459	0	0	0
ReadyAndValidImplyGrant_A	394330459	1987794	0	0
ReqAndReadyImplyGrant_A	394330459	1987794	0	0
ReqImpliesValid_A	394330459	1987794	0	0
ReqStaysHighUntilGranted0_M	394330459	0	0	0
RoundRobin_A	394330459	8	0	906
ValidKnown_A	394330459	394245207	0	0
gen_data_port_assertion.DataFlow_A	394330459	1987794	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	394245207	0	0
T1	63085	63033	0	0
T2	157570	157536	0	0
T3	19407	19326	0	0
T4	7330	7269	0	0
T5	17830	17759	0	0
T6	3059	2985	0	0
T7	21553	21469	0	0
T8	1361	1290	0	0
T9	290860	290799	0	0
T10	61736	61666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	394245207	0	0
T1	63085	63033	0	0
T2	157570	157536	0	0
T3	19407	19326	0	0
T4	7330	7269	0	0
T5	17830	17759	0	0
T6	3059	2985	0	0
T7	21553	21469	0	0
T8	1361	1290	0	0
T9	290860	290799	0	0
T10	61736	61666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	394245207	0	0
T1	63085	63033	0	0
T2	157570	157536	0	0
T3	19407	19326	0	0
T4	7330	7269	0	0
T5	17830	17759	0	0
T6	3059	2985	0	0
T7	21553	21469	0	0
T8	1361	1290	0	0
T9	290860	290799	0	0
T10	61736	61666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	8	0	906
T22	677246	0	0	1
T46	349612	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	1820	0	0	1
T55	225016	0	0	1
T56	2761	0	0	1
T57	194892	0	0	1
T58	10824	0	0	1
T59	101723	0	0	1
T60	545517	0	0	1
T61	19916	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	394245207	0	0
T1	63085	63033	0	0
T2	157570	157536	0	0
T3	19407	19326	0	0
T4	7330	7269	0	0
T5	17830	17759	0	0
T6	3059	2985	0	0
T7	21553	21469	0	0
T8	1361	1290	0	0
T9	290860	290799	0	0
T10	61736	61666	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394330459	1987794	0	0
T1	63085	832	0	0
T2	157570	4386	0	0
T3	19407	832	0	0
T4	7330	25	0	0
T5	17830	832	0	0
T6	3059	832	0	0
T7	21553	832	0	0
T8	1361	0	0	0
T9	290860	832	0	0
T10	61736	832	0	0
T11	0	1088	0	0