| T820 |
/workspace/coverage/default/5.spi_device_tpm_all.2691595754 |
|
|
May 21 12:26:23 PM PDT 24 |
May 21 12:27:12 PM PDT 24 |
16734282 ps |
| T821 |
/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2630039089 |
|
|
May 21 12:26:55 PM PDT 24 |
May 21 12:28:05 PM PDT 24 |
14936119167 ps |
| T822 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.3342924095 |
|
|
May 21 12:26:08 PM PDT 24 |
May 21 12:26:39 PM PDT 24 |
5096685220 ps |
| T254 |
/workspace/coverage/default/1.spi_device_stress_all.3489649584 |
|
|
May 21 12:26:22 PM PDT 24 |
May 21 12:31:01 PM PDT 24 |
37988534395 ps |
| T823 |
/workspace/coverage/default/40.spi_device_cfg_cmd.3896562772 |
|
|
May 21 12:27:48 PM PDT 24 |
May 21 12:28:56 PM PDT 24 |
1182193253 ps |
| T824 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.3217574394 |
|
|
May 21 12:27:17 PM PDT 24 |
May 21 12:28:18 PM PDT 24 |
20612536 ps |
| T825 |
/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.760953646 |
|
|
May 21 12:27:33 PM PDT 24 |
May 21 12:28:39 PM PDT 24 |
381944490 ps |
| T826 |
/workspace/coverage/default/6.spi_device_flash_all.2455813082 |
|
|
May 21 12:26:25 PM PDT 24 |
May 21 12:27:32 PM PDT 24 |
11614205074 ps |
| T827 |
/workspace/coverage/default/32.spi_device_flash_mode.1016933973 |
|
|
May 21 12:27:22 PM PDT 24 |
May 21 12:28:25 PM PDT 24 |
134238058 ps |
| T828 |
/workspace/coverage/default/7.spi_device_flash_and_tpm.1171589873 |
|
|
May 21 12:26:18 PM PDT 24 |
May 21 12:28:05 PM PDT 24 |
13360913468 ps |
| T829 |
/workspace/coverage/default/10.spi_device_mailbox.3915378125 |
|
|
May 21 12:26:25 PM PDT 24 |
May 21 12:28:20 PM PDT 24 |
30735575031 ps |
| T830 |
/workspace/coverage/default/7.spi_device_upload.3218738928 |
|
|
May 21 12:26:34 PM PDT 24 |
May 21 12:27:39 PM PDT 24 |
4782023748 ps |
| T831 |
/workspace/coverage/default/25.spi_device_pass_cmd_filtering.131383235 |
|
|
May 21 12:27:07 PM PDT 24 |
May 21 12:28:12 PM PDT 24 |
453876619 ps |
| T253 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.233692918 |
|
|
May 21 12:27:42 PM PDT 24 |
May 21 12:33:19 PM PDT 24 |
103058073893 ps |
| T832 |
/workspace/coverage/default/15.spi_device_cfg_cmd.2231667971 |
|
|
May 21 12:26:33 PM PDT 24 |
May 21 12:27:44 PM PDT 24 |
3665942813 ps |
| T833 |
/workspace/coverage/default/12.spi_device_csb_read.1323295239 |
|
|
May 21 12:26:38 PM PDT 24 |
May 21 12:27:37 PM PDT 24 |
16823515 ps |
| T834 |
/workspace/coverage/default/33.spi_device_flash_mode.3722553235 |
|
|
May 21 12:27:16 PM PDT 24 |
May 21 12:28:22 PM PDT 24 |
335815820 ps |
| T835 |
/workspace/coverage/default/47.spi_device_alert_test.826000643 |
|
|
May 21 12:28:21 PM PDT 24 |
May 21 12:29:08 PM PDT 24 |
11708453 ps |
| T836 |
/workspace/coverage/default/20.spi_device_flash_and_tpm.3394160803 |
|
|
May 21 12:27:00 PM PDT 24 |
May 21 12:34:39 PM PDT 24 |
44521498625 ps |
| T837 |
/workspace/coverage/default/37.spi_device_tpm_sts_read.755730218 |
|
|
May 21 12:27:38 PM PDT 24 |
May 21 12:28:38 PM PDT 24 |
98204813 ps |
| T838 |
/workspace/coverage/default/13.spi_device_flash_all.446782101 |
|
|
May 21 12:26:38 PM PDT 24 |
May 21 12:28:27 PM PDT 24 |
2521030466 ps |
| T839 |
/workspace/coverage/default/43.spi_device_intercept.3040160640 |
|
|
May 21 12:28:05 PM PDT 24 |
May 21 12:29:08 PM PDT 24 |
8384332432 ps |
| T840 |
/workspace/coverage/default/11.spi_device_alert_test.1298177037 |
|
|
May 21 12:26:26 PM PDT 24 |
May 21 12:27:19 PM PDT 24 |
28309677 ps |
| T841 |
/workspace/coverage/default/32.spi_device_tpm_sts_read.3053685739 |
|
|
May 21 12:27:24 PM PDT 24 |
May 21 12:28:25 PM PDT 24 |
32821985 ps |
| T842 |
/workspace/coverage/default/16.spi_device_tpm_rw.1057798787 |
|
|
May 21 12:26:35 PM PDT 24 |
May 21 12:27:36 PM PDT 24 |
1187486384 ps |
| T24 |
/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2565658315 |
|
|
May 21 12:27:06 PM PDT 24 |
May 21 12:28:34 PM PDT 24 |
5925455235 ps |
| T843 |
/workspace/coverage/default/5.spi_device_pass_cmd_filtering.1198321859 |
|
|
May 21 12:26:27 PM PDT 24 |
May 21 12:27:23 PM PDT 24 |
311371863 ps |
| T844 |
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.636725436 |
|
|
May 21 12:26:30 PM PDT 24 |
May 21 12:27:30 PM PDT 24 |
1412573452 ps |
| T845 |
/workspace/coverage/default/49.spi_device_flash_mode.3845010133 |
|
|
May 21 12:28:25 PM PDT 24 |
May 21 12:29:31 PM PDT 24 |
1385522359 ps |
| T846 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2846042767 |
|
|
May 21 12:28:07 PM PDT 24 |
May 21 12:29:07 PM PDT 24 |
3164571547 ps |
| T847 |
/workspace/coverage/default/48.spi_device_read_buffer_direct.2916415557 |
|
|
May 21 12:28:18 PM PDT 24 |
May 21 12:29:14 PM PDT 24 |
4055436828 ps |
| T848 |
/workspace/coverage/default/9.spi_device_alert_test.3338583545 |
|
|
May 21 12:26:31 PM PDT 24 |
May 21 12:27:27 PM PDT 24 |
39736731 ps |
| T849 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1431654905 |
|
|
May 21 12:27:08 PM PDT 24 |
May 21 12:28:15 PM PDT 24 |
3161752247 ps |
| T850 |
/workspace/coverage/default/19.spi_device_cfg_cmd.3419845739 |
|
|
May 21 12:26:57 PM PDT 24 |
May 21 12:27:57 PM PDT 24 |
128776213 ps |
| T851 |
/workspace/coverage/default/15.spi_device_tpm_rw.1248158296 |
|
|
May 21 12:26:51 PM PDT 24 |
May 21 12:27:49 PM PDT 24 |
22104118 ps |
| T852 |
/workspace/coverage/default/46.spi_device_alert_test.3170570718 |
|
|
May 21 12:28:13 PM PDT 24 |
May 21 12:29:02 PM PDT 24 |
18051436 ps |
| T239 |
/workspace/coverage/default/31.spi_device_flash_and_tpm.2567560872 |
|
|
May 21 12:27:16 PM PDT 24 |
May 21 12:30:39 PM PDT 24 |
19640190418 ps |
| T853 |
/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1220912896 |
|
|
May 21 12:28:14 PM PDT 24 |
May 21 12:29:14 PM PDT 24 |
66843077395 ps |
| T854 |
/workspace/coverage/default/12.spi_device_tpm_rw.3454961760 |
|
|
May 21 12:26:17 PM PDT 24 |
May 21 12:27:06 PM PDT 24 |
239044293 ps |
| T855 |
/workspace/coverage/default/32.spi_device_read_buffer_direct.3481322449 |
|
|
May 21 12:27:20 PM PDT 24 |
May 21 12:28:33 PM PDT 24 |
4290941034 ps |
| T266 |
/workspace/coverage/default/30.spi_device_stress_all.3988669005 |
|
|
May 21 12:27:16 PM PDT 24 |
May 21 12:32:27 PM PDT 24 |
14711401375 ps |
| T856 |
/workspace/coverage/default/18.spi_device_pass_cmd_filtering.1020842776 |
|
|
May 21 12:26:46 PM PDT 24 |
May 21 12:28:04 PM PDT 24 |
29114227538 ps |
| T857 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3371603117 |
|
|
May 21 12:26:18 PM PDT 24 |
May 21 12:29:18 PM PDT 24 |
20051658232 ps |
| T858 |
/workspace/coverage/default/20.spi_device_read_buffer_direct.2836194989 |
|
|
May 21 12:26:48 PM PDT 24 |
May 21 12:27:53 PM PDT 24 |
1787727810 ps |
| T859 |
/workspace/coverage/default/6.spi_device_flash_and_tpm.2729513182 |
|
|
May 21 12:26:14 PM PDT 24 |
May 21 12:28:31 PM PDT 24 |
120982275010 ps |
| T860 |
/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3503826865 |
|
|
May 21 12:27:21 PM PDT 24 |
May 21 12:28:28 PM PDT 24 |
2515321323 ps |
| T861 |
/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1177107592 |
|
|
May 21 12:26:42 PM PDT 24 |
May 21 12:35:25 PM PDT 24 |
185049550774 ps |
| T862 |
/workspace/coverage/default/39.spi_device_pass_cmd_filtering.125071283 |
|
|
May 21 12:27:52 PM PDT 24 |
May 21 12:28:59 PM PDT 24 |
7070779768 ps |
| T863 |
/workspace/coverage/default/21.spi_device_tpm_rw.220367913 |
|
|
May 21 12:26:47 PM PDT 24 |
May 21 12:27:45 PM PDT 24 |
134417027 ps |
| T864 |
/workspace/coverage/default/36.spi_device_stress_all.3876673457 |
|
|
May 21 12:27:38 PM PDT 24 |
May 21 12:28:39 PM PDT 24 |
39979791 ps |
| T865 |
/workspace/coverage/default/33.spi_device_tpm_all.1339414313 |
|
|
May 21 12:27:24 PM PDT 24 |
May 21 12:28:45 PM PDT 24 |
1360404895 ps |
| T866 |
/workspace/coverage/default/22.spi_device_tpm_rw.3304166668 |
|
|
May 21 12:26:46 PM PDT 24 |
May 21 12:27:45 PM PDT 24 |
13551918 ps |
| T867 |
/workspace/coverage/default/18.spi_device_stress_all.1859554074 |
|
|
May 21 12:26:48 PM PDT 24 |
May 21 12:29:58 PM PDT 24 |
53542654160 ps |
| T868 |
/workspace/coverage/default/1.spi_device_csb_read.4005359494 |
|
|
May 21 12:26:11 PM PDT 24 |
May 21 12:26:44 PM PDT 24 |
20419799 ps |
| T251 |
/workspace/coverage/default/29.spi_device_flash_and_tpm.381947215 |
|
|
May 21 12:27:14 PM PDT 24 |
May 21 12:37:44 PM PDT 24 |
301749574427 ps |
| T869 |
/workspace/coverage/default/38.spi_device_tpm_all.2999591760 |
|
|
May 21 12:27:43 PM PDT 24 |
May 21 12:28:47 PM PDT 24 |
1032802633 ps |
| T870 |
/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2749311800 |
|
|
May 21 12:26:35 PM PDT 24 |
May 21 12:27:35 PM PDT 24 |
1090491970 ps |
| T871 |
/workspace/coverage/default/36.spi_device_tpm_rw.1492723319 |
|
|
May 21 12:27:34 PM PDT 24 |
May 21 12:28:37 PM PDT 24 |
786302566 ps |
| T872 |
/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.270822703 |
|
|
May 21 12:27:25 PM PDT 24 |
May 21 12:28:33 PM PDT 24 |
529802822 ps |
| T873 |
/workspace/coverage/default/42.spi_device_pass_cmd_filtering.3615551634 |
|
|
May 21 12:27:53 PM PDT 24 |
May 21 12:28:54 PM PDT 24 |
1352424789 ps |
| T52 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.895135572 |
|
|
May 21 12:26:37 PM PDT 24 |
May 21 12:29:55 PM PDT 24 |
189732324604 ps |
| T874 |
/workspace/coverage/default/13.spi_device_csb_read.488240808 |
|
|
May 21 12:26:47 PM PDT 24 |
May 21 12:27:45 PM PDT 24 |
30984389 ps |
| T875 |
/workspace/coverage/default/35.spi_device_flash_mode.3290814594 |
|
|
May 21 12:27:34 PM PDT 24 |
May 21 12:28:42 PM PDT 24 |
843047678 ps |
| T876 |
/workspace/coverage/default/43.spi_device_stress_all.1539973411 |
|
|
May 21 12:28:04 PM PDT 24 |
May 21 12:28:56 PM PDT 24 |
94493128 ps |
| T877 |
/workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1190984420 |
|
|
May 21 12:28:01 PM PDT 24 |
May 21 12:29:22 PM PDT 24 |
2609979325 ps |
| T878 |
/workspace/coverage/default/21.spi_device_stress_all.618954038 |
|
|
May 21 12:26:58 PM PDT 24 |
May 21 12:32:22 PM PDT 24 |
38864574717 ps |
| T879 |
/workspace/coverage/default/11.spi_device_cfg_cmd.3904298248 |
|
|
May 21 12:26:28 PM PDT 24 |
May 21 12:27:29 PM PDT 24 |
814353462 ps |
| T880 |
/workspace/coverage/default/29.spi_device_cfg_cmd.1040132756 |
|
|
May 21 12:27:09 PM PDT 24 |
May 21 12:28:12 PM PDT 24 |
85836515 ps |
| T881 |
/workspace/coverage/default/44.spi_device_tpm_rw.1778685598 |
|
|
May 21 12:28:10 PM PDT 24 |
May 21 12:29:00 PM PDT 24 |
50637057 ps |
| T882 |
/workspace/coverage/default/18.spi_device_cfg_cmd.3455381207 |
|
|
May 21 12:26:45 PM PDT 24 |
May 21 12:27:45 PM PDT 24 |
124533652 ps |
| T883 |
/workspace/coverage/default/23.spi_device_tpm_rw.665384622 |
|
|
May 21 12:27:04 PM PDT 24 |
May 21 12:28:06 PM PDT 24 |
246218900 ps |
| T884 |
/workspace/coverage/default/19.spi_device_pass_cmd_filtering.2342663220 |
|
|
May 21 12:26:54 PM PDT 24 |
May 21 12:27:56 PM PDT 24 |
361484639 ps |
| T885 |
/workspace/coverage/default/7.spi_device_cfg_cmd.2442258577 |
|
|
May 21 12:26:19 PM PDT 24 |
May 21 12:27:10 PM PDT 24 |
202471206 ps |
| T886 |
/workspace/coverage/default/8.spi_device_tpm_rw.3889066802 |
|
|
May 21 12:26:15 PM PDT 24 |
May 21 12:26:58 PM PDT 24 |
169213441 ps |
| T887 |
/workspace/coverage/default/25.spi_device_read_buffer_direct.2801410129 |
|
|
May 21 12:27:04 PM PDT 24 |
May 21 12:28:07 PM PDT 24 |
147557981 ps |
| T888 |
/workspace/coverage/default/21.spi_device_read_buffer_direct.1196785110 |
|
|
May 21 12:27:07 PM PDT 24 |
May 21 12:28:26 PM PDT 24 |
1250011257 ps |
| T889 |
/workspace/coverage/default/12.spi_device_stress_all.2307784660 |
|
|
May 21 12:27:02 PM PDT 24 |
May 21 12:28:03 PM PDT 24 |
58848154 ps |
| T890 |
/workspace/coverage/default/29.spi_device_alert_test.3406740306 |
|
|
May 21 12:27:12 PM PDT 24 |
May 21 12:28:14 PM PDT 24 |
12126808 ps |
| T891 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2636700137 |
|
|
May 21 12:27:29 PM PDT 24 |
May 21 12:28:48 PM PDT 24 |
42126883776 ps |
| T892 |
/workspace/coverage/default/12.spi_device_pass_cmd_filtering.930207964 |
|
|
May 21 12:26:24 PM PDT 24 |
May 21 12:27:20 PM PDT 24 |
715321487 ps |
| T893 |
/workspace/coverage/default/35.spi_device_tpm_rw.210072538 |
|
|
May 21 12:27:28 PM PDT 24 |
May 21 12:28:30 PM PDT 24 |
1008875429 ps |
| T894 |
/workspace/coverage/default/22.spi_device_intercept.2774334890 |
|
|
May 21 12:27:08 PM PDT 24 |
May 21 12:28:12 PM PDT 24 |
364811379 ps |
| T895 |
/workspace/coverage/default/24.spi_device_flash_mode.1322985265 |
|
|
May 21 12:27:06 PM PDT 24 |
May 21 12:28:11 PM PDT 24 |
213949208 ps |
| T896 |
/workspace/coverage/default/47.spi_device_flash_mode.1219940777 |
|
|
May 21 12:28:15 PM PDT 24 |
May 21 12:29:23 PM PDT 24 |
1413970696 ps |
| T897 |
/workspace/coverage/default/23.spi_device_cfg_cmd.1766027704 |
|
|
May 21 12:27:06 PM PDT 24 |
May 21 12:28:08 PM PDT 24 |
582685720 ps |
| T898 |
/workspace/coverage/default/39.spi_device_tpm_rw.3838099833 |
|
|
May 21 12:27:48 PM PDT 24 |
May 21 12:28:45 PM PDT 24 |
126164723 ps |
| T899 |
/workspace/coverage/default/0.spi_device_mailbox.2354036271 |
|
|
May 21 12:26:05 PM PDT 24 |
May 21 12:26:45 PM PDT 24 |
14056788845 ps |
| T900 |
/workspace/coverage/default/37.spi_device_tpm_all.3409000627 |
|
|
May 21 12:27:32 PM PDT 24 |
May 21 12:28:32 PM PDT 24 |
18336049 ps |
| T901 |
/workspace/coverage/default/41.spi_device_pass_cmd_filtering.3793882986 |
|
|
May 21 12:27:56 PM PDT 24 |
May 21 12:29:01 PM PDT 24 |
2287368118 ps |
| T902 |
/workspace/coverage/default/33.spi_device_intercept.1146541509 |
|
|
May 21 12:27:13 PM PDT 24 |
May 21 12:28:29 PM PDT 24 |
1536141648 ps |
| T903 |
/workspace/coverage/default/38.spi_device_csb_read.257535334 |
|
|
May 21 12:27:41 PM PDT 24 |
May 21 12:28:40 PM PDT 24 |
16674195 ps |
| T904 |
/workspace/coverage/default/47.spi_device_flash_and_tpm.98271901 |
|
|
May 21 12:28:20 PM PDT 24 |
May 21 12:30:06 PM PDT 24 |
13304393521 ps |
| T905 |
/workspace/coverage/default/43.spi_device_upload.3431668148 |
|
|
May 21 12:28:05 PM PDT 24 |
May 21 12:28:58 PM PDT 24 |
574176746 ps |
| T906 |
/workspace/coverage/default/7.spi_device_read_buffer_direct.163337345 |
|
|
May 21 12:26:16 PM PDT 24 |
May 21 12:27:05 PM PDT 24 |
518942929 ps |
| T907 |
/workspace/coverage/default/8.spi_device_tpm_sts_read.1204450854 |
|
|
May 21 12:26:21 PM PDT 24 |
May 21 12:27:10 PM PDT 24 |
21592737 ps |
| T908 |
/workspace/coverage/default/25.spi_device_intercept.1768371286 |
|
|
May 21 12:26:57 PM PDT 24 |
May 21 12:27:59 PM PDT 24 |
149184813 ps |
| T909 |
/workspace/coverage/default/49.spi_device_pass_cmd_filtering.2789816684 |
|
|
May 21 12:28:22 PM PDT 24 |
May 21 12:29:27 PM PDT 24 |
21418010172 ps |
| T910 |
/workspace/coverage/default/9.spi_device_flash_all.2348643478 |
|
|
May 21 12:26:18 PM PDT 24 |
May 21 12:27:32 PM PDT 24 |
1511565891 ps |
| T911 |
/workspace/coverage/default/27.spi_device_tpm_all.1238310929 |
|
|
May 21 12:27:08 PM PDT 24 |
May 21 12:28:23 PM PDT 24 |
5493099088 ps |
| T912 |
/workspace/coverage/default/36.spi_device_cfg_cmd.729217713 |
|
|
May 21 12:27:33 PM PDT 24 |
May 21 12:28:38 PM PDT 24 |
1858320008 ps |
| T913 |
/workspace/coverage/default/28.spi_device_stress_all.3323367527 |
|
|
May 21 12:27:07 PM PDT 24 |
May 21 12:28:13 PM PDT 24 |
5022795044 ps |
| T255 |
/workspace/coverage/default/27.spi_device_flash_all.847473782 |
|
|
May 21 12:27:01 PM PDT 24 |
May 21 12:35:21 PM PDT 24 |
66469185393 ps |
| T914 |
/workspace/coverage/default/15.spi_device_flash_mode.3060414688 |
|
|
May 21 12:26:22 PM PDT 24 |
May 21 12:27:15 PM PDT 24 |
1102054856 ps |
| T915 |
/workspace/coverage/default/45.spi_device_flash_mode.3489369641 |
|
|
May 21 12:28:06 PM PDT 24 |
May 21 12:29:32 PM PDT 24 |
11203856548 ps |
| T916 |
/workspace/coverage/default/46.spi_device_tpm_sts_read.3457179250 |
|
|
May 21 12:28:06 PM PDT 24 |
May 21 12:28:57 PM PDT 24 |
29694267 ps |
| T917 |
/workspace/coverage/default/25.spi_device_stress_all.43737597 |
|
|
May 21 12:27:08 PM PDT 24 |
May 21 12:28:10 PM PDT 24 |
306208190 ps |
| T918 |
/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2451488285 |
|
|
May 21 12:27:06 PM PDT 24 |
May 21 12:28:06 PM PDT 24 |
23671051 ps |
| T919 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.993711494 |
|
|
May 21 12:26:41 PM PDT 24 |
May 21 12:27:41 PM PDT 24 |
549885966 ps |
| T920 |
/workspace/coverage/default/11.spi_device_upload.2538739622 |
|
|
May 21 12:26:55 PM PDT 24 |
May 21 12:28:00 PM PDT 24 |
448707105 ps |
| T921 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.1890103050 |
|
|
May 21 12:26:09 PM PDT 24 |
May 21 12:26:37 PM PDT 24 |
74729211 ps |
| T922 |
/workspace/coverage/default/17.spi_device_mailbox.2406862516 |
|
|
May 21 12:26:35 PM PDT 24 |
May 21 12:28:09 PM PDT 24 |
3583410523 ps |
| T923 |
/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2713839019 |
|
|
May 21 12:27:26 PM PDT 24 |
May 21 12:28:37 PM PDT 24 |
1986455477 ps |
| T924 |
/workspace/coverage/default/17.spi_device_flash_and_tpm.2637270451 |
|
|
May 21 12:26:55 PM PDT 24 |
May 21 12:28:38 PM PDT 24 |
4408499673 ps |
| T925 |
/workspace/coverage/default/25.spi_device_tpm_sts_read.2621018601 |
|
|
May 21 12:26:59 PM PDT 24 |
May 21 12:27:58 PM PDT 24 |
430163843 ps |
| T926 |
/workspace/coverage/default/22.spi_device_csb_read.3225343118 |
|
|
May 21 12:26:49 PM PDT 24 |
May 21 12:27:47 PM PDT 24 |
17832506 ps |
| T927 |
/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3894269201 |
|
|
May 21 12:26:13 PM PDT 24 |
May 21 12:26:56 PM PDT 24 |
1046477077 ps |
| T928 |
/workspace/coverage/default/12.spi_device_mailbox.140487045 |
|
|
May 21 12:26:29 PM PDT 24 |
May 21 12:27:47 PM PDT 24 |
1156598586 ps |
| T929 |
/workspace/coverage/default/49.spi_device_flash_and_tpm.2653855881 |
|
|
May 21 12:28:29 PM PDT 24 |
May 21 12:31:34 PM PDT 24 |
40113275678 ps |
| T930 |
/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1114001755 |
|
|
May 21 12:27:06 PM PDT 24 |
May 21 12:28:52 PM PDT 24 |
51098797138 ps |
| T931 |
/workspace/coverage/default/13.spi_device_flash_and_tpm.3221706356 |
|
|
May 21 12:26:32 PM PDT 24 |
May 21 12:30:27 PM PDT 24 |
126025756822 ps |
| T932 |
/workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1003878058 |
|
|
May 21 12:26:04 PM PDT 24 |
May 21 12:26:32 PM PDT 24 |
854630178 ps |
| T240 |
/workspace/coverage/default/47.spi_device_flash_all.1009291158 |
|
|
May 21 12:28:20 PM PDT 24 |
May 21 12:30:30 PM PDT 24 |
8682746121 ps |
| T933 |
/workspace/coverage/default/22.spi_device_mailbox.466068492 |
|
|
May 21 12:26:59 PM PDT 24 |
May 21 12:28:00 PM PDT 24 |
58555617 ps |
| T934 |
/workspace/coverage/default/25.spi_device_csb_read.1614574380 |
|
|
May 21 12:27:08 PM PDT 24 |
May 21 12:28:09 PM PDT 24 |
40551121 ps |
| T935 |
/workspace/coverage/default/40.spi_device_mailbox.3652192243 |
|
|
May 21 12:27:47 PM PDT 24 |
May 21 12:29:12 PM PDT 24 |
6168890036 ps |
| T936 |
/workspace/coverage/default/35.spi_device_tpm_sts_read.1508783726 |
|
|
May 21 12:27:27 PM PDT 24 |
May 21 12:28:27 PM PDT 24 |
70397504 ps |
| T937 |
/workspace/coverage/default/17.spi_device_intercept.822628026 |
|
|
May 21 12:27:03 PM PDT 24 |
May 21 12:28:07 PM PDT 24 |
136090261 ps |
| T938 |
/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2596142136 |
|
|
May 21 12:27:43 PM PDT 24 |
May 21 12:28:44 PM PDT 24 |
1777069778 ps |
| T939 |
/workspace/coverage/default/31.spi_device_upload.488603746 |
|
|
May 21 12:27:24 PM PDT 24 |
May 21 12:28:42 PM PDT 24 |
9755234699 ps |
| T940 |
/workspace/coverage/default/33.spi_device_tpm_sts_read.4165401237 |
|
|
May 21 12:27:14 PM PDT 24 |
May 21 12:28:15 PM PDT 24 |
47789428 ps |
| T941 |
/workspace/coverage/default/36.spi_device_flash_all.1111877742 |
|
|
May 21 12:27:35 PM PDT 24 |
May 21 12:33:18 PM PDT 24 |
40331542925 ps |
| T942 |
/workspace/coverage/default/4.spi_device_flash_mode.3666528451 |
|
|
May 21 12:26:16 PM PDT 24 |
May 21 12:27:14 PM PDT 24 |
5709708916 ps |
| T943 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.498832111 |
|
|
May 21 12:26:59 PM PDT 24 |
May 21 12:27:59 PM PDT 24 |
267105758 ps |
| T944 |
/workspace/coverage/default/36.spi_device_pass_cmd_filtering.475173071 |
|
|
May 21 12:27:32 PM PDT 24 |
May 21 12:28:50 PM PDT 24 |
20908648060 ps |
| T945 |
/workspace/coverage/default/13.spi_device_cfg_cmd.898865875 |
|
|
May 21 12:26:19 PM PDT 24 |
May 21 12:27:10 PM PDT 24 |
339690227 ps |
| T946 |
/workspace/coverage/default/21.spi_device_mailbox.3497047640 |
|
|
May 21 12:26:59 PM PDT 24 |
May 21 12:29:03 PM PDT 24 |
27410496789 ps |
| T947 |
/workspace/coverage/default/33.spi_device_upload.219997094 |
|
|
May 21 12:27:18 PM PDT 24 |
May 21 12:28:26 PM PDT 24 |
1146648533 ps |
| T948 |
/workspace/coverage/default/14.spi_device_stress_all.2455376767 |
|
|
May 21 12:26:33 PM PDT 24 |
May 21 12:32:01 PM PDT 24 |
30673661346 ps |
| T949 |
/workspace/coverage/default/44.spi_device_tpm_sts_read.3877745887 |
|
|
May 21 12:28:02 PM PDT 24 |
May 21 12:28:55 PM PDT 24 |
27811499 ps |
| T950 |
/workspace/coverage/default/48.spi_device_tpm_sts_read.1860858585 |
|
|
May 21 12:28:15 PM PDT 24 |
May 21 12:29:03 PM PDT 24 |
16509874 ps |
| T951 |
/workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.876610619 |
|
|
May 21 12:28:16 PM PDT 24 |
May 21 12:30:22 PM PDT 24 |
5651734849 ps |
| T952 |
/workspace/coverage/default/6.spi_device_cfg_cmd.4069719341 |
|
|
May 21 12:26:25 PM PDT 24 |
May 21 12:27:23 PM PDT 24 |
697179853 ps |
| T953 |
/workspace/coverage/default/10.spi_device_intercept.2761195564 |
|
|
May 21 12:26:27 PM PDT 24 |
May 21 12:27:49 PM PDT 24 |
9443003225 ps |
| T954 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.1928917512 |
|
|
May 21 12:28:16 PM PDT 24 |
May 21 12:29:08 PM PDT 24 |
184554939 ps |
| T955 |
/workspace/coverage/default/4.spi_device_tpm_rw.1436404383 |
|
|
May 21 12:26:19 PM PDT 24 |
May 21 12:27:07 PM PDT 24 |
292760243 ps |
| T956 |
/workspace/coverage/default/48.spi_device_flash_mode.2923850935 |
|
|
May 21 12:28:15 PM PDT 24 |
May 21 12:29:13 PM PDT 24 |
814065093 ps |
| T957 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2063203181 |
|
|
May 21 12:27:13 PM PDT 24 |
May 21 12:28:19 PM PDT 24 |
3615251496 ps |
| T958 |
/workspace/coverage/default/26.spi_device_intercept.246612889 |
|
|
May 21 12:27:06 PM PDT 24 |
May 21 12:28:10 PM PDT 24 |
1371288272 ps |
| T959 |
/workspace/coverage/default/44.spi_device_flash_mode.3041201263 |
|
|
May 21 12:28:14 PM PDT 24 |
May 21 12:29:08 PM PDT 24 |
556905379 ps |
| T960 |
/workspace/coverage/default/47.spi_device_tpm_rw.4137381027 |
|
|
May 21 12:28:19 PM PDT 24 |
May 21 12:29:07 PM PDT 24 |
49068280 ps |
| T961 |
/workspace/coverage/default/19.spi_device_intercept.4128792074 |
|
|
May 21 12:26:38 PM PDT 24 |
May 21 12:27:45 PM PDT 24 |
4846498895 ps |
| T962 |
/workspace/coverage/default/39.spi_device_alert_test.3224383223 |
|
|
May 21 12:27:48 PM PDT 24 |
May 21 12:28:45 PM PDT 24 |
45392127 ps |
| T963 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.3322137932 |
|
|
May 21 12:26:04 PM PDT 24 |
May 21 12:26:27 PM PDT 24 |
21850861 ps |
| T964 |
/workspace/coverage/default/2.spi_device_read_buffer_direct.102462978 |
|
|
May 21 12:26:12 PM PDT 24 |
May 21 12:26:59 PM PDT 24 |
1459756011 ps |
| T53 |
/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1888882658 |
|
|
May 21 12:26:18 PM PDT 24 |
May 21 12:30:06 PM PDT 24 |
45426333205 ps |
| T965 |
/workspace/coverage/default/13.spi_device_upload.2973808815 |
|
|
May 21 12:26:43 PM PDT 24 |
May 21 12:27:43 PM PDT 24 |
301615765 ps |
| T127 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3076333538 |
|
|
May 21 03:27:24 PM PDT 24 |
May 21 03:27:27 PM PDT 24 |
52096310 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4274840077 |
|
|
May 21 03:27:31 PM PDT 24 |
May 21 03:27:35 PM PDT 24 |
100544756 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2237651177 |
|
|
May 21 03:27:19 PM PDT 24 |
May 21 03:27:42 PM PDT 24 |
817848562 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3903932266 |
|
|
May 21 03:27:12 PM PDT 24 |
May 21 03:27:17 PM PDT 24 |
53764591 ps |
| T70 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2043045307 |
|
|
May 21 03:27:36 PM PDT 24 |
May 21 03:27:43 PM PDT 24 |
932229451 ps |
| T71 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2862521524 |
|
|
May 21 03:27:50 PM PDT 24 |
May 21 03:27:57 PM PDT 24 |
610844011 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2774951793 |
|
|
May 21 03:27:07 PM PDT 24 |
May 21 03:27:09 PM PDT 24 |
16766182 ps |
| T966 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.657366228 |
|
|
May 21 03:28:06 PM PDT 24 |
May 21 03:28:10 PM PDT 24 |
14959835 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1331284507 |
|
|
May 21 03:27:21 PM PDT 24 |
May 21 03:27:23 PM PDT 24 |
12397345 ps |
| T112 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2628317043 |
|
|
May 21 03:27:52 PM PDT 24 |
May 21 03:27:59 PM PDT 24 |
139533764 ps |
| T968 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.352439059 |
|
|
May 21 03:28:07 PM PDT 24 |
May 21 03:28:10 PM PDT 24 |
43350158 ps |
| T969 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.4265323904 |
|
|
May 21 03:28:05 PM PDT 24 |
May 21 03:28:08 PM PDT 24 |
33910855 ps |
| T110 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2909581909 |
|
|
May 21 03:27:37 PM PDT 24 |
May 21 03:27:44 PM PDT 24 |
385353410 ps |
| T970 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.725933634 |
|
|
May 21 03:28:03 PM PDT 24 |
May 21 03:28:06 PM PDT 24 |
34242176 ps |
| T111 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.327681499 |
|
|
May 21 03:27:33 PM PDT 24 |
May 21 03:27:37 PM PDT 24 |
277217598 ps |
| T153 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.211087057 |
|
|
May 21 03:27:56 PM PDT 24 |
May 21 03:28:00 PM PDT 24 |
19831797 ps |
| T113 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.618864278 |
|
|
May 21 03:27:44 PM PDT 24 |
May 21 03:27:48 PM PDT 24 |
38449152 ps |
| T971 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.4004797716 |
|
|
May 21 03:27:59 PM PDT 24 |
May 21 03:28:01 PM PDT 24 |
11127486 ps |
| T154 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3598033881 |
|
|
May 21 03:27:44 PM PDT 24 |
May 21 03:27:48 PM PDT 24 |
165901050 ps |
| T972 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2381371718 |
|
|
May 21 03:28:02 PM PDT 24 |
May 21 03:28:05 PM PDT 24 |
10896034 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1497306241 |
|
|
May 21 03:27:49 PM PDT 24 |
May 21 03:27:56 PM PDT 24 |
47856553 ps |
| T973 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.1696830880 |
|
|
May 21 03:27:48 PM PDT 24 |
May 21 03:27:52 PM PDT 24 |
31599033 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4278222995 |
|
|
May 21 03:27:16 PM PDT 24 |
May 21 03:27:18 PM PDT 24 |
30545552 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2572202315 |
|
|
May 21 03:27:43 PM PDT 24 |
May 21 03:27:46 PM PDT 24 |
101670285 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2548089841 |
|
|
May 21 03:27:30 PM PDT 24 |
May 21 03:28:06 PM PDT 24 |
555394550 ps |
| T132 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1100814197 |
|
|
May 21 03:27:48 PM PDT 24 |
May 21 03:27:52 PM PDT 24 |
35622373 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4118635483 |
|
|
May 21 03:27:22 PM PDT 24 |
May 21 03:27:24 PM PDT 24 |
18290011 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2725368030 |
|
|
May 21 03:27:06 PM PDT 24 |
May 21 03:27:14 PM PDT 24 |
209951065 ps |
| T117 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2310523322 |
|
|
May 21 03:27:31 PM PDT 24 |
May 21 03:27:35 PM PDT 24 |
182936790 ps |
| T133 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1934586372 |
|
|
May 21 03:27:22 PM PDT 24 |
May 21 03:27:24 PM PDT 24 |
150649276 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.472013768 |
|
|
May 21 03:27:26 PM PDT 24 |
May 21 03:27:38 PM PDT 24 |
191535296 ps |
| T977 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.11264291 |
|
|
May 21 03:28:08 PM PDT 24 |
May 21 03:28:11 PM PDT 24 |
12838587 ps |
| T125 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3492615007 |
|
|
May 21 03:27:42 PM PDT 24 |
May 21 03:27:47 PM PDT 24 |
454748361 ps |
| T978 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.8178445 |
|
|
May 21 03:27:50 PM PDT 24 |
May 21 03:27:57 PM PDT 24 |
58450580 ps |
| T979 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2343774749 |
|
|
May 21 03:28:00 PM PDT 24 |
May 21 03:28:02 PM PDT 24 |
20104993 ps |
| T980 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2288952793 |
|
|
May 21 03:27:54 PM PDT 24 |
May 21 03:27:58 PM PDT 24 |
28477331 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2998364281 |
|
|
May 21 03:27:08 PM PDT 24 |
May 21 03:27:11 PM PDT 24 |
29820207 ps |
| T115 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2773821654 |
|
|
May 21 03:27:42 PM PDT 24 |
May 21 03:28:04 PM PDT 24 |
317795371 ps |
| T120 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4246449201 |
|
|
May 21 03:27:49 PM PDT 24 |
May 21 03:27:55 PM PDT 24 |
274651131 ps |
| T161 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2651189179 |
|
|
May 21 03:27:45 PM PDT 24 |
May 21 03:27:48 PM PDT 24 |
372133113 ps |
| T982 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1850150528 |
|
|
May 21 03:28:02 PM PDT 24 |
May 21 03:28:05 PM PDT 24 |
19848818 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1890239394 |
|
|
May 21 03:27:17 PM PDT 24 |
May 21 03:27:20 PM PDT 24 |
33319505 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2772073064 |
|
|
May 21 03:27:16 PM PDT 24 |
May 21 03:27:20 PM PDT 24 |
211300052 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.658734301 |
|
|
May 21 03:27:24 PM PDT 24 |
May 21 03:27:28 PM PDT 24 |
258012413 ps |
| T986 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.3965677625 |
|
|
May 21 03:28:11 PM PDT 24 |
May 21 03:28:12 PM PDT 24 |
29441544 ps |
| T134 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3124935940 |
|
|
May 21 03:27:53 PM PDT 24 |
May 21 03:27:58 PM PDT 24 |
71437666 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2979684859 |
|
|
May 21 03:28:00 PM PDT 24 |
May 21 03:28:04 PM PDT 24 |
247787947 ps |
| T988 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2213040825 |
|
|
May 21 03:28:16 PM PDT 24 |
May 21 03:28:18 PM PDT 24 |
26425317 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2909814733 |
|
|
May 21 03:27:12 PM PDT 24 |
May 21 03:27:17 PM PDT 24 |
166812320 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2506359413 |
|
|
May 21 03:27:19 PM PDT 24 |
May 21 03:27:33 PM PDT 24 |
937029143 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2896544320 |
|
|
May 21 03:27:43 PM PDT 24 |
May 21 03:27:45 PM PDT 24 |
33451824 ps |
| T116 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2593392346 |
|
|
May 21 03:27:43 PM PDT 24 |
May 21 03:28:00 PM PDT 24 |
756083540 ps |
| T118 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2862576762 |
|
|
May 21 03:27:49 PM PDT 24 |
May 21 03:27:56 PM PDT 24 |
239419820 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.737081446 |
|
|
May 21 03:27:37 PM PDT 24 |
May 21 03:27:40 PM PDT 24 |
47753097 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1854789098 |
|
|
May 21 03:27:19 PM PDT 24 |
May 21 03:27:21 PM PDT 24 |
150618114 ps |
| T993 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.2134521896 |
|
|
May 21 03:27:54 PM PDT 24 |
May 21 03:27:58 PM PDT 24 |
13212719 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3447582588 |
|
|
May 21 03:27:51 PM PDT 24 |
May 21 03:27:58 PM PDT 24 |
181569507 ps |
| T162 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.91965669 |
|
|
May 21 03:27:54 PM PDT 24 |
May 21 03:28:01 PM PDT 24 |
1443172732 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.540783815 |
|
|
May 21 03:27:52 PM PDT 24 |
May 21 03:27:58 PM PDT 24 |
40574555 ps |
| T995 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.649763047 |
|
|
May 21 03:27:41 PM PDT 24 |
May 21 03:27:46 PM PDT 24 |
162746746 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.4187597430 |
|
|
May 21 03:27:10 PM PDT 24 |
May 21 03:27:12 PM PDT 24 |
52642803 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2917123354 |
|
|
May 21 03:27:30 PM PDT 24 |
May 21 03:27:32 PM PDT 24 |
101985026 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1837376402 |
|
|
May 21 03:27:24 PM PDT 24 |
May 21 03:27:29 PM PDT 24 |
98081493 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3270174890 |
|
|
May 21 03:27:48 PM PDT 24 |
May 21 03:27:53 PM PDT 24 |
252309824 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1489851251 |
|
|
May 21 03:27:48 PM PDT 24 |
May 21 03:27:52 PM PDT 24 |
83032823 ps |
| T163 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1648367503 |
|
|
May 21 03:27:38 PM PDT 24 |
May 21 03:27:44 PM PDT 24 |
913839485 ps |
| T137 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2129852695 |
|
|
May 21 03:27:31 PM PDT 24 |
May 21 03:27:33 PM PDT 24 |
40584618 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.875013042 |
|
|
May 21 03:27:16 PM PDT 24 |
May 21 03:27:18 PM PDT 24 |
22888007 ps |
| T164 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2364875804 |
|
|
May 21 03:27:45 PM PDT 24 |
May 21 03:27:48 PM PDT 24 |
131375194 ps |
| T1001 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2667533570 |
|
|
May 21 03:28:09 PM PDT 24 |
May 21 03:28:12 PM PDT 24 |
12657631 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.537125211 |
|
|
May 21 03:27:48 PM PDT 24 |
May 21 03:27:51 PM PDT 24 |
90087827 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4033453585 |
|
|
May 21 03:27:23 PM PDT 24 |
May 21 03:27:39 PM PDT 24 |
770281312 ps |
| T1004 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.339049674 |
|
|
May 21 03:27:44 PM PDT 24 |
May 21 03:27:49 PM PDT 24 |
457363228 ps |
| T1005 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2068719630 |
|
|
May 21 03:27:17 PM PDT 24 |
May 21 03:27:20 PM PDT 24 |
69516850 ps |
| T1006 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1548510527 |
|
|
May 21 03:27:49 PM PDT 24 |
May 21 03:27:53 PM PDT 24 |
11963742 ps |
| T281 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3048063535 |
|
|
May 21 03:27:50 PM PDT 24 |
May 21 03:28:01 PM PDT 24 |
197638709 ps |
| T1007 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.1288693148 |
|
|
May 21 03:27:37 PM PDT 24 |
May 21 03:27:39 PM PDT 24 |
14073334 ps |
| T1008 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.4079702227 |
|
|
May 21 03:27:59 PM PDT 24 |
May 21 03:28:01 PM PDT 24 |
13202167 ps |
| T1009 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.875641061 |
|
|
May 21 03:27:47 PM PDT 24 |
May 21 03:27:52 PM PDT 24 |
73962206 ps |
| T1010 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.4053797988 |
|
|
May 21 03:28:00 PM PDT 24 |
May 21 03:28:03 PM PDT 24 |
19654257 ps |
| T1011 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2338071569 |
|
|
May 21 03:27:31 PM PDT 24 |
May 21 03:27:36 PM PDT 24 |
153626751 ps |
| T1012 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.882387270 |
|
|
May 21 03:27:06 PM PDT 24 |
May 21 03:27:19 PM PDT 24 |
786837777 ps |
| T1013 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3931355640 |
|
|
May 21 03:27:06 PM PDT 24 |
May 21 03:27:08 PM PDT 24 |
101827406 ps |
| T165 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1827294899 |
|
|
May 21 03:27:37 PM PDT 24 |
May 21 03:27:55 PM PDT 24 |
701975773 ps |
| T138 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3488300415 |
|
|
May 21 03:27:36 PM PDT 24 |
May 21 03:27:39 PM PDT 24 |
55767072 ps |
| T1014 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2354979808 |
|
|
May 21 03:27:49 PM PDT 24 |
May 21 03:27:52 PM PDT 24 |
63065210 ps |
| T1015 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.634388593 |
|
|
May 21 03:28:07 PM PDT 24 |
May 21 03:28:10 PM PDT 24 |
13172054 ps |
| T1016 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.398269740 |
|
|
May 21 03:27:49 PM PDT 24 |
May 21 03:27:56 PM PDT 24 |
475174592 ps |
| T139 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3398019595 |
|
|
May 21 03:27:54 PM PDT 24 |
May 21 03:27:59 PM PDT 24 |
179627224 ps |
| T166 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1558832808 |
|
|
May 21 03:27:05 PM PDT 24 |
May 21 03:27:29 PM PDT 24 |
1036335419 ps |
| T123 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.981294878 |
|
|
May 21 03:27:54 PM PDT 24 |
May 21 03:28:02 PM PDT 24 |
223583274 ps |
| T1017 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.2030387253 |
|
|
May 21 03:28:05 PM PDT 24 |
May 21 03:28:08 PM PDT 24 |
13350065 ps |
| T1018 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1926834102 |
|
|
May 21 03:27:24 PM PDT 24 |
May 21 03:27:26 PM PDT 24 |
36714482 ps |
| T140 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1967684958 |
|
|
May 21 03:27:44 PM PDT 24 |
May 21 03:27:48 PM PDT 24 |
434064825 ps |