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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.92 98.30 94.11 98.61 89.36 97.06 95.83 98.17


Total test records in report: 1081
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T141 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.686911463 May 21 03:27:05 PM PDT 24 May 21 03:27:09 PM PDT 24 37659790 ps
T1019 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1786728485 May 21 03:27:59 PM PDT 24 May 21 03:28:02 PM PDT 24 35136564 ps
T1020 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3347398013 May 21 03:28:00 PM PDT 24 May 21 03:28:03 PM PDT 24 35466799 ps
T273 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1758997626 May 21 03:27:55 PM PDT 24 May 21 03:28:05 PM PDT 24 265329562 ps
T1021 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4135630322 May 21 03:27:07 PM PDT 24 May 21 03:27:10 PM PDT 24 145907379 ps
T1022 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3133083365 May 21 03:28:02 PM PDT 24 May 21 03:28:06 PM PDT 24 13105172 ps
T1023 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.320197925 May 21 03:27:54 PM PDT 24 May 21 03:27:58 PM PDT 24 11291354 ps
T1024 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2616511380 May 21 03:27:12 PM PDT 24 May 21 03:27:15 PM PDT 24 22593600 ps
T1025 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3031834540 May 21 03:27:48 PM PDT 24 May 21 03:27:51 PM PDT 24 40916608 ps
T1026 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2825628662 May 21 03:28:06 PM PDT 24 May 21 03:28:10 PM PDT 24 13835237 ps
T1027 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.750245676 May 21 03:28:04 PM PDT 24 May 21 03:28:06 PM PDT 24 21621824 ps
T1028 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1191256943 May 21 03:27:30 PM PDT 24 May 21 03:27:34 PM PDT 24 371597636 ps
T1029 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3362461124 May 21 03:27:31 PM PDT 24 May 21 03:27:33 PM PDT 24 56880976 ps
T1030 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2832584063 May 21 03:27:48 PM PDT 24 May 21 03:27:52 PM PDT 24 26991648 ps
T167 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4289694831 May 21 03:27:56 PM PDT 24 May 21 03:28:06 PM PDT 24 634372703 ps
T1031 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2175854919 May 21 03:28:00 PM PDT 24 May 21 03:28:05 PM PDT 24 69503716 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1400609917 May 21 03:27:45 PM PDT 24 May 21 03:27:50 PM PDT 24 156835386 ps
T1033 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1885165434 May 21 03:27:29 PM PDT 24 May 21 03:27:33 PM PDT 24 108817586 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2231382591 May 21 03:27:24 PM PDT 24 May 21 03:27:26 PM PDT 24 17076935 ps
T1035 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.466991413 May 21 03:28:06 PM PDT 24 May 21 03:28:09 PM PDT 24 39841745 ps
T91 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2177801957 May 21 03:27:16 PM PDT 24 May 21 03:27:18 PM PDT 24 97506504 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1087216825 May 21 03:27:04 PM PDT 24 May 21 03:27:06 PM PDT 24 11294444 ps
T121 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.349289394 May 21 03:27:51 PM PDT 24 May 21 03:27:55 PM PDT 24 84636543 ps
T1037 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2495633201 May 21 03:27:37 PM PDT 24 May 21 03:27:40 PM PDT 24 106633182 ps
T274 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366177241 May 21 03:27:23 PM PDT 24 May 21 03:27:46 PM PDT 24 3656226334 ps
T92 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1596442036 May 21 03:27:12 PM PDT 24 May 21 03:27:15 PM PDT 24 89539830 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1486681365 May 21 03:27:31 PM PDT 24 May 21 03:27:34 PM PDT 24 163984501 ps
T276 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3162193702 May 21 03:27:19 PM PDT 24 May 21 03:27:33 PM PDT 24 1069168166 ps
T122 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1497017679 May 21 03:27:52 PM PDT 24 May 21 03:27:58 PM PDT 24 308771398 ps
T280 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2379815846 May 21 03:27:12 PM PDT 24 May 21 03:27:26 PM PDT 24 794542913 ps
T1039 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.559083720 May 21 03:28:11 PM PDT 24 May 21 03:28:13 PM PDT 24 15558443 ps
T1040 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.344532977 May 21 03:28:00 PM PDT 24 May 21 03:28:03 PM PDT 24 84612098 ps
T278 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.493717988 May 21 03:27:37 PM PDT 24 May 21 03:27:57 PM PDT 24 663121985 ps
T277 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3550362759 May 21 03:27:51 PM PDT 24 May 21 03:28:10 PM PDT 24 1400653054 ps
T1041 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3375112688 May 21 03:27:47 PM PDT 24 May 21 03:27:49 PM PDT 24 67251385 ps
T1042 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.454960540 May 21 03:27:24 PM PDT 24 May 21 03:27:27 PM PDT 24 18702188 ps
T279 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.361065498 May 21 03:27:50 PM PDT 24 May 21 03:28:01 PM PDT 24 368609886 ps
T142 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2912474863 May 21 03:27:11 PM PDT 24 May 21 03:27:27 PM PDT 24 9092962707 ps
T1043 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1731982779 May 21 03:27:56 PM PDT 24 May 21 03:28:01 PM PDT 24 35155017 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1149700585 May 21 03:27:32 PM PDT 24 May 21 03:27:41 PM PDT 24 3399147082 ps
T1045 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3102557024 May 21 03:28:06 PM PDT 24 May 21 03:28:09 PM PDT 24 13556057 ps
T275 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2461447046 May 21 03:27:56 PM PDT 24 May 21 03:28:23 PM PDT 24 2003973181 ps
T1046 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1057945534 May 21 03:28:02 PM PDT 24 May 21 03:28:05 PM PDT 24 28821555 ps
T1047 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1793517824 May 21 03:27:41 PM PDT 24 May 21 03:27:44 PM PDT 24 58442235 ps
T1048 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1238496770 May 21 03:27:54 PM PDT 24 May 21 03:28:14 PM PDT 24 712979160 ps
T1049 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3445866873 May 21 03:27:36 PM PDT 24 May 21 03:27:46 PM PDT 24 1503167662 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.458985570 May 21 03:27:31 PM PDT 24 May 21 03:27:54 PM PDT 24 1710289178 ps
T1051 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.410165943 May 21 03:27:47 PM PDT 24 May 21 03:27:50 PM PDT 24 50466354 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1251523259 May 21 03:27:23 PM PDT 24 May 21 03:27:26 PM PDT 24 53506863 ps
T1053 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2909062101 May 21 03:27:53 PM PDT 24 May 21 03:28:00 PM PDT 24 839597768 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.159997774 May 21 03:27:25 PM PDT 24 May 21 03:27:41 PM PDT 24 556448806 ps
T93 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.855643753 May 21 03:27:06 PM PDT 24 May 21 03:27:09 PM PDT 24 43356813 ps
T1055 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1047473933 May 21 03:27:43 PM PDT 24 May 21 03:28:00 PM PDT 24 2378257266 ps
T1056 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1917647778 May 21 03:27:31 PM PDT 24 May 21 03:27:34 PM PDT 24 52882150 ps
T1057 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2007395909 May 21 03:27:51 PM PDT 24 May 21 03:27:56 PM PDT 24 256652518 ps
T1058 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1172648541 May 21 03:27:38 PM PDT 24 May 21 03:27:40 PM PDT 24 13339372 ps
T1059 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.783834910 May 21 03:27:55 PM PDT 24 May 21 03:28:02 PM PDT 24 236188699 ps
T1060 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1621125476 May 21 03:27:53 PM PDT 24 May 21 03:27:58 PM PDT 24 325939445 ps
T1061 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3755050489 May 21 03:27:43 PM PDT 24 May 21 03:27:48 PM PDT 24 106083625 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3493877491 May 21 03:27:24 PM PDT 24 May 21 03:27:29 PM PDT 24 59584174 ps
T1063 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2538925984 May 21 03:28:00 PM PDT 24 May 21 03:28:02 PM PDT 24 12050751 ps
T1064 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4137989940 May 21 03:27:53 PM PDT 24 May 21 03:27:58 PM PDT 24 122376302 ps
T1065 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2159716207 May 21 03:27:52 PM PDT 24 May 21 03:27:59 PM PDT 24 1200863368 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1931692985 May 21 03:27:42 PM PDT 24 May 21 03:27:45 PM PDT 24 15206681 ps
T1067 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3627698900 May 21 03:27:38 PM PDT 24 May 21 03:27:40 PM PDT 24 14122032 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1159786077 May 21 03:27:23 PM PDT 24 May 21 03:27:27 PM PDT 24 334766191 ps
T271 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2086948302 May 21 03:27:22 PM PDT 24 May 21 03:27:27 PM PDT 24 165429503 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4236542443 May 21 03:27:17 PM PDT 24 May 21 03:27:20 PM PDT 24 48383922 ps
T1070 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4274955987 May 21 03:28:04 PM PDT 24 May 21 03:28:06 PM PDT 24 17845174 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1544728669 May 21 03:27:11 PM PDT 24 May 21 03:27:13 PM PDT 24 11678806 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2893953546 May 21 03:27:53 PM PDT 24 May 21 03:27:57 PM PDT 24 53480088 ps
T1073 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3024623481 May 21 03:28:08 PM PDT 24 May 21 03:28:11 PM PDT 24 15508424 ps
T1074 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2047211179 May 21 03:27:52 PM PDT 24 May 21 03:28:21 PM PDT 24 2184265773 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1912439242 May 21 03:27:38 PM PDT 24 May 21 03:27:42 PM PDT 24 587025012 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2389574786 May 21 03:27:12 PM PDT 24 May 21 03:27:15 PM PDT 24 114855209 ps
T1077 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.94409333 May 21 03:28:01 PM PDT 24 May 21 03:28:04 PM PDT 24 15096519 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.721856033 May 21 03:27:49 PM PDT 24 May 21 03:27:55 PM PDT 24 565397899 ps
T1079 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3179583856 May 21 03:27:43 PM PDT 24 May 21 03:27:47 PM PDT 24 241689736 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3179414242 May 21 03:27:56 PM PDT 24 May 21 03:28:01 PM PDT 24 542463944 ps
T272 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.449566007 May 21 03:27:48 PM PDT 24 May 21 03:27:53 PM PDT 24 305929149 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3337055229 May 21 03:27:12 PM PDT 24 May 21 03:27:22 PM PDT 24 107880634 ps

Test location /workspace/coverage/default/48.spi_device_stress_all.1848709061
Short name T2
Test name
Test status
Simulation time 41466189974 ps
CPU time 140.03 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:31:23 PM PDT 24
Peak memory 240396 kb
Host smart-a482d86f-0452-4d8a-81a1-8a55264a41a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848709061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1848709061
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.996272834
Short name T21
Test name
Test status
Simulation time 5341422510 ps
CPU time 64.92 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 256400 kb
Host smart-562a9ffe-de23-4fa6-bcbc-3290ed8a7653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996272834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.996272834
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.637676302
Short name T96
Test name
Test status
Simulation time 14766205087 ps
CPU time 125.36 seconds
Started May 21 12:26:02 PM PDT 24
Finished May 21 12:28:29 PM PDT 24
Peak memory 252772 kb
Host smart-3f0f5d62-d115-4945-9546-4f28213176ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637676302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.637676302
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4119054801
Short name T35
Test name
Test status
Simulation time 236073640850 ps
CPU time 1028.13 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:45:14 PM PDT 24
Peak memory 281680 kb
Host smart-82032477-ee94-4739-9ac7-c73a98de5f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119054801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4119054801
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2628317043
Short name T112
Test name
Test status
Simulation time 139533764 ps
CPU time 3.71 seconds
Started May 21 03:27:52 PM PDT 24
Finished May 21 03:27:59 PM PDT 24
Peak memory 217420 kb
Host smart-b131565f-f953-4c42-8f45-df2882a64852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628317043 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2628317043
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3976611376
Short name T14
Test name
Test status
Simulation time 39198437411 ps
CPU time 171.16 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:31:35 PM PDT 24
Peak memory 263792 kb
Host smart-0fc4e30e-b252-44e5-9a4e-16bfc0f87abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976611376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3976611376
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.125717878
Short name T170
Test name
Test status
Simulation time 192387197223 ps
CPU time 985.02 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:44:00 PM PDT 24
Peak memory 298028 kb
Host smart-313e828a-6815-4997-b48a-4d5024d5ac07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125717878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.125717878
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1972361403
Short name T73
Test name
Test status
Simulation time 17731356 ps
CPU time 0.75 seconds
Started May 21 12:26:06 PM PDT 24
Finished May 21 12:26:32 PM PDT 24
Peak memory 215908 kb
Host smart-a4147404-79ee-4e3a-89da-b69fe5ce7392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972361403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1972361403
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.782839110
Short name T60
Test name
Test status
Simulation time 22730118460 ps
CPU time 147.74 seconds
Started May 21 12:27:36 PM PDT 24
Finished May 21 12:31:03 PM PDT 24
Peak memory 263336 kb
Host smart-591ec4dd-f448-4e5c-9e75-0851519f73dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782839110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.782839110
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1911129860
Short name T74
Test name
Test status
Simulation time 250561071 ps
CPU time 1.03 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:39 PM PDT 24
Peak memory 234492 kb
Host smart-87df4bfd-9784-4445-aa87-158009eeca94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911129860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1911129860
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2275844171
Short name T101
Test name
Test status
Simulation time 9020957215 ps
CPU time 108.06 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:29:57 PM PDT 24
Peak memory 240748 kb
Host smart-db2ed086-1722-4ada-a3e7-33cd8eaaa523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275844171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2275844171
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1065732233
Short name T189
Test name
Test status
Simulation time 20629335705 ps
CPU time 315.56 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 281704 kb
Host smart-6db1fbe2-0167-4956-8606-98b7038112f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065732233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1065732233
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.958138095
Short name T11
Test name
Test status
Simulation time 3242030684 ps
CPU time 48.75 seconds
Started May 21 12:27:49 PM PDT 24
Finished May 21 12:29:33 PM PDT 24
Peak memory 240596 kb
Host smart-6da5928e-557e-4f3f-9e4f-03b9a7c4950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958138095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.958138095
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1361730973
Short name T34
Test name
Test status
Simulation time 89850943352 ps
CPU time 193.67 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 257276 kb
Host smart-2008880a-4ffb-441e-8aba-f2d46aeb9921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361730973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1361730973
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.403780991
Short name T37
Test name
Test status
Simulation time 5003276106 ps
CPU time 108.9 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:29:53 PM PDT 24
Peak memory 252560 kb
Host smart-fb6c2321-90ef-43a4-b7d4-09224d20bcc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403780991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.403780991
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2593392346
Short name T116
Test name
Test status
Simulation time 756083540 ps
CPU time 15.21 seconds
Started May 21 03:27:43 PM PDT 24
Finished May 21 03:28:00 PM PDT 24
Peak memory 215488 kb
Host smart-2bfb9f5e-a06f-4541-8ec2-4110917d9aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593392346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2593392346
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4229587131
Short name T208
Test name
Test status
Simulation time 69934292871 ps
CPU time 470.83 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:35:27 PM PDT 24
Peak memory 254240 kb
Host smart-d574ce75-a2ce-4c72-b0d4-c389cb84f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229587131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4229587131
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3124935940
Short name T134
Test name
Test status
Simulation time 71437666 ps
CPU time 2.55 seconds
Started May 21 03:27:53 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 206964 kb
Host smart-ddc02715-ea7c-456b-b248-0ea85dd1a1d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124935940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3124935940
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2043045307
Short name T70
Test name
Test status
Simulation time 932229451 ps
CPU time 5.42 seconds
Started May 21 03:27:36 PM PDT 24
Finished May 21 03:27:43 PM PDT 24
Peak memory 215376 kb
Host smart-caf85b8c-6337-4574-b483-160a1893c495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043045307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
043045307
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4272180461
Short name T206
Test name
Test status
Simulation time 12014719596 ps
CPU time 77.34 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:28:33 PM PDT 24
Peak memory 248996 kb
Host smart-38a97529-2091-435d-89cd-8aeaf971fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272180461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4272180461
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2435241450
Short name T263
Test name
Test status
Simulation time 6926192909 ps
CPU time 63.06 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 248812 kb
Host smart-baf041f2-c4fa-49d4-b9a2-840a63d11951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435241450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2435241450
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1101390497
Short name T42
Test name
Test status
Simulation time 191208154033 ps
CPU time 284.7 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:31:37 PM PDT 24
Peak memory 254340 kb
Host smart-34ec095a-fcd8-4174-9eb1-3b8f420b88d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101390497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1101390497
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3048613650
Short name T106
Test name
Test status
Simulation time 11174108697 ps
CPU time 14.48 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:26:59 PM PDT 24
Peak memory 216020 kb
Host smart-f569c25c-6d96-48a2-9184-5c4bf7590f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048613650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3048613650
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2015559297
Short name T22
Test name
Test status
Simulation time 82590255436 ps
CPU time 638.29 seconds
Started May 21 12:26:23 PM PDT 24
Finished May 21 12:37:50 PM PDT 24
Peak memory 272256 kb
Host smart-d873f83e-c8a0-4116-a79d-fe9d4a0c6056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015559297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2015559297
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3394945430
Short name T262
Test name
Test status
Simulation time 109709735764 ps
CPU time 195.82 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 257140 kb
Host smart-0f671b3a-4c9f-43ac-a46e-1ecd9120ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394945430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3394945430
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1888882658
Short name T53
Test name
Test status
Simulation time 45426333205 ps
CPU time 184.21 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:30:06 PM PDT 24
Peak memory 265184 kb
Host smart-38ebcdcb-31d5-409d-b459-988d1d7ac301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888882658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1888882658
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1780026488
Short name T335
Test name
Test status
Simulation time 29930742 ps
CPU time 0.68 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 204504 kb
Host smart-58191d87-06db-457c-b65d-e6e8f8da326d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780026488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1780026488
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2461447046
Short name T275
Test name
Test status
Simulation time 2003973181 ps
CPU time 24.27 seconds
Started May 21 03:27:56 PM PDT 24
Finished May 21 03:28:23 PM PDT 24
Peak memory 215492 kb
Host smart-f6203972-71f2-4f91-a449-8164a96fc0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461447046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2461447046
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3831186442
Short name T232
Test name
Test status
Simulation time 44203475332 ps
CPU time 366.1 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:34:15 PM PDT 24
Peak memory 248932 kb
Host smart-6a4133fa-957e-4dfd-883f-9b22522d5f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831186442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3831186442
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4132551848
Short name T313
Test name
Test status
Simulation time 358307000 ps
CPU time 11.72 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:28 PM PDT 24
Peak memory 232772 kb
Host smart-175208a0-3f7c-44cf-8945-e9a96804e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132551848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4132551848
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2121519969
Short name T180
Test name
Test status
Simulation time 56452544894 ps
CPU time 235.61 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:32:12 PM PDT 24
Peak memory 253200 kb
Host smart-21877372-06c6-4ae9-8781-6fdf43042218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121519969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2121519969
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3550362759
Short name T277
Test name
Test status
Simulation time 1400653054 ps
CPU time 15.61 seconds
Started May 21 03:27:51 PM PDT 24
Finished May 21 03:28:10 PM PDT 24
Peak memory 215372 kb
Host smart-e2ccc6d6-8314-4b44-b258-e701a3fb8667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550362759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3550362759
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2860794343
Short name T252
Test name
Test status
Simulation time 4996734315 ps
CPU time 56.15 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:28:24 PM PDT 24
Peak memory 251200 kb
Host smart-73d0562e-38f8-4f07-81e5-b7f5aeff5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860794343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2860794343
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2693224499
Short name T237
Test name
Test status
Simulation time 194587982996 ps
CPU time 381.78 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:34:56 PM PDT 24
Peak memory 264980 kb
Host smart-0f25c24e-b281-4b9d-93d8-8de739730dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693224499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2693224499
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1458844792
Short name T23
Test name
Test status
Simulation time 225691376986 ps
CPU time 603.49 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:37:15 PM PDT 24
Peak memory 281792 kb
Host smart-33893fa3-c7a0-45e1-8ef2-1da0dd08ab67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458844792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1458844792
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1208714899
Short name T28
Test name
Test status
Simulation time 19391532698 ps
CPU time 87.81 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:28:51 PM PDT 24
Peak memory 239168 kb
Host smart-3ca34ee5-85b1-4341-8ab2-3fe1b1537329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208714899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1208714899
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3489649584
Short name T254
Test name
Test status
Simulation time 37988534395 ps
CPU time 230.82 seconds
Started May 21 12:26:22 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 257044 kb
Host smart-5950b6e9-7825-4450-b219-719fd9333a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489649584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3489649584
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3031027120
Short name T308
Test name
Test status
Simulation time 3455346554 ps
CPU time 64.03 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 238712 kb
Host smart-300145ea-b383-4594-b7fb-58d52852341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031027120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3031027120
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1983665804
Short name T68
Test name
Test status
Simulation time 15866067562 ps
CPU time 115.77 seconds
Started May 21 12:27:42 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 249648 kb
Host smart-f78e82ef-cbcd-498a-9144-54b777d958b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983665804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1983665804
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2992466021
Short name T245
Test name
Test status
Simulation time 73804906441 ps
CPU time 662.59 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:38:24 PM PDT 24
Peak memory 251832 kb
Host smart-83cb0cb1-911b-427e-99b9-3734b5bd1310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992466021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2992466021
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1568469204
Short name T107
Test name
Test status
Simulation time 229702716 ps
CPU time 5.59 seconds
Started May 21 12:27:47 PM PDT 24
Finished May 21 12:28:48 PM PDT 24
Peak memory 233032 kb
Host smart-ba39f46d-a2e3-484f-8242-711110017e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568469204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1568469204
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.783834910
Short name T1059
Test name
Test status
Simulation time 236188699 ps
CPU time 3.69 seconds
Started May 21 03:27:55 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 215460 kb
Host smart-6e9a6439-fc7f-4f9f-b764-498252841a11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783834910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.783834910
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.449566007
Short name T272
Test name
Test status
Simulation time 305929149 ps
CPU time 3.38 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:53 PM PDT 24
Peak memory 215328 kb
Host smart-95c11850-42e9-4608-bd3e-c718063027e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449566007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.449566007
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1873734619
Short name T656
Test name
Test status
Simulation time 888089744 ps
CPU time 5.75 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:09 PM PDT 24
Peak memory 218604 kb
Host smart-4293697e-58e2-484e-a117-a9ca07569695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873734619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1873734619
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1183483953
Short name T200
Test name
Test status
Simulation time 293041971693 ps
CPU time 101.59 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 251360 kb
Host smart-74025a2c-eec4-4c3d-bf56-43688ade0df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183483953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1183483953
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3287648073
Short name T290
Test name
Test status
Simulation time 453273836 ps
CPU time 3.31 seconds
Started May 21 12:26:46 PM PDT 24
Finished May 21 12:27:48 PM PDT 24
Peak memory 218408 kb
Host smart-3a2ab61c-d913-4d6a-9e93-a4b08303235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287648073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3287648073
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1247144523
Short name T264
Test name
Test status
Simulation time 137134038674 ps
CPU time 250.56 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 253032 kb
Host smart-623e64b6-1f99-4b0c-a454-6dc5c9597eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247144523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1247144523
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.625247495
Short name T233
Test name
Test status
Simulation time 1994429908 ps
CPU time 40.97 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:43 PM PDT 24
Peak memory 251832 kb
Host smart-3cfcb58c-4ae5-4f4a-98ed-e1d2d659f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625247495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.625247495
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.471693529
Short name T82
Test name
Test status
Simulation time 1573588023 ps
CPU time 6.83 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 219540 kb
Host smart-0afef774-eb5e-4969-af9f-d5be778ac9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471693529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.471693529
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.855643753
Short name T93
Test name
Test status
Simulation time 43356813 ps
CPU time 1.38 seconds
Started May 21 03:27:06 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 206948 kb
Host smart-fd9ec0e8-0c4d-45ae-bb12-20773ed7b1fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855643753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.855643753
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2735387710
Short name T157
Test name
Test status
Simulation time 243054885 ps
CPU time 4 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 222536 kb
Host smart-35f78167-8c27-4892-9f4f-12c9cc8564fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2735387710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2735387710
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2616511380
Short name T1024
Test name
Test status
Simulation time 22593600 ps
CPU time 1.48 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:15 PM PDT 24
Peak memory 215340 kb
Host smart-dddb4ee3-6877-4bdf-bc0f-80d89c18f6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616511380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
616511380
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1558832808
Short name T166
Test name
Test status
Simulation time 1036335419 ps
CPU time 22.44 seconds
Started May 21 03:27:05 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 215148 kb
Host smart-6a982cb2-396c-4d19-a0c5-59ec418c6844
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558832808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1558832808
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.882387270
Short name T1012
Test name
Test status
Simulation time 786837777 ps
CPU time 11.75 seconds
Started May 21 03:27:06 PM PDT 24
Finished May 21 03:27:19 PM PDT 24
Peak memory 206944 kb
Host smart-e00481d7-4e68-4188-8f4b-d3014339f2e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882387270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.882387270
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3903932266
Short name T69
Test name
Test status
Simulation time 53764591 ps
CPU time 3.81 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:17 PM PDT 24
Peak memory 217996 kb
Host smart-0aa64eb9-71e2-4d09-a3e7-0e456b4ef1ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903932266 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3903932266
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.686911463
Short name T141
Test name
Test status
Simulation time 37659790 ps
CPU time 2.33 seconds
Started May 21 03:27:05 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 215112 kb
Host smart-3e354201-0822-47b5-a63a-f7b9bfd37bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686911463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.686911463
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3931355640
Short name T1013
Test name
Test status
Simulation time 101827406 ps
CPU time 0.72 seconds
Started May 21 03:27:06 PM PDT 24
Finished May 21 03:27:08 PM PDT 24
Peak memory 203612 kb
Host smart-bf1554ef-4804-4816-985d-b19d81920ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931355640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
931355640
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2774951793
Short name T130
Test name
Test status
Simulation time 16766182 ps
CPU time 1.37 seconds
Started May 21 03:27:07 PM PDT 24
Finished May 21 03:27:09 PM PDT 24
Peak memory 215328 kb
Host smart-bf0c7f0c-f51a-419d-9a4a-22d506952079
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774951793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2774951793
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1087216825
Short name T1036
Test name
Test status
Simulation time 11294444 ps
CPU time 0.63 seconds
Started May 21 03:27:04 PM PDT 24
Finished May 21 03:27:06 PM PDT 24
Peak memory 203492 kb
Host smart-846774ba-c6e3-4350-8c36-700654d896ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087216825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1087216825
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2998364281
Short name T981
Test name
Test status
Simulation time 29820207 ps
CPU time 1.83 seconds
Started May 21 03:27:08 PM PDT 24
Finished May 21 03:27:11 PM PDT 24
Peak memory 215248 kb
Host smart-9e80e98a-1efb-40f3-b0a5-b726b017baab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998364281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2998364281
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4135630322
Short name T1021
Test name
Test status
Simulation time 145907379 ps
CPU time 2.29 seconds
Started May 21 03:27:07 PM PDT 24
Finished May 21 03:27:10 PM PDT 24
Peak memory 215456 kb
Host smart-abb34156-5aa7-45dd-9cf8-934d020a6dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135630322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
135630322
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2725368030
Short name T114
Test name
Test status
Simulation time 209951065 ps
CPU time 6.68 seconds
Started May 21 03:27:06 PM PDT 24
Finished May 21 03:27:14 PM PDT 24
Peak memory 215388 kb
Host smart-33bd0328-2a4b-4abc-8048-634ad7db170e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725368030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2725368030
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3337055229
Short name T1081
Test name
Test status
Simulation time 107880634 ps
CPU time 7.42 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:22 PM PDT 24
Peak memory 207008 kb
Host smart-0345ce50-378d-45c2-8464-d7d14ddf0e21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337055229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3337055229
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2912474863
Short name T142
Test name
Test status
Simulation time 9092962707 ps
CPU time 14.25 seconds
Started May 21 03:27:11 PM PDT 24
Finished May 21 03:27:27 PM PDT 24
Peak memory 207028 kb
Host smart-cac2b177-9b38-4033-8e33-b13eceb6050a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912474863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2912474863
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1596442036
Short name T92
Test name
Test status
Simulation time 89539830 ps
CPU time 1.39 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:15 PM PDT 24
Peak memory 206960 kb
Host smart-ef069ae0-28d9-4192-9a8f-2ce8614cffe4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596442036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1596442036
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2068719630
Short name T1005
Test name
Test status
Simulation time 69516850 ps
CPU time 2.72 seconds
Started May 21 03:27:17 PM PDT 24
Finished May 21 03:27:20 PM PDT 24
Peak memory 216544 kb
Host smart-4439772a-3aef-4469-89da-f699ce9c9848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068719630 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2068719630
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2909814733
Short name T989
Test name
Test status
Simulation time 166812320 ps
CPU time 2.65 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:17 PM PDT 24
Peak memory 206952 kb
Host smart-60a065d6-da4a-4056-b6f3-0a88437a3eb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909814733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
909814733
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4187597430
Short name T996
Test name
Test status
Simulation time 52642803 ps
CPU time 0.72 seconds
Started May 21 03:27:10 PM PDT 24
Finished May 21 03:27:12 PM PDT 24
Peak memory 203888 kb
Host smart-4cd6a529-4871-41fb-ab65-fc994b9fe735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187597430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
187597430
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2389574786
Short name T1076
Test name
Test status
Simulation time 114855209 ps
CPU time 1.38 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:15 PM PDT 24
Peak memory 215240 kb
Host smart-86363c04-d9d3-4bc0-ab2a-6ed68fb7cd23
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389574786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2389574786
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1544728669
Short name T1071
Test name
Test status
Simulation time 11678806 ps
CPU time 0.67 seconds
Started May 21 03:27:11 PM PDT 24
Finished May 21 03:27:13 PM PDT 24
Peak memory 203480 kb
Host smart-a452c6b1-2e71-4e38-9175-db66630543bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544728669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1544728669
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2772073064
Short name T984
Test name
Test status
Simulation time 211300052 ps
CPU time 3.71 seconds
Started May 21 03:27:16 PM PDT 24
Finished May 21 03:27:20 PM PDT 24
Peak memory 215212 kb
Host smart-8549b8c1-3921-4c4a-be99-a922ec43210c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772073064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2772073064
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2379815846
Short name T280
Test name
Test status
Simulation time 794542913 ps
CPU time 11.74 seconds
Started May 21 03:27:12 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 215316 kb
Host smart-2522ddb4-9674-42eb-b00c-8ad7a6b6a1fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379815846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2379815846
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.339049674
Short name T1004
Test name
Test status
Simulation time 457363228 ps
CPU time 3.9 seconds
Started May 21 03:27:44 PM PDT 24
Finished May 21 03:27:49 PM PDT 24
Peak memory 216712 kb
Host smart-e7214e6c-ca13-47cd-a18b-7a87519a8326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339049674 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.339049674
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1967684958
Short name T140
Test name
Test status
Simulation time 434064825 ps
CPU time 3 seconds
Started May 21 03:27:44 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 215180 kb
Host smart-260524cf-5361-4bb4-a0b2-fe27bce29bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967684958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1967684958
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3375112688
Short name T1041
Test name
Test status
Simulation time 67251385 ps
CPU time 0.76 seconds
Started May 21 03:27:47 PM PDT 24
Finished May 21 03:27:49 PM PDT 24
Peak memory 203904 kb
Host smart-7d4a48a8-c313-4167-abd7-98d4fbc7263f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375112688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3375112688
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2572202315
Short name T975
Test name
Test status
Simulation time 101670285 ps
CPU time 1.62 seconds
Started May 21 03:27:43 PM PDT 24
Finished May 21 03:27:46 PM PDT 24
Peak memory 215272 kb
Host smart-85493213-2cf2-4b14-ab9c-bfeaab0617d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572202315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2572202315
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.875641061
Short name T1009
Test name
Test status
Simulation time 73962206 ps
CPU time 4.74 seconds
Started May 21 03:27:47 PM PDT 24
Finished May 21 03:27:52 PM PDT 24
Peak memory 215476 kb
Host smart-be09ddce-af61-45f4-8e75-11fbb59e004a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875641061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.875641061
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2773821654
Short name T115
Test name
Test status
Simulation time 317795371 ps
CPU time 20 seconds
Started May 21 03:27:42 PM PDT 24
Finished May 21 03:28:04 PM PDT 24
Peak memory 215416 kb
Host smart-def8f4d7-406f-4390-9434-c448e963bc7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773821654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2773821654
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1400609917
Short name T1032
Test name
Test status
Simulation time 156835386 ps
CPU time 3.97 seconds
Started May 21 03:27:45 PM PDT 24
Finished May 21 03:27:50 PM PDT 24
Peak memory 218252 kb
Host smart-64ec54e0-a89d-4ec2-ad2d-8ed687ae8056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400609917 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1400609917
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3755050489
Short name T1061
Test name
Test status
Simulation time 106083625 ps
CPU time 2.87 seconds
Started May 21 03:27:43 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 215224 kb
Host smart-d67b96c7-8fa6-4c14-b1ff-bb48be8f1025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755050489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3755050489
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2896544320
Short name T990
Test name
Test status
Simulation time 33451824 ps
CPU time 0.72 seconds
Started May 21 03:27:43 PM PDT 24
Finished May 21 03:27:45 PM PDT 24
Peak memory 203904 kb
Host smart-c6f66fe6-9ca2-4371-8f5c-759958bf45dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896544320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2896544320
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2364875804
Short name T164
Test name
Test status
Simulation time 131375194 ps
CPU time 1.88 seconds
Started May 21 03:27:45 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 215216 kb
Host smart-120afacf-4ca6-442c-8cbb-246c0d2cabe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364875804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2364875804
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.618864278
Short name T113
Test name
Test status
Simulation time 38449152 ps
CPU time 2.57 seconds
Started May 21 03:27:44 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 215292 kb
Host smart-fc5357f7-0678-4141-a7b2-c282629e97c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618864278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.618864278
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1047473933
Short name T1055
Test name
Test status
Simulation time 2378257266 ps
CPU time 15.22 seconds
Started May 21 03:27:43 PM PDT 24
Finished May 21 03:28:00 PM PDT 24
Peak memory 215560 kb
Host smart-7a5b0dea-adb7-4485-9d68-d008badfbaa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047473933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1047473933
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1489851251
Short name T999
Test name
Test status
Simulation time 83032823 ps
CPU time 1.58 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:52 PM PDT 24
Peak memory 215260 kb
Host smart-e86de0e1-f15d-4fed-9c7b-39883d957048
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489851251 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1489851251
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3270174890
Short name T998
Test name
Test status
Simulation time 252309824 ps
CPU time 1.53 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:53 PM PDT 24
Peak memory 207088 kb
Host smart-e3a5022d-a852-4772-9076-f915e46a4408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270174890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3270174890
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2354979808
Short name T1014
Test name
Test status
Simulation time 63065210 ps
CPU time 0.71 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:52 PM PDT 24
Peak memory 203580 kb
Host smart-240fae7f-b7a6-468c-804b-59249506826c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354979808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2354979808
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.398269740
Short name T1016
Test name
Test status
Simulation time 475174592 ps
CPU time 3.95 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:56 PM PDT 24
Peak memory 215220 kb
Host smart-3443071d-3006-483e-b9ce-71005224d69e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398269740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.398269740
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.361065498
Short name T279
Test name
Test status
Simulation time 368609886 ps
CPU time 8.4 seconds
Started May 21 03:27:50 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 215520 kb
Host smart-74c51f1b-c6af-4a4a-9583-9bff0c065da3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361065498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.361065498
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1497306241
Short name T124
Test name
Test status
Simulation time 47856553 ps
CPU time 3.74 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:56 PM PDT 24
Peak memory 216888 kb
Host smart-c256a79a-e86b-4fa8-b840-9dc236ddcec1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497306241 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1497306241
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2007395909
Short name T1057
Test name
Test status
Simulation time 256652518 ps
CPU time 2.37 seconds
Started May 21 03:27:51 PM PDT 24
Finished May 21 03:27:56 PM PDT 24
Peak memory 215128 kb
Host smart-2350d564-5cd3-4690-ba16-07d181b4db07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007395909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2007395909
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3031834540
Short name T1025
Test name
Test status
Simulation time 40916608 ps
CPU time 0.68 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:51 PM PDT 24
Peak memory 203564 kb
Host smart-339e4775-b75f-43e9-87e5-de38ba7d0be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031834540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3031834540
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.537125211
Short name T1002
Test name
Test status
Simulation time 90087827 ps
CPU time 1.74 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:51 PM PDT 24
Peak memory 215224 kb
Host smart-390596b2-44c3-4429-88c9-e4db0f8d0be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537125211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.537125211
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3447582588
Short name T119
Test name
Test status
Simulation time 181569507 ps
CPU time 3.25 seconds
Started May 21 03:27:51 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 216440 kb
Host smart-cc5c5a1e-2cb2-4a0c-89a6-0bb5dbbb2c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447582588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3447582588
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4246449201
Short name T120
Test name
Test status
Simulation time 274651131 ps
CPU time 2.76 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:55 PM PDT 24
Peak memory 216972 kb
Host smart-9d4eb415-bd76-462f-9c1a-d0a4ccbeb7d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246449201 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4246449201
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.410165943
Short name T1051
Test name
Test status
Simulation time 50466354 ps
CPU time 1.76 seconds
Started May 21 03:27:47 PM PDT 24
Finished May 21 03:27:50 PM PDT 24
Peak memory 215216 kb
Host smart-2b61ed9f-e32f-4962-a498-09034002fd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410165943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.410165943
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1696830880
Short name T973
Test name
Test status
Simulation time 31599033 ps
CPU time 0.71 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:52 PM PDT 24
Peak memory 203608 kb
Host smart-d02b18b6-ee59-4e99-8b9e-cc958410c5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696830880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1696830880
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2832584063
Short name T1030
Test name
Test status
Simulation time 26991648 ps
CPU time 1.61 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:52 PM PDT 24
Peak memory 215248 kb
Host smart-7ffd3c8a-e08c-417f-965e-8e19ec88abf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832584063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2832584063
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2862576762
Short name T118
Test name
Test status
Simulation time 239419820 ps
CPU time 3.71 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:56 PM PDT 24
Peak memory 215352 kb
Host smart-2c5caf1f-86c4-4c7d-8fbe-5a29a8b44e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862576762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2862576762
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2047211179
Short name T1074
Test name
Test status
Simulation time 2184265773 ps
CPU time 25.71 seconds
Started May 21 03:27:52 PM PDT 24
Finished May 21 03:28:21 PM PDT 24
Peak memory 215304 kb
Host smart-849536fe-fbc4-4aa1-a325-5b3a411696ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047211179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2047211179
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2159716207
Short name T1065
Test name
Test status
Simulation time 1200863368 ps
CPU time 3.76 seconds
Started May 21 03:27:52 PM PDT 24
Finished May 21 03:27:59 PM PDT 24
Peak memory 216540 kb
Host smart-ddec5b6a-28ca-4dfe-a8aa-363e24b76992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159716207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2159716207
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1100814197
Short name T132
Test name
Test status
Simulation time 35622373 ps
CPU time 1.3 seconds
Started May 21 03:27:48 PM PDT 24
Finished May 21 03:27:52 PM PDT 24
Peak memory 206952 kb
Host smart-dc03a67b-0d84-49f9-9ffa-a0a9ef50d480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100814197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1100814197
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1548510527
Short name T1006
Test name
Test status
Simulation time 11963742 ps
CPU time 0.78 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:53 PM PDT 24
Peak memory 203636 kb
Host smart-65614bc0-f88d-440d-895f-f5cc0419d3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548510527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1548510527
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.8178445
Short name T978
Test name
Test status
Simulation time 58450580 ps
CPU time 3.9 seconds
Started May 21 03:27:50 PM PDT 24
Finished May 21 03:27:57 PM PDT 24
Peak memory 215212 kb
Host smart-e28a52fe-1ffb-4ce4-954c-8dcc8c044527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8178445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi
_device_same_csr_outstanding.8178445
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.349289394
Short name T121
Test name
Test status
Simulation time 84636543 ps
CPU time 1.35 seconds
Started May 21 03:27:51 PM PDT 24
Finished May 21 03:27:55 PM PDT 24
Peak memory 215340 kb
Host smart-0c563324-9fc1-486f-80c4-a2ef727744b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349289394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.349289394
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3048063535
Short name T281
Test name
Test status
Simulation time 197638709 ps
CPU time 6.81 seconds
Started May 21 03:27:50 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 217124 kb
Host smart-3570aba2-85dc-4533-8653-cfd4b5886a75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048063535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3048063535
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3398019595
Short name T139
Test name
Test status
Simulation time 179627224 ps
CPU time 2.56 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:27:59 PM PDT 24
Peak memory 215104 kb
Host smart-7832f515-af86-415f-9281-acd718d541ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398019595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3398019595
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.320197925
Short name T1023
Test name
Test status
Simulation time 11291354 ps
CPU time 0.73 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 203580 kb
Host smart-b8e892a8-bdfe-420a-a4af-123ee710bba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320197925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.320197925
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.91965669
Short name T162
Test name
Test status
Simulation time 1443172732 ps
CPU time 3.55 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 215200 kb
Host smart-be9036da-b027-4987-a723-046e8ec72eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91965669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp
i_device_same_csr_outstanding.91965669
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1621125476
Short name T1060
Test name
Test status
Simulation time 325939445 ps
CPU time 2.17 seconds
Started May 21 03:27:53 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 215488 kb
Host smart-b0a132bb-b249-4a53-bb11-170ce60b3999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621125476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1621125476
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4289694831
Short name T167
Test name
Test status
Simulation time 634372703 ps
CPU time 7.5 seconds
Started May 21 03:27:56 PM PDT 24
Finished May 21 03:28:06 PM PDT 24
Peak memory 215224 kb
Host smart-0d1d8359-126a-49a4-a242-973f92ac1cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289694831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4289694831
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.540783815
Short name T994
Test name
Test status
Simulation time 40574555 ps
CPU time 2.95 seconds
Started May 21 03:27:52 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 216964 kb
Host smart-f08c6aa9-3ade-44d3-8bac-b4f2d4a9a157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540783815 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.540783815
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1731982779
Short name T1043
Test name
Test status
Simulation time 35155017 ps
CPU time 2.26 seconds
Started May 21 03:27:56 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 214968 kb
Host smart-ed8fc42b-ba1c-4559-9856-a93ba5fac95c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731982779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1731982779
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2288952793
Short name T980
Test name
Test status
Simulation time 28477331 ps
CPU time 0.72 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 203608 kb
Host smart-72582d05-8e98-44f6-add6-afcae21ee521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288952793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2288952793
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4137989940
Short name T1064
Test name
Test status
Simulation time 122376302 ps
CPU time 1.87 seconds
Started May 21 03:27:53 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 215272 kb
Host smart-3e0dcf48-410c-4c0b-907e-0a7fac7969fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137989940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4137989940
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1758997626
Short name T273
Test name
Test status
Simulation time 265329562 ps
CPU time 6.95 seconds
Started May 21 03:27:55 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 215300 kb
Host smart-5aa0cac6-d1ed-4ef5-9a20-c1a733221e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758997626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1758997626
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2909062101
Short name T1053
Test name
Test status
Simulation time 839597768 ps
CPU time 3.87 seconds
Started May 21 03:27:53 PM PDT 24
Finished May 21 03:28:00 PM PDT 24
Peak memory 217712 kb
Host smart-c1330ab5-4c1c-472e-8540-e26b07b3dd64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909062101 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2909062101
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2893953546
Short name T1072
Test name
Test status
Simulation time 53480088 ps
CPU time 0.74 seconds
Started May 21 03:27:53 PM PDT 24
Finished May 21 03:27:57 PM PDT 24
Peak memory 203912 kb
Host smart-4d938287-0203-4afa-a118-23472a89ce8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893953546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2893953546
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3179414242
Short name T1080
Test name
Test status
Simulation time 542463944 ps
CPU time 3.04 seconds
Started May 21 03:27:56 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 215180 kb
Host smart-33ffefcd-68da-4d08-8e29-7aaf79b4ef4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179414242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3179414242
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1497017679
Short name T122
Test name
Test status
Simulation time 308771398 ps
CPU time 3.09 seconds
Started May 21 03:27:52 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 215540 kb
Host smart-294b7ce5-1155-4a98-b559-4305a8351db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497017679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1497017679
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2979684859
Short name T987
Test name
Test status
Simulation time 247787947 ps
CPU time 1.69 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:04 PM PDT 24
Peak memory 216276 kb
Host smart-6d04ba03-91c9-4cae-9290-174d7063d8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979684859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2979684859
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.211087057
Short name T153
Test name
Test status
Simulation time 19831797 ps
CPU time 1.16 seconds
Started May 21 03:27:56 PM PDT 24
Finished May 21 03:28:00 PM PDT 24
Peak memory 214940 kb
Host smart-8a9dd96a-6725-4f53-a119-30c6a8cd9e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211087057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.211087057
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2134521896
Short name T993
Test name
Test status
Simulation time 13212719 ps
CPU time 0.73 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:27:58 PM PDT 24
Peak memory 203740 kb
Host smart-41308b20-2e21-4083-a2ef-b63c7aea4b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134521896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2134521896
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2175854919
Short name T1031
Test name
Test status
Simulation time 69503716 ps
CPU time 1.9 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 215180 kb
Host smart-3e059e71-94c9-41fb-8e18-07db07678b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175854919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2175854919
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.981294878
Short name T123
Test name
Test status
Simulation time 223583274 ps
CPU time 4.32 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 216280 kb
Host smart-ac7e41e0-4a6e-4b17-8055-8fff1ea08323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981294878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.981294878
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1238496770
Short name T1048
Test name
Test status
Simulation time 712979160 ps
CPU time 16.69 seconds
Started May 21 03:27:54 PM PDT 24
Finished May 21 03:28:14 PM PDT 24
Peak memory 215244 kb
Host smart-89914f17-a3d0-4231-8f3d-de3d1c9759cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238496770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1238496770
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2237651177
Short name T129
Test name
Test status
Simulation time 817848562 ps
CPU time 21.69 seconds
Started May 21 03:27:19 PM PDT 24
Finished May 21 03:27:42 PM PDT 24
Peak memory 215152 kb
Host smart-29690444-aa32-4c9d-9825-f91b46ac28b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237651177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2237651177
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2506359413
Short name T135
Test name
Test status
Simulation time 937029143 ps
CPU time 12.78 seconds
Started May 21 03:27:19 PM PDT 24
Finished May 21 03:27:33 PM PDT 24
Peak memory 206940 kb
Host smart-18df89ab-1d5c-45d9-a49a-e1ccba621fee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506359413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2506359413
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2177801957
Short name T91
Test name
Test status
Simulation time 97506504 ps
CPU time 1.04 seconds
Started May 21 03:27:16 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 206764 kb
Host smart-31babf3d-f04e-4548-b026-56a831f5ca1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177801957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2177801957
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1837376402
Short name T997
Test name
Test status
Simulation time 98081493 ps
CPU time 2.83 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 217748 kb
Host smart-48219bcd-407f-43b5-91ad-0e0b0443fb81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837376402 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1837376402
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1890239394
Short name T983
Test name
Test status
Simulation time 33319505 ps
CPU time 2 seconds
Started May 21 03:27:17 PM PDT 24
Finished May 21 03:27:20 PM PDT 24
Peak memory 215156 kb
Host smart-71870a5e-d0d5-4a2c-92de-993072112168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890239394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
890239394
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.875013042
Short name T1000
Test name
Test status
Simulation time 22888007 ps
CPU time 0.74 seconds
Started May 21 03:27:16 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 203584 kb
Host smart-6e2b40e8-d1ba-490c-be34-a728e40a6819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875013042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.875013042
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1854789098
Short name T992
Test name
Test status
Simulation time 150618114 ps
CPU time 1.31 seconds
Started May 21 03:27:19 PM PDT 24
Finished May 21 03:27:21 PM PDT 24
Peak memory 215304 kb
Host smart-ab47d02a-facf-4c16-9c06-2754c169c424
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854789098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1854789098
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4278222995
Short name T974
Test name
Test status
Simulation time 30545552 ps
CPU time 0.66 seconds
Started May 21 03:27:16 PM PDT 24
Finished May 21 03:27:18 PM PDT 24
Peak memory 203504 kb
Host smart-21123385-e8a1-42ff-993e-2c49a2651180
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278222995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4278222995
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.658734301
Short name T985
Test name
Test status
Simulation time 258012413 ps
CPU time 2.04 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:28 PM PDT 24
Peak memory 215200 kb
Host smart-4a531fb9-f310-42dd-b9a8-cfdd92ff552b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658734301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.658734301
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4236542443
Short name T1069
Test name
Test status
Simulation time 48383922 ps
CPU time 1.46 seconds
Started May 21 03:27:17 PM PDT 24
Finished May 21 03:27:20 PM PDT 24
Peak memory 216324 kb
Host smart-e2042244-6ff0-4eab-bd3f-11154a877d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236542443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
236542443
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3162193702
Short name T276
Test name
Test status
Simulation time 1069168166 ps
CPU time 12.3 seconds
Started May 21 03:27:19 PM PDT 24
Finished May 21 03:27:33 PM PDT 24
Peak memory 215256 kb
Host smart-d2a59f07-d2ba-45a4-8fe2-d451d023ad57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162193702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3162193702
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1786728485
Short name T1019
Test name
Test status
Simulation time 35136564 ps
CPU time 0.76 seconds
Started May 21 03:27:59 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 203600 kb
Host smart-bcfc2f69-e058-496b-8211-ae97cd8d8338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786728485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1786728485
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.750245676
Short name T1027
Test name
Test status
Simulation time 21621824 ps
CPU time 0.71 seconds
Started May 21 03:28:04 PM PDT 24
Finished May 21 03:28:06 PM PDT 24
Peak memory 203908 kb
Host smart-c16da79b-3de1-44fd-bd21-4ca3a2f2fb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750245676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.750245676
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2381371718
Short name T972
Test name
Test status
Simulation time 10896034 ps
CPU time 0.72 seconds
Started May 21 03:28:02 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 203588 kb
Host smart-1fc480e5-387f-42c2-9887-e823bb8bd963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381371718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2381371718
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1850150528
Short name T982
Test name
Test status
Simulation time 19848818 ps
CPU time 0.78 seconds
Started May 21 03:28:02 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 203632 kb
Host smart-c1dd5673-b4aa-4a54-86af-2ed67b907236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850150528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1850150528
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2538925984
Short name T1063
Test name
Test status
Simulation time 12050751 ps
CPU time 0.83 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 203624 kb
Host smart-670e1a59-ed76-4c12-ba63-ed9d57a87d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538925984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2538925984
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4004797716
Short name T971
Test name
Test status
Simulation time 11127486 ps
CPU time 0.69 seconds
Started May 21 03:27:59 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 203888 kb
Host smart-1d47654e-9669-4297-94d5-d36d65e090ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004797716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4004797716
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2343774749
Short name T979
Test name
Test status
Simulation time 20104993 ps
CPU time 0.77 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:02 PM PDT 24
Peak memory 203588 kb
Host smart-163f5fa5-1067-4259-a911-b036b82799b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343774749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2343774749
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1057945534
Short name T1046
Test name
Test status
Simulation time 28821555 ps
CPU time 0.74 seconds
Started May 21 03:28:02 PM PDT 24
Finished May 21 03:28:05 PM PDT 24
Peak memory 203568 kb
Host smart-1cb68ac5-16d2-4c76-9a64-795abb43bb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057945534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1057945534
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.466991413
Short name T1035
Test name
Test status
Simulation time 39841745 ps
CPU time 0.73 seconds
Started May 21 03:28:06 PM PDT 24
Finished May 21 03:28:09 PM PDT 24
Peak memory 203900 kb
Host smart-b0c15ed9-2a92-4c93-ad1c-958fc600346a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466991413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.466991413
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3347398013
Short name T1020
Test name
Test status
Simulation time 35466799 ps
CPU time 0.74 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:03 PM PDT 24
Peak memory 203588 kb
Host smart-8e1b7e70-d57f-483d-98f0-da998f57c361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347398013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3347398013
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4033453585
Short name T1003
Test name
Test status
Simulation time 770281312 ps
CPU time 15.04 seconds
Started May 21 03:27:23 PM PDT 24
Finished May 21 03:27:39 PM PDT 24
Peak memory 215132 kb
Host smart-a6e60105-aba5-4442-a5e5-884b16bc8c1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033453585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4033453585
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.472013768
Short name T136
Test name
Test status
Simulation time 191535296 ps
CPU time 11.64 seconds
Started May 21 03:27:26 PM PDT 24
Finished May 21 03:27:38 PM PDT 24
Peak memory 215136 kb
Host smart-4f67f9ea-1234-4834-a3eb-f789ef7d217e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472013768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.472013768
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.454960540
Short name T1042
Test name
Test status
Simulation time 18702188 ps
CPU time 1.16 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:27 PM PDT 24
Peak memory 216200 kb
Host smart-24df9a11-deed-4117-a736-4efb3a32e0f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454960540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.454960540
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1159786077
Short name T1068
Test name
Test status
Simulation time 334766191 ps
CPU time 3.16 seconds
Started May 21 03:27:23 PM PDT 24
Finished May 21 03:27:27 PM PDT 24
Peak memory 216608 kb
Host smart-b445506a-13de-4868-be92-2c078fc530b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159786077 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1159786077
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1934586372
Short name T133
Test name
Test status
Simulation time 150649276 ps
CPU time 1.35 seconds
Started May 21 03:27:22 PM PDT 24
Finished May 21 03:27:24 PM PDT 24
Peak memory 206968 kb
Host smart-e96d5bf5-5d16-4797-a577-007b05669a2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934586372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
934586372
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4118635483
Short name T976
Test name
Test status
Simulation time 18290011 ps
CPU time 0.76 seconds
Started May 21 03:27:22 PM PDT 24
Finished May 21 03:27:24 PM PDT 24
Peak memory 203616 kb
Host smart-11d34514-c11a-471f-b8b5-d1d9c9e153d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118635483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
118635483
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3076333538
Short name T127
Test name
Test status
Simulation time 52096310 ps
CPU time 2.22 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:27 PM PDT 24
Peak memory 215308 kb
Host smart-0ed6a4c8-a572-4a15-946c-c55ba7a79efe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076333538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3076333538
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1331284507
Short name T967
Test name
Test status
Simulation time 12397345 ps
CPU time 0.67 seconds
Started May 21 03:27:21 PM PDT 24
Finished May 21 03:27:23 PM PDT 24
Peak memory 203456 kb
Host smart-9236a1d9-f929-4638-9686-a5a31d87d1b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331284507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1331284507
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3493877491
Short name T1062
Test name
Test status
Simulation time 59584174 ps
CPU time 3.98 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:29 PM PDT 24
Peak memory 215160 kb
Host smart-218a5736-e7c1-4ecf-934a-be73f99d9d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493877491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3493877491
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1251523259
Short name T1052
Test name
Test status
Simulation time 53506863 ps
CPU time 1.71 seconds
Started May 21 03:27:23 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 215476 kb
Host smart-6fe9d9fa-b103-484e-b197-7a1be505ac24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251523259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
251523259
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366177241
Short name T274
Test name
Test status
Simulation time 3656226334 ps
CPU time 21.61 seconds
Started May 21 03:27:23 PM PDT 24
Finished May 21 03:27:46 PM PDT 24
Peak memory 215908 kb
Host smart-42976580-6bdb-4566-9daf-e960f922b803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366177241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2366177241
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4079702227
Short name T1008
Test name
Test status
Simulation time 13202167 ps
CPU time 0.7 seconds
Started May 21 03:27:59 PM PDT 24
Finished May 21 03:28:01 PM PDT 24
Peak memory 203604 kb
Host smart-771750e2-642b-4d81-bd67-44cb82df01e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079702227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4079702227
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4274955987
Short name T1070
Test name
Test status
Simulation time 17845174 ps
CPU time 0.74 seconds
Started May 21 03:28:04 PM PDT 24
Finished May 21 03:28:06 PM PDT 24
Peak memory 203592 kb
Host smart-f38a4d6c-b3b3-4fe2-bdb0-bf311464ad7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274955987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4274955987
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.725933634
Short name T970
Test name
Test status
Simulation time 34242176 ps
CPU time 0.74 seconds
Started May 21 03:28:03 PM PDT 24
Finished May 21 03:28:06 PM PDT 24
Peak memory 203588 kb
Host smart-57ed5d74-b66a-42b2-9fc6-fc664af573b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725933634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.725933634
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4053797988
Short name T1010
Test name
Test status
Simulation time 19654257 ps
CPU time 0.68 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:03 PM PDT 24
Peak memory 203612 kb
Host smart-fafed386-21a9-4f68-a88e-b80fdb18037f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053797988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4053797988
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3133083365
Short name T1022
Test name
Test status
Simulation time 13105172 ps
CPU time 0.74 seconds
Started May 21 03:28:02 PM PDT 24
Finished May 21 03:28:06 PM PDT 24
Peak memory 203604 kb
Host smart-104c83c7-160c-4517-9d9b-cb904b7f3b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133083365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3133083365
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.344532977
Short name T1040
Test name
Test status
Simulation time 84612098 ps
CPU time 0.73 seconds
Started May 21 03:28:00 PM PDT 24
Finished May 21 03:28:03 PM PDT 24
Peak memory 203576 kb
Host smart-a7a2ac48-4cad-4b45-9f89-fd2b8096f9b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344532977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.344532977
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.94409333
Short name T1077
Test name
Test status
Simulation time 15096519 ps
CPU time 0.71 seconds
Started May 21 03:28:01 PM PDT 24
Finished May 21 03:28:04 PM PDT 24
Peak memory 203868 kb
Host smart-58514fe6-6ccc-4f1a-a2fa-d77139cc8e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94409333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.94409333
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3102557024
Short name T1045
Test name
Test status
Simulation time 13556057 ps
CPU time 0.69 seconds
Started May 21 03:28:06 PM PDT 24
Finished May 21 03:28:09 PM PDT 24
Peak memory 203904 kb
Host smart-baa88854-71b7-4d76-a88c-d03d4754ca2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102557024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3102557024
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4265323904
Short name T969
Test name
Test status
Simulation time 33910855 ps
CPU time 0.68 seconds
Started May 21 03:28:05 PM PDT 24
Finished May 21 03:28:08 PM PDT 24
Peak memory 203632 kb
Host smart-20772602-e013-4f50-839f-3121f52edc0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265323904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4265323904
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2667533570
Short name T1001
Test name
Test status
Simulation time 12657631 ps
CPU time 0.72 seconds
Started May 21 03:28:09 PM PDT 24
Finished May 21 03:28:12 PM PDT 24
Peak memory 203596 kb
Host smart-17dc0156-1b7a-4b87-b682-fe8db46bd382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667533570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2667533570
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1149700585
Short name T1044
Test name
Test status
Simulation time 3399147082 ps
CPU time 8.29 seconds
Started May 21 03:27:32 PM PDT 24
Finished May 21 03:27:41 PM PDT 24
Peak memory 207020 kb
Host smart-f6846b7b-20d6-46e0-a433-c44f0e89f205
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149700585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1149700585
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2548089841
Short name T131
Test name
Test status
Simulation time 555394550 ps
CPU time 35.06 seconds
Started May 21 03:27:30 PM PDT 24
Finished May 21 03:28:06 PM PDT 24
Peak memory 206912 kb
Host smart-73a46805-fcff-4434-b07b-d98357143701
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548089841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2548089841
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2917123354
Short name T90
Test name
Test status
Simulation time 101985026 ps
CPU time 1.46 seconds
Started May 21 03:27:30 PM PDT 24
Finished May 21 03:27:32 PM PDT 24
Peak memory 206900 kb
Host smart-13e45b24-5d89-43b1-90cd-4c14a90cbcea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917123354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2917123354
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1191256943
Short name T1028
Test name
Test status
Simulation time 371597636 ps
CPU time 3.07 seconds
Started May 21 03:27:30 PM PDT 24
Finished May 21 03:27:34 PM PDT 24
Peak memory 216548 kb
Host smart-ffc5c178-23aa-4d34-8dc8-376402eb614a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191256943 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1191256943
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4274840077
Short name T128
Test name
Test status
Simulation time 100544756 ps
CPU time 2.75 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:35 PM PDT 24
Peak memory 215196 kb
Host smart-38b93c44-d584-4f3f-b893-d8e968cf7d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274840077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
274840077
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2231382591
Short name T1034
Test name
Test status
Simulation time 17076935 ps
CPU time 0.77 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 203600 kb
Host smart-6c8e1122-afac-48ad-823f-c5a8e7725f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231382591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
231382591
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1486681365
Short name T1038
Test name
Test status
Simulation time 163984501 ps
CPU time 1.85 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:34 PM PDT 24
Peak memory 215292 kb
Host smart-01c16c8a-4031-4b0d-8235-fb0ec8b8f268
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486681365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1486681365
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1926834102
Short name T1018
Test name
Test status
Simulation time 36714482 ps
CPU time 0.66 seconds
Started May 21 03:27:24 PM PDT 24
Finished May 21 03:27:26 PM PDT 24
Peak memory 203484 kb
Host smart-331ab60d-0760-4a2e-83a5-db45eda56578
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926834102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1926834102
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1885165434
Short name T1033
Test name
Test status
Simulation time 108817586 ps
CPU time 2.77 seconds
Started May 21 03:27:29 PM PDT 24
Finished May 21 03:27:33 PM PDT 24
Peak memory 215240 kb
Host smart-84de4393-c9bd-4be1-8b03-923a99b30037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885165434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1885165434
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2086948302
Short name T271
Test name
Test status
Simulation time 165429503 ps
CPU time 2.83 seconds
Started May 21 03:27:22 PM PDT 24
Finished May 21 03:27:27 PM PDT 24
Peak memory 215460 kb
Host smart-542cc363-ec84-4406-aacd-c0ccd23c7722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086948302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
086948302
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.159997774
Short name T1054
Test name
Test status
Simulation time 556448806 ps
CPU time 14.99 seconds
Started May 21 03:27:25 PM PDT 24
Finished May 21 03:27:41 PM PDT 24
Peak memory 215348 kb
Host smart-8abb56a1-08e3-45f8-9d24-8864091bccc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159997774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.159997774
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.634388593
Short name T1015
Test name
Test status
Simulation time 13172054 ps
CPU time 0.77 seconds
Started May 21 03:28:07 PM PDT 24
Finished May 21 03:28:10 PM PDT 24
Peak memory 203576 kb
Host smart-4671cb4d-53f5-4b62-8da2-19ecf915e9d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634388593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.634388593
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.559083720
Short name T1039
Test name
Test status
Simulation time 15558443 ps
CPU time 0.77 seconds
Started May 21 03:28:11 PM PDT 24
Finished May 21 03:28:13 PM PDT 24
Peak memory 203596 kb
Host smart-a1289be4-a4b5-4aea-bb36-43440b684de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559083720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.559083720
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2825628662
Short name T1026
Test name
Test status
Simulation time 13835237 ps
CPU time 0.69 seconds
Started May 21 03:28:06 PM PDT 24
Finished May 21 03:28:10 PM PDT 24
Peak memory 203564 kb
Host smart-6c5b23c0-d7af-41fa-a925-321705107b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825628662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2825628662
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.352439059
Short name T968
Test name
Test status
Simulation time 43350158 ps
CPU time 0.78 seconds
Started May 21 03:28:07 PM PDT 24
Finished May 21 03:28:10 PM PDT 24
Peak memory 203904 kb
Host smart-160fcf24-4108-48fc-a941-7b127947ff0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352439059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.352439059
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.11264291
Short name T977
Test name
Test status
Simulation time 12838587 ps
CPU time 0.75 seconds
Started May 21 03:28:08 PM PDT 24
Finished May 21 03:28:11 PM PDT 24
Peak memory 203568 kb
Host smart-934062c5-ad46-4081-9d60-0fb9aae8dfda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11264291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.11264291
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2213040825
Short name T988
Test name
Test status
Simulation time 26425317 ps
CPU time 0.86 seconds
Started May 21 03:28:16 PM PDT 24
Finished May 21 03:28:18 PM PDT 24
Peak memory 203900 kb
Host smart-6b679eb5-bd53-40fd-a22e-e48ce8d7daf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213040825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2213040825
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3965677625
Short name T986
Test name
Test status
Simulation time 29441544 ps
CPU time 0.79 seconds
Started May 21 03:28:11 PM PDT 24
Finished May 21 03:28:12 PM PDT 24
Peak memory 203904 kb
Host smart-d91422c8-2951-4154-aa1e-8ebe9226942e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965677625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3965677625
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.657366228
Short name T966
Test name
Test status
Simulation time 14959835 ps
CPU time 0.71 seconds
Started May 21 03:28:06 PM PDT 24
Finished May 21 03:28:10 PM PDT 24
Peak memory 203604 kb
Host smart-b78cdca9-be3d-4652-9d43-bdc3d75004db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657366228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.657366228
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2030387253
Short name T1017
Test name
Test status
Simulation time 13350065 ps
CPU time 0.7 seconds
Started May 21 03:28:05 PM PDT 24
Finished May 21 03:28:08 PM PDT 24
Peak memory 203896 kb
Host smart-fe04594c-0040-4199-b16f-a560be20ba76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030387253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2030387253
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3024623481
Short name T1073
Test name
Test status
Simulation time 15508424 ps
CPU time 0.8 seconds
Started May 21 03:28:08 PM PDT 24
Finished May 21 03:28:11 PM PDT 24
Peak memory 203532 kb
Host smart-9c8db7c6-cac0-4af5-b4f1-b389428bcb5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024623481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3024623481
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1917647778
Short name T1056
Test name
Test status
Simulation time 52882150 ps
CPU time 1.64 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:34 PM PDT 24
Peak memory 215320 kb
Host smart-1ed13088-4ba3-452b-9add-04a9294e4682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917647778 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1917647778
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2129852695
Short name T137
Test name
Test status
Simulation time 40584618 ps
CPU time 1.28 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:33 PM PDT 24
Peak memory 206964 kb
Host smart-4db69c6d-2f3d-44cd-bfc0-156006783375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129852695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
129852695
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3362461124
Short name T1029
Test name
Test status
Simulation time 56880976 ps
CPU time 0.79 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:33 PM PDT 24
Peak memory 203576 kb
Host smart-7759d724-1b99-442a-ac7e-a6c6927e85ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362461124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
362461124
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2338071569
Short name T1011
Test name
Test status
Simulation time 153626751 ps
CPU time 4 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:36 PM PDT 24
Peak memory 215240 kb
Host smart-c6671c9c-52d4-4a2f-9191-4226b09825b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338071569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2338071569
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.327681499
Short name T111
Test name
Test status
Simulation time 277217598 ps
CPU time 3.34 seconds
Started May 21 03:27:33 PM PDT 24
Finished May 21 03:27:37 PM PDT 24
Peak memory 215388 kb
Host smart-e0caf696-8196-455a-ab80-4a8f61e8ee21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327681499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.327681499
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.458985570
Short name T1050
Test name
Test status
Simulation time 1710289178 ps
CPU time 22.28 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:54 PM PDT 24
Peak memory 215240 kb
Host smart-9d040f7c-42bc-4265-b47e-937502786e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458985570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.458985570
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2862521524
Short name T71
Test name
Test status
Simulation time 610844011 ps
CPU time 3.73 seconds
Started May 21 03:27:50 PM PDT 24
Finished May 21 03:27:57 PM PDT 24
Peak memory 217988 kb
Host smart-c610ef29-969a-46b2-a7fc-a37ba4d03644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862521524 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2862521524
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3488300415
Short name T138
Test name
Test status
Simulation time 55767072 ps
CPU time 1.87 seconds
Started May 21 03:27:36 PM PDT 24
Finished May 21 03:27:39 PM PDT 24
Peak memory 215168 kb
Host smart-7f11d1ac-25bf-4197-8629-c71ac9291388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488300415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
488300415
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3627698900
Short name T1067
Test name
Test status
Simulation time 14122032 ps
CPU time 0.75 seconds
Started May 21 03:27:38 PM PDT 24
Finished May 21 03:27:40 PM PDT 24
Peak memory 203872 kb
Host smart-cb3abfe4-bde4-4121-8911-474d545696b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627698900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
627698900
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2495633201
Short name T1037
Test name
Test status
Simulation time 106633182 ps
CPU time 1.88 seconds
Started May 21 03:27:37 PM PDT 24
Finished May 21 03:27:40 PM PDT 24
Peak memory 207172 kb
Host smart-fe888b01-3bdb-432e-8640-fc884f98436c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495633201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2495633201
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2310523322
Short name T117
Test name
Test status
Simulation time 182936790 ps
CPU time 3.52 seconds
Started May 21 03:27:31 PM PDT 24
Finished May 21 03:27:35 PM PDT 24
Peak memory 215344 kb
Host smart-015fea77-a7e8-4e01-bb90-319ead8fb9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310523322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
310523322
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1827294899
Short name T165
Test name
Test status
Simulation time 701975773 ps
CPU time 16.24 seconds
Started May 21 03:27:37 PM PDT 24
Finished May 21 03:27:55 PM PDT 24
Peak memory 216368 kb
Host smart-c30494fc-ddaf-4c39-811e-9316e7662e61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827294899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1827294899
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.737081446
Short name T991
Test name
Test status
Simulation time 47753097 ps
CPU time 1.85 seconds
Started May 21 03:27:37 PM PDT 24
Finished May 21 03:27:40 PM PDT 24
Peak memory 215256 kb
Host smart-76e99618-eacd-49a9-ba3f-34f727157458
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737081446 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.737081446
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1912439242
Short name T1075
Test name
Test status
Simulation time 587025012 ps
CPU time 2.27 seconds
Started May 21 03:27:38 PM PDT 24
Finished May 21 03:27:42 PM PDT 24
Peak memory 215140 kb
Host smart-23df003a-d3cb-4b98-a8ef-07169ab72c81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912439242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
912439242
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1288693148
Short name T1007
Test name
Test status
Simulation time 14073334 ps
CPU time 0.7 seconds
Started May 21 03:27:37 PM PDT 24
Finished May 21 03:27:39 PM PDT 24
Peak memory 203608 kb
Host smart-fb76221e-af2d-4cbd-b252-53b392880efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288693148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
288693148
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1648367503
Short name T163
Test name
Test status
Simulation time 913839485 ps
CPU time 4.63 seconds
Started May 21 03:27:38 PM PDT 24
Finished May 21 03:27:44 PM PDT 24
Peak memory 215200 kb
Host smart-157a2bf5-8868-44b7-acaf-ca8730f9d454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648367503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1648367503
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3445866873
Short name T1049
Test name
Test status
Simulation time 1503167662 ps
CPU time 8.08 seconds
Started May 21 03:27:36 PM PDT 24
Finished May 21 03:27:46 PM PDT 24
Peak memory 215268 kb
Host smart-8240f2aa-7dc9-43c0-b210-a31aef513e75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445866873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3445866873
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3492615007
Short name T125
Test name
Test status
Simulation time 454748361 ps
CPU time 2.79 seconds
Started May 21 03:27:42 PM PDT 24
Finished May 21 03:27:47 PM PDT 24
Peak memory 216708 kb
Host smart-620c7c63-fabf-4b30-812c-21943df8aeaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492615007 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3492615007
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3179583856
Short name T1079
Test name
Test status
Simulation time 241689736 ps
CPU time 2.1 seconds
Started May 21 03:27:43 PM PDT 24
Finished May 21 03:27:47 PM PDT 24
Peak memory 206980 kb
Host smart-9aa4ea3b-5bc9-4f25-8153-71a05089724f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179583856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
179583856
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1172648541
Short name T1058
Test name
Test status
Simulation time 13339372 ps
CPU time 0.72 seconds
Started May 21 03:27:38 PM PDT 24
Finished May 21 03:27:40 PM PDT 24
Peak memory 203848 kb
Host smart-236d9aaf-a1ad-41f7-91ca-6f615f86a15c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172648541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
172648541
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3598033881
Short name T154
Test name
Test status
Simulation time 165901050 ps
CPU time 2.8 seconds
Started May 21 03:27:44 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 215212 kb
Host smart-f234c28f-3446-4534-82df-59067631a262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598033881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3598033881
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2909581909
Short name T110
Test name
Test status
Simulation time 385353410 ps
CPU time 5.51 seconds
Started May 21 03:27:37 PM PDT 24
Finished May 21 03:27:44 PM PDT 24
Peak memory 215352 kb
Host smart-963c6e16-1c4b-41f0-8c7d-a76460bb3c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909581909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
909581909
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.493717988
Short name T278
Test name
Test status
Simulation time 663121985 ps
CPU time 18.41 seconds
Started May 21 03:27:37 PM PDT 24
Finished May 21 03:27:57 PM PDT 24
Peak memory 215240 kb
Host smart-61d7de85-d362-4e71-aaf5-2d4e4c608ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493717988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.493717988
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.721856033
Short name T1078
Test name
Test status
Simulation time 565397899 ps
CPU time 3.25 seconds
Started May 21 03:27:49 PM PDT 24
Finished May 21 03:27:55 PM PDT 24
Peak memory 217128 kb
Host smart-2b737a92-ecca-494e-82cb-f619f5db00f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721856033 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.721856033
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2651189179
Short name T161
Test name
Test status
Simulation time 372133113 ps
CPU time 1.45 seconds
Started May 21 03:27:45 PM PDT 24
Finished May 21 03:27:48 PM PDT 24
Peak memory 215192 kb
Host smart-211c7c1e-3058-44e0-9075-598811842b75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651189179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
651189179
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1931692985
Short name T1066
Test name
Test status
Simulation time 15206681 ps
CPU time 0.75 seconds
Started May 21 03:27:42 PM PDT 24
Finished May 21 03:27:45 PM PDT 24
Peak memory 203604 kb
Host smart-73cf0f78-5321-45b9-a987-b3abc38efbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931692985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
931692985
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.649763047
Short name T995
Test name
Test status
Simulation time 162746746 ps
CPU time 2.85 seconds
Started May 21 03:27:41 PM PDT 24
Finished May 21 03:27:46 PM PDT 24
Peak memory 215168 kb
Host smart-18d986c5-63cd-4881-ad6d-a93f93e12ace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649763047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.649763047
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1793517824
Short name T1047
Test name
Test status
Simulation time 58442235 ps
CPU time 1.92 seconds
Started May 21 03:27:41 PM PDT 24
Finished May 21 03:27:44 PM PDT 24
Peak memory 215616 kb
Host smart-d4a0a583-b0b8-4c16-b88f-3dda83eb920f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793517824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
793517824
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2695667285
Short name T449
Test name
Test status
Simulation time 20315136 ps
CPU time 0.71 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:52 PM PDT 24
Peak memory 205144 kb
Host smart-721547e3-1be9-4af9-88cf-783db28abb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695667285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
695667285
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1185014285
Short name T372
Test name
Test status
Simulation time 239064277 ps
CPU time 2.38 seconds
Started May 21 12:26:22 PM PDT 24
Finished May 21 12:27:13 PM PDT 24
Peak memory 218196 kb
Host smart-1b2a7f8e-862e-447a-b13f-2a34a359221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185014285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1185014285
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.944966468
Short name T557
Test name
Test status
Simulation time 24647251 ps
CPU time 0.85 seconds
Started May 21 12:25:58 PM PDT 24
Finished May 21 12:26:18 PM PDT 24
Peak memory 206372 kb
Host smart-e84de392-3174-49b9-a78a-e6e74445a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944966468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.944966468
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2719675068
Short name T661
Test name
Test status
Simulation time 13251384674 ps
CPU time 35.32 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:27:18 PM PDT 24
Peak memory 240644 kb
Host smart-4ac23a79-421c-4547-b583-76c163fa88ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719675068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2719675068
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2560585643
Short name T257
Test name
Test status
Simulation time 2961186502 ps
CPU time 75.43 seconds
Started May 21 12:25:54 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 248840 kb
Host smart-5545df4e-e820-43dd-859c-46f1b89939e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560585643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2560585643
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2094481413
Short name T818
Test name
Test status
Simulation time 141750387 ps
CPU time 4.15 seconds
Started May 21 12:26:03 PM PDT 24
Finished May 21 12:26:29 PM PDT 24
Peak memory 232396 kb
Host smart-77590177-70de-4e01-9355-d8da60d6aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094481413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2094481413
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.41484665
Short name T626
Test name
Test status
Simulation time 284448656 ps
CPU time 5.71 seconds
Started May 21 12:25:56 PM PDT 24
Finished May 21 12:26:22 PM PDT 24
Peak memory 218272 kb
Host smart-93daddb2-9bb1-4445-92d2-8a769f4f49eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41484665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.41484665
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2354036271
Short name T899
Test name
Test status
Simulation time 14056788845 ps
CPU time 14.98 seconds
Started May 21 12:26:05 PM PDT 24
Finished May 21 12:26:45 PM PDT 24
Peak memory 246112 kb
Host smart-065f2552-b440-4725-8c52-4845f71f4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354036271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2354036271
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2832580971
Short name T506
Test name
Test status
Simulation time 46127811801 ps
CPU time 31.85 seconds
Started May 21 12:26:08 PM PDT 24
Finished May 21 12:27:07 PM PDT 24
Peak memory 234604 kb
Host smart-af6338e9-d84a-4daa-a83b-7c5057c843c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832580971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2832580971
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3038495572
Short name T726
Test name
Test status
Simulation time 1772163760 ps
CPU time 13.39 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:27:01 PM PDT 24
Peak memory 232880 kb
Host smart-d9c64751-c037-4b26-b19a-89b19b31911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038495572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3038495572
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.756474319
Short name T727
Test name
Test status
Simulation time 3686333226 ps
CPU time 10.24 seconds
Started May 21 12:26:02 PM PDT 24
Finished May 21 12:26:34 PM PDT 24
Peak memory 222228 kb
Host smart-dfd9cc20-74ba-4aeb-9dfa-59e156b50467
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=756474319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.756474319
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1320144914
Short name T75
Test name
Test status
Simulation time 54199619 ps
CPU time 1 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:08 PM PDT 24
Peak memory 234560 kb
Host smart-787b1476-14d3-49a8-9e1f-e4098dad2d49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320144914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1320144914
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3169745476
Short name T371
Test name
Test status
Simulation time 6210568527 ps
CPU time 21.2 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:27 PM PDT 24
Peak memory 215940 kb
Host smart-695ff9b8-370b-43c2-8f08-95b75ca3231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169745476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3169745476
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3812425192
Short name T356
Test name
Test status
Simulation time 613219077 ps
CPU time 2.91 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:43 PM PDT 24
Peak memory 215936 kb
Host smart-9f755cb3-07ac-489f-8fe4-c1132f03f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812425192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3812425192
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3155600035
Short name T802
Test name
Test status
Simulation time 155617059 ps
CPU time 2.71 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:26:55 PM PDT 24
Peak memory 215984 kb
Host smart-491f620e-7838-4c3c-8696-9f6db1ff0f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155600035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3155600035
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1890103050
Short name T921
Test name
Test status
Simulation time 74729211 ps
CPU time 0.79 seconds
Started May 21 12:26:09 PM PDT 24
Finished May 21 12:26:37 PM PDT 24
Peak memory 205500 kb
Host smart-ec563121-9a00-40d0-827a-f4385d34c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890103050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1890103050
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2260899317
Short name T337
Test name
Test status
Simulation time 467900810 ps
CPU time 2.26 seconds
Started May 21 12:26:01 PM PDT 24
Finished May 21 12:26:25 PM PDT 24
Peak memory 207612 kb
Host smart-765ac86f-bbd4-4a04-a933-3c0e69ea4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260899317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2260899317
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.387978638
Short name T583
Test name
Test status
Simulation time 24129003 ps
CPU time 0.71 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:03 PM PDT 24
Peak memory 204568 kb
Host smart-489eef52-ff30-4eea-bb18-a1999b137190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387978638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.387978638
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2043326615
Short name T763
Test name
Test status
Simulation time 395548337 ps
CPU time 3.68 seconds
Started May 21 12:26:15 PM PDT 24
Finished May 21 12:26:59 PM PDT 24
Peak memory 234096 kb
Host smart-5cb34e55-af40-419e-92f8-8c4265b4e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043326615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2043326615
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4005359494
Short name T868
Test name
Test status
Simulation time 20419799 ps
CPU time 0.81 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:26:44 PM PDT 24
Peak memory 206308 kb
Host smart-75287904-92dd-42f5-98e9-7b8c23465519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005359494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4005359494
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4100556168
Short name T792
Test name
Test status
Simulation time 6424092748 ps
CPU time 18.25 seconds
Started May 21 12:26:00 PM PDT 24
Finished May 21 12:26:40 PM PDT 24
Peak memory 240660 kb
Host smart-115d437e-3012-46b3-be03-85af4bd491eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100556168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4100556168
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.348434088
Short name T774
Test name
Test status
Simulation time 43908591198 ps
CPU time 101.43 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:28:48 PM PDT 24
Peak memory 240724 kb
Host smart-6c7373cc-ab1a-463c-ae95-5db058a9fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348434088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
348434088
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1791555730
Short name T404
Test name
Test status
Simulation time 167826705 ps
CPU time 4.47 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:54 PM PDT 24
Peak memory 224108 kb
Host smart-3ab880f0-eace-4069-bf15-3fd953d811d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791555730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1791555730
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1266486555
Short name T323
Test name
Test status
Simulation time 104663851 ps
CPU time 1.95 seconds
Started May 21 12:26:23 PM PDT 24
Finished May 21 12:27:14 PM PDT 24
Peak memory 215760 kb
Host smart-557fecde-74af-48ef-a1b8-9cbbc4bd5d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266486555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1266486555
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3765496484
Short name T754
Test name
Test status
Simulation time 485126677 ps
CPU time 6.2 seconds
Started May 21 12:26:03 PM PDT 24
Finished May 21 12:26:31 PM PDT 24
Peak memory 233944 kb
Host smart-00a83921-8d22-49cf-b8e3-e92b79ed73d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765496484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3765496484
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3708065494
Short name T516
Test name
Test status
Simulation time 16746616109 ps
CPU time 14.81 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:15 PM PDT 24
Peak memory 240512 kb
Host smart-7e7b4cf3-6c4c-405c-a8fc-15ecadfba8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708065494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3708065494
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1816403379
Short name T717
Test name
Test status
Simulation time 1992257937 ps
CPU time 6.52 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:52 PM PDT 24
Peak memory 220212 kb
Host smart-3d1abb3c-a46a-473c-8d16-3d0592f099f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1816403379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1816403379
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.106836368
Short name T76
Test name
Test status
Simulation time 84377342 ps
CPU time 1.11 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:26:43 PM PDT 24
Peak memory 234528 kb
Host smart-8a150fbe-14ed-4213-8fbf-9be6eb3bf2c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106836368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.106836368
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2906503387
Short name T332
Test name
Test status
Simulation time 46815269 ps
CPU time 0.69 seconds
Started May 21 12:26:07 PM PDT 24
Finished May 21 12:26:34 PM PDT 24
Peak memory 205340 kb
Host smart-6ed8f590-0aaa-4b7b-8a5d-2785ec669ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906503387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2906503387
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2038221390
Short name T349
Test name
Test status
Simulation time 84537925 ps
CPU time 4.57 seconds
Started May 21 12:25:53 PM PDT 24
Finished May 21 12:26:17 PM PDT 24
Peak memory 216120 kb
Host smart-c3627a71-f366-4f27-b530-4980a57ac213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038221390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2038221390
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3322137932
Short name T963
Test name
Test status
Simulation time 21850861 ps
CPU time 0.66 seconds
Started May 21 12:26:04 PM PDT 24
Finished May 21 12:26:27 PM PDT 24
Peak memory 205332 kb
Host smart-2403d68a-2560-4623-ab01-3191cecddcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322137932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3322137932
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1216745382
Short name T511
Test name
Test status
Simulation time 3068556755 ps
CPU time 5.62 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:56 PM PDT 24
Peak memory 218696 kb
Host smart-fcf7a682-f002-4fad-b4bd-ccd5f44abfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216745382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1216745382
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3212493666
Short name T353
Test name
Test status
Simulation time 11222049 ps
CPU time 0.68 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:17 PM PDT 24
Peak memory 205488 kb
Host smart-8d23f3d7-751a-4c2d-a884-c32aef1e4894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212493666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3212493666
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1201885489
Short name T298
Test name
Test status
Simulation time 618057890 ps
CPU time 5.41 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:11 PM PDT 24
Peak memory 218288 kb
Host smart-ddb1d4eb-0f60-4636-8935-61c2984d7a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201885489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1201885489
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2790129592
Short name T13
Test name
Test status
Simulation time 59073218 ps
CPU time 0.71 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:15 PM PDT 24
Peak memory 205236 kb
Host smart-2e4d6441-6baf-4e0d-b094-a6e86f775b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790129592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2790129592
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1648670862
Short name T267
Test name
Test status
Simulation time 16109197409 ps
CPU time 56.71 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:54 PM PDT 24
Peak memory 249408 kb
Host smart-6801479c-23b7-4e10-a15d-6a8b752c938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648670862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1648670862
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2592597167
Short name T249
Test name
Test status
Simulation time 58779709492 ps
CPU time 278.82 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:31:45 PM PDT 24
Peak memory 255904 kb
Host smart-90a1373e-cdcd-4d3c-b5a4-3cb8efb49c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592597167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2592597167
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.780802961
Short name T510
Test name
Test status
Simulation time 2495208008 ps
CPU time 31.43 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 238664 kb
Host smart-f7d55d59-07ae-47f5-9e7a-70c4abb0f22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780802961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.780802961
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2761195564
Short name T953
Test name
Test status
Simulation time 9443003225 ps
CPU time 30.28 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:49 PM PDT 24
Peak memory 219852 kb
Host smart-dfcac26f-6c6b-4423-a756-680793db1881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761195564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2761195564
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3915378125
Short name T829
Test name
Test status
Simulation time 30735575031 ps
CPU time 63.92 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 245044 kb
Host smart-4203441f-1b47-49c6-a4ed-ac08d6fa5a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915378125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3915378125
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3948199432
Short name T468
Test name
Test status
Simulation time 1462623009 ps
CPU time 5.07 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:12 PM PDT 24
Peak memory 235076 kb
Host smart-a8402f3c-ee94-4060-ad0e-dbda708e46c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948199432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3948199432
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1156949171
Short name T522
Test name
Test status
Simulation time 110885524 ps
CPU time 2.37 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:21 PM PDT 24
Peak memory 220980 kb
Host smart-53121e2a-0ce0-42fe-8493-12354b3f5cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156949171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1156949171
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1129344933
Short name T397
Test name
Test status
Simulation time 1038144959 ps
CPU time 3.94 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:02 PM PDT 24
Peak memory 220076 kb
Host smart-4db48139-7ff9-4d6e-a004-96653e74c8d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1129344933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1129344933
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.661804347
Short name T294
Test name
Test status
Simulation time 14920887573 ps
CPU time 178.42 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:30:06 PM PDT 24
Peak memory 256968 kb
Host smart-93a0280c-9c90-4143-a392-83513d8124dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661804347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.661804347
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3701554211
Short name T316
Test name
Test status
Simulation time 940867435 ps
CPU time 5.05 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:26 PM PDT 24
Peak memory 216072 kb
Host smart-164f25b6-35e8-4a3b-a565-fc82dc8440f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701554211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3701554211
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3169327298
Short name T98
Test name
Test status
Simulation time 20237237853 ps
CPU time 14.99 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 215912 kb
Host smart-4ba644cd-7a15-4fed-a288-b0ad02f50e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169327298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3169327298
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1276618370
Short name T500
Test name
Test status
Simulation time 48304785 ps
CPU time 1.43 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:27 PM PDT 24
Peak memory 216100 kb
Host smart-95ecbe39-965a-4180-838d-aa681d80de8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276618370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1276618370
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3591115633
Short name T629
Test name
Test status
Simulation time 25439218 ps
CPU time 0.76 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:01 PM PDT 24
Peak memory 205568 kb
Host smart-f01fdb27-98d9-48dd-86e7-8115d836ca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591115633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3591115633
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3869700765
Short name T210
Test name
Test status
Simulation time 796524769 ps
CPU time 2.31 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 218876 kb
Host smart-8b46bc49-cceb-4900-9cdb-df98d4866f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869700765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3869700765
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1298177037
Short name T840
Test name
Test status
Simulation time 28309677 ps
CPU time 0.72 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:19 PM PDT 24
Peak memory 205168 kb
Host smart-689cf443-834e-4b3d-8865-8d749a10210f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298177037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1298177037
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3904298248
Short name T879
Test name
Test status
Simulation time 814353462 ps
CPU time 7.64 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:27:29 PM PDT 24
Peak memory 233600 kb
Host smart-097a40e0-afc0-4df8-ba68-f9029e287255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904298248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3904298248
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3510140531
Short name T54
Test name
Test status
Simulation time 18988915 ps
CPU time 0.76 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:18 PM PDT 24
Peak memory 206312 kb
Host smart-34a2a871-3563-4b63-b249-64f9750c455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510140531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3510140531
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3375080141
Short name T287
Test name
Test status
Simulation time 34940300699 ps
CPU time 69.96 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:28:41 PM PDT 24
Peak memory 248892 kb
Host smart-5824ceaf-b273-498a-9681-1fb97ca34d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375080141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3375080141
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2821919942
Short name T743
Test name
Test status
Simulation time 8773509195 ps
CPU time 28.03 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:28:02 PM PDT 24
Peak memory 217380 kb
Host smart-644e0053-c82a-478d-a7ef-9a570e3e84a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821919942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2821919942
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3439123130
Short name T670
Test name
Test status
Simulation time 2645430452 ps
CPU time 15.23 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 232868 kb
Host smart-fb51d737-311d-40eb-bfc3-39e7ef98a03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439123130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3439123130
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.721380465
Short name T737
Test name
Test status
Simulation time 121455906 ps
CPU time 2.21 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:24 PM PDT 24
Peak memory 220632 kb
Host smart-be142bb7-8202-47de-8c8a-c539ff14bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721380465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.721380465
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.220739946
Short name T7
Test name
Test status
Simulation time 219946270 ps
CPU time 4.79 seconds
Started May 21 12:26:22 PM PDT 24
Finished May 21 12:27:14 PM PDT 24
Peak memory 233400 kb
Host smart-39144457-147c-4edd-8d61-ba0def737875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220739946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.220739946
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2898981113
Short name T494
Test name
Test status
Simulation time 406482775 ps
CPU time 2.51 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:27:28 PM PDT 24
Peak memory 218352 kb
Host smart-838dae26-35de-4552-8324-60fdea5e5c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898981113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2898981113
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.734745486
Short name T668
Test name
Test status
Simulation time 707305152 ps
CPU time 5.21 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 218468 kb
Host smart-31c9e62d-2a4a-440b-8109-83455122c9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734745486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.734745486
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2914957251
Short name T551
Test name
Test status
Simulation time 1184443990 ps
CPU time 11.84 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:19 PM PDT 24
Peak memory 222728 kb
Host smart-db02e1aa-21f0-4f9a-9c1b-41a1c481209a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2914957251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2914957251
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3641563583
Short name T179
Test name
Test status
Simulation time 4917651254 ps
CPU time 46.19 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:48 PM PDT 24
Peak memory 255784 kb
Host smart-7bf25e87-fc09-43a5-aab0-d1fe2a8bffbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641563583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3641563583
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1809384473
Short name T738
Test name
Test status
Simulation time 16495187648 ps
CPU time 24.46 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:46 PM PDT 24
Peak memory 216076 kb
Host smart-59804397-5c40-498d-a00f-7541d6419668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809384473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1809384473
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3658245021
Short name T424
Test name
Test status
Simulation time 2418273884 ps
CPU time 6.22 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:12 PM PDT 24
Peak memory 216016 kb
Host smart-d68183dd-e26c-472e-b253-68eb2e60a268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658245021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3658245021
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1672632335
Short name T634
Test name
Test status
Simulation time 139761426 ps
CPU time 2.36 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 216424 kb
Host smart-4bef0ad0-82e3-49d3-99c8-d0594e5eaa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672632335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1672632335
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.68462074
Short name T536
Test name
Test status
Simulation time 180152829 ps
CPU time 0.86 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:15 PM PDT 24
Peak memory 205500 kb
Host smart-8db6f5a8-b67a-405e-84ba-f9aa5a2bb7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68462074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.68462074
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2538739622
Short name T920
Test name
Test status
Simulation time 448707105 ps
CPU time 7.56 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 234468 kb
Host smart-e649dd47-c779-4316-aa67-f092651f5b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538739622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2538739622
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4155991778
Short name T611
Test name
Test status
Simulation time 13305266 ps
CPU time 0.68 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 205144 kb
Host smart-9cbc9a23-c010-48b9-b80b-8245f860756e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155991778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4155991778
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2770993099
Short name T508
Test name
Test status
Simulation time 209415556 ps
CPU time 2.29 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 218336 kb
Host smart-b3ec9da0-d416-4b6a-bcc7-b6881af7881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770993099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2770993099
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1323295239
Short name T833
Test name
Test status
Simulation time 16823515 ps
CPU time 0.72 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:37 PM PDT 24
Peak memory 205620 kb
Host smart-9da6e2e1-b23e-4b76-87d5-1ce89ecd1e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323295239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1323295239
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.710364487
Short name T283
Test name
Test status
Simulation time 5078349065 ps
CPU time 58.94 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 255268 kb
Host smart-c610806f-083f-460c-aa85-34099564ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710364487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.710364487
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.578651158
Short name T152
Test name
Test status
Simulation time 207727254571 ps
CPU time 505.27 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:35:53 PM PDT 24
Peak memory 268296 kb
Host smart-b2dbcbaa-daf2-46e4-a22a-f48ff5f56092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578651158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.578651158
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3637780301
Short name T38
Test name
Test status
Simulation time 332825923 ps
CPU time 3.22 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 232396 kb
Host smart-83df3a70-89bb-42a2-bba8-f4c72c23f38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637780301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3637780301
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3733710145
Short name T696
Test name
Test status
Simulation time 1041411367 ps
CPU time 4.48 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:27:31 PM PDT 24
Peak memory 218300 kb
Host smart-ff586691-7cd9-48ef-a281-de09bfca3e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733710145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3733710145
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.140487045
Short name T928
Test name
Test status
Simulation time 1156598586 ps
CPU time 19.42 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 234052 kb
Host smart-217f1359-976f-4dd9-a968-306f68244a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140487045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.140487045
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2063914663
Short name T729
Test name
Test status
Simulation time 6794434849 ps
CPU time 18.82 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:54 PM PDT 24
Peak memory 227268 kb
Host smart-853901b7-e1ea-4ecf-80e5-42b71c6800e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063914663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2063914663
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.930207964
Short name T892
Test name
Test status
Simulation time 715321487 ps
CPU time 6.18 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:20 PM PDT 24
Peak memory 240592 kb
Host smart-69cbf724-6917-471a-9d3a-2124ac8a0f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930207964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.930207964
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2070099653
Short name T365
Test name
Test status
Simulation time 472788989 ps
CPU time 3.81 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:34 PM PDT 24
Peak memory 218484 kb
Host smart-9f4552fe-e02f-4625-ad99-550f1616f0a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2070099653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2070099653
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2307784660
Short name T889
Test name
Test status
Simulation time 58848154 ps
CPU time 0.97 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:28:03 PM PDT 24
Peak memory 206668 kb
Host smart-2dfca29a-8b55-43f1-8e7d-60fc03574fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307784660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2307784660
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4024514436
Short name T699
Test name
Test status
Simulation time 1295959680 ps
CPU time 16.55 seconds
Started May 21 12:26:42 PM PDT 24
Finished May 21 12:28:01 PM PDT 24
Peak memory 215952 kb
Host smart-56c5a288-9e8e-4e80-bbbf-7f5184a2dce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024514436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4024514436
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2186317652
Short name T803
Test name
Test status
Simulation time 777243494 ps
CPU time 1.31 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 207608 kb
Host smart-add0fd01-1319-489f-983e-6ada897cfe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186317652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2186317652
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3454961760
Short name T854
Test name
Test status
Simulation time 239044293 ps
CPU time 4.83 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:06 PM PDT 24
Peak memory 215920 kb
Host smart-15d90a7a-e177-44d1-9c2a-c62c99136f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454961760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3454961760
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2412185513
Short name T466
Test name
Test status
Simulation time 61275065 ps
CPU time 0.76 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:08 PM PDT 24
Peak memory 205528 kb
Host smart-f59b0fe8-db2e-4938-898e-88d27ea7399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412185513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2412185513
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.605814572
Short name T666
Test name
Test status
Simulation time 779559198 ps
CPU time 2.93 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:27:31 PM PDT 24
Peak memory 235260 kb
Host smart-bad6d8bf-f503-48e5-9b81-d6f0bb73d3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605814572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.605814572
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.279930706
Short name T596
Test name
Test status
Simulation time 32492547 ps
CPU time 0.68 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:36 PM PDT 24
Peak memory 205100 kb
Host smart-bc32e8d2-c5bd-4988-bd12-590b8d202f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279930706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.279930706
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.898865875
Short name T945
Test name
Test status
Simulation time 339690227 ps
CPU time 4.26 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:10 PM PDT 24
Peak memory 234060 kb
Host smart-fbf3f6cb-2d00-42ba-841a-0534c947ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898865875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.898865875
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.488240808
Short name T874
Test name
Test status
Simulation time 30984389 ps
CPU time 0.73 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 205612 kb
Host smart-5faea319-b0b3-41fc-9afd-6468a52b8ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488240808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.488240808
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.446782101
Short name T838
Test name
Test status
Simulation time 2521030466 ps
CPU time 49.9 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 248788 kb
Host smart-b02e78ed-d492-45de-82bc-40338c49c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446782101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.446782101
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3221706356
Short name T931
Test name
Test status
Simulation time 126025756822 ps
CPU time 178.92 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 248916 kb
Host smart-78ff2552-0405-47a4-94d0-3dee44f95a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221706356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3221706356
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1796039468
Short name T270
Test name
Test status
Simulation time 69334438263 ps
CPU time 264.85 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 248620 kb
Host smart-bc9df5ad-e351-436d-9838-33c2ed6519f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796039468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1796039468
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3909706824
Short name T718
Test name
Test status
Simulation time 2253462473 ps
CPU time 28.77 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:53 PM PDT 24
Peak memory 233104 kb
Host smart-02dd9bd1-90a7-41be-9393-4b52d3037cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909706824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3909706824
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1363404887
Short name T613
Test name
Test status
Simulation time 120106836 ps
CPU time 3.68 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:41 PM PDT 24
Peak memory 217392 kb
Host smart-7100d28a-3f3a-41af-9bc4-21c849ec9f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363404887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1363404887
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1790567185
Short name T304
Test name
Test status
Simulation time 7240893349 ps
CPU time 55.45 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 234648 kb
Host smart-7324345d-f78a-48c3-94ab-1e1ef9dd3238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790567185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1790567185
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3005498951
Short name T576
Test name
Test status
Simulation time 3094515409 ps
CPU time 9.41 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 218364 kb
Host smart-3a7605d0-c401-4a43-b0b7-2e9e21bcc9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005498951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3005498951
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.67588818
Short name T383
Test name
Test status
Simulation time 300203583 ps
CPU time 3.58 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:40 PM PDT 24
Peak memory 222508 kb
Host smart-4a1e189a-bc1f-4e4c-85a4-4173c8248647
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67588818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direc
t.67588818
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.304010246
Short name T49
Test name
Test status
Simulation time 3520403739 ps
CPU time 46.64 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 248888 kb
Host smart-bad53cc5-f3c5-4eaa-a3cf-d3db2fc5db7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304010246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.304010246
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3252790149
Short name T318
Test name
Test status
Simulation time 8164535106 ps
CPU time 41.32 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:28:03 PM PDT 24
Peak memory 216172 kb
Host smart-21865aad-6e94-47fb-8bca-94fb10d6700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252790149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3252790149
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2216300931
Short name T336
Test name
Test status
Simulation time 14380162931 ps
CPU time 18.35 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:24 PM PDT 24
Peak memory 215920 kb
Host smart-a8917ba4-6313-437a-b95f-b3649817e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216300931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2216300931
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4112645937
Short name T4
Test name
Test status
Simulation time 1466486106 ps
CPU time 1.57 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 215968 kb
Host smart-0f3989a6-b2d1-4e7c-8629-1b671d93182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112645937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4112645937
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.117591337
Short name T331
Test name
Test status
Simulation time 156497313 ps
CPU time 0.98 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:35 PM PDT 24
Peak memory 205648 kb
Host smart-12fb956d-a0a6-4933-b933-d14a2864f219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117591337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.117591337
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2973808815
Short name T965
Test name
Test status
Simulation time 301615765 ps
CPU time 2.3 seconds
Started May 21 12:26:43 PM PDT 24
Finished May 21 12:27:43 PM PDT 24
Peak memory 218688 kb
Host smart-e3469166-6228-469d-958b-b4955814b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973808815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2973808815
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2771793452
Short name T66
Test name
Test status
Simulation time 12147942 ps
CPU time 0.75 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:25 PM PDT 24
Peak memory 205140 kb
Host smart-7ca0bca3-828c-453b-ace4-2c59319b74b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771793452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2771793452
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.783798336
Short name T213
Test name
Test status
Simulation time 422045420 ps
CPU time 5.54 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:27:36 PM PDT 24
Peak memory 218148 kb
Host smart-6791b308-51e1-49e4-be9b-8ff652bcf584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783798336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.783798336
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4237139296
Short name T375
Test name
Test status
Simulation time 14034810 ps
CPU time 0.71 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:27:29 PM PDT 24
Peak memory 205256 kb
Host smart-7f36755c-971b-4227-9e60-38b757c85f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237139296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4237139296
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1997127231
Short name T150
Test name
Test status
Simulation time 44898559847 ps
CPU time 420.93 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:34:23 PM PDT 24
Peak memory 254840 kb
Host smart-a49fc548-3676-46ca-825e-4910875aef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997127231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1997127231
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2973196897
Short name T807
Test name
Test status
Simulation time 14889859602 ps
CPU time 60.65 seconds
Started May 21 12:27:00 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 248948 kb
Host smart-c59fbe7e-7240-4de9-b5b0-fd4f77af2918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973196897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2973196897
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4201432206
Short name T732
Test name
Test status
Simulation time 738611209 ps
CPU time 8.72 seconds
Started May 21 12:26:36 PM PDT 24
Finished May 21 12:27:43 PM PDT 24
Peak memory 232348 kb
Host smart-db45f522-29a8-4d31-a2d7-bbfe0024e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201432206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4201432206
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3474372609
Short name T305
Test name
Test status
Simulation time 805320236 ps
CPU time 11.37 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:27:42 PM PDT 24
Peak memory 240600 kb
Host smart-de39a7f4-7830-4d11-a527-482fc0ef7189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474372609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3474372609
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3880268130
Short name T235
Test name
Test status
Simulation time 2509472646 ps
CPU time 9.93 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 226828 kb
Host smart-b4078875-0c4d-4d90-ac75-cc2df2a42f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880268130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3880268130
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2485317569
Short name T379
Test name
Test status
Simulation time 177386874498 ps
CPU time 29.26 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:28:17 PM PDT 24
Peak memory 232988 kb
Host smart-ed91e9a2-3355-4bed-a643-47a7fd067e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485317569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2485317569
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4246409727
Short name T814
Test name
Test status
Simulation time 525257800 ps
CPU time 4.79 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 218984 kb
Host smart-4b7147be-685f-412f-aa10-28b723605f81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4246409727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4246409727
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2455376767
Short name T948
Test name
Test status
Simulation time 30673661346 ps
CPU time 270.56 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 269400 kb
Host smart-f4af635d-1c1c-4336-9ddf-d00aa8f1884a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455376767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2455376767
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2273938703
Short name T61
Test name
Test status
Simulation time 207500194 ps
CPU time 3.26 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 218688 kb
Host smart-e6bc8bce-86e0-49d4-8d6d-e71a92cf9b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273938703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2273938703
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3265088283
Short name T401
Test name
Test status
Simulation time 501933155 ps
CPU time 1.42 seconds
Started May 21 12:26:48 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 207608 kb
Host smart-53116f56-d0ee-4bf4-94d6-430efb276ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265088283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3265088283
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2028963604
Short name T20
Test name
Test status
Simulation time 535951539 ps
CPU time 0.96 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:25 PM PDT 24
Peak memory 206692 kb
Host smart-2a927623-fb0f-46d9-b9e9-848f3c5bbe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028963604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2028963604
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.111443873
Short name T620
Test name
Test status
Simulation time 246065187 ps
CPU time 0.89 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 205520 kb
Host smart-9c2aab77-7346-43b1-ba87-69533f900864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111443873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.111443873
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3285527783
Short name T181
Test name
Test status
Simulation time 550954612 ps
CPU time 9.73 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:37 PM PDT 24
Peak memory 240256 kb
Host smart-81effd37-13c6-45b0-b2a0-4c5f16d28872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285527783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3285527783
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2231667971
Short name T832
Test name
Test status
Simulation time 3665942813 ps
CPU time 13.89 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:44 PM PDT 24
Peak memory 233944 kb
Host smart-d0bb405e-272f-4f48-8997-250f064806e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231667971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2231667971
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1288674387
Short name T346
Test name
Test status
Simulation time 20602708 ps
CPU time 0.79 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 206312 kb
Host smart-22894050-d13a-4c93-aa81-cc8989f992b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288674387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1288674387
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3710432812
Short name T555
Test name
Test status
Simulation time 24357789205 ps
CPU time 156.93 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 249904 kb
Host smart-dd0b1502-02cb-4f2d-9f03-c9e50ff2234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710432812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3710432812
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3222137341
Short name T526
Test name
Test status
Simulation time 83157054064 ps
CPU time 159.82 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:30:09 PM PDT 24
Peak memory 253040 kb
Host smart-9a7e54f4-5e6f-4c01-b120-ca81803a8210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222137341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3222137341
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3060414688
Short name T914
Test name
Test status
Simulation time 1102054856 ps
CPU time 5.5 seconds
Started May 21 12:26:22 PM PDT 24
Finished May 21 12:27:15 PM PDT 24
Peak memory 224200 kb
Host smart-0778d6f8-cb77-4271-8484-ff0d09069543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060414688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3060414688
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1548218572
Short name T530
Test name
Test status
Simulation time 213323645 ps
CPU time 3.43 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:27:35 PM PDT 24
Peak memory 233752 kb
Host smart-2ccd2735-b8cc-4555-a1e9-7d6f01c2a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548218572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1548218572
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1448110916
Short name T291
Test name
Test status
Simulation time 9349241120 ps
CPU time 13.75 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:23 PM PDT 24
Peak memory 237780 kb
Host smart-46431d91-2841-41b5-b242-e4c30de66692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448110916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1448110916
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2718378710
Short name T586
Test name
Test status
Simulation time 16665846837 ps
CPU time 14.86 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 236320 kb
Host smart-5291c182-747b-4f54-8a16-3f1b2d9bf0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718378710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2718378710
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1326012372
Short name T784
Test name
Test status
Simulation time 3140318822 ps
CPU time 6.72 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 217588 kb
Host smart-f8c23147-e3a3-459d-aa5d-f6391320084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326012372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1326012372
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4027344223
Short name T681
Test name
Test status
Simulation time 1029683060 ps
CPU time 6.72 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:44 PM PDT 24
Peak memory 217500 kb
Host smart-c102cc1a-9928-4938-a22c-a358296fa7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027344223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4027344223
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.447974619
Short name T776
Test name
Test status
Simulation time 14010259 ps
CPU time 0.69 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:37 PM PDT 24
Peak memory 205424 kb
Host smart-36e2195e-1ff4-4bcc-bd4c-011090083c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447974619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.447974619
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1248158296
Short name T851
Test name
Test status
Simulation time 22104118 ps
CPU time 0.66 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:27:49 PM PDT 24
Peak memory 205440 kb
Host smart-1467f8e3-1519-4d72-8109-2e80e0a9968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248158296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1248158296
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2898911074
Short name T648
Test name
Test status
Simulation time 360374976 ps
CPU time 0.97 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 205520 kb
Host smart-40b52159-2d45-41d6-996f-c91b2ccd456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898911074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2898911074
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3249328147
Short name T30
Test name
Test status
Simulation time 14405875998 ps
CPU time 26.24 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 240032 kb
Host smart-0bd9ae06-42f2-4422-9534-6f1c606c6aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249328147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3249328147
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4174098808
Short name T750
Test name
Test status
Simulation time 15237330 ps
CPU time 0.72 seconds
Started May 21 12:26:40 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 205412 kb
Host smart-5654cdd9-8ef6-4316-a3ae-2aeb564de5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174098808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4174098808
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4077501554
Short name T406
Test name
Test status
Simulation time 436234699 ps
CPU time 2.12 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 215768 kb
Host smart-a700206f-cab2-4ccd-8247-8f1504622e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077501554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4077501554
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1434677759
Short name T173
Test name
Test status
Simulation time 50426039 ps
CPU time 0.73 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 206272 kb
Host smart-15ab07bb-75e9-40d2-89a6-e46c7fe40d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434677759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1434677759
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4205948259
Short name T243
Test name
Test status
Simulation time 78869301826 ps
CPU time 219.89 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 251880 kb
Host smart-ddc14f94-d54a-4d43-b485-7e31de47df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205948259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4205948259
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.895135572
Short name T52
Test name
Test status
Simulation time 189732324604 ps
CPU time 140.51 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:29:55 PM PDT 24
Peak memory 240272 kb
Host smart-567835d3-0509-4aa5-8946-0244f54c0170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895135572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.895135572
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3656083251
Short name T296
Test name
Test status
Simulation time 2219678183 ps
CPU time 20.54 seconds
Started May 21 12:26:44 PM PDT 24
Finished May 21 12:28:02 PM PDT 24
Peak memory 232524 kb
Host smart-7ddb8b2d-dc27-4274-9550-0f60a4fd8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656083251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3656083251
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2213373804
Short name T172
Test name
Test status
Simulation time 952061179 ps
CPU time 3.58 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:27:52 PM PDT 24
Peak memory 233836 kb
Host smart-ad0fee6e-9f49-4e86-8625-c54466dc60ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213373804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2213373804
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.841211722
Short name T1
Test name
Test status
Simulation time 630880052 ps
CPU time 5.59 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 220204 kb
Host smart-4dc92bb0-42ad-40b5-9f73-f32350b6af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841211722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.841211722
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3790302875
Short name T627
Test name
Test status
Simulation time 1712463344 ps
CPU time 7.28 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 221232 kb
Host smart-86aa5d09-6ea3-416a-b657-0b7bdd1232a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790302875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3790302875
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.118238744
Short name T483
Test name
Test status
Simulation time 169508633 ps
CPU time 2.89 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:39 PM PDT 24
Peak memory 234156 kb
Host smart-281d6f67-dd3d-42e7-a940-a6bd9fc7c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118238744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.118238744
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.329478777
Short name T748
Test name
Test status
Simulation time 1235730068 ps
CPU time 5.29 seconds
Started May 21 12:26:48 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 222560 kb
Host smart-c42154a5-a2eb-45f4-bdaf-ae439f6048b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=329478777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.329478777
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.613765539
Short name T246
Test name
Test status
Simulation time 95434540838 ps
CPU time 385.4 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 263376 kb
Host smart-d230a647-b1f2-4626-8152-00b4f1d524bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613765539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.613765539
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1280661330
Short name T740
Test name
Test status
Simulation time 13014225162 ps
CPU time 34.1 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:28:30 PM PDT 24
Peak memory 215984 kb
Host smart-d48af6c3-f595-4bae-b709-131d87c7ebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280661330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1280661330
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3549569067
Short name T387
Test name
Test status
Simulation time 1591739091 ps
CPU time 4.67 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:39 PM PDT 24
Peak memory 216324 kb
Host smart-c7cbfcb4-06bd-4611-9dca-7dd3296a02f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549569067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3549569067
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1057798787
Short name T842
Test name
Test status
Simulation time 1187486384 ps
CPU time 3.19 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:27:36 PM PDT 24
Peak memory 216020 kb
Host smart-c33d0636-2639-4c26-92fe-0d1c93d86a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057798787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1057798787
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3800858367
Short name T442
Test name
Test status
Simulation time 151565943 ps
CPU time 0.9 seconds
Started May 21 12:26:48 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 205660 kb
Host smart-213d19bb-bde6-4688-92f3-0eed4ac88fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800858367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3800858367
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2792182062
Short name T488
Test name
Test status
Simulation time 21488149087 ps
CPU time 15.98 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 219252 kb
Host smart-2ca8cbfd-5bf9-4a20-a1bd-68243f61ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792182062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2792182062
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3389012444
Short name T703
Test name
Test status
Simulation time 14988316 ps
CPU time 0.73 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:35 PM PDT 24
Peak memory 205592 kb
Host smart-52a9c419-20bd-4405-9177-fcf99041ed77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389012444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3389012444
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3376358250
Short name T580
Test name
Test status
Simulation time 837640838 ps
CPU time 6.78 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 218332 kb
Host smart-e0b1bd9c-67db-4385-9408-dc125722cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376358250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3376358250
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.572768163
Short name T395
Test name
Test status
Simulation time 16801474 ps
CPU time 0.76 seconds
Started May 21 12:26:40 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 206220 kb
Host smart-79409921-c281-41bd-a871-941b01d37f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572768163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.572768163
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1329958690
Short name T201
Test name
Test status
Simulation time 8522446470 ps
CPU time 20.67 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 248844 kb
Host smart-0fb03597-7b7f-425c-95c7-d5402672624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329958690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1329958690
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2637270451
Short name T924
Test name
Test status
Simulation time 4408499673 ps
CPU time 44.56 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 249148 kb
Host smart-aff7bede-c8bd-4a37-b07b-572e33f956b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637270451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2637270451
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1177107592
Short name T861
Test name
Test status
Simulation time 185049550774 ps
CPU time 465.51 seconds
Started May 21 12:26:42 PM PDT 24
Finished May 21 12:35:25 PM PDT 24
Peak memory 255364 kb
Host smart-0ba94e34-7f55-4e8f-88cb-24983b6a6298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177107592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1177107592
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3524847139
Short name T610
Test name
Test status
Simulation time 116048789 ps
CPU time 2.75 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 224228 kb
Host smart-28dc2707-f357-48ea-b4d7-5bd4bd1817b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524847139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3524847139
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.822628026
Short name T937
Test name
Test status
Simulation time 136090261 ps
CPU time 4.7 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:07 PM PDT 24
Peak memory 233644 kb
Host smart-f73e1382-b706-44d1-8593-38fcaa924aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822628026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.822628026
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2406862516
Short name T922
Test name
Test status
Simulation time 3583410523 ps
CPU time 36.5 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 224716 kb
Host smart-96fc84f5-eb95-45e6-9437-c9860178519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406862516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2406862516
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3871040683
Short name T512
Test name
Test status
Simulation time 2215606077 ps
CPU time 7.24 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 218644 kb
Host smart-1fb82ece-050b-4e50-8ea3-259bea230d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871040683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3871040683
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3603393392
Short name T808
Test name
Test status
Simulation time 1841414909 ps
CPU time 5.98 seconds
Started May 21 12:26:48 PM PDT 24
Finished May 21 12:27:52 PM PDT 24
Peak memory 232772 kb
Host smart-0355d6fe-a453-4bd5-961d-e76b0471c714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603393392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3603393392
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2532812883
Short name T160
Test name
Test status
Simulation time 1846320672 ps
CPU time 3.73 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:25 PM PDT 24
Peak memory 219184 kb
Host smart-1858a5cf-2d08-44bb-824e-d6a0bf62007d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2532812883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2532812883
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.229962447
Short name T187
Test name
Test status
Simulation time 124303697496 ps
CPU time 187.05 seconds
Started May 21 12:26:53 PM PDT 24
Finished May 21 12:30:59 PM PDT 24
Peak memory 254448 kb
Host smart-3ea9e83f-50d0-42b5-a1fc-57887a05db10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229962447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.229962447
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.786228853
Short name T528
Test name
Test status
Simulation time 3200752782 ps
CPU time 19.85 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 216108 kb
Host smart-ab93130a-3fe8-4ee2-9132-731d622d43a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786228853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.786228853
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2749311800
Short name T870
Test name
Test status
Simulation time 1090491970 ps
CPU time 2.95 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:27:35 PM PDT 24
Peak memory 215944 kb
Host smart-17637e38-be55-4668-b1c7-50204820a1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749311800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2749311800
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1041015419
Short name T438
Test name
Test status
Simulation time 207104851 ps
CPU time 1.39 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 207772 kb
Host smart-64219d91-3e98-4ab9-a03f-98606d3e248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041015419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1041015419
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.699049000
Short name T812
Test name
Test status
Simulation time 151475426 ps
CPU time 0.78 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 205464 kb
Host smart-74e623a9-a38c-4f24-b349-4c45dde531f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699049000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.699049000
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1194206245
Short name T783
Test name
Test status
Simulation time 344701736 ps
CPU time 2.4 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 233680 kb
Host smart-8717190f-b8d2-4ec7-9228-a16a97c2e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194206245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1194206245
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.387333921
Short name T691
Test name
Test status
Simulation time 12958169 ps
CPU time 0.72 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 205240 kb
Host smart-10bf903f-fa0a-4518-8eb3-96a09825f703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387333921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.387333921
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3455381207
Short name T882
Test name
Test status
Simulation time 124533652 ps
CPU time 2.14 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 221400 kb
Host smart-55c4f492-cdb0-44ef-b312-d7759366ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455381207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3455381207
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1063223351
Short name T443
Test name
Test status
Simulation time 63215382 ps
CPU time 0.79 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:27:48 PM PDT 24
Peak memory 206340 kb
Host smart-0ff5237a-b788-418e-89b9-04bb3ce83ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063223351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1063223351
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2100571274
Short name T250
Test name
Test status
Simulation time 44486879219 ps
CPU time 315.19 seconds
Started May 21 12:26:53 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 254204 kb
Host smart-e064c5ea-a4fd-434c-801e-36a104e2ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100571274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2100571274
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3868365622
Short name T216
Test name
Test status
Simulation time 18174171053 ps
CPU time 160.08 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:30:15 PM PDT 24
Peak memory 251348 kb
Host smart-1981f0c6-008f-47dd-8965-f9993ddf5cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868365622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3868365622
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.200443960
Short name T151
Test name
Test status
Simulation time 4902335482 ps
CPU time 22.34 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:59 PM PDT 24
Peak memory 239284 kb
Host smart-0fcad32b-5fb5-496c-bcb6-53660499b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200443960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.200443960
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4015003567
Short name T355
Test name
Test status
Simulation time 354047450 ps
CPU time 3.25 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:27:34 PM PDT 24
Peak memory 232400 kb
Host smart-4337e59e-cf77-4d65-b49b-40bd97e0433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015003567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4015003567
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2692570632
Short name T795
Test name
Test status
Simulation time 336061909 ps
CPU time 3.39 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 233492 kb
Host smart-287f9a9b-4dad-4783-9a9a-e2ad4d1b70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692570632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2692570632
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4008160590
Short name T630
Test name
Test status
Simulation time 1919135636 ps
CPU time 14.27 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:57 PM PDT 24
Peak memory 236832 kb
Host smart-656905c2-d86a-43bb-a4f7-5d0e2a654757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008160590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4008160590
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.993711494
Short name T919
Test name
Test status
Simulation time 549885966 ps
CPU time 2.61 seconds
Started May 21 12:26:41 PM PDT 24
Finished May 21 12:27:41 PM PDT 24
Peak memory 218368 kb
Host smart-db013c7e-cfb2-4896-bbac-c275bce6f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993711494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.993711494
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1020842776
Short name T856
Test name
Test status
Simulation time 29114227538 ps
CPU time 20.67 seconds
Started May 21 12:26:46 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 234988 kb
Host smart-9ae59a30-b6e3-4435-8deb-d0bf436ef142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020842776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1020842776
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1664601839
Short name T491
Test name
Test status
Simulation time 87557731 ps
CPU time 4.11 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:39 PM PDT 24
Peak memory 222640 kb
Host smart-8d2120d2-303b-4cd6-b77c-7212be58b20f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1664601839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1664601839
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1859554074
Short name T867
Test name
Test status
Simulation time 53542654160 ps
CPU time 131.89 seconds
Started May 21 12:26:48 PM PDT 24
Finished May 21 12:29:58 PM PDT 24
Peak memory 252272 kb
Host smart-6d965027-7294-4db9-b2b6-9071ae527871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859554074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1859554074
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2742370979
Short name T314
Test name
Test status
Simulation time 5393692091 ps
CPU time 28.29 seconds
Started May 21 12:26:36 PM PDT 24
Finished May 21 12:28:01 PM PDT 24
Peak memory 216072 kb
Host smart-5ba239ce-feaa-482f-8bf1-3431326876a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742370979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2742370979
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4230622894
Short name T552
Test name
Test status
Simulation time 3298531877 ps
CPU time 8.88 seconds
Started May 21 12:26:42 PM PDT 24
Finished May 21 12:27:49 PM PDT 24
Peak memory 215964 kb
Host smart-6d6c1d82-c17e-4061-b1d0-d4e0c4e939e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230622894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4230622894
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.637389380
Short name T781
Test name
Test status
Simulation time 26813053 ps
CPU time 1.32 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 215996 kb
Host smart-05a55e42-846a-4d9a-9956-348eb7dd80ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637389380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.637389380
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4288744431
Short name T105
Test name
Test status
Simulation time 27699111 ps
CPU time 0.73 seconds
Started May 21 12:26:40 PM PDT 24
Finished May 21 12:27:39 PM PDT 24
Peak memory 205588 kb
Host smart-ab307ddb-61f5-4c23-adbf-fa4b3e1d6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288744431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4288744431
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.572418793
Short name T478
Test name
Test status
Simulation time 617494542 ps
CPU time 2.16 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:27:55 PM PDT 24
Peak memory 212380 kb
Host smart-59fd2d40-2ba2-4aca-9098-6720c17aa4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572418793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.572418793
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2715431236
Short name T575
Test name
Test status
Simulation time 14896265 ps
CPU time 0.72 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 205480 kb
Host smart-df68e93a-8d0c-4571-a712-944711a340c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715431236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2715431236
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3419845739
Short name T850
Test name
Test status
Simulation time 128776213 ps
CPU time 2.94 seconds
Started May 21 12:26:57 PM PDT 24
Finished May 21 12:27:57 PM PDT 24
Peak memory 234256 kb
Host smart-ba9e23eb-672d-4d70-a0d3-2c87257b872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419845739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3419845739
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1326904543
Short name T677
Test name
Test status
Simulation time 54197708 ps
CPU time 0.76 seconds
Started May 21 12:26:36 PM PDT 24
Finished May 21 12:27:34 PM PDT 24
Peak memory 206332 kb
Host smart-d7019375-8080-4e8d-a1fb-e234e4d4deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326904543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1326904543
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1553367856
Short name T31
Test name
Test status
Simulation time 32647156948 ps
CPU time 80.62 seconds
Started May 21 12:26:49 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 250480 kb
Host smart-54d893bc-bbef-46ac-9a87-f62f1e4a54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553367856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1553367856
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4066602267
Short name T299
Test name
Test status
Simulation time 24330362385 ps
CPU time 68.12 seconds
Started May 21 12:26:36 PM PDT 24
Finished May 21 12:28:41 PM PDT 24
Peak memory 237436 kb
Host smart-28facd93-60e2-4daa-902a-458d86451043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066602267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4066602267
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2219651115
Short name T317
Test name
Test status
Simulation time 43918759130 ps
CPU time 45.44 seconds
Started May 21 12:26:44 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 217060 kb
Host smart-3e0650b5-4c58-42d2-89f6-ffb28f6cf139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219651115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2219651115
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2618300223
Short name T325
Test name
Test status
Simulation time 375093624 ps
CPU time 4.12 seconds
Started May 21 12:26:53 PM PDT 24
Finished May 21 12:27:56 PM PDT 24
Peak memory 224244 kb
Host smart-b44491bd-84fd-44a1-b25c-d342d1eaab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618300223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2618300223
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4128792074
Short name T961
Test name
Test status
Simulation time 4846498895 ps
CPU time 10.19 seconds
Started May 21 12:26:38 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 219556 kb
Host smart-a746b82f-a246-4a35-bda3-3b4a4bedd23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128792074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4128792074
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3172671610
Short name T43
Test name
Test status
Simulation time 1892490672 ps
CPU time 10.01 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 239560 kb
Host smart-15d1111c-eddb-4d16-b07f-876c47edafa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172671610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3172671610
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1970124912
Short name T817
Test name
Test status
Simulation time 747757236 ps
CPU time 2.54 seconds
Started May 21 12:26:41 PM PDT 24
Finished May 21 12:27:42 PM PDT 24
Peak memory 217084 kb
Host smart-38a9354d-50f4-4c9b-bb84-c6f4b36e9e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970124912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1970124912
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2342663220
Short name T884
Test name
Test status
Simulation time 361484639 ps
CPU time 4.14 seconds
Started May 21 12:26:54 PM PDT 24
Finished May 21 12:27:56 PM PDT 24
Peak memory 235208 kb
Host smart-f234d543-f31b-4919-809f-1c53cbbec945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342663220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2342663220
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1314430145
Short name T158
Test name
Test status
Simulation time 385887984 ps
CPU time 6.83 seconds
Started May 21 12:26:54 PM PDT 24
Finished May 21 12:27:59 PM PDT 24
Peak memory 222468 kb
Host smart-873664fa-7656-4347-8580-78ca6736b64f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1314430145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1314430145
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1550416835
Short name T785
Test name
Test status
Simulation time 122278692 ps
CPU time 1.05 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:27:59 PM PDT 24
Peak memory 206808 kb
Host smart-8b5eccf5-5ebe-4e61-b781-2c212b800493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550416835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1550416835
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4124643675
Short name T315
Test name
Test status
Simulation time 5527212474 ps
CPU time 30.4 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 216120 kb
Host smart-54c18e90-c425-4d89-95d8-cbca9ce1e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124643675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4124643675
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.793603455
Short name T775
Test name
Test status
Simulation time 63988991194 ps
CPU time 15.81 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:28:11 PM PDT 24
Peak memory 216048 kb
Host smart-132c8a3e-6424-4d89-85c0-3135fd24379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793603455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.793603455
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2718213894
Short name T809
Test name
Test status
Simulation time 20183418 ps
CPU time 0.86 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:27:29 PM PDT 24
Peak memory 206296 kb
Host smart-40f2844b-66de-4877-835a-0f2a1e210cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718213894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2718213894
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2243389658
Short name T334
Test name
Test status
Simulation time 87081183 ps
CPU time 0.75 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 205536 kb
Host smart-4d789bf9-e907-4cdd-86c1-092830693c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243389658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2243389658
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2872930411
Short name T399
Test name
Test status
Simulation time 1250416572 ps
CPU time 2.06 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 207628 kb
Host smart-77e64665-8de2-40dc-8f51-d2b8226d7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872930411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2872930411
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2897634690
Short name T64
Test name
Test status
Simulation time 65328501 ps
CPU time 0.71 seconds
Started May 21 12:26:03 PM PDT 24
Finished May 21 12:26:25 PM PDT 24
Peak memory 205128 kb
Host smart-8c5d92ba-8c46-4adf-aa38-623f609edaae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897634690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
897634690
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3150610700
Short name T793
Test name
Test status
Simulation time 108953244 ps
CPU time 2.25 seconds
Started May 21 12:26:04 PM PDT 24
Finished May 21 12:26:28 PM PDT 24
Peak memory 221024 kb
Host smart-30b3c9a7-fa56-4e4f-91b4-a9b8bf31f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150610700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3150610700
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1124851965
Short name T176
Test name
Test status
Simulation time 21839361 ps
CPU time 0.75 seconds
Started May 21 12:25:54 PM PDT 24
Finished May 21 12:26:16 PM PDT 24
Peak memory 206236 kb
Host smart-7558791a-73de-4ade-b1e9-06600a40ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124851965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1124851965
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2457656203
Short name T183
Test name
Test status
Simulation time 161895931244 ps
CPU time 246.38 seconds
Started May 21 12:25:58 PM PDT 24
Finished May 21 12:30:24 PM PDT 24
Peak memory 256996 kb
Host smart-a8fe456a-2398-4f76-b539-f0d825d5c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457656203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2457656203
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3128677374
Short name T15
Test name
Test status
Simulation time 7108398101 ps
CPU time 21.12 seconds
Started May 21 12:26:06 PM PDT 24
Finished May 21 12:26:53 PM PDT 24
Peak memory 217136 kb
Host smart-314ec6e7-f11b-458d-8894-99267ba589e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128677374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3128677374
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4277993286
Short name T469
Test name
Test status
Simulation time 4377671409 ps
CPU time 100.19 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 265260 kb
Host smart-81e44a5f-1fcf-4bf3-be71-c033287ce3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277993286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4277993286
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4193588194
Short name T384
Test name
Test status
Simulation time 605583999 ps
CPU time 5.33 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:43 PM PDT 24
Peak memory 232408 kb
Host smart-68d654bb-67ff-47c3-881f-a77084c0dd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193588194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4193588194
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1257017297
Short name T751
Test name
Test status
Simulation time 1812554064 ps
CPU time 5.68 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:46 PM PDT 24
Peak memory 216448 kb
Host smart-9927472f-ddb5-4cdf-adf9-8e732de8590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257017297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1257017297
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4534184
Short name T734
Test name
Test status
Simulation time 7142328894 ps
CPU time 43.64 seconds
Started May 21 12:26:00 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 235744 kb
Host smart-39dcff95-7df9-476f-8d3a-00851bc5295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4534184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4534184
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.418504785
Short name T545
Test name
Test status
Simulation time 333147538 ps
CPU time 2.9 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:52 PM PDT 24
Peak memory 233392 kb
Host smart-cf51972b-fdae-4ce7-89e9-50a116dbd1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418504785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
418504785
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.613741476
Short name T190
Test name
Test status
Simulation time 5597560775 ps
CPU time 16.75 seconds
Started May 21 12:26:05 PM PDT 24
Finished May 21 12:26:47 PM PDT 24
Peak memory 219564 kb
Host smart-fb4b36c1-aaa2-4f52-a3f9-aa7f3881c427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613741476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.613741476
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.102462978
Short name T964
Test name
Test status
Simulation time 1459756011 ps
CPU time 12.19 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:59 PM PDT 24
Peak memory 218372 kb
Host smart-3ae0f88c-c488-45cc-9b2a-e328e35064e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=102462978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.102462978
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4287277247
Short name T78
Test name
Test status
Simulation time 301253562 ps
CPU time 1.13 seconds
Started May 21 12:26:01 PM PDT 24
Finished May 21 12:26:23 PM PDT 24
Peak memory 234488 kb
Host smart-092cb3ac-7720-42cd-856f-5cabbe534960
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287277247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4287277247
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2401548294
Short name T497
Test name
Test status
Simulation time 44914913 ps
CPU time 1.16 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:26:59 PM PDT 24
Peak memory 206712 kb
Host smart-402df9e8-cbbf-45d0-bdb1-17a7f880dadb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401548294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2401548294
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2817961582
Short name T79
Test name
Test status
Simulation time 1101739180 ps
CPU time 3.26 seconds
Started May 21 12:26:03 PM PDT 24
Finished May 21 12:26:29 PM PDT 24
Peak memory 218372 kb
Host smart-c57465f1-d986-4b2b-a346-71be8db0a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817961582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2817961582
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3894269201
Short name T927
Test name
Test status
Simulation time 1046477077 ps
CPU time 5.97 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:56 PM PDT 24
Peak memory 215956 kb
Host smart-e4b27b5c-4472-425d-a568-838754ba536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894269201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3894269201
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3870175254
Short name T686
Test name
Test status
Simulation time 100251906 ps
CPU time 1.03 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:49 PM PDT 24
Peak memory 207120 kb
Host smart-f6b1fc3e-9c4e-4405-9e8f-0d75b0ea7424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870175254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3870175254
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3608040914
Short name T330
Test name
Test status
Simulation time 10054279 ps
CPU time 0.71 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:26:43 PM PDT 24
Peak memory 205708 kb
Host smart-c406622d-0573-41a9-8f55-ca2743581120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608040914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3608040914
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.415074385
Short name T374
Test name
Test status
Simulation time 395556049 ps
CPU time 2.81 seconds
Started May 21 12:26:05 PM PDT 24
Finished May 21 12:26:32 PM PDT 24
Peak memory 232300 kb
Host smart-a25a03ef-b044-45b5-b3b6-dccb1c17d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415074385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.415074385
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1100135584
Short name T501
Test name
Test status
Simulation time 35861728 ps
CPU time 0.69 seconds
Started May 21 12:26:43 PM PDT 24
Finished May 21 12:27:41 PM PDT 24
Peak memory 204600 kb
Host smart-328e8971-6b2e-4519-b638-2034dc6b1880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100135584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1100135584
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.290537356
Short name T669
Test name
Test status
Simulation time 150862962 ps
CPU time 2.83 seconds
Started May 21 12:26:41 PM PDT 24
Finished May 21 12:27:42 PM PDT 24
Peak memory 233808 kb
Host smart-d4a4374b-e118-45d1-9cdd-c17a478eed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290537356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.290537356
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1340918936
Short name T689
Test name
Test status
Simulation time 22384818 ps
CPU time 0.73 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:38 PM PDT 24
Peak memory 205964 kb
Host smart-ebfa147a-2875-49f5-8960-a7745bdbd9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340918936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1340918936
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.562866925
Short name T479
Test name
Test status
Simulation time 13251535 ps
CPU time 0.75 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:27:48 PM PDT 24
Peak memory 215668 kb
Host smart-5c8302e3-c17d-42ef-a960-8870fee574c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562866925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.562866925
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3394160803
Short name T836
Test name
Test status
Simulation time 44521498625 ps
CPU time 399.1 seconds
Started May 21 12:27:00 PM PDT 24
Finished May 21 12:34:39 PM PDT 24
Peak memory 248916 kb
Host smart-a410b044-d687-47e5-8515-88ce3b4b1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394160803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3394160803
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.119402182
Short name T547
Test name
Test status
Simulation time 6805535453 ps
CPU time 16.71 seconds
Started May 21 12:26:49 PM PDT 24
Finished May 21 12:28:03 PM PDT 24
Peak memory 217100 kb
Host smart-abec4568-803a-4c8c-874c-600175bcb95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119402182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.119402182
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.11672645
Short name T338
Test name
Test status
Simulation time 627024707 ps
CPU time 9.17 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:27:57 PM PDT 24
Peak memory 240596 kb
Host smart-af324c91-e98c-4556-bb01-c74198fa91ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11672645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.11672645
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.756997178
Short name T366
Test name
Test status
Simulation time 399931285 ps
CPU time 3.97 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:27:52 PM PDT 24
Peak memory 218280 kb
Host smart-7c503985-b236-48c4-b827-900403ea1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756997178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.756997178
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3684923287
Short name T598
Test name
Test status
Simulation time 513643592 ps
CPU time 13.09 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 233128 kb
Host smart-28418e91-9c97-457b-ab93-d4b0d1c10ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684923287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3684923287
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4133079086
Short name T747
Test name
Test status
Simulation time 9382558919 ps
CPU time 11.18 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:54 PM PDT 24
Peak memory 233324 kb
Host smart-8d7dc441-6763-4eb8-ae61-9f5c8bb0ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133079086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4133079086
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2836194989
Short name T858
Test name
Test status
Simulation time 1787727810 ps
CPU time 6.82 seconds
Started May 21 12:26:48 PM PDT 24
Finished May 21 12:27:53 PM PDT 24
Peak memory 221420 kb
Host smart-b0e1049e-ab3b-4ca1-98f1-0a82856d99d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836194989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2836194989
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1207664081
Short name T604
Test name
Test status
Simulation time 66724449474 ps
CPU time 184.82 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:30:50 PM PDT 24
Peak memory 256176 kb
Host smart-9387fe75-33bd-47f2-9f35-6dcb7679f7fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207664081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1207664081
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.778901299
Short name T177
Test name
Test status
Simulation time 5632097129 ps
CPU time 12.1 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 216088 kb
Host smart-21f468ba-27dd-4009-ba8f-71b9a02d31ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778901299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.778901299
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1183837371
Short name T778
Test name
Test status
Simulation time 3983464087 ps
CPU time 3.8 seconds
Started May 21 12:26:52 PM PDT 24
Finished May 21 12:27:53 PM PDT 24
Peak memory 216004 kb
Host smart-27a9a7a6-eafa-4de3-8438-26f6d738db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183837371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1183837371
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1079533307
Short name T787
Test name
Test status
Simulation time 378958682 ps
CPU time 1.76 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 216040 kb
Host smart-cb131995-53ba-4c1c-bcef-5c41451740fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079533307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1079533307
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.498832111
Short name T943
Test name
Test status
Simulation time 267105758 ps
CPU time 0.87 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:27:59 PM PDT 24
Peak memory 205544 kb
Host smart-809d8937-0392-48ef-93fb-cd00c20d69c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498832111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.498832111
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3640679295
Short name T195
Test name
Test status
Simulation time 2067831773 ps
CPU time 2.55 seconds
Started May 21 12:26:54 PM PDT 24
Finished May 21 12:27:55 PM PDT 24
Peak memory 217312 kb
Host smart-82bd8fa4-f181-4870-b6c5-8e66cb589390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640679295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3640679295
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4199238211
Short name T63
Test name
Test status
Simulation time 57948187 ps
CPU time 0.69 seconds
Started May 21 12:26:46 PM PDT 24
Finished May 21 12:27:44 PM PDT 24
Peak memory 205172 kb
Host smart-fefb49ba-9f8e-4f59-9fe8-8f1036a06977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199238211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4199238211
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1613659326
Short name T675
Test name
Test status
Simulation time 1826421470 ps
CPU time 3.19 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:34 PM PDT 24
Peak memory 233732 kb
Host smart-5df011cc-11a2-4aec-840f-b8c85a7474da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613659326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1613659326
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.527367402
Short name T84
Test name
Test status
Simulation time 48174335 ps
CPU time 0.79 seconds
Started May 21 12:26:45 PM PDT 24
Finished May 21 12:27:44 PM PDT 24
Peak memory 205960 kb
Host smart-95cf6b7a-8638-416b-abff-f4ca37ba20c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527367402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.527367402
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2938004806
Short name T25
Test name
Test status
Simulation time 344408120 ps
CPU time 6.05 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 232356 kb
Host smart-0fbe9552-e1d0-40a6-b392-b1c5bccc9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938004806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2938004806
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3193996037
Short name T758
Test name
Test status
Simulation time 1776943574 ps
CPU time 33.63 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 224272 kb
Host smart-1ef38b41-e3cb-40f5-8152-3d81dbc39b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193996037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3193996037
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3832548638
Short name T81
Test name
Test status
Simulation time 10709965149 ps
CPU time 99.93 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:29:36 PM PDT 24
Peak memory 257080 kb
Host smart-b754b0b0-ddd0-43a6-a02c-40b80ae0c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832548638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3832548638
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3213253014
Short name T541
Test name
Test status
Simulation time 904616904 ps
CPU time 11.37 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:27:56 PM PDT 24
Peak memory 233108 kb
Host smart-a8bbeccd-a1ab-4491-90b7-b3e761492234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213253014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3213253014
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2371654835
Short name T437
Test name
Test status
Simulation time 32988769 ps
CPU time 2.33 seconds
Started May 21 12:26:50 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 221292 kb
Host smart-7314c11b-b007-41fa-bd0b-f069ee7bd25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371654835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2371654835
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3497047640
Short name T946
Test name
Test status
Simulation time 27410496789 ps
CPU time 65.38 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:29:03 PM PDT 24
Peak memory 224200 kb
Host smart-172c3ad8-075f-485f-a988-9e6ce148921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497047640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3497047640
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2630039089
Short name T821
Test name
Test status
Simulation time 14936119167 ps
CPU time 11.49 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 228176 kb
Host smart-64eed54f-8f0c-4069-b4bb-38f55a6c4811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630039089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2630039089
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1475340633
Short name T430
Test name
Test status
Simulation time 6319170318 ps
CPU time 11.67 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 237560 kb
Host smart-16ac4630-5ae0-42c7-9aa4-b413956150e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475340633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1475340633
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1196785110
Short name T888
Test name
Test status
Simulation time 1250011257 ps
CPU time 17.35 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 220232 kb
Host smart-51103d26-9c24-4f8b-b8f8-c26a5b29fbd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1196785110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1196785110
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.618954038
Short name T878
Test name
Test status
Simulation time 38864574717 ps
CPU time 267.09 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:32:22 PM PDT 24
Peak memory 265356 kb
Host smart-ee0920aa-3138-4853-acba-8f6889d28ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618954038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.618954038
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2324843499
Short name T144
Test name
Test status
Simulation time 16975507773 ps
CPU time 21.35 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 216036 kb
Host smart-2af96219-ea0b-4586-8ce9-f5609363bb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324843499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2324843499
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2359827537
Short name T657
Test name
Test status
Simulation time 34707444979 ps
CPU time 7.45 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:27:56 PM PDT 24
Peak memory 215548 kb
Host smart-c7abce44-d4f9-4d2f-8a97-5acfbf1371c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359827537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2359827537
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.220367913
Short name T863
Test name
Test status
Simulation time 134417027 ps
CPU time 0.66 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 205428 kb
Host smart-d3f2b5b8-a87a-47a6-8c0e-ae60a6db2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220367913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.220367913
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2909361164
Short name T644
Test name
Test status
Simulation time 299673410 ps
CPU time 0.88 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:27:58 PM PDT 24
Peak memory 205816 kb
Host smart-147a1850-a71d-48b4-b2e5-16955f01c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909361164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2909361164
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4155024581
Short name T519
Test name
Test status
Simulation time 3117593012 ps
CPU time 5.11 seconds
Started May 21 12:26:40 PM PDT 24
Finished May 21 12:27:43 PM PDT 24
Peak memory 232472 kb
Host smart-a5dc74e2-54d6-4765-9677-2521a2f19991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155024581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4155024581
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3179735
Short name T462
Test name
Test status
Simulation time 36452023 ps
CPU time 0.68 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:06 PM PDT 24
Peak memory 204548 kb
Host smart-4da910e2-37c9-439d-a29e-ebaa09628013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.3179735
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3952254601
Short name T418
Test name
Test status
Simulation time 161678202 ps
CPU time 3.2 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 219400 kb
Host smart-92383f68-b221-46f6-9de0-5e3e660a5c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952254601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3952254601
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3225343118
Short name T926
Test name
Test status
Simulation time 17832506 ps
CPU time 0.74 seconds
Started May 21 12:26:49 PM PDT 24
Finished May 21 12:27:47 PM PDT 24
Peak memory 205236 kb
Host smart-0d2a3f58-00db-466f-aa70-4f780df358d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225343118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3225343118
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1114001755
Short name T930
Test name
Test status
Simulation time 51098797138 ps
CPU time 45.89 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:52 PM PDT 24
Peak memory 219116 kb
Host smart-31fa8f56-a006-43c4-9ec3-c3c792629c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114001755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1114001755
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1794705132
Short name T788
Test name
Test status
Simulation time 4011519448 ps
CPU time 27.6 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:28:16 PM PDT 24
Peak memory 236040 kb
Host smart-492c160c-2dff-490f-a31f-57a8148a5d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794705132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1794705132
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2774334890
Short name T894
Test name
Test status
Simulation time 364811379 ps
CPU time 3.1 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:12 PM PDT 24
Peak memory 218084 kb
Host smart-6153aceb-5429-4313-8b36-a11f9adbace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774334890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2774334890
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.466068492
Short name T933
Test name
Test status
Simulation time 58555617 ps
CPU time 1.95 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 215828 kb
Host smart-7ab316f1-345b-422c-b7fe-e29df3aa9eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466068492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.466068492
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2554556885
Short name T260
Test name
Test status
Simulation time 707011907 ps
CPU time 6.36 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 235840 kb
Host smart-78d13924-a39f-461e-9469-90469cbaf61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554556885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2554556885
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1134513514
Short name T55
Test name
Test status
Simulation time 4891649510 ps
CPU time 7.07 seconds
Started May 21 12:27:00 PM PDT 24
Finished May 21 12:28:06 PM PDT 24
Peak memory 218336 kb
Host smart-74a9e67f-0e1b-49e0-8854-fa7e32ee69d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134513514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1134513514
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3419005579
Short name T143
Test name
Test status
Simulation time 712536507 ps
CPU time 5.73 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 219984 kb
Host smart-d556a0d6-005e-45d8-8e42-e8cf286b949f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3419005579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3419005579
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3720726041
Short name T168
Test name
Test status
Simulation time 6110731075 ps
CPU time 72.56 seconds
Started May 21 12:26:54 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 254752 kb
Host smart-0be27d7b-70c7-455c-bf02-0e5804ecafc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720726041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3720726041
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4163177363
Short name T408
Test name
Test status
Simulation time 6568343138 ps
CPU time 8.91 seconds
Started May 21 12:26:37 PM PDT 24
Finished May 21 12:27:44 PM PDT 24
Peak memory 216152 kb
Host smart-a14d24bb-c8dc-4aad-a984-e3d24691705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163177363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4163177363
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1966526154
Short name T594
Test name
Test status
Simulation time 501412347 ps
CPU time 3.35 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 215972 kb
Host smart-4544b1a1-8467-4b22-a10b-a8f7774a11a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966526154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1966526154
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3304166668
Short name T866
Test name
Test status
Simulation time 13551918 ps
CPU time 0.8 seconds
Started May 21 12:26:46 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 206172 kb
Host smart-45215c6e-f85e-4d99-aef8-aa144354cea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304166668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3304166668
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1016641111
Short name T587
Test name
Test status
Simulation time 25280721 ps
CPU time 0.79 seconds
Started May 21 12:26:52 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 205528 kb
Host smart-12f0ea5e-0092-47b9-92e9-47f8cc98a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016641111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1016641111
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.719521850
Short name T417
Test name
Test status
Simulation time 94551940 ps
CPU time 2.17 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 215780 kb
Host smart-0d0acbc0-7128-4b1a-91de-2589dfcb7061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719521850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.719521850
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3778821248
Short name T473
Test name
Test status
Simulation time 24033917 ps
CPU time 0.68 seconds
Started May 21 12:26:56 PM PDT 24
Finished May 21 12:27:54 PM PDT 24
Peak memory 204508 kb
Host smart-a64a870e-540d-41aa-bcf7-76d1985e314c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778821248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3778821248
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1766027704
Short name T897
Test name
Test status
Simulation time 582685720 ps
CPU time 2.8 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 218452 kb
Host smart-0715688c-229c-4db1-b5ef-4b05d71b8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766027704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1766027704
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4241540666
Short name T362
Test name
Test status
Simulation time 54758806 ps
CPU time 0.74 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 205708 kb
Host smart-95a2ace6-02f7-4f48-b57d-ccaed7ee6dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241540666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4241540666
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3603679010
Short name T544
Test name
Test status
Simulation time 16625034740 ps
CPU time 109.86 seconds
Started May 21 12:26:54 PM PDT 24
Finished May 21 12:29:42 PM PDT 24
Peak memory 255744 kb
Host smart-bf517930-1787-41a9-9882-c46277450515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603679010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3603679010
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3505823814
Short name T147
Test name
Test status
Simulation time 4900337847 ps
CPU time 58.62 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:29:00 PM PDT 24
Peak memory 233252 kb
Host smart-0a0ba551-cba3-41a0-9835-2edceb3b2ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505823814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3505823814
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3051625590
Short name T601
Test name
Test status
Simulation time 3608079181 ps
CPU time 18.76 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 219192 kb
Host smart-c026cbc5-852c-4011-baf9-676addbe7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051625590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3051625590
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2792760105
Short name T444
Test name
Test status
Simulation time 706074746 ps
CPU time 5.15 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 235776 kb
Host smart-9baf6ccf-92f5-4ef1-ab2c-301102300f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792760105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2792760105
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3495170492
Short name T242
Test name
Test status
Simulation time 13208886077 ps
CPU time 12.69 seconds
Started May 21 12:26:55 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 248596 kb
Host smart-539d0875-c729-4663-a9fa-052a96dfb500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495170492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3495170492
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3521956055
Short name T227
Test name
Test status
Simulation time 94678694 ps
CPU time 2.57 seconds
Started May 21 12:26:57 PM PDT 24
Finished May 21 12:27:57 PM PDT 24
Peak memory 232548 kb
Host smart-f462d9e5-56ff-40de-ab6c-bd263e99cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521956055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3521956055
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.757660806
Short name T454
Test name
Test status
Simulation time 1136899230 ps
CPU time 3.64 seconds
Started May 21 12:26:53 PM PDT 24
Finished May 21 12:27:55 PM PDT 24
Peak memory 219852 kb
Host smart-a7a8a32d-27d9-4bce-9b1c-db0ce9ebae4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=757660806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.757660806
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3882154973
Short name T261
Test name
Test status
Simulation time 14641609832 ps
CPU time 229.7 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:31:50 PM PDT 24
Peak memory 265312 kb
Host smart-cf210c7b-82d8-4d38-b9e9-0fc08eb51089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882154973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3882154973
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.225521367
Short name T655
Test name
Test status
Simulation time 18227768380 ps
CPU time 22.1 seconds
Started May 21 12:26:57 PM PDT 24
Finished May 21 12:28:17 PM PDT 24
Peak memory 216048 kb
Host smart-0c48457b-133a-4d4b-8aa0-c5bb91b4bc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225521367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.225521367
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1899477124
Short name T523
Test name
Test status
Simulation time 149321347 ps
CPU time 1.21 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:28:03 PM PDT 24
Peak memory 207620 kb
Host smart-9b80b555-8f9d-4410-bd41-530806671583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899477124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1899477124
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.665384622
Short name T883
Test name
Test status
Simulation time 246218900 ps
CPU time 2.41 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:06 PM PDT 24
Peak memory 215916 kb
Host smart-1d62a02a-3456-4c3a-b773-050ff7514398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665384622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.665384622
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3229839498
Short name T423
Test name
Test status
Simulation time 435997594 ps
CPU time 0.96 seconds
Started May 21 12:26:51 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 206532 kb
Host smart-20fdc87f-aec8-4de9-ac36-7e996f4908cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229839498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3229839498
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3537021428
Short name T184
Test name
Test status
Simulation time 1795677033 ps
CPU time 3.71 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:07 PM PDT 24
Peak memory 217048 kb
Host smart-5885ca56-d64d-4639-ae21-5e8b0460973c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537021428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3537021428
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3263103689
Short name T65
Test name
Test status
Simulation time 43501556 ps
CPU time 0.71 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:27:57 PM PDT 24
Peak memory 205080 kb
Host smart-5a8696a4-cd7b-426e-882a-63fc83a9b16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263103689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3263103689
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2419950165
Short name T57
Test name
Test status
Simulation time 1988699539 ps
CPU time 19.34 seconds
Started May 21 12:27:00 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 234852 kb
Host smart-9bcf4233-fea2-4bc4-b786-05e395661b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419950165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2419950165
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2618443865
Short name T432
Test name
Test status
Simulation time 149542985 ps
CPU time 0.8 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 205288 kb
Host smart-03f04abd-abe9-4421-8b75-a782bd08e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618443865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2618443865
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3132768121
Short name T435
Test name
Test status
Simulation time 23448444342 ps
CPU time 96.99 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:29:22 PM PDT 24
Peak memory 248884 kb
Host smart-3e5aafd3-e774-41c9-9b2c-41ed2f425d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132768121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3132768121
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1401448886
Short name T293
Test name
Test status
Simulation time 24554800905 ps
CPU time 139.27 seconds
Started May 21 12:26:57 PM PDT 24
Finished May 21 12:30:14 PM PDT 24
Peak memory 248948 kb
Host smart-84d0b1aa-cdc1-4460-b2a0-f9f1733e6ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401448886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1401448886
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2565658315
Short name T24
Test name
Test status
Simulation time 5925455235 ps
CPU time 28.5 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:34 PM PDT 24
Peak memory 249312 kb
Host smart-730a744a-e674-42eb-ab59-149057fd4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565658315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2565658315
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1322985265
Short name T895
Test name
Test status
Simulation time 213949208 ps
CPU time 5.11 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:11 PM PDT 24
Peak memory 232400 kb
Host smart-928f00c0-8f28-41e7-989d-57dc53a1c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322985265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1322985265
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.839584318
Short name T225
Test name
Test status
Simulation time 654513136 ps
CPU time 7.86 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:16 PM PDT 24
Peak memory 217664 kb
Host smart-81cd5e02-16cb-4693-a3e7-3dd9ac8a70ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839584318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.839584318
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2123538569
Short name T573
Test name
Test status
Simulation time 2965934661 ps
CPU time 44.89 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:48 PM PDT 24
Peak memory 232412 kb
Host smart-e78ba6d3-d156-40e2-b0e8-c830ae31b565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123538569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2123538569
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2816313146
Short name T730
Test name
Test status
Simulation time 17369929643 ps
CPU time 23.37 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 233456 kb
Host smart-2784dbb7-c66b-4fde-b912-de103c918d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816313146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2816313146
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1396594697
Short name T300
Test name
Test status
Simulation time 1041303830 ps
CPU time 4.99 seconds
Started May 21 12:26:47 PM PDT 24
Finished May 21 12:27:50 PM PDT 24
Peak memory 216592 kb
Host smart-3bdbd780-18c1-4cfd-a2dc-8ef578132ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396594697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1396594697
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4257097444
Short name T409
Test name
Test status
Simulation time 957070843 ps
CPU time 4.57 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 222788 kb
Host smart-7cca104b-10fe-4597-8992-27e79192e90e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257097444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4257097444
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3579386400
Short name T589
Test name
Test status
Simulation time 13329351568 ps
CPU time 18.69 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 216036 kb
Host smart-23a5df2b-d10b-4c10-a82b-51fdccafd85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579386400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3579386400
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3594326701
Short name T777
Test name
Test status
Simulation time 2749862023 ps
CPU time 5.33 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 216008 kb
Host smart-166afe39-c0d5-4d10-9c68-6ca7ad317511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594326701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3594326701
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1273143447
Short name T27
Test name
Test status
Simulation time 40278260 ps
CPU time 0.8 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 206304 kb
Host smart-845aa990-fc1f-456f-8900-3ae58e5a3601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273143447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1273143447
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3508754564
Short name T18
Test name
Test status
Simulation time 156459473 ps
CPU time 0.77 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 205656 kb
Host smart-0998999c-b72f-415f-809f-8cc8bcef0944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508754564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3508754564
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1101420797
Short name T285
Test name
Test status
Simulation time 949403592 ps
CPU time 6.87 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 218880 kb
Host smart-48803c24-0f13-4d1a-85df-0e01512fd13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101420797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1101420797
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1843464161
Short name T386
Test name
Test status
Simulation time 15315369 ps
CPU time 0.71 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:27:58 PM PDT 24
Peak memory 205540 kb
Host smart-00151e11-c048-41b5-9f66-f26a1ba6272a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843464161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1843464161
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.862418895
Short name T582
Test name
Test status
Simulation time 12339785316 ps
CPU time 26.95 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:30 PM PDT 24
Peak memory 224220 kb
Host smart-59b6f423-deab-445b-8294-a04eecfbd0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862418895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.862418895
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1614574380
Short name T934
Test name
Test status
Simulation time 40551121 ps
CPU time 0.73 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 206320 kb
Host smart-0612310a-eb89-4db5-9783-8e85edba37ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614574380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1614574380
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.997510000
Short name T635
Test name
Test status
Simulation time 39387884 ps
CPU time 0.76 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:01 PM PDT 24
Peak memory 215676 kb
Host smart-48f1be75-79b5-4630-8682-fd0734eed3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997510000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.997510000
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.960529676
Short name T419
Test name
Test status
Simulation time 16545723407 ps
CPU time 164.88 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 239240 kb
Host smart-0a7f7feb-7d8b-4026-a07f-33ce15d9b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960529676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.960529676
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1768371286
Short name T908
Test name
Test status
Simulation time 149184813 ps
CPU time 4.01 seconds
Started May 21 12:26:57 PM PDT 24
Finished May 21 12:27:59 PM PDT 24
Peak memory 233224 kb
Host smart-b88a1e2d-2099-4ec8-bc08-7043ab6cb1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768371286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1768371286
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3809793777
Short name T798
Test name
Test status
Simulation time 2448966219 ps
CPU time 23.6 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:24 PM PDT 24
Peak memory 234000 kb
Host smart-9e58c8e9-687b-4114-a042-f43f96e47e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809793777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3809793777
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2844249706
Short name T9
Test name
Test status
Simulation time 2998498410 ps
CPU time 12.71 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 233524 kb
Host smart-1cb2090c-b99b-4ed6-ae4c-f8b14b1d326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844249706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2844249706
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.131383235
Short name T831
Test name
Test status
Simulation time 453876619 ps
CPU time 5.7 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:12 PM PDT 24
Peak memory 233320 kb
Host smart-6dccd549-99f9-4b7a-8367-9d5fb85b6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131383235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.131383235
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2801410129
Short name T887
Test name
Test status
Simulation time 147557981 ps
CPU time 3.54 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:07 PM PDT 24
Peak memory 222468 kb
Host smart-1aa6f92c-f16a-435c-90ed-ccaa02fa16ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801410129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2801410129
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.43737597
Short name T917
Test name
Test status
Simulation time 306208190 ps
CPU time 1.2 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 206972 kb
Host smart-f5838e11-9c4a-44a7-b8ed-7eea23184e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43737597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress
_all.43737597
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3894154226
Short name T550
Test name
Test status
Simulation time 4247193175 ps
CPU time 12.46 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 216040 kb
Host smart-80962487-2043-484c-a49e-be68d3e16ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894154226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3894154226
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1498944807
Short name T728
Test name
Test status
Simulation time 844098290 ps
CPU time 3.8 seconds
Started May 21 12:26:58 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 216100 kb
Host smart-70f7fae3-84d4-4d1c-a6a7-7fb60072cdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498944807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1498944807
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3667586135
Short name T321
Test name
Test status
Simulation time 43620616 ps
CPU time 1.98 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 216008 kb
Host smart-884b61f4-76f0-4260-9719-90ea6d7d9281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667586135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3667586135
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2621018601
Short name T925
Test name
Test status
Simulation time 430163843 ps
CPU time 1.05 seconds
Started May 21 12:26:59 PM PDT 24
Finished May 21 12:27:58 PM PDT 24
Peak memory 205508 kb
Host smart-d562fcf2-e5f1-4b8b-9618-0f0c4aca93eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621018601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2621018601
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1769145121
Short name T188
Test name
Test status
Simulation time 8159828532 ps
CPU time 11.72 seconds
Started May 21 12:26:52 PM PDT 24
Finished May 21 12:28:02 PM PDT 24
Peak memory 248440 kb
Host smart-6e2513d3-2128-4df5-b378-757823b4b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769145121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1769145121
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.388083769
Short name T722
Test name
Test status
Simulation time 14753947 ps
CPU time 0.73 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:04 PM PDT 24
Peak memory 205120 kb
Host smart-f2c1d07b-52fe-4da8-84ef-8407f325f5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388083769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.388083769
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1271480096
Short name T628
Test name
Test status
Simulation time 286716516 ps
CPU time 2.17 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 218384 kb
Host smart-631c5362-8812-4fb5-8b44-acf8170ffb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271480096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1271480096
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.294043765
Short name T612
Test name
Test status
Simulation time 14356085 ps
CPU time 0.76 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 206740 kb
Host smart-774b586b-4cfb-49fc-a878-d8c74379394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294043765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.294043765
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3341171513
Short name T370
Test name
Test status
Simulation time 1088956690 ps
CPU time 25.42 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 251792 kb
Host smart-beaa72eb-f89f-41e8-9c92-03338f3983c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341171513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3341171513
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3958411402
Short name T693
Test name
Test status
Simulation time 4507760161 ps
CPU time 27.65 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 232168 kb
Host smart-9a5807bb-a042-4eb7-8803-323ccd78e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958411402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3958411402
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.993674140
Short name T286
Test name
Test status
Simulation time 85398670088 ps
CPU time 176.85 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:31:06 PM PDT 24
Peak memory 238156 kb
Host smart-0c940144-d8aa-494e-bc98-f5ab3c8a30a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993674140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.993674140
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2936640471
Short name T671
Test name
Test status
Simulation time 1057957741 ps
CPU time 5.66 seconds
Started May 21 12:27:02 PM PDT 24
Finished May 21 12:28:07 PM PDT 24
Peak memory 240584 kb
Host smart-bd5462c6-fc3d-4ac2-8d40-a1c5f799e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936640471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2936640471
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.246612889
Short name T958
Test name
Test status
Simulation time 1371288272 ps
CPU time 4.84 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 218304 kb
Host smart-5c34a6ef-8d84-40ad-9d47-9f52499b05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246612889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.246612889
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2334967067
Short name T513
Test name
Test status
Simulation time 5966515784 ps
CPU time 23.21 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:36 PM PDT 24
Peak memory 232496 kb
Host smart-326df4e2-897a-4584-b019-b9abf88ec27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334967067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2334967067
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3219804649
Short name T205
Test name
Test status
Simulation time 2633565425 ps
CPU time 3.07 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:06 PM PDT 24
Peak memory 218244 kb
Host smart-9284d565-7b43-445f-99e3-a4592f7c0c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219804649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3219804649
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2056556323
Short name T744
Test name
Test status
Simulation time 413280135 ps
CPU time 2.13 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 215740 kb
Host smart-df5059ec-22ad-43f7-ac8a-287e19c255d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056556323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2056556323
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.878231522
Short name T486
Test name
Test status
Simulation time 727454202 ps
CPU time 10.09 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 219652 kb
Host smart-d70f3c3b-2468-4e61-84c6-29d37b4c9c78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878231522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.878231522
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.214356683
Short name T493
Test name
Test status
Simulation time 12689182756 ps
CPU time 21.67 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:28:23 PM PDT 24
Peak memory 216128 kb
Host smart-442e77a7-a8d9-459c-9c4c-175162b1ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214356683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.214356683
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2063203181
Short name T957
Test name
Test status
Simulation time 3615251496 ps
CPU time 5.5 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 215996 kb
Host smart-d0df1e31-245a-40df-ac18-9e13b740d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063203181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2063203181
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1724414020
Short name T707
Test name
Test status
Simulation time 28814158 ps
CPU time 1.12 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 207716 kb
Host smart-c8a4c845-6dde-4c83-86f2-5b423ccafbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724414020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1724414020
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4161082913
Short name T145
Test name
Test status
Simulation time 341687202 ps
CPU time 0.92 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 205852 kb
Host smart-6713ccdc-e5b6-4f54-b701-9d8154a41dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161082913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4161082913
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3087499261
Short name T577
Test name
Test status
Simulation time 297902684 ps
CPU time 2.59 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 232548 kb
Host smart-12e125b8-d7c4-4b59-8ab2-00a91d97c0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087499261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3087499261
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.227081845
Short name T471
Test name
Test status
Simulation time 11811455 ps
CPU time 0.67 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:11 PM PDT 24
Peak memory 204572 kb
Host smart-47837baa-8ecd-4d48-b309-70cff8b2834f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227081845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.227081845
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.745039846
Short name T223
Test name
Test status
Simulation time 424795946 ps
CPU time 2.31 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:06 PM PDT 24
Peak memory 218264 kb
Host smart-2b9ef50e-6573-429e-9fa9-aeb91146f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745039846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.745039846
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1923420145
Short name T361
Test name
Test status
Simulation time 42796523 ps
CPU time 0.74 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 205232 kb
Host smart-6cf09d25-9332-4334-a331-16904dea0e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923420145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1923420145
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.847473782
Short name T255
Test name
Test status
Simulation time 66469185393 ps
CPU time 440.8 seconds
Started May 21 12:27:01 PM PDT 24
Finished May 21 12:35:21 PM PDT 24
Peak memory 257068 kb
Host smart-cc3f96a2-c465-48ce-ae06-4310031b98b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847473782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.847473782
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1391708386
Short name T515
Test name
Test status
Simulation time 16067460543 ps
CPU time 32.07 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:36 PM PDT 24
Peak memory 217196 kb
Host smart-04ed3684-d953-47e6-8b0d-e42571a416f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391708386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1391708386
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3545662520
Short name T51
Test name
Test status
Simulation time 37613056471 ps
CPU time 91.19 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:29:42 PM PDT 24
Peak memory 248916 kb
Host smart-764395f4-9b7c-4867-8c33-bc09f526def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545662520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3545662520
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1244101048
Short name T307
Test name
Test status
Simulation time 3331653066 ps
CPU time 18.11 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:22 PM PDT 24
Peak memory 240132 kb
Host smart-638db7ab-8e1a-4e67-b96e-8169e0ba02b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244101048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1244101048
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2603646875
Short name T714
Test name
Test status
Simulation time 2181346895 ps
CPU time 11.6 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 218240 kb
Host smart-c9d658a9-7494-4227-90c8-e6c13006ae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603646875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2603646875
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2144822724
Short name T226
Test name
Test status
Simulation time 577312188 ps
CPU time 9.52 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 217648 kb
Host smart-29edfa10-9317-4ed6-b607-c79b1e99ead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144822724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2144822724
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2971956933
Short name T436
Test name
Test status
Simulation time 5391782792 ps
CPU time 10.92 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 227600 kb
Host smart-96b12151-ab37-458e-b174-7e777759fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971956933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2971956933
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1934699773
Short name T458
Test name
Test status
Simulation time 1432207760 ps
CPU time 5.28 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 216588 kb
Host smart-14273057-31be-4735-bfd1-3920bedb31ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934699773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1934699773
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1906908866
Short name T520
Test name
Test status
Simulation time 336648408 ps
CPU time 5.55 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 221760 kb
Host smart-3749112c-7a16-49a5-9cae-764ff9cc2005
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1906908866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1906908866
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.555404357
Short name T692
Test name
Test status
Simulation time 23466306654 ps
CPU time 199.93 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:31:26 PM PDT 24
Peak memory 248972 kb
Host smart-1f847bd9-5cb0-4a59-878e-7de57cc0ef70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555404357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.555404357
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1238310929
Short name T911
Test name
Test status
Simulation time 5493099088 ps
CPU time 15.04 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:23 PM PDT 24
Peak memory 219568 kb
Host smart-d9f6f36a-47fc-4bb6-8202-35a5f14ce3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238310929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1238310929
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.200388713
Short name T687
Test name
Test status
Simulation time 942623521 ps
CPU time 5.13 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:12 PM PDT 24
Peak memory 215924 kb
Host smart-4834df35-c4a1-40e4-a557-31c2af07e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200388713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.200388713
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.597360154
Short name T463
Test name
Test status
Simulation time 37925748 ps
CPU time 0.71 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 205596 kb
Host smart-3569ed63-a80f-4d8f-897d-ef5b9a5d36b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597360154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.597360154
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1538321570
Short name T797
Test name
Test status
Simulation time 188695703 ps
CPU time 0.81 seconds
Started May 21 12:27:04 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 205556 kb
Host smart-5c7c93f0-f5f0-4de1-847a-5828358c53ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538321570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1538321570
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.343910820
Short name T556
Test name
Test status
Simulation time 529867665 ps
CPU time 2.44 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 218652 kb
Host smart-28a5986f-8b6e-478e-a9e7-5012fe870e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343910820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.343910820
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2240740066
Short name T640
Test name
Test status
Simulation time 27161340 ps
CPU time 0.72 seconds
Started May 21 12:27:00 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 204660 kb
Host smart-266007be-4ab3-46d5-8ef7-01151dc15a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240740066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2240740066
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1454093958
Short name T348
Test name
Test status
Simulation time 474663182 ps
CPU time 2.1 seconds
Started May 21 12:27:14 PM PDT 24
Finished May 21 12:28:16 PM PDT 24
Peak memory 215832 kb
Host smart-b71e6978-dbe7-43f3-848a-56fac5904f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454093958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1454093958
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3325391185
Short name T590
Test name
Test status
Simulation time 24788858 ps
CPU time 0.73 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 205288 kb
Host smart-4d286c0e-9539-44c3-93f6-43e804966699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325391185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3325391185
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2089913898
Short name T230
Test name
Test status
Simulation time 48657223401 ps
CPU time 351.41 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:34:00 PM PDT 24
Peak memory 248876 kb
Host smart-1aa2daa0-6eb0-4fa1-bc7c-da4b9bcf256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089913898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2089913898
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3903183442
Short name T204
Test name
Test status
Simulation time 25525968686 ps
CPU time 259.56 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:32:24 PM PDT 24
Peak memory 253032 kb
Host smart-36426b01-6339-43b3-b463-3eecea6af0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903183442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3903183442
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1034977547
Short name T690
Test name
Test status
Simulation time 2607140211 ps
CPU time 39.25 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 236308 kb
Host smart-1095adbb-051c-437a-bae5-e7e246101c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034977547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1034977547
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.256896628
Short name T597
Test name
Test status
Simulation time 133651581 ps
CPU time 3.88 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 232424 kb
Host smart-7180b773-7b05-4f5c-bf09-11321c23505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256896628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.256896628
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3044399607
Short name T212
Test name
Test status
Simulation time 176577379 ps
CPU time 4.03 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:17 PM PDT 24
Peak memory 218312 kb
Host smart-8cf80a3f-e05c-4b35-9055-ccea9701d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044399607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3044399607
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.782895265
Short name T80
Test name
Test status
Simulation time 21955462329 ps
CPU time 50.22 seconds
Started May 21 12:27:03 PM PDT 24
Finished May 21 12:28:52 PM PDT 24
Peak memory 235760 kb
Host smart-14b60f97-fd39-4700-8a94-9317bedfb939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782895265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.782895265
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1350496553
Short name T667
Test name
Test status
Simulation time 1444103592 ps
CPU time 7.02 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 235528 kb
Host smart-5dd53efd-6b00-41a4-9380-facd0a53599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350496553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1350496553
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4148451639
Short name T10
Test name
Test status
Simulation time 2469496611 ps
CPU time 7.12 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:11 PM PDT 24
Peak memory 233564 kb
Host smart-ec69ba68-1e2d-438f-8ce1-b13fac0c6f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148451639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4148451639
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1767914790
Short name T623
Test name
Test status
Simulation time 896085186 ps
CPU time 4.68 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 222156 kb
Host smart-2b9a5bc9-26f7-4fe2-a022-8d8ec4075419
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1767914790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1767914790
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3323367527
Short name T913
Test name
Test status
Simulation time 5022795044 ps
CPU time 5.56 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 224348 kb
Host smart-7791fb0d-c889-47b8-a8b3-e95346746ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323367527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3323367527
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.278025609
Short name T425
Test name
Test status
Simulation time 1742152632 ps
CPU time 13.49 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 215964 kb
Host smart-7cf25d28-c72b-4205-ba79-f226bb3e382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278025609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.278025609
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3825284139
Short name T100
Test name
Test status
Simulation time 27006364154 ps
CPU time 16.01 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 215936 kb
Host smart-d2f32811-66a2-4f6a-aa03-b37b96aec592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825284139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3825284139
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4039564640
Short name T482
Test name
Test status
Simulation time 192597278 ps
CPU time 6.91 seconds
Started May 21 12:27:14 PM PDT 24
Finished May 21 12:28:21 PM PDT 24
Peak memory 216016 kb
Host smart-20402267-721a-4c1e-bc50-3f44d671a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039564640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4039564640
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1978576711
Short name T104
Test name
Test status
Simulation time 131359784 ps
CPU time 0.98 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:08 PM PDT 24
Peak memory 205476 kb
Host smart-6f184a94-44d7-48d8-93d3-767ef3008338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978576711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1978576711
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.190350397
Short name T565
Test name
Test status
Simulation time 302833259 ps
CPU time 3.08 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:17 PM PDT 24
Peak memory 216228 kb
Host smart-fcad5a98-0fde-4b59-bd6a-cb3f0985372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190350397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.190350397
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3406740306
Short name T890
Test name
Test status
Simulation time 12126808 ps
CPU time 0.69 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 204572 kb
Host smart-a7c0912a-f37c-420d-a4d1-017be774f13f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406740306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3406740306
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1040132756
Short name T880
Test name
Test status
Simulation time 85836515 ps
CPU time 2.76 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:12 PM PDT 24
Peak memory 233028 kb
Host smart-031c02c3-d059-4d29-9e1d-95abe6b2f796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040132756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1040132756
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.685424348
Short name T328
Test name
Test status
Simulation time 38208186 ps
CPU time 0.76 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 206324 kb
Host smart-d47a7821-360a-4f69-a38a-1d2d656b5980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685424348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.685424348
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3829023445
Short name T292
Test name
Test status
Simulation time 52080114445 ps
CPU time 351.05 seconds
Started May 21 12:27:17 PM PDT 24
Finished May 21 12:34:08 PM PDT 24
Peak memory 252540 kb
Host smart-5323de12-aed6-4964-ac17-807751c05ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829023445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3829023445
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.381947215
Short name T251
Test name
Test status
Simulation time 301749574427 ps
CPU time 568.81 seconds
Started May 21 12:27:14 PM PDT 24
Finished May 21 12:37:44 PM PDT 24
Peak memory 257212 kb
Host smart-126147dd-1048-4540-99b5-de07208e5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381947215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.381947215
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3846056597
Short name T741
Test name
Test status
Simulation time 4183964569 ps
CPU time 76.15 seconds
Started May 21 12:27:15 PM PDT 24
Finished May 21 12:29:31 PM PDT 24
Peak memory 257236 kb
Host smart-ca42e30a-d791-4187-9aac-c88817d0add5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846056597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3846056597
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3129988167
Short name T156
Test name
Test status
Simulation time 838141181 ps
CPU time 14.12 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 232444 kb
Host smart-9b5edbec-c3ef-4bc1-8c1d-2ccebff3696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129988167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3129988167
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3428732154
Short name T461
Test name
Test status
Simulation time 299682934 ps
CPU time 5.58 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 218928 kb
Host smart-dc77f45e-04c3-4807-b57c-d22078278bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428732154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3428732154
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1841714699
Short name T652
Test name
Test status
Simulation time 10333651137 ps
CPU time 43.54 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 239176 kb
Host smart-bfc558e9-4c2c-4f9b-9b09-09b46a359a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841714699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1841714699
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1431654905
Short name T849
Test name
Test status
Simulation time 3161752247 ps
CPU time 7.61 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 224188 kb
Host smart-e3e1b455-d213-412b-ac57-8e0d21b4539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431654905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1431654905
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4288085641
Short name T537
Test name
Test status
Simulation time 9489585546 ps
CPU time 17.33 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:28 PM PDT 24
Peak memory 227924 kb
Host smart-ebe825dc-f80a-4143-85e2-23e99514fe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288085641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4288085641
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.688366105
Short name T584
Test name
Test status
Simulation time 77078070 ps
CPU time 3.62 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 222620 kb
Host smart-50f0bafa-b1fc-4016-9089-e0208f2508ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=688366105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.688366105
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.737141419
Short name T169
Test name
Test status
Simulation time 65724764 ps
CPU time 1.04 seconds
Started May 21 12:27:15 PM PDT 24
Finished May 21 12:28:16 PM PDT 24
Peak memory 206804 kb
Host smart-935baeab-2da0-4e87-af6e-23d70cd88296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737141419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.737141419
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3749674310
Short name T566
Test name
Test status
Simulation time 6362824007 ps
CPU time 31.21 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:41 PM PDT 24
Peak memory 216080 kb
Host smart-011fd9a7-e051-4692-9c76-88eec698939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749674310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3749674310
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2451488285
Short name T918
Test name
Test status
Simulation time 23671051 ps
CPU time 0.68 seconds
Started May 21 12:27:06 PM PDT 24
Finished May 21 12:28:06 PM PDT 24
Peak memory 205396 kb
Host smart-d0e72a07-8c01-4794-9abf-9e6f7f2c4102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451488285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2451488285
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.231346027
Short name T638
Test name
Test status
Simulation time 160175233 ps
CPU time 2.74 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 215988 kb
Host smart-db5a6c3c-947b-4e82-ac36-9808e4f776bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231346027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.231346027
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.736096754
Short name T799
Test name
Test status
Simulation time 177458114 ps
CPU time 0.82 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 205536 kb
Host smart-fe975e17-4118-4c00-ad66-f4ca5e30ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736096754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.736096754
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1828283649
Short name T215
Test name
Test status
Simulation time 6548857814 ps
CPU time 5.54 seconds
Started May 21 12:27:17 PM PDT 24
Finished May 21 12:28:23 PM PDT 24
Peak memory 228676 kb
Host smart-86df4dc4-d2a0-4d86-af62-d8368ef70116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828283649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1828283649
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.58754016
Short name T659
Test name
Test status
Simulation time 21636148 ps
CPU time 0.71 seconds
Started May 21 12:26:23 PM PDT 24
Finished May 21 12:27:14 PM PDT 24
Peak memory 205080 kb
Host smart-60c28c54-775b-416e-81e4-859b998ed832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58754016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.58754016
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.845257571
Short name T58
Test name
Test status
Simulation time 108272297 ps
CPU time 3.44 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:09 PM PDT 24
Peak memory 234120 kb
Host smart-bea33576-f567-4bf1-ab7c-ea3e3a720c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845257571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.845257571
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4112522184
Short name T85
Test name
Test status
Simulation time 63253618 ps
CPU time 0.77 seconds
Started May 21 12:26:15 PM PDT 24
Finished May 21 12:26:56 PM PDT 24
Peak memory 206624 kb
Host smart-ede95b1a-d130-4e23-af2a-054895f389e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112522184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4112522184
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2625437437
Short name T492
Test name
Test status
Simulation time 184178170 ps
CPU time 4.26 seconds
Started May 21 12:26:15 PM PDT 24
Finished May 21 12:26:59 PM PDT 24
Peak memory 240584 kb
Host smart-f3de701e-397a-4486-a09b-d3c95d4f4d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625437437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2625437437
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.13546592
Short name T532
Test name
Test status
Simulation time 4292310649 ps
CPU time 28.77 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:27:21 PM PDT 24
Peak memory 220380 kb
Host smart-07b0dcb9-e583-427a-b0ca-9cd416ea911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13546592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.13546592
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2469714764
Short name T440
Test name
Test status
Simulation time 20310229387 ps
CPU time 58.53 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:59 PM PDT 24
Peak memory 236924 kb
Host smart-c3f728f2-8095-49fe-8b79-be0c74bcabeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469714764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2469714764
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1992725708
Short name T481
Test name
Test status
Simulation time 290797906 ps
CPU time 2.5 seconds
Started May 21 12:26:22 PM PDT 24
Finished May 21 12:27:12 PM PDT 24
Peak memory 224148 kb
Host smart-e9f695d6-d72f-4613-a6f8-10a4f5b50493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992725708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1992725708
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.721839199
Short name T617
Test name
Test status
Simulation time 2334839528 ps
CPU time 24.15 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:27:12 PM PDT 24
Peak memory 224216 kb
Host smart-814d8950-71a7-4539-bba0-f0663014c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721839199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.721839199
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2575354292
Short name T711
Test name
Test status
Simulation time 20110168588 ps
CPU time 90.71 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 240436 kb
Host smart-935f880b-89b6-411d-b918-efdca42cf987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575354292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2575354292
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3404369106
Short name T680
Test name
Test status
Simulation time 13917392051 ps
CPU time 11.49 seconds
Started May 21 12:26:04 PM PDT 24
Finished May 21 12:26:38 PM PDT 24
Peak memory 233408 kb
Host smart-4267ff6e-f621-49dc-a19e-20a5588fe322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404369106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3404369106
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3342924095
Short name T822
Test name
Test status
Simulation time 5096685220 ps
CPU time 5.44 seconds
Started May 21 12:26:08 PM PDT 24
Finished May 21 12:26:39 PM PDT 24
Peak memory 218788 kb
Host smart-873dcec6-2c25-40a0-bb72-94c2c58e6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342924095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3342924095
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2196839171
Short name T654
Test name
Test status
Simulation time 401967436 ps
CPU time 5.55 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:44 PM PDT 24
Peak memory 222620 kb
Host smart-f5c82813-5e4b-4075-960f-717acbea81f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2196839171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2196839171
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1922623954
Short name T77
Test name
Test status
Simulation time 134635754 ps
CPU time 1.2 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:16 PM PDT 24
Peak memory 233912 kb
Host smart-61940856-1087-4279-8f22-ac6045c89075
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922623954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1922623954
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3956678818
Short name T433
Test name
Test status
Simulation time 2392703867 ps
CPU time 15.07 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:19 PM PDT 24
Peak memory 216140 kb
Host smart-47d4d0d3-a210-4375-90c4-0145e682a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956678818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3956678818
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2814613974
Short name T341
Test name
Test status
Simulation time 1273638565 ps
CPU time 5.9 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:08 PM PDT 24
Peak memory 216252 kb
Host smart-f5ec82a0-d16b-4a3b-a904-90f0ef2f5387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814613974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2814613974
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3606353933
Short name T819
Test name
Test status
Simulation time 255914085 ps
CPU time 1.89 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:49 PM PDT 24
Peak memory 215952 kb
Host smart-04dfe5d1-4126-4432-b645-7a2cefc4bd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606353933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3606353933
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2684910652
Short name T568
Test name
Test status
Simulation time 70903499 ps
CPU time 0.74 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:26:46 PM PDT 24
Peak memory 205444 kb
Host smart-2acbd9c0-c9aa-4ca4-83a7-51f966f74820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684910652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2684910652
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1938862489
Short name T609
Test name
Test status
Simulation time 1197739307 ps
CPU time 5.78 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:36 PM PDT 24
Peak memory 240800 kb
Host smart-d66c6ecf-d324-4102-a7da-8bc0e9d952e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938862489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1938862489
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.819714637
Short name T369
Test name
Test status
Simulation time 90909126 ps
CPU time 0.69 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 205516 kb
Host smart-7949e841-a136-4ee8-ade9-b846fc07a35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819714637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.819714637
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2384667523
Short name T427
Test name
Test status
Simulation time 7873759386 ps
CPU time 25.09 seconds
Started May 21 12:27:18 PM PDT 24
Finished May 21 12:28:43 PM PDT 24
Peak memory 219952 kb
Host smart-c460684e-4e72-414b-963b-d31a21306975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384667523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2384667523
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.343533235
Short name T546
Test name
Test status
Simulation time 70947358 ps
CPU time 0.75 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 205280 kb
Host smart-65bbdc29-d185-4705-b480-95da45ac3876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343533235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.343533235
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2937812088
Short name T509
Test name
Test status
Simulation time 44657918425 ps
CPU time 48.31 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 249692 kb
Host smart-2a5069f5-2c3d-478e-a803-259cf5119843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937812088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2937812088
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1992375612
Short name T149
Test name
Test status
Simulation time 41182517301 ps
CPU time 231.08 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:31:59 PM PDT 24
Peak memory 249676 kb
Host smart-1bc91e05-26a0-42d5-a2a4-7ecd0c5b69f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992375612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1992375612
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2648838034
Short name T228
Test name
Test status
Simulation time 49202158557 ps
CPU time 348.75 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 262092 kb
Host smart-0b6f7c7b-da87-4883-b5a9-bb81972365a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648838034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2648838034
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2489555598
Short name T622
Test name
Test status
Simulation time 2215828527 ps
CPU time 20.58 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:34 PM PDT 24
Peak memory 239328 kb
Host smart-f98255f0-c342-4697-be7f-bc26fd6a528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489555598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2489555598
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3876940363
Short name T771
Test name
Test status
Simulation time 1340868950 ps
CPU time 13.33 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:23 PM PDT 24
Peak memory 233444 kb
Host smart-8f84b25f-add7-4299-945d-9b2e6b527791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876940363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3876940363
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1820859844
Short name T5
Test name
Test status
Simulation time 3566425529 ps
CPU time 4.84 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:17 PM PDT 24
Peak memory 218228 kb
Host smart-059b4129-3cec-4272-9e5f-a08481c72e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820859844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1820859844
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4259906103
Short name T456
Test name
Test status
Simulation time 821441849 ps
CPU time 8.8 seconds
Started May 21 12:27:09 PM PDT 24
Finished May 21 12:28:18 PM PDT 24
Peak memory 230476 kb
Host smart-0c0d964c-8f45-4d53-8c8d-409e2f5ecaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259906103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4259906103
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.912009139
Short name T221
Test name
Test status
Simulation time 132176553 ps
CPU time 2.78 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 218528 kb
Host smart-778e3405-13e1-44d9-8228-5f1cb445f052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912009139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.912009139
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3482866457
Short name T41
Test name
Test status
Simulation time 4597361200 ps
CPU time 7.93 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:17 PM PDT 24
Peak memory 221796 kb
Host smart-44aec8b7-b513-4bcd-99d0-041d057df5c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482866457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3482866457
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3988669005
Short name T266
Test name
Test status
Simulation time 14711401375 ps
CPU time 249.87 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:32:27 PM PDT 24
Peak memory 281836 kb
Host smart-99d11fe7-753b-4bd4-83d2-31679675660d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988669005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3988669005
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1876627327
Short name T646
Test name
Test status
Simulation time 28158921965 ps
CPU time 40.55 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 216056 kb
Host smart-42774b28-311b-426e-8243-c325c7bc852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876627327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1876627327
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3506514338
Short name T637
Test name
Test status
Simulation time 930455386 ps
CPU time 4.04 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:18 PM PDT 24
Peak memory 215880 kb
Host smart-a4a9ea7a-e393-42f0-a533-61ace8173ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506514338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3506514338
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4157918930
Short name T624
Test name
Test status
Simulation time 1173868312 ps
CPU time 10.56 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:24 PM PDT 24
Peak memory 216000 kb
Host smart-44993f0a-0492-4c0d-9711-70a202803463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157918930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4157918930
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1508173708
Short name T672
Test name
Test status
Simulation time 15777888 ps
CPU time 0.68 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:09 PM PDT 24
Peak memory 205580 kb
Host smart-d587b671-f411-45cc-9bf3-1eb2d3c61619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508173708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1508173708
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3754273526
Short name T405
Test name
Test status
Simulation time 273679432 ps
CPU time 4.69 seconds
Started May 21 12:27:08 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 239680 kb
Host smart-af6d37e7-9b18-40b4-bf58-dba54364f5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754273526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3754273526
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4115205707
Short name T398
Test name
Test status
Simulation time 14666980 ps
CPU time 0.72 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 205136 kb
Host smart-d7b0d4a8-48fa-4493-bf54-9e462c2e66dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115205707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4115205707
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3855242001
Short name T662
Test name
Test status
Simulation time 190178356 ps
CPU time 2.98 seconds
Started May 21 12:27:22 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 218592 kb
Host smart-3b5dcd76-ddfe-4da3-9725-f23c406c6610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855242001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3855242001
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2182328803
Short name T457
Test name
Test status
Simulation time 15639950 ps
CPU time 0.74 seconds
Started May 21 12:27:05 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 205312 kb
Host smart-db53799f-9064-4e4f-ae9a-e1ea35b4160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182328803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2182328803
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2567560872
Short name T239
Test name
Test status
Simulation time 19640190418 ps
CPU time 142 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 234328 kb
Host smart-d1a56396-3dbe-445b-b72d-bb03b69ed1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567560872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2567560872
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2069485428
Short name T742
Test name
Test status
Simulation time 158479436752 ps
CPU time 285.81 seconds
Started May 21 12:27:23 PM PDT 24
Finished May 21 12:33:10 PM PDT 24
Peak memory 255348 kb
Host smart-7d0c913f-db2b-4afc-8792-6469dbf3e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069485428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2069485428
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1342377727
Short name T761
Test name
Test status
Simulation time 233421620 ps
CPU time 6.96 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 232152 kb
Host smart-3bda7374-43fb-4c12-a7fe-4510fd16ae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342377727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1342377727
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3667791230
Short name T203
Test name
Test status
Simulation time 335046553 ps
CPU time 4.81 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:30 PM PDT 24
Peak memory 219148 kb
Host smart-16a5fcb2-d96c-48e7-a757-3073e0b0b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667791230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3667791230
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1847025737
Short name T412
Test name
Test status
Simulation time 2468268642 ps
CPU time 10.39 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:24 PM PDT 24
Peak memory 235516 kb
Host smart-d45a79c4-5b34-49fb-8a1f-2480fa062838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847025737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1847025737
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1320289860
Short name T248
Test name
Test status
Simulation time 79458679 ps
CPU time 2.45 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:28 PM PDT 24
Peak memory 218344 kb
Host smart-07ef65fe-ccd3-4905-869e-1947d49e4db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320289860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1320289860
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2437532258
Short name T333
Test name
Test status
Simulation time 150209658 ps
CPU time 2.56 seconds
Started May 21 12:27:17 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 232384 kb
Host smart-ce7a4b40-c3b6-4c2b-8644-36615ebdb958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437532258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2437532258
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2978105282
Short name T159
Test name
Test status
Simulation time 299037760 ps
CPU time 3.71 seconds
Started May 21 12:27:19 PM PDT 24
Finished May 21 12:28:22 PM PDT 24
Peak memory 220168 kb
Host smart-938402ed-bc50-4330-9516-04e8ce3d8562
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2978105282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2978105282
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3353238718
Short name T295
Test name
Test status
Simulation time 71396180022 ps
CPU time 278.23 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:33:04 PM PDT 24
Peak memory 256876 kb
Host smart-ca6794de-e669-477e-8062-3f66e34458b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353238718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3353238718
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1324406920
Short name T694
Test name
Test status
Simulation time 3128771501 ps
CPU time 9 seconds
Started May 21 12:27:14 PM PDT 24
Finished May 21 12:28:24 PM PDT 24
Peak memory 216108 kb
Host smart-76ba8103-36ea-480c-800c-69684fc41df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324406920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1324406920
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3023929910
Short name T351
Test name
Test status
Simulation time 5261177342 ps
CPU time 7.24 seconds
Started May 21 12:27:07 PM PDT 24
Finished May 21 12:28:14 PM PDT 24
Peak memory 215992 kb
Host smart-c84d0d0e-371c-4c92-999b-3ae5aa7fbe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023929910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3023929910
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.922688701
Short name T562
Test name
Test status
Simulation time 147523146 ps
CPU time 2.54 seconds
Started May 21 12:27:12 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 215992 kb
Host smart-b9247880-032d-4b8d-ba1a-91d12191819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922688701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.922688701
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3217574394
Short name T824
Test name
Test status
Simulation time 20612536 ps
CPU time 0.7 seconds
Started May 21 12:27:17 PM PDT 24
Finished May 21 12:28:18 PM PDT 24
Peak memory 205528 kb
Host smart-0f80b1f2-0074-4cab-a21e-c33edaf1629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217574394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3217574394
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.488603746
Short name T939
Test name
Test status
Simulation time 9755234699 ps
CPU time 17.14 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:42 PM PDT 24
Peak memory 239492 kb
Host smart-fef38be8-6247-4737-aa01-d6e4a658df7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488603746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.488603746
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3415705122
Short name T521
Test name
Test status
Simulation time 15880132 ps
CPU time 0.73 seconds
Started May 21 12:27:23 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 205160 kb
Host smart-f7ecc1d5-4580-46d1-9122-42b876d73fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415705122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3415705122
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2083848986
Short name T3
Test name
Test status
Simulation time 776349388 ps
CPU time 5.46 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 234560 kb
Host smart-e488917e-ed4e-4954-bfff-30f5416a5dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083848986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2083848986
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3702602117
Short name T643
Test name
Test status
Simulation time 32963559 ps
CPU time 0.72 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 205044 kb
Host smart-87fc69f1-4d59-401a-9efa-5da84fe5bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702602117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3702602117
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2477801701
Short name T199
Test name
Test status
Simulation time 3683460293 ps
CPU time 36.26 seconds
Started May 21 12:27:22 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 232592 kb
Host smart-55adea64-c1ea-4252-86b2-198655d90bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477801701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2477801701
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1768265676
Short name T381
Test name
Test status
Simulation time 52705502172 ps
CPU time 116.13 seconds
Started May 21 12:27:20 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 248836 kb
Host smart-641ad300-46f4-441f-9a1b-9ae9d566c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768265676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1768265676
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2176176200
Short name T241
Test name
Test status
Simulation time 146371052430 ps
CPU time 634.77 seconds
Started May 21 12:27:18 PM PDT 24
Finished May 21 12:38:53 PM PDT 24
Peak memory 272440 kb
Host smart-04a6f0b4-71a2-4490-b6c8-21584a9322ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176176200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2176176200
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1016933973
Short name T827
Test name
Test status
Simulation time 134238058 ps
CPU time 3.18 seconds
Started May 21 12:27:22 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 224196 kb
Host smart-de206925-10ac-4702-89fe-195e8960fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016933973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1016933973
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.147512047
Short name T326
Test name
Test status
Simulation time 781347420 ps
CPU time 7.46 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:19 PM PDT 24
Peak memory 218432 kb
Host smart-f8fda268-601d-4198-b155-de9859833b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147512047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.147512047
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2702763639
Short name T769
Test name
Test status
Simulation time 1444124857 ps
CPU time 12.35 seconds
Started May 21 12:27:11 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 226552 kb
Host smart-dd293529-55fb-4e19-98b3-87f19cef73d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702763639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2702763639
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2636700137
Short name T891
Test name
Test status
Simulation time 42126883776 ps
CPU time 18.85 seconds
Started May 21 12:27:29 PM PDT 24
Finished May 21 12:28:48 PM PDT 24
Peak memory 233148 kb
Host smart-29df1295-502d-4e2b-9882-934d5c739f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636700137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2636700137
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3395449069
Short name T487
Test name
Test status
Simulation time 256065822 ps
CPU time 2.69 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:16 PM PDT 24
Peak memory 233100 kb
Host smart-f0bcd139-1963-4e92-a74f-1c0cd33924ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395449069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3395449069
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3481322449
Short name T855
Test name
Test status
Simulation time 4290941034 ps
CPU time 12.71 seconds
Started May 21 12:27:20 PM PDT 24
Finished May 21 12:28:33 PM PDT 24
Peak memory 222772 kb
Host smart-91f39e77-160d-46d8-9f3b-691026cd82ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3481322449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3481322449
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3169849945
Short name T265
Test name
Test status
Simulation time 84076233291 ps
CPU time 434.69 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:35:40 PM PDT 24
Peak memory 252340 kb
Host smart-f18fe53b-f572-49ae-a80e-03ddea4f9d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169849945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3169849945
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4287476461
Short name T664
Test name
Test status
Simulation time 14708624035 ps
CPU time 24 seconds
Started May 21 12:27:21 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 219724 kb
Host smart-dda28533-efa7-41d5-81f3-61dc509d6a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287476461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4287476461
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1444690868
Short name T674
Test name
Test status
Simulation time 4039301503 ps
CPU time 11.58 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 216020 kb
Host smart-bdf85135-c642-48b7-aa8c-61961eb68ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444690868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1444690868
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1065454938
Short name T327
Test name
Test status
Simulation time 21173147 ps
CPU time 0.86 seconds
Started May 21 12:27:14 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 207048 kb
Host smart-53cf8f78-15ba-4a59-9bce-0784cbf0ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065454938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1065454938
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3053685739
Short name T841
Test name
Test status
Simulation time 32821985 ps
CPU time 0.81 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:25 PM PDT 24
Peak memory 205552 kb
Host smart-8287f65f-85d6-45b3-864b-40766034268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053685739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3053685739
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4140941572
Short name T591
Test name
Test status
Simulation time 7514204548 ps
CPU time 25.87 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:51 PM PDT 24
Peak memory 237884 kb
Host smart-f5f89bb0-0502-4bd2-89da-3474e30b1dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140941572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4140941572
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2209519322
Short name T653
Test name
Test status
Simulation time 13995194 ps
CPU time 0.66 seconds
Started May 21 12:27:21 PM PDT 24
Finished May 21 12:28:22 PM PDT 24
Peak memory 205128 kb
Host smart-ba747a15-78e9-4369-b948-11bebdeeccbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209519322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2209519322
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.244159190
Short name T804
Test name
Test status
Simulation time 35902713 ps
CPU time 2.37 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 232408 kb
Host smart-f79d6f21-2f08-4fd5-ab5b-55a7b8fb26c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244159190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.244159190
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3580668302
Short name T446
Test name
Test status
Simulation time 34428578 ps
CPU time 0.75 seconds
Started May 21 12:27:10 PM PDT 24
Finished May 21 12:28:11 PM PDT 24
Peak memory 205224 kb
Host smart-b367813f-4260-4c2e-b510-b98cf7442009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580668302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3580668302
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2230037366
Short name T301
Test name
Test status
Simulation time 3152725703 ps
CPU time 9.07 seconds
Started May 21 12:27:21 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 224156 kb
Host smart-08c33216-9d77-4a7a-98c9-9eb582e9a96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230037366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2230037366
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2009442241
Short name T238
Test name
Test status
Simulation time 114462837364 ps
CPU time 315.55 seconds
Started May 21 12:27:21 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 264940 kb
Host smart-b9c57112-1682-4074-b72b-8c50a94d8c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009442241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2009442241
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1391272826
Short name T485
Test name
Test status
Simulation time 13952036977 ps
CPU time 37.91 seconds
Started May 21 12:27:22 PM PDT 24
Finished May 21 12:29:00 PM PDT 24
Peak memory 217016 kb
Host smart-04bbfe65-1c73-4787-aa2f-c61140b8a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391272826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1391272826
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3722553235
Short name T834
Test name
Test status
Simulation time 335815820 ps
CPU time 5.48 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:28:22 PM PDT 24
Peak memory 224132 kb
Host smart-b51ce02d-34ba-49a2-a29b-018fc034bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722553235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3722553235
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1146541509
Short name T902
Test name
Test status
Simulation time 1536141648 ps
CPU time 15.23 seconds
Started May 21 12:27:13 PM PDT 24
Finished May 21 12:28:29 PM PDT 24
Peak memory 232580 kb
Host smart-87b4bc50-b658-4ed5-a141-8ef962d64569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146541509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1146541509
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.97785863
Short name T605
Test name
Test status
Simulation time 89345097 ps
CPU time 2.07 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 221340 kb
Host smart-2bd4de8e-6632-4817-b49a-d9cc6a3c1580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97785863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.97785863
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2826519277
Short name T231
Test name
Test status
Simulation time 703051428 ps
CPU time 8.06 seconds
Started May 21 12:27:20 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 239616 kb
Host smart-53741d5b-54d8-4b8d-8951-016a456e8e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826519277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2826519277
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1529671631
Short name T448
Test name
Test status
Simulation time 1858770187 ps
CPU time 4.6 seconds
Started May 21 12:27:19 PM PDT 24
Finished May 21 12:28:23 PM PDT 24
Peak memory 218288 kb
Host smart-fbbdc1d4-d20e-460b-bfd7-900527e0f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529671631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1529671631
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1590544758
Short name T805
Test name
Test status
Simulation time 3191085348 ps
CPU time 8.83 seconds
Started May 21 12:27:22 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 219872 kb
Host smart-b4f6e5d7-dfec-483d-8826-b441e8992069
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1590544758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1590544758
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.461400873
Short name T48
Test name
Test status
Simulation time 32868549557 ps
CPU time 252.12 seconds
Started May 21 12:27:23 PM PDT 24
Finished May 21 12:32:35 PM PDT 24
Peak memory 268144 kb
Host smart-fd01c6b3-64f1-478e-bfd0-e3b77d6988b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461400873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.461400873
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1339414313
Short name T865
Test name
Test status
Simulation time 1360404895 ps
CPU time 20.72 seconds
Started May 21 12:27:24 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 215784 kb
Host smart-0a18b6bc-8300-4236-a2e8-8b922744e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339414313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1339414313
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2819474634
Short name T354
Test name
Test status
Simulation time 10423460137 ps
CPU time 9.99 seconds
Started May 21 12:27:20 PM PDT 24
Finished May 21 12:28:29 PM PDT 24
Peak memory 216020 kb
Host smart-7b85b9ab-9ebf-4a9e-b553-4745e39a89eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819474634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2819474634
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.209304682
Short name T725
Test name
Test status
Simulation time 31434219 ps
CPU time 0.69 seconds
Started May 21 12:27:22 PM PDT 24
Finished May 21 12:28:24 PM PDT 24
Peak memory 205284 kb
Host smart-03ec5971-57b6-4403-a440-84f00341fd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209304682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.209304682
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4165401237
Short name T940
Test name
Test status
Simulation time 47789428 ps
CPU time 0.82 seconds
Started May 21 12:27:14 PM PDT 24
Finished May 21 12:28:15 PM PDT 24
Peak memory 205536 kb
Host smart-8584fd37-7679-475a-bfec-91edaf47d3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165401237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4165401237
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.219997094
Short name T947
Test name
Test status
Simulation time 1146648533 ps
CPU time 7.28 seconds
Started May 21 12:27:18 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 216212 kb
Host smart-cf6ced5d-9c8a-43eb-9b59-32966603a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219997094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.219997094
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3322378552
Short name T83
Test name
Test status
Simulation time 14928313 ps
CPU time 0.7 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 205456 kb
Host smart-abad1a05-fac0-4752-84bb-14055fcfc118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322378552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3322378552
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2929996941
Short name T496
Test name
Test status
Simulation time 276466294 ps
CPU time 3.3 seconds
Started May 21 12:27:29 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 218508 kb
Host smart-d2eb0ba1-fb28-42c3-89ee-d098039c18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929996941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2929996941
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3809540905
Short name T789
Test name
Test status
Simulation time 34448567 ps
CPU time 0.76 seconds
Started May 21 12:27:20 PM PDT 24
Finished May 21 12:28:20 PM PDT 24
Peak memory 206260 kb
Host smart-c18c1fc0-0cb1-4289-acd3-1999e97ddf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809540905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3809540905
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3140339249
Short name T36
Test name
Test status
Simulation time 3332795175 ps
CPU time 78.36 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:29:44 PM PDT 24
Peak memory 265228 kb
Host smart-b81526e1-7f3d-4b2f-8874-c0dc29d81cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140339249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3140339249
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1581221384
Short name T688
Test name
Test status
Simulation time 13856695401 ps
CPU time 95.95 seconds
Started May 21 12:27:27 PM PDT 24
Finished May 21 12:30:02 PM PDT 24
Peak memory 249156 kb
Host smart-13ad7e97-c9ab-4ba0-a62b-7a3c6e8cc8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581221384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1581221384
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1243602444
Short name T770
Test name
Test status
Simulation time 99527353780 ps
CPU time 179.73 seconds
Started May 21 12:27:28 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 250228 kb
Host smart-b55dcf9e-9d91-4eb7-b175-5b0f2c55e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243602444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1243602444
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.150000936
Short name T324
Test name
Test status
Simulation time 103308409 ps
CPU time 3.01 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:30 PM PDT 24
Peak memory 224200 kb
Host smart-2cb18dee-39c3-419c-a0b2-6eeca0e05917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150000936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.150000936
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1524058256
Short name T345
Test name
Test status
Simulation time 5478694029 ps
CPU time 24.06 seconds
Started May 21 12:27:21 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 222916 kb
Host smart-fc0dd5e7-3c0a-49ef-813d-fd9284ee5875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524058256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1524058256
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2701213467
Short name T633
Test name
Test status
Simulation time 6252580724 ps
CPU time 63.49 seconds
Started May 21 12:27:16 PM PDT 24
Finished May 21 12:29:20 PM PDT 24
Peak memory 240664 kb
Host smart-3d8c9ea3-56ed-436b-bb92-1d31648de264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701213467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2701213467
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1761965044
Short name T772
Test name
Test status
Simulation time 4309731018 ps
CPU time 10.68 seconds
Started May 21 12:27:17 PM PDT 24
Finished May 21 12:28:28 PM PDT 24
Peak memory 239112 kb
Host smart-283ec142-100d-4d39-b304-4f967b9233f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761965044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1761965044
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1062179564
Short name T800
Test name
Test status
Simulation time 2233379458 ps
CPU time 3.46 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:29 PM PDT 24
Peak memory 219088 kb
Host smart-c10f9c9d-34a3-4f33-ba67-62556474143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062179564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1062179564
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3322576254
Short name T695
Test name
Test status
Simulation time 1793078132 ps
CPU time 5.84 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 218892 kb
Host smart-ba262672-9c20-41c9-b812-b05dc862e8c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3322576254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3322576254
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.331561349
Short name T268
Test name
Test status
Simulation time 9665007168 ps
CPU time 117.22 seconds
Started May 21 12:27:28 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 265348 kb
Host smart-98b0feef-4bf6-45f2-a99a-bfcbbcaa8de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331561349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.331561349
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1124290832
Short name T779
Test name
Test status
Simulation time 12483474131 ps
CPU time 17.68 seconds
Started May 21 12:27:19 PM PDT 24
Finished May 21 12:28:36 PM PDT 24
Peak memory 216116 kb
Host smart-63b5529c-d0d9-4bb0-983d-0087eaf50073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124290832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1124290832
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3503826865
Short name T860
Test name
Test status
Simulation time 2515321323 ps
CPU time 7.79 seconds
Started May 21 12:27:21 PM PDT 24
Finished May 21 12:28:28 PM PDT 24
Peak memory 216004 kb
Host smart-04ad0042-e400-4feb-a348-86bd7cad6234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503826865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3503826865
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1857308078
Short name T367
Test name
Test status
Simulation time 52500559 ps
CPU time 1.19 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 207724 kb
Host smart-ce9c2e12-234e-4150-8e12-523003e7a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857308078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1857308078
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.647720898
Short name T445
Test name
Test status
Simulation time 26145303 ps
CPU time 0.82 seconds
Started May 21 12:27:17 PM PDT 24
Finished May 21 12:28:18 PM PDT 24
Peak memory 205504 kb
Host smart-f4baeec0-4b15-4827-b24f-a78507d3abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647720898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.647720898
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2973092738
Short name T460
Test name
Test status
Simulation time 259032086 ps
CPU time 2.61 seconds
Started May 21 12:27:19 PM PDT 24
Finished May 21 12:28:21 PM PDT 24
Peak memory 216948 kb
Host smart-c22ac8b1-1458-4ffb-b53a-92b15f4b4037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973092738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2973092738
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3517941319
Short name T745
Test name
Test status
Simulation time 37212630 ps
CPU time 0.74 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 204572 kb
Host smart-0bdc38e6-15fc-40c4-a1c0-f6f0701d2e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517941319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3517941319
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2206905942
Short name T202
Test name
Test status
Simulation time 594159634 ps
CPU time 3.91 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:36 PM PDT 24
Peak memory 233840 kb
Host smart-9efbe75e-f64f-46c1-a58e-51a1aa233038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206905942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2206905942
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1169050124
Short name T563
Test name
Test status
Simulation time 13673257 ps
CPU time 0.73 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:26 PM PDT 24
Peak memory 205244 kb
Host smart-e18e9942-79a7-41f5-8de3-6c45444d673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169050124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1169050124
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3002517086
Short name T256
Test name
Test status
Simulation time 14820818171 ps
CPU time 118.31 seconds
Started May 21 12:27:40 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 251412 kb
Host smart-ec770214-b9fb-40f5-b33f-529009b5410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002517086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3002517086
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.409623739
Short name T746
Test name
Test status
Simulation time 20932193248 ps
CPU time 88.79 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:30:03 PM PDT 24
Peak memory 240696 kb
Host smart-7122e4f5-05be-4de0-b63e-818aa14c6654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409623739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.409623739
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3290814594
Short name T875
Test name
Test status
Simulation time 843047678 ps
CPU time 8.13 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:42 PM PDT 24
Peak memory 232760 kb
Host smart-a9265889-c706-4ba4-81be-2d276da0d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290814594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3290814594
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2231600892
Short name T194
Test name
Test status
Simulation time 276567210 ps
CPU time 4.94 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 224092 kb
Host smart-34dd6992-0b28-499c-adce-99098ca5f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231600892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2231600892
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.920480520
Short name T663
Test name
Test status
Simulation time 5147790586 ps
CPU time 24.53 seconds
Started May 21 12:27:30 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 218352 kb
Host smart-df6ce94a-59e5-4c22-9992-901d6c3d0998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920480520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.920480520
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.270822703
Short name T872
Test name
Test status
Simulation time 529802822 ps
CPU time 5.6 seconds
Started May 21 12:27:25 PM PDT 24
Finished May 21 12:28:33 PM PDT 24
Peak memory 218388 kb
Host smart-897201b0-a1fc-476b-b8dc-6d3b38a12c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270822703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.270822703
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4287012254
Short name T765
Test name
Test status
Simulation time 252225690 ps
CPU time 5.27 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 218516 kb
Host smart-e75213d2-71ed-459f-9cec-2003ccec28dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287012254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4287012254
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.622839356
Short name T816
Test name
Test status
Simulation time 6892036302 ps
CPU time 12.36 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 222736 kb
Host smart-bef1afd9-0e87-4a7d-b90d-a2431986b811
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=622839356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.622839356
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.729714490
Short name T319
Test name
Test status
Simulation time 7656327825 ps
CPU time 26.32 seconds
Started May 21 12:27:27 PM PDT 24
Finished May 21 12:28:53 PM PDT 24
Peak memory 216048 kb
Host smart-564570a6-b349-4974-b727-669270a14d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729714490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.729714490
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2713839019
Short name T923
Test name
Test status
Simulation time 1986455477 ps
CPU time 10.73 seconds
Started May 21 12:27:26 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 215956 kb
Host smart-0a1b155a-c811-45bc-9b56-3e040bfd106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713839019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2713839019
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.210072538
Short name T893
Test name
Test status
Simulation time 1008875429 ps
CPU time 2.45 seconds
Started May 21 12:27:28 PM PDT 24
Finished May 21 12:28:30 PM PDT 24
Peak memory 216316 kb
Host smart-bcdcb6c7-4d0e-4ff4-9070-081b05905bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210072538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.210072538
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1508783726
Short name T936
Test name
Test status
Simulation time 70397504 ps
CPU time 0.84 seconds
Started May 21 12:27:27 PM PDT 24
Finished May 21 12:28:27 PM PDT 24
Peak memory 205528 kb
Host smart-2c6b8b4d-b490-45e2-a14f-d9c00b0c55a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508783726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1508783726
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3226990936
Short name T782
Test name
Test status
Simulation time 3005337797 ps
CPU time 3.96 seconds
Started May 21 12:27:27 PM PDT 24
Finished May 21 12:28:30 PM PDT 24
Peak memory 233336 kb
Host smart-90e1002e-9e56-4b54-9a97-8a3602f97ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226990936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3226990936
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.606917673
Short name T450
Test name
Test status
Simulation time 24180951 ps
CPU time 0.69 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:28:35 PM PDT 24
Peak memory 204688 kb
Host smart-d51658d3-b484-49c4-a16e-37384de1ddc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606917673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.606917673
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.729217713
Short name T912
Test name
Test status
Simulation time 1858320008 ps
CPU time 5.45 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 218120 kb
Host smart-cdc52860-2cd8-48b9-a75b-c63e8a4f922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729217713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.729217713
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2521218753
Short name T760
Test name
Test status
Simulation time 17803791 ps
CPU time 0.76 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:34 PM PDT 24
Peak memory 206600 kb
Host smart-4fd6f63d-b982-4969-95f2-5f7a56acea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521218753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2521218753
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1111877742
Short name T941
Test name
Test status
Simulation time 40331542925 ps
CPU time 283.77 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 249880 kb
Host smart-a38264a8-20e9-4102-8552-696be540c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111877742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1111877742
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3361765697
Short name T95
Test name
Test status
Simulation time 52816974211 ps
CPU time 57.33 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:29:29 PM PDT 24
Peak memory 249920 kb
Host smart-827c3b26-04a2-4e92-b195-5166e3af8c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361765697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3361765697
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2725593653
Short name T701
Test name
Test status
Simulation time 13126627977 ps
CPU time 76.53 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:29:50 PM PDT 24
Peak memory 251168 kb
Host smart-65971d30-d90a-4ded-a36f-2d601512c365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725593653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2725593653
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2015096677
Short name T581
Test name
Test status
Simulation time 85831086 ps
CPU time 2.69 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 224184 kb
Host smart-799b1e43-e39f-45b0-8817-a3980da686e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015096677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2015096677
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1550960091
Short name T709
Test name
Test status
Simulation time 398034527 ps
CPU time 4.54 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 219116 kb
Host smart-836660ac-79a8-4eb1-9d2d-819bc3654575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550960091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1550960091
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.644698665
Short name T616
Test name
Test status
Simulation time 1658606937 ps
CPU time 21.29 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 238448 kb
Host smart-53a4a120-8569-45db-96c6-a5bd52ba092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644698665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.644698665
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3861225672
Short name T32
Test name
Test status
Simulation time 23576544937 ps
CPU time 15.41 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:47 PM PDT 24
Peak memory 235624 kb
Host smart-36c4b948-f5ca-4f1d-b549-605253a17f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861225672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3861225672
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.475173071
Short name T944
Test name
Test status
Simulation time 20908648060 ps
CPU time 18.41 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:50 PM PDT 24
Peak memory 240596 kb
Host smart-abe4dc6d-48e4-46cd-a72f-469d95aec167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475173071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.475173071
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2087070879
Short name T155
Test name
Test status
Simulation time 117511814 ps
CPU time 4.21 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:36 PM PDT 24
Peak memory 221952 kb
Host smart-15cce7ac-149b-45a9-b626-a41f799d6b41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087070879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2087070879
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3876673457
Short name T864
Test name
Test status
Simulation time 39979791 ps
CPU time 0.92 seconds
Started May 21 12:27:38 PM PDT 24
Finished May 21 12:28:39 PM PDT 24
Peak memory 206452 kb
Host smart-a6273b53-bca6-4673-a8ad-717ba3066cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876673457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3876673457
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.612895278
Short name T59
Test name
Test status
Simulation time 2119217677 ps
CPU time 14.84 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:47 PM PDT 24
Peak memory 216004 kb
Host smart-e2b939f7-7e84-4e86-9385-2bfcc6360f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612895278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.612895278
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3793811267
Short name T651
Test name
Test status
Simulation time 1394375601 ps
CPU time 4.79 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 215964 kb
Host smart-128139f3-1360-47e9-bcd0-5c7292a36a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793811267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3793811267
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1492723319
Short name T871
Test name
Test status
Simulation time 786302566 ps
CPU time 3.44 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 216164 kb
Host smart-384cc445-613a-45cf-898f-c8925b65656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492723319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1492723319
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2801932701
Short name T414
Test name
Test status
Simulation time 52502972 ps
CPU time 0.82 seconds
Started May 21 12:27:38 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 205496 kb
Host smart-ed0a3f13-3d93-4036-8037-e0ca82040944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801932701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2801932701
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1158046843
Short name T467
Test name
Test status
Simulation time 1901613417 ps
CPU time 10.06 seconds
Started May 21 12:27:36 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 218408 kb
Host smart-52df68af-0918-4eac-a816-e47a324a0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158046843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1158046843
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2730329184
Short name T813
Test name
Test status
Simulation time 51322819 ps
CPU time 0.75 seconds
Started May 21 12:27:40 PM PDT 24
Finished May 21 12:28:39 PM PDT 24
Peak memory 205076 kb
Host smart-e640a000-798c-4f79-8488-77a429e66bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730329184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2730329184
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2848712973
Short name T108
Test name
Test status
Simulation time 3106297676 ps
CPU time 8.61 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:40 PM PDT 24
Peak memory 219324 kb
Host smart-a00c89d4-8bab-4c0c-92b7-041c27beac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848712973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2848712973
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4192133096
Short name T434
Test name
Test status
Simulation time 15272433 ps
CPU time 0.74 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:34 PM PDT 24
Peak memory 205268 kb
Host smart-92beb5f2-23cb-4913-bc6b-3fc3e58d57e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192133096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4192133096
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3578580965
Short name T182
Test name
Test status
Simulation time 14669438322 ps
CPU time 109.06 seconds
Started May 21 12:27:41 PM PDT 24
Finished May 21 12:30:28 PM PDT 24
Peak memory 248808 kb
Host smart-a87ca1dc-ead1-4728-bf37-c6cd68dfcd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578580965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3578580965
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.233692918
Short name T253
Test name
Test status
Simulation time 103058073893 ps
CPU time 278.98 seconds
Started May 21 12:27:42 PM PDT 24
Finished May 21 12:33:19 PM PDT 24
Peak memory 255632 kb
Host smart-6df06844-6932-4128-b754-688913198cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233692918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.233692918
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2618659473
Short name T50
Test name
Test status
Simulation time 14450976920 ps
CPU time 93.84 seconds
Started May 21 12:27:40 PM PDT 24
Finished May 21 12:30:13 PM PDT 24
Peak memory 250964 kb
Host smart-22892bf0-7207-4b12-b7c6-1214296bc856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618659473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2618659473
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1784527747
Short name T297
Test name
Test status
Simulation time 12807942483 ps
CPU time 32.29 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:29:05 PM PDT 24
Peak memory 240728 kb
Host smart-42ed7e2e-21de-4859-9c70-7d963e74ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784527747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1784527747
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1185398246
Short name T517
Test name
Test status
Simulation time 337526159 ps
CPU time 2.67 seconds
Started May 21 12:27:36 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 224164 kb
Host smart-e8bfcaa0-e8e5-4dd9-b986-99a5e502d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185398246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1185398246
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3695314196
Short name T426
Test name
Test status
Simulation time 1665231663 ps
CPU time 6.36 seconds
Started May 21 12:27:35 PM PDT 24
Finished May 21 12:28:40 PM PDT 24
Peak memory 234692 kb
Host smart-66b19b15-f06a-4ec9-a318-dd4dd5d86892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695314196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3695314196
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.760953646
Short name T825
Test name
Test status
Simulation time 381944490 ps
CPU time 6.11 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:39 PM PDT 24
Peak memory 236664 kb
Host smart-bcefb1f6-6af5-4d3a-9b0b-c02c3805d658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760953646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.760953646
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1488859979
Short name T126
Test name
Test status
Simulation time 87029395 ps
CPU time 2.76 seconds
Started May 21 12:27:34 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 233712 kb
Host smart-0bf9b783-da4f-4dc6-8cd2-09b682caf7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488859979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1488859979
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.569345841
Short name T560
Test name
Test status
Simulation time 167142492 ps
CPU time 4.16 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:37 PM PDT 24
Peak memory 221460 kb
Host smart-5edf2eeb-4b94-4b15-80d7-7a0bf294d917
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=569345841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.569345841
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3409000627
Short name T900
Test name
Test status
Simulation time 18336049 ps
CPU time 0.71 seconds
Started May 21 12:27:32 PM PDT 24
Finished May 21 12:28:32 PM PDT 24
Peak memory 205356 kb
Host smart-6bdf13ef-4e2f-40da-8a54-4f21f8624ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409000627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3409000627
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2687691396
Short name T392
Test name
Test status
Simulation time 28032619664 ps
CPU time 22.44 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:55 PM PDT 24
Peak memory 216068 kb
Host smart-4c55e403-5389-4ef1-b982-e17f67810b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687691396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2687691396
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.699935050
Short name T525
Test name
Test status
Simulation time 1039337315 ps
CPU time 9.27 seconds
Started May 21 12:27:33 PM PDT 24
Finished May 21 12:28:41 PM PDT 24
Peak memory 215980 kb
Host smart-9c79b205-d208-45c4-a11c-43ee1bf74900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699935050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.699935050
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.755730218
Short name T837
Test name
Test status
Simulation time 98204813 ps
CPU time 0.91 seconds
Started May 21 12:27:38 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 205844 kb
Host smart-e55c4bb9-dfc9-40fb-9367-11c201e8718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755730218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.755730218
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2551895840
Short name T193
Test name
Test status
Simulation time 28004472247 ps
CPU time 28.87 seconds
Started May 21 12:27:37 PM PDT 24
Finished May 21 12:29:05 PM PDT 24
Peak memory 239556 kb
Host smart-e671ae77-bbc0-4dc1-8d6f-c38f5ee68c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551895840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2551895840
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3268093175
Short name T608
Test name
Test status
Simulation time 13080088 ps
CPU time 0.69 seconds
Started May 21 12:27:53 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 205152 kb
Host smart-09fb00ae-a24e-45a4-817f-f30cdd1de325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268093175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3268093175
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3040583750
Short name T359
Test name
Test status
Simulation time 266162429 ps
CPU time 2.17 seconds
Started May 21 12:27:40 PM PDT 24
Finished May 21 12:28:41 PM PDT 24
Peak memory 221288 kb
Host smart-2ad479f9-5b90-4988-aa4d-6263f9658b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040583750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3040583750
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.257535334
Short name T903
Test name
Test status
Simulation time 16674195 ps
CPU time 0.85 seconds
Started May 21 12:27:41 PM PDT 24
Finished May 21 12:28:40 PM PDT 24
Peak memory 205208 kb
Host smart-0937e6e8-0cbc-4ff5-892e-ff6d0076988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257535334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.257535334
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.190069375
Short name T191
Test name
Test status
Simulation time 99057671764 ps
CPU time 347.1 seconds
Started May 21 12:27:42 PM PDT 24
Finished May 21 12:34:27 PM PDT 24
Peak memory 250916 kb
Host smart-25c07dee-00bf-4490-81f0-6642e00ff8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190069375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.190069375
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3331783680
Short name T579
Test name
Test status
Simulation time 26357541793 ps
CPU time 154.72 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 256204 kb
Host smart-db4eeae2-46ba-4e9f-9b7d-bf5179a384f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331783680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3331783680
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1841453390
Short name T175
Test name
Test status
Simulation time 35574419933 ps
CPU time 300.64 seconds
Started May 21 12:27:46 PM PDT 24
Finished May 21 12:33:42 PM PDT 24
Peak memory 248928 kb
Host smart-2c5550c9-1204-4697-85fc-f7b604ea7407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841453390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1841453390
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3095211855
Short name T631
Test name
Test status
Simulation time 139604808 ps
CPU time 4.11 seconds
Started May 21 12:27:43 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 233368 kb
Host smart-672d8de4-29e9-49cf-bbde-b20ca29b9aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095211855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3095211855
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3061691096
Short name T174
Test name
Test status
Simulation time 1457869290 ps
CPU time 7.09 seconds
Started May 21 12:27:42 PM PDT 24
Finished May 21 12:28:46 PM PDT 24
Peak memory 218484 kb
Host smart-34be93d4-bcce-4d32-8fb5-029f2a48a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061691096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3061691096
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.906931536
Short name T428
Test name
Test status
Simulation time 11285693568 ps
CPU time 25.63 seconds
Started May 21 12:27:43 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 236188 kb
Host smart-99b81442-4bec-4950-844d-c58b407dc8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906931536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.906931536
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1649271101
Short name T716
Test name
Test status
Simulation time 989170957 ps
CPU time 6.03 seconds
Started May 21 12:27:40 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 233328 kb
Host smart-5a793599-4f84-4aa5-a3db-e7bb4f752744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649271101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1649271101
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1025951546
Short name T217
Test name
Test status
Simulation time 441428965 ps
CPU time 3.55 seconds
Started May 21 12:27:41 PM PDT 24
Finished May 21 12:28:43 PM PDT 24
Peak memory 216640 kb
Host smart-03eb6ca0-15cc-4855-b7c7-f79c7b08a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025951546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1025951546
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.332876443
Short name T410
Test name
Test status
Simulation time 589754354 ps
CPU time 3.78 seconds
Started May 21 12:27:41 PM PDT 24
Finished May 21 12:28:43 PM PDT 24
Peak memory 218516 kb
Host smart-d72245a8-9719-4167-8f4a-8a0a9b922754
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332876443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.332876443
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.481731091
Short name T47
Test name
Test status
Simulation time 5519074630 ps
CPU time 83.38 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:30:12 PM PDT 24
Peak memory 248900 kb
Host smart-d2ced102-43e6-4024-a094-0e14dd96497b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481731091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.481731091
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2999591760
Short name T869
Test name
Test status
Simulation time 1032802633 ps
CPU time 7.5 seconds
Started May 21 12:27:43 PM PDT 24
Finished May 21 12:28:47 PM PDT 24
Peak memory 216088 kb
Host smart-41708de0-de6d-46cb-918e-5e2cdfc09d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999591760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2999591760
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2596142136
Short name T938
Test name
Test status
Simulation time 1777069778 ps
CPU time 4.09 seconds
Started May 21 12:27:43 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 215876 kb
Host smart-d9801f8a-73d2-4c9a-8dd2-d520fec22c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596142136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2596142136
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3352607008
Short name T45
Test name
Test status
Simulation time 295343874 ps
CPU time 2.57 seconds
Started May 21 12:27:39 PM PDT 24
Finished May 21 12:28:40 PM PDT 24
Peak memory 215908 kb
Host smart-d49db058-ea34-41f8-baca-87717dc8b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352607008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3352607008
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2210293351
Short name T503
Test name
Test status
Simulation time 69034380 ps
CPU time 0.75 seconds
Started May 21 12:27:38 PM PDT 24
Finished May 21 12:28:38 PM PDT 24
Peak memory 205548 kb
Host smart-01497a44-bb73-41ab-b6e7-8fc8c8eeed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210293351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2210293351
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.47304864
Short name T564
Test name
Test status
Simulation time 21356496898 ps
CPU time 22.95 seconds
Started May 21 12:27:39 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 240428 kb
Host smart-da71fb1a-b96f-4a83-9f40-15d64ad6e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47304864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.47304864
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3224383223
Short name T962
Test name
Test status
Simulation time 45392127 ps
CPU time 0.75 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 205128 kb
Host smart-bcae8966-7448-4111-9a1a-505fa0232d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224383223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3224383223
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2426754639
Short name T697
Test name
Test status
Simulation time 27849169 ps
CPU time 0.75 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 205596 kb
Host smart-076858b2-64b4-4aa2-abd9-e5766b168a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426754639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2426754639
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3876683483
Short name T214
Test name
Test status
Simulation time 51387291550 ps
CPU time 187.79 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 251004 kb
Host smart-6c98c6dd-826a-4313-9a23-ae9e187680b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876683483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3876683483
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2025254427
Short name T683
Test name
Test status
Simulation time 29422532842 ps
CPU time 52.74 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:29:37 PM PDT 24
Peak memory 224360 kb
Host smart-3bb3d913-6f3e-47d1-9b0c-1ae6aad48714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025254427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2025254427
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.751960371
Short name T89
Test name
Test status
Simulation time 30715170973 ps
CPU time 119.11 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 249120 kb
Host smart-bd4d219c-fd50-472a-8dfb-f64eb1240dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751960371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.751960371
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.667728933
Short name T309
Test name
Test status
Simulation time 775773295 ps
CPU time 8.33 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 232416 kb
Host smart-a5ccbb91-640e-4f18-af49-6f86c2686aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667728933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.667728933
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1950684776
Short name T766
Test name
Test status
Simulation time 121378740 ps
CPU time 4.27 seconds
Started May 21 12:27:49 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 218160 kb
Host smart-2a38351f-ba81-4e81-8065-def4376b0abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950684776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1950684776
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2312467696
Short name T402
Test name
Test status
Simulation time 8438835308 ps
CPU time 39.76 seconds
Started May 21 12:27:50 PM PDT 24
Finished May 21 12:29:25 PM PDT 24
Peak memory 222712 kb
Host smart-828ea274-a415-4b5e-bae3-6a2ce1e4769c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312467696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2312467696
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2395237754
Short name T641
Test name
Test status
Simulation time 867289110 ps
CPU time 7.33 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:51 PM PDT 24
Peak memory 218612 kb
Host smart-bdbed2cc-5e72-4373-ba2c-a41800fab9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395237754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2395237754
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.125071283
Short name T862
Test name
Test status
Simulation time 7070779768 ps
CPU time 11.98 seconds
Started May 21 12:27:52 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 236296 kb
Host smart-e5f63f78-98d6-4abe-9875-709cdef39233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125071283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.125071283
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3293103422
Short name T752
Test name
Test status
Simulation time 250254694 ps
CPU time 5.03 seconds
Started May 21 12:27:50 PM PDT 24
Finished May 21 12:28:50 PM PDT 24
Peak memory 221992 kb
Host smart-73ab8bd5-37a3-4e86-90fc-05320b230531
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3293103422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3293103422
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2335812838
Short name T67
Test name
Test status
Simulation time 1154108470 ps
CPU time 2.87 seconds
Started May 21 12:27:47 PM PDT 24
Finished May 21 12:28:46 PM PDT 24
Peak memory 221960 kb
Host smart-dcfbff84-8446-4314-9788-e18229ca07e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335812838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2335812838
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2544592369
Short name T146
Test name
Test status
Simulation time 5596001778 ps
CPU time 23.17 seconds
Started May 21 12:27:50 PM PDT 24
Finished May 21 12:29:09 PM PDT 24
Peak memory 219812 kb
Host smart-6d44d69e-1977-495b-ad9d-4d29b8c7de0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544592369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2544592369
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4288308916
Short name T572
Test name
Test status
Simulation time 2022643490 ps
CPU time 4.29 seconds
Started May 21 12:27:53 PM PDT 24
Finished May 21 12:28:52 PM PDT 24
Peak memory 215908 kb
Host smart-88483dac-fff9-4612-b264-ab0e05db3eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288308916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4288308916
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3838099833
Short name T898
Test name
Test status
Simulation time 126164723 ps
CPU time 1.13 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:45 PM PDT 24
Peak memory 207704 kb
Host smart-7e68431f-2595-4b91-b4dd-2dfbfb80201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838099833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3838099833
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.51646334
Short name T16
Test name
Test status
Simulation time 201807674 ps
CPU time 0.87 seconds
Started May 21 12:27:47 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 206588 kb
Host smart-a527df3d-36cc-49d9-824f-8b260354e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51646334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.51646334
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2044853672
Short name T39
Test name
Test status
Simulation time 268448386 ps
CPU time 3.63 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:47 PM PDT 24
Peak memory 218576 kb
Host smart-08c6190c-82a3-4219-b4ae-683457cc8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044853672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2044853672
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2986111493
Short name T554
Test name
Test status
Simulation time 14253591 ps
CPU time 0.78 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:02 PM PDT 24
Peak memory 205116 kb
Host smart-54efa295-b5aa-452c-8765-d9b4b5311ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986111493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
986111493
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.980617030
Short name T352
Test name
Test status
Simulation time 5327624102 ps
CPU time 6.1 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:44 PM PDT 24
Peak memory 218340 kb
Host smart-bd71bbf9-ac67-4ee5-be15-c09f5e5b9d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980617030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.980617030
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1668437065
Short name T796
Test name
Test status
Simulation time 27314857 ps
CPU time 0.77 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:04 PM PDT 24
Peak memory 206264 kb
Host smart-8535382a-79b5-458c-9fe5-6837b78b32da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668437065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1668437065
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.995710788
Short name T682
Test name
Test status
Simulation time 4996837155 ps
CPU time 48.76 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:28:10 PM PDT 24
Peak memory 240620 kb
Host smart-6d9d17b8-fa2e-4736-be87-76f227e310f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995710788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.995710788
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2394641337
Short name T148
Test name
Test status
Simulation time 18791521485 ps
CPU time 78.13 seconds
Started May 21 12:26:15 PM PDT 24
Finished May 21 12:28:13 PM PDT 24
Peak memory 232616 kb
Host smart-c95e40b0-9182-4f5c-9d51-18f5ce8709fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394641337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2394641337
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3666528451
Short name T942
Test name
Test status
Simulation time 5709708916 ps
CPU time 16.51 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:14 PM PDT 24
Peak memory 224168 kb
Host smart-85c14d1e-6432-48f3-a67d-c6cb0d0faea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666528451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3666528451
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3768533247
Short name T495
Test name
Test status
Simulation time 4155171839 ps
CPU time 4.4 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:45 PM PDT 24
Peak memory 224188 kb
Host smart-f597e58a-788f-4f53-aa8e-d55ca51453b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768533247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3768533247
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.330081000
Short name T712
Test name
Test status
Simulation time 56083711341 ps
CPU time 111.59 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:28:42 PM PDT 24
Peak memory 233404 kb
Host smart-29587c6a-7dc9-407a-9b74-15e83e51c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330081000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.330081000
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.981541423
Short name T791
Test name
Test status
Simulation time 8587538006 ps
CPU time 14.09 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:28 PM PDT 24
Peak memory 224256 kb
Host smart-17b02355-fb4b-4cce-8e16-d107ac717002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981541423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
981541423
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3781389016
Short name T329
Test name
Test status
Simulation time 57627484 ps
CPU time 1.82 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:13 PM PDT 24
Peak memory 215836 kb
Host smart-8142cb66-4d42-40f4-8275-622241d0d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781389016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3781389016
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2306112170
Short name T625
Test name
Test status
Simulation time 1227198485 ps
CPU time 7.39 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 218588 kb
Host smart-0ac72f3e-e47c-4b9f-9de4-fd3c5794d082
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306112170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2306112170
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.841037590
Short name T403
Test name
Test status
Simulation time 59938175 ps
CPU time 0.86 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:08 PM PDT 24
Peak memory 206612 kb
Host smart-dc917d72-bc42-4ed4-a4be-5f444f97f79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841037590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.841037590
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3336815950
Short name T376
Test name
Test status
Simulation time 41558170550 ps
CPU time 49.69 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:57 PM PDT 24
Peak memory 216060 kb
Host smart-0a83bfc6-93ee-445f-92c9-25d4a09a74ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336815950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3336815950
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1003878058
Short name T932
Test name
Test status
Simulation time 854630178 ps
CPU time 5.07 seconds
Started May 21 12:26:04 PM PDT 24
Finished May 21 12:26:32 PM PDT 24
Peak memory 215876 kb
Host smart-3caa50ee-7fce-4176-99ef-0c06f091bace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003878058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1003878058
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1436404383
Short name T955
Test name
Test status
Simulation time 292760243 ps
CPU time 1.71 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:07 PM PDT 24
Peak memory 215956 kb
Host smart-c0176b57-ed24-4543-80e0-1dd36615b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436404383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1436404383
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3749826859
Short name T474
Test name
Test status
Simulation time 76766274 ps
CPU time 0.78 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:08 PM PDT 24
Peak memory 205560 kb
Host smart-aacf41f8-a7ff-4e53-807d-1d8b1c0109b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749826859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3749826859
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.707303220
Short name T567
Test name
Test status
Simulation time 269203859 ps
CPU time 4.26 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:27:31 PM PDT 24
Peak memory 216012 kb
Host smart-c2264b66-e2bf-4bbe-82b6-5838c78add8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707303220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.707303220
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3153220373
Short name T360
Test name
Test status
Simulation time 17100439 ps
CPU time 0.76 seconds
Started May 21 12:27:51 PM PDT 24
Finished May 21 12:28:46 PM PDT 24
Peak memory 205260 kb
Host smart-b30eed14-ebbd-46f5-a557-8096000055c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153220373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3153220373
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3896562772
Short name T823
Test name
Test status
Simulation time 1182193253 ps
CPU time 12.57 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 219804 kb
Host smart-9a5ddf50-fd94-47ce-9ca5-692056e0d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896562772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3896562772
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3750828762
Short name T731
Test name
Test status
Simulation time 62687042 ps
CPU time 0.78 seconds
Started May 21 12:27:53 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 206632 kb
Host smart-18daf740-f34e-4592-8bc2-6b75489cd36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750828762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3750828762
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.425461264
Short name T12
Test name
Test status
Simulation time 3336362236 ps
CPU time 37.7 seconds
Started May 21 12:27:50 PM PDT 24
Finished May 21 12:29:23 PM PDT 24
Peak memory 248920 kb
Host smart-687dfb6a-97bb-44a2-a318-4116973fbd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425461264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.425461264
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1854263245
Short name T258
Test name
Test status
Simulation time 9767959931 ps
CPU time 53.31 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:29:37 PM PDT 24
Peak memory 249500 kb
Host smart-8d78451d-e606-4cc9-a6cb-d86570024abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854263245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1854263245
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2106687853
Short name T282
Test name
Test status
Simulation time 862927862 ps
CPU time 4.86 seconds
Started May 21 12:27:49 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 234004 kb
Host smart-9660cbc0-60b5-4235-9527-3e2b1746647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106687853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2106687853
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3652192243
Short name T935
Test name
Test status
Simulation time 6168890036 ps
CPU time 29.61 seconds
Started May 21 12:27:47 PM PDT 24
Finished May 21 12:29:12 PM PDT 24
Peak memory 232416 kb
Host smart-b185910a-94d4-4ef2-b618-0ecd5fb13f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652192243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3652192243
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2219184808
Short name T192
Test name
Test status
Simulation time 4949663904 ps
CPU time 11.39 seconds
Started May 21 12:27:52 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 237156 kb
Host smart-03bbabef-8d6e-475b-8676-811ed75c7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219184808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2219184808
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2126597039
Short name T447
Test name
Test status
Simulation time 4675830039 ps
CPU time 5.12 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 217708 kb
Host smart-b5216370-987f-4633-97d8-3e0c5d5f0107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126597039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2126597039
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.791949462
Short name T702
Test name
Test status
Simulation time 1314897064 ps
CPU time 12.29 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:29:00 PM PDT 24
Peak memory 218324 kb
Host smart-3fcbdbd5-0f38-44f6-b917-4c3557f64334
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=791949462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.791949462
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.162959025
Short name T72
Test name
Test status
Simulation time 399746336 ps
CPU time 1.01 seconds
Started May 21 12:27:47 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 206672 kb
Host smart-79f8cf8e-2fd4-44e0-b70c-78c5c19e0a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162959025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.162959025
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2418311886
Short name T343
Test name
Test status
Simulation time 1886543785 ps
CPU time 11.46 seconds
Started May 21 12:27:52 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 215968 kb
Host smart-1068680f-e711-434c-ac69-68dc6ebe3d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418311886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2418311886
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4188960192
Short name T407
Test name
Test status
Simulation time 3734293145 ps
CPU time 3.51 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:47 PM PDT 24
Peak memory 216308 kb
Host smart-36faffbd-60b6-4eec-a9ea-d79b3a9f1cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188960192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4188960192
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1757786238
Short name T650
Test name
Test status
Simulation time 37055178 ps
CPU time 0.74 seconds
Started May 21 12:27:51 PM PDT 24
Finished May 21 12:28:46 PM PDT 24
Peak memory 205596 kb
Host smart-0968d1ea-b955-4cc4-95d6-42c04e7a8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757786238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1757786238
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3903220314
Short name T749
Test name
Test status
Simulation time 37505117 ps
CPU time 0.84 seconds
Started May 21 12:27:48 PM PDT 24
Finished May 21 12:28:44 PM PDT 24
Peak memory 205484 kb
Host smart-ad35a239-d374-4b30-ae19-366ab45b9a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903220314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3903220314
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.336268114
Short name T489
Test name
Test status
Simulation time 151129512 ps
CPU time 2.33 seconds
Started May 21 12:27:49 PM PDT 24
Finished May 21 12:28:47 PM PDT 24
Peak memory 213016 kb
Host smart-26ed607e-ea0f-47ad-ab79-e3eb403c75cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336268114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.336268114
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3417284549
Short name T388
Test name
Test status
Simulation time 19590215 ps
CPU time 0.7 seconds
Started May 21 12:27:55 PM PDT 24
Finished May 21 12:28:50 PM PDT 24
Peak memory 205472 kb
Host smart-c5262788-e20e-47a2-b89d-98106d3f7255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417284549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3417284549
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1250822320
Short name T400
Test name
Test status
Simulation time 343210448 ps
CPU time 2.6 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 218580 kb
Host smart-892d7966-89ec-4d93-9151-80c6cd2ad5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250822320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1250822320
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1881827210
Short name T542
Test name
Test status
Simulation time 13950730 ps
CPU time 0.74 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:28:49 PM PDT 24
Peak memory 206256 kb
Host smart-df354310-aab4-4d70-8f15-a1fd805474e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881827210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1881827210
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.458726792
Short name T592
Test name
Test status
Simulation time 827639866 ps
CPU time 9.39 seconds
Started May 21 12:27:56 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 234232 kb
Host smart-603cda33-c3bf-4a5d-9da0-9d8e9bd48786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458726792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.458726792
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2982738880
Short name T504
Test name
Test status
Simulation time 3153195156 ps
CPU time 81.42 seconds
Started May 21 12:27:58 PM PDT 24
Finished May 21 12:30:13 PM PDT 24
Peak memory 249084 kb
Host smart-a617b3b2-7db2-43b7-850d-c65fbe3e87ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982738880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2982738880
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3019120900
Short name T429
Test name
Test status
Simulation time 3350344145 ps
CPU time 51.28 seconds
Started May 21 12:27:55 PM PDT 24
Finished May 21 12:29:40 PM PDT 24
Peak memory 248928 kb
Host smart-a1accd0b-1320-4bdf-b6f4-c214d4f3a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019120900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3019120900
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2313092895
Short name T312
Test name
Test status
Simulation time 805052426 ps
CPU time 8.17 seconds
Started May 21 12:27:55 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 240616 kb
Host smart-b9d31658-07f2-446f-b523-0085a046b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313092895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2313092895
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.372270189
Short name T698
Test name
Test status
Simulation time 848899325 ps
CPU time 7.96 seconds
Started May 21 12:28:02 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 218124 kb
Host smart-75437d09-7c13-480b-a698-fa48cf4c1d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372270189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.372270189
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2162624158
Short name T595
Test name
Test status
Simulation time 9264463946 ps
CPU time 9.3 seconds
Started May 21 12:28:02 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 222776 kb
Host smart-b36333c0-860f-4017-8393-3d7fd2d68c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162624158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2162624158
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.210559432
Short name T302
Test name
Test status
Simulation time 3206573496 ps
CPU time 9.72 seconds
Started May 21 12:28:00 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 235360 kb
Host smart-6f4d6339-8346-46ee-a7d1-966b4f615672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210559432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.210559432
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3793882986
Short name T901
Test name
Test status
Simulation time 2287368118 ps
CPU time 11.76 seconds
Started May 21 12:27:56 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 228652 kb
Host smart-83dd03b7-f009-4893-ad8c-8c6938f49b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793882986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3793882986
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.187074291
Short name T394
Test name
Test status
Simulation time 2380652825 ps
CPU time 9.46 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 219748 kb
Host smart-82fbc905-19d6-4612-8c2c-839e0c3bde35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187074291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.187074291
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.609766308
Short name T739
Test name
Test status
Simulation time 348870043 ps
CPU time 0.91 seconds
Started May 21 12:28:00 PM PDT 24
Finished May 21 12:28:52 PM PDT 24
Peak memory 206684 kb
Host smart-2e6a68ee-d4f2-43ca-9810-e3d95b537b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609766308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.609766308
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2296072798
Short name T559
Test name
Test status
Simulation time 6408616222 ps
CPU time 26.37 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:29:15 PM PDT 24
Peak memory 216060 kb
Host smart-14193c7e-8f89-40f4-917b-8c3f42dc5b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296072798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2296072798
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2607882116
Short name T700
Test name
Test status
Simulation time 563670485 ps
CPU time 3.99 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:28:55 PM PDT 24
Peak memory 215932 kb
Host smart-513938e8-ea61-4251-ac47-bab7be44054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607882116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2607882116
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1325066353
Short name T340
Test name
Test status
Simulation time 513319843 ps
CPU time 3.25 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:28:52 PM PDT 24
Peak memory 215948 kb
Host smart-0a524fb6-6587-4db5-9f9d-93b0b723de36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325066353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1325066353
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2871637791
Short name T606
Test name
Test status
Simulation time 56995240 ps
CPU time 0.8 seconds
Started May 21 12:27:56 PM PDT 24
Finished May 21 12:28:50 PM PDT 24
Peak memory 205896 kb
Host smart-61abbc1c-8f08-4eaa-b09f-019c6503cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871637791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2871637791
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1630437855
Short name T806
Test name
Test status
Simulation time 4264023124 ps
CPU time 19.13 seconds
Started May 21 12:27:54 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 240580 kb
Host smart-002c54df-8e1c-4f99-b6af-7748c4bf4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630437855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1630437855
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3581391585
Short name T484
Test name
Test status
Simulation time 46029502 ps
CPU time 0.7 seconds
Started May 21 12:28:05 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 204512 kb
Host smart-a45c6761-8358-4475-b44b-8d3cfb7821f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581391585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3581391585
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.56202281
Short name T224
Test name
Test status
Simulation time 76017430 ps
CPU time 2.28 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 218216 kb
Host smart-354fecd5-13fb-4ef6-9b64-3fe4c4ac6a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56202281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.56202281
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2398257341
Short name T636
Test name
Test status
Simulation time 49579916 ps
CPU time 0.74 seconds
Started May 21 12:27:58 PM PDT 24
Finished May 21 12:28:52 PM PDT 24
Peak memory 205636 kb
Host smart-37193b69-2ee0-402d-8361-0b7fb60a0316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398257341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2398257341
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1388215913
Short name T585
Test name
Test status
Simulation time 2121794909 ps
CPU time 8.74 seconds
Started May 21 12:28:01 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 240556 kb
Host smart-47cdfa0b-3480-4ca8-b1ff-01e14c46921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388215913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1388215913
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1350465081
Short name T561
Test name
Test status
Simulation time 3093400458 ps
CPU time 79.52 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 248964 kb
Host smart-4459535a-ec63-4e48-8106-941501ef8738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350465081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1350465081
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1190984420
Short name T877
Test name
Test status
Simulation time 2609979325 ps
CPU time 30.04 seconds
Started May 21 12:28:01 PM PDT 24
Finished May 21 12:29:22 PM PDT 24
Peak memory 218180 kb
Host smart-a1d68443-4b77-4268-8a9a-4dd4c04c6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190984420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1190984420
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3732651701
Short name T549
Test name
Test status
Simulation time 837739727 ps
CPU time 11.33 seconds
Started May 21 12:27:57 PM PDT 24
Finished May 21 12:29:02 PM PDT 24
Peak memory 240608 kb
Host smart-a28a0981-78ca-403c-9c71-e915f160ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732651701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3732651701
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1207319394
Short name T531
Test name
Test status
Simulation time 1236399761 ps
CPU time 2.38 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 218132 kb
Host smart-53fa010e-3abf-4191-aa98-358a0bbe856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207319394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1207319394
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.318371444
Short name T196
Test name
Test status
Simulation time 387111743 ps
CPU time 10.61 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:29:02 PM PDT 24
Peak memory 228436 kb
Host smart-5d7c80ce-bd0b-4ccc-8cfa-467b1c56e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318371444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.318371444
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.184941085
Short name T368
Test name
Test status
Simulation time 287352690 ps
CPU time 2.7 seconds
Started May 21 12:27:58 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 218488 kb
Host smart-5ba5a616-6535-43ba-b70c-7dfca0751345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184941085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.184941085
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3615551634
Short name T873
Test name
Test status
Simulation time 1352424789 ps
CPU time 6.66 seconds
Started May 21 12:27:53 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 237616 kb
Host smart-882568d7-c079-42cf-b9b1-f2c14a838a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615551634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3615551634
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3498200430
Short name T86
Test name
Test status
Simulation time 851603288 ps
CPU time 7.9 seconds
Started May 21 12:28:02 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 219468 kb
Host smart-9d162d9d-b2fe-4832-8614-55cc82d1ce31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3498200430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3498200430
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3096311844
Short name T764
Test name
Test status
Simulation time 58430059 ps
CPU time 1.21 seconds
Started May 21 12:28:05 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 206992 kb
Host smart-7b1093d5-7e10-4f0a-8a56-43999c25ec44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096311844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3096311844
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1688066916
Short name T178
Test name
Test status
Simulation time 25226066409 ps
CPU time 43.53 seconds
Started May 21 12:28:00 PM PDT 24
Finished May 21 12:29:35 PM PDT 24
Peak memory 216068 kb
Host smart-c19f2bed-0eb4-4f38-b52f-1500f842f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688066916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1688066916
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3664850863
Short name T453
Test name
Test status
Simulation time 548346578 ps
CPU time 1.75 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:28:53 PM PDT 24
Peak memory 207448 kb
Host smart-a84e5c06-b240-4b42-aef5-760adea9f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664850863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3664850863
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2379862299
Short name T19
Test name
Test status
Simulation time 741603267 ps
CPU time 13.49 seconds
Started May 21 12:27:56 PM PDT 24
Finished May 21 12:29:03 PM PDT 24
Peak memory 215936 kb
Host smart-251d5412-bd0d-484a-ba4d-17443b76a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379862299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2379862299
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1799533868
Short name T499
Test name
Test status
Simulation time 185640308 ps
CPU time 0.98 seconds
Started May 21 12:27:55 PM PDT 24
Finished May 21 12:28:50 PM PDT 24
Peak memory 205556 kb
Host smart-b82a21df-286c-474d-9bbc-53a2c65b0a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799533868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1799533868
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2660182018
Short name T615
Test name
Test status
Simulation time 715736412 ps
CPU time 7.66 seconds
Started May 21 12:27:59 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 240240 kb
Host smart-e99ff930-07dd-44e3-bbc1-aa7fc20ab390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660182018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2660182018
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3870339231
Short name T794
Test name
Test status
Simulation time 51354394 ps
CPU time 0.68 seconds
Started May 21 12:28:05 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 205064 kb
Host smart-fceb0394-c443-45b8-9e7b-bbe3d482bed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870339231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3870339231
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3032225193
Short name T56
Test name
Test status
Simulation time 110490085 ps
CPU time 2.3 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 221204 kb
Host smart-e4bf0af0-ecf8-4ad3-8a03-1a391dd434c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032225193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3032225193
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3253919306
Short name T8
Test name
Test status
Simulation time 13638495 ps
CPU time 0.75 seconds
Started May 21 12:28:05 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 205292 kb
Host smart-b03396b7-d661-4c66-bfd1-a7be3388b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253919306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3253919306
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2513812537
Short name T236
Test name
Test status
Simulation time 25508354925 ps
CPU time 78.22 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:30:15 PM PDT 24
Peak memory 257020 kb
Host smart-c579d5af-a910-451c-b1ed-147f1c12bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513812537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2513812537
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1545992435
Short name T658
Test name
Test status
Simulation time 10879554468 ps
CPU time 121.41 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 256412 kb
Host smart-7d846644-2ffa-43ed-ab72-f81c6fd77aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545992435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1545992435
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2727632369
Short name T88
Test name
Test status
Simulation time 11012855752 ps
CPU time 92.1 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 224276 kb
Host smart-f82cf9ce-e2a0-4a2f-8102-6a92b79e9d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727632369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2727632369
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1242646797
Short name T310
Test name
Test status
Simulation time 856755000 ps
CPU time 9.59 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 224136 kb
Host smart-235ab9a0-6f99-4041-9423-79673f24d6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242646797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1242646797
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3040160640
Short name T839
Test name
Test status
Simulation time 8384332432 ps
CPU time 12.1 seconds
Started May 21 12:28:05 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 233276 kb
Host smart-06ce5caf-0530-4f99-a1db-c4b375aa7e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040160640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3040160640
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3429346292
Short name T755
Test name
Test status
Simulation time 1101052882 ps
CPU time 16.32 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:29:12 PM PDT 24
Peak memory 233264 kb
Host smart-9be98bea-42dd-4466-8ea4-6537d5e9a25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429346292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3429346292
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3832610484
Short name T439
Test name
Test status
Simulation time 3169266405 ps
CPU time 4.66 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 224200 kb
Host smart-5de82414-267a-4201-b30f-dc8d63d8f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832610484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3832610484
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1416385226
Short name T222
Test name
Test status
Simulation time 1948485515 ps
CPU time 4.64 seconds
Started May 21 12:28:00 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 218208 kb
Host smart-72b702e7-bbe0-4058-832f-9d82b638d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416385226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1416385226
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4158995170
Short name T642
Test name
Test status
Simulation time 490102722 ps
CPU time 3.99 seconds
Started May 21 12:28:01 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 222052 kb
Host smart-25b235d1-1a3b-47e0-b354-3126be2f9220
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4158995170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4158995170
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1539973411
Short name T876
Test name
Test status
Simulation time 94493128 ps
CPU time 0.92 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 205484 kb
Host smart-43017d8a-f711-4962-84fe-114e297b6c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539973411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1539973411
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4194283926
Short name T391
Test name
Test status
Simulation time 21793140 ps
CPU time 0.8 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 205472 kb
Host smart-1412ce6e-9119-4273-b7fd-25f25ccd4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194283926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4194283926
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4155149477
Short name T527
Test name
Test status
Simulation time 753176114 ps
CPU time 4.38 seconds
Started May 21 12:28:03 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 215928 kb
Host smart-d2b11c57-4f26-4c48-8084-ef6905d4dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155149477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4155149477
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4257313882
Short name T518
Test name
Test status
Simulation time 190049755 ps
CPU time 1.83 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 216032 kb
Host smart-1e130e72-a6df-4c51-a87c-7b4acb86e13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257313882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4257313882
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.577976994
Short name T451
Test name
Test status
Simulation time 303632180 ps
CPU time 0.88 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 205528 kb
Host smart-f6ea37bc-e4c8-437a-98fa-267c1328d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577976994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.577976994
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3431668148
Short name T905
Test name
Test status
Simulation time 574176746 ps
CPU time 2.2 seconds
Started May 21 12:28:05 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 233208 kb
Host smart-7401a63d-5ef6-412d-9b00-76b1f48aca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431668148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3431668148
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4111992340
Short name T364
Test name
Test status
Simulation time 34606597 ps
CPU time 0.68 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 204600 kb
Host smart-56b0c1eb-cb5d-4bc3-9a9c-1153d2c06dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111992340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4111992340
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4009682374
Short name T757
Test name
Test status
Simulation time 83890788 ps
CPU time 2.18 seconds
Started May 21 12:28:09 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 232324 kb
Host smart-404d2791-63f5-43ff-84d8-e93b929380e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009682374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4009682374
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2490094840
Short name T767
Test name
Test status
Simulation time 14534677 ps
CPU time 0.8 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:28:56 PM PDT 24
Peak memory 205560 kb
Host smart-fea4b984-7410-4c8f-b4cd-af2d8c8fdca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490094840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2490094840
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3706421480
Short name T524
Test name
Test status
Simulation time 11871810289 ps
CPU time 88.83 seconds
Started May 21 12:28:08 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 250796 kb
Host smart-4f8fef25-4ae5-4dca-ac09-8ea3d90a2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706421480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3706421480
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2777940105
Short name T477
Test name
Test status
Simulation time 3525392994 ps
CPU time 38.26 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:35 PM PDT 24
Peak memory 239396 kb
Host smart-a182f19c-4181-49b2-a607-0285d3ef6865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777940105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2777940105
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.557921422
Short name T103
Test name
Test status
Simulation time 4338640172 ps
CPU time 38.11 seconds
Started May 21 12:28:08 PM PDT 24
Finished May 21 12:29:36 PM PDT 24
Peak memory 238396 kb
Host smart-613bcb84-9d07-4d81-b69a-85fb4eed9ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557921422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.557921422
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3041201263
Short name T959
Test name
Test status
Simulation time 556905379 ps
CPU time 5.79 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 240016 kb
Host smart-989b4f56-7586-4ca9-9812-6d273386b2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041201263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3041201263
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.903664789
Short name T198
Test name
Test status
Simulation time 1420619922 ps
CPU time 6.29 seconds
Started May 21 12:28:11 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 232760 kb
Host smart-bfa1493c-3227-4326-9b7a-448c934fcdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903664789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.903664789
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1453431679
Short name T619
Test name
Test status
Simulation time 869807209 ps
CPU time 18.35 seconds
Started May 21 12:28:11 PM PDT 24
Finished May 21 12:29:19 PM PDT 24
Peak memory 239552 kb
Host smart-c8376e50-2cc3-4c75-998d-ddbea15f5e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453431679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1453431679
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3681773130
Short name T470
Test name
Test status
Simulation time 143663892 ps
CPU time 3.07 seconds
Started May 21 12:28:13 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 236256 kb
Host smart-2f1df916-c95f-421d-8490-7fba84db2545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681773130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3681773130
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1622673479
Short name T733
Test name
Test status
Simulation time 246084900 ps
CPU time 5.02 seconds
Started May 21 12:28:11 PM PDT 24
Finished May 21 12:29:05 PM PDT 24
Peak memory 235008 kb
Host smart-c59ec487-8b7e-4858-bede-6583ac6654db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622673479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1622673479
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.49033415
Short name T40
Test name
Test status
Simulation time 86429340 ps
CPU time 4.39 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 222656 kb
Host smart-117e69b1-6cce-43e0-95e9-a4b55f69d28b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49033415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direc
t.49033415
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1202303433
Short name T762
Test name
Test status
Simulation time 139400223990 ps
CPU time 345.28 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:34:42 PM PDT 24
Peak memory 266588 kb
Host smart-0262ed81-fe83-4a66-8773-0e3cd51b3cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202303433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1202303433
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1604165405
Short name T99
Test name
Test status
Simulation time 7636972425 ps
CPU time 17.57 seconds
Started May 21 12:28:04 PM PDT 24
Finished May 21 12:29:13 PM PDT 24
Peak memory 216044 kb
Host smart-88f4a527-ba3b-46de-ad06-dbccd71576c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604165405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1604165405
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3246861004
Short name T801
Test name
Test status
Simulation time 173737101 ps
CPU time 1.69 seconds
Started May 21 12:28:01 PM PDT 24
Finished May 21 12:28:54 PM PDT 24
Peak memory 207440 kb
Host smart-82498a15-4833-4e29-a212-0c9ee1218f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246861004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3246861004
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1778685598
Short name T881
Test name
Test status
Simulation time 50637057 ps
CPU time 0.95 seconds
Started May 21 12:28:10 PM PDT 24
Finished May 21 12:29:00 PM PDT 24
Peak memory 206748 kb
Host smart-9cfcae42-93a7-4301-b10c-a50112082101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778685598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1778685598
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3877745887
Short name T949
Test name
Test status
Simulation time 27811499 ps
CPU time 0.67 seconds
Started May 21 12:28:02 PM PDT 24
Finished May 21 12:28:55 PM PDT 24
Peak memory 205340 kb
Host smart-59b0a6d4-c0e9-4524-8f90-68ba28f19512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877745887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3877745887
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1428092032
Short name T704
Test name
Test status
Simulation time 5380720230 ps
CPU time 11.29 seconds
Started May 21 12:28:08 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 234448 kb
Host smart-1165c3b9-f86e-44c6-aa22-be3769c5a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428092032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1428092032
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.912807195
Short name T416
Test name
Test status
Simulation time 11369415 ps
CPU time 0.7 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 204576 kb
Host smart-d788c192-ffa5-466a-b6b8-45278c3c4d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912807195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.912807195
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2783870489
Short name T455
Test name
Test status
Simulation time 428593588 ps
CPU time 2.45 seconds
Started May 21 12:28:09 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 218432 kb
Host smart-92f89b68-1cf8-4e20-aa17-155923ac6261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783870489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2783870489
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3149744305
Short name T347
Test name
Test status
Simulation time 22922049 ps
CPU time 0.74 seconds
Started May 21 12:28:12 PM PDT 24
Finished May 21 12:29:01 PM PDT 24
Peak memory 206256 kb
Host smart-fb9a0416-b8b6-4d99-82b2-3d7e456d5a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149744305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3149744305
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.689390434
Short name T289
Test name
Test status
Simulation time 11151876233 ps
CPU time 82.35 seconds
Started May 21 12:28:08 PM PDT 24
Finished May 21 12:30:19 PM PDT 24
Peak memory 251116 kb
Host smart-00cf5149-0d14-4521-be34-eb5fbc6b247c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689390434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.689390434
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2356857033
Short name T607
Test name
Test status
Simulation time 5074690127 ps
CPU time 90.37 seconds
Started May 21 12:28:12 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 253244 kb
Host smart-2d155b14-6f2a-47ec-9946-3acac4196510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356857033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2356857033
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1931381965
Short name T569
Test name
Test status
Simulation time 2834665800 ps
CPU time 21.58 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:18 PM PDT 24
Peak memory 219032 kb
Host smart-d3b0bc79-330a-425a-a1e7-4b0390cb1d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931381965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1931381965
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3489369641
Short name T915
Test name
Test status
Simulation time 11203856548 ps
CPU time 36 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:29:32 PM PDT 24
Peak memory 234144 kb
Host smart-01245b2a-5b26-4373-89f6-d31b88d8230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489369641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3489369641
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3438854494
Short name T571
Test name
Test status
Simulation time 663505488 ps
CPU time 6.06 seconds
Started May 21 12:28:12 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 234096 kb
Host smart-5136d75e-4190-4c34-af3a-9da97723d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438854494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3438854494
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3325986722
Short name T753
Test name
Test status
Simulation time 4645416327 ps
CPU time 43.7 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:40 PM PDT 24
Peak memory 233272 kb
Host smart-50fc1496-7bd3-4e6b-beaf-aeab0e22a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325986722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3325986722
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1759152075
Short name T705
Test name
Test status
Simulation time 1196648795 ps
CPU time 10.07 seconds
Started May 21 12:28:11 PM PDT 24
Finished May 21 12:29:10 PM PDT 24
Peak memory 238072 kb
Host smart-c453ef47-ddff-40d3-92dc-55342030a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759152075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1759152075
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.33412721
Short name T6
Test name
Test status
Simulation time 122406490 ps
CPU time 2.34 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 232388 kb
Host smart-3db77372-195e-4d91-9303-5f337bbabe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33412721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.33412721
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3567041068
Short name T603
Test name
Test status
Simulation time 239253747 ps
CPU time 5.28 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:02 PM PDT 24
Peak memory 218808 kb
Host smart-7d0e5b20-92c9-4581-92d4-37f02104b188
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567041068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3567041068
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.543590659
Short name T415
Test name
Test status
Simulation time 270963594 ps
CPU time 1.11 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 206840 kb
Host smart-8c2b3abf-79ab-4b0f-aee0-ff185c34f223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543590659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.543590659
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1313569880
Short name T102
Test name
Test status
Simulation time 2640009392 ps
CPU time 25.03 seconds
Started May 21 12:28:09 PM PDT 24
Finished May 21 12:29:23 PM PDT 24
Peak memory 216224 kb
Host smart-4443d292-1d10-49b8-98e2-c2ff67ce5d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313569880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1313569880
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2846042767
Short name T846
Test name
Test status
Simulation time 3164571547 ps
CPU time 10.49 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 215968 kb
Host smart-883a5764-b773-4332-83d8-687ce58036f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846042767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2846042767
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3827425608
Short name T44
Test name
Test status
Simulation time 194779752 ps
CPU time 3.31 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 216060 kb
Host smart-2f9df4aa-48e8-4913-ac7d-962fcf5173fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827425608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3827425608
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.918260503
Short name T540
Test name
Test status
Simulation time 126620714 ps
CPU time 0.85 seconds
Started May 21 12:28:08 PM PDT 24
Finished May 21 12:28:59 PM PDT 24
Peak memory 205532 kb
Host smart-3a6dbe0f-65b3-4aee-a804-5b2d5204df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918260503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.918260503
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1892090644
Short name T660
Test name
Test status
Simulation time 4780345470 ps
CPU time 7.77 seconds
Started May 21 12:28:11 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 224224 kb
Host smart-9be70086-1c6e-4472-b5ee-130c95663808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892090644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1892090644
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3170570718
Short name T852
Test name
Test status
Simulation time 18051436 ps
CPU time 0.72 seconds
Started May 21 12:28:13 PM PDT 24
Finished May 21 12:29:02 PM PDT 24
Peak memory 204576 kb
Host smart-a21112c8-37af-4d7a-9d68-b5127e0db0c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170570718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3170570718
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.736007437
Short name T421
Test name
Test status
Simulation time 3064346609 ps
CPU time 9.47 seconds
Started May 21 12:28:09 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 234176 kb
Host smart-44c2713e-f9f5-4e2b-9e9a-6922ce4a4d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736007437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.736007437
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.705756824
Short name T396
Test name
Test status
Simulation time 40658397 ps
CPU time 0.76 seconds
Started May 21 12:28:08 PM PDT 24
Finished May 21 12:28:58 PM PDT 24
Peak memory 206628 kb
Host smart-c6295e60-d24b-4096-a24d-7c243c3e2db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705756824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.705756824
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3654548832
Short name T723
Test name
Test status
Simulation time 58943598682 ps
CPU time 208.55 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 248816 kb
Host smart-c5cf686c-3dc4-4641-95ba-b2d4ac4d7d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654548832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3654548832
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.66986739
Short name T97
Test name
Test status
Simulation time 40302164292 ps
CPU time 98.28 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 236836 kb
Host smart-b7042712-3f29-4c55-a5d4-1c55f0c35109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66986739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.66986739
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2020804011
Short name T87
Test name
Test status
Simulation time 1165761194 ps
CPU time 20.97 seconds
Started May 21 12:28:18 PM PDT 24
Finished May 21 12:29:25 PM PDT 24
Peak memory 248804 kb
Host smart-214c2bf0-d542-47cc-bc1c-3667bd64815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020804011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2020804011
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.539003991
Short name T306
Test name
Test status
Simulation time 10826614593 ps
CPU time 37.37 seconds
Started May 21 12:28:17 PM PDT 24
Finished May 21 12:29:41 PM PDT 24
Peak memory 248960 kb
Host smart-965f8169-1053-4e63-92c4-1f8359a766f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539003991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.539003991
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2596816768
Short name T588
Test name
Test status
Simulation time 209888886 ps
CPU time 3.83 seconds
Started May 21 12:28:09 PM PDT 24
Finished May 21 12:29:02 PM PDT 24
Peak memory 236656 kb
Host smart-3320cf90-6a44-4fd8-b676-b8440b1775c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596816768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2596816768
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1961177249
Short name T185
Test name
Test status
Simulation time 400862140 ps
CPU time 8.2 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:10 PM PDT 24
Peak memory 229652 kb
Host smart-2785ce0b-114d-430d-8bca-085a0fdee211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961177249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1961177249
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1432051610
Short name T578
Test name
Test status
Simulation time 12802932603 ps
CPU time 5.8 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 219448 kb
Host smart-fbd470cd-1c5d-4356-baf9-80973a83a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432051610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1432051610
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3552723110
Short name T621
Test name
Test status
Simulation time 3753572353 ps
CPU time 7.42 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 235472 kb
Host smart-598f572d-983d-4573-95fd-b6b144b6715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552723110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3552723110
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.250858492
Short name T380
Test name
Test status
Simulation time 1149461212 ps
CPU time 4.13 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 219976 kb
Host smart-29da8cd9-fd99-4ea4-a233-966f47f27beb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=250858492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.250858492
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2059441721
Short name T46
Test name
Test status
Simulation time 145673218996 ps
CPU time 323.83 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:34:27 PM PDT 24
Peak memory 253468 kb
Host smart-f48bb605-8184-4e26-8819-f98e3229ac65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059441721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2059441721
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1538334810
Short name T322
Test name
Test status
Simulation time 27713859045 ps
CPU time 37.91 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:40 PM PDT 24
Peak memory 216076 kb
Host smart-d96af83a-c291-41ba-86df-e5c9393f725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538334810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1538334810
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1947584544
Short name T574
Test name
Test status
Simulation time 5526189039 ps
CPU time 7.88 seconds
Started May 21 12:28:07 PM PDT 24
Finished May 21 12:29:05 PM PDT 24
Peak memory 215976 kb
Host smart-9add16dc-0a5b-4c63-b60e-8a90ae5aaee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947584544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1947584544
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2566618323
Short name T720
Test name
Test status
Simulation time 46836231 ps
CPU time 1.39 seconds
Started May 21 12:28:12 PM PDT 24
Finished May 21 12:29:02 PM PDT 24
Peak memory 216040 kb
Host smart-8a4fba3c-766b-4ac9-af90-e172fcfedc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566618323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2566618323
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3457179250
Short name T916
Test name
Test status
Simulation time 29694267 ps
CPU time 0.76 seconds
Started May 21 12:28:06 PM PDT 24
Finished May 21 12:28:57 PM PDT 24
Peak memory 205536 kb
Host smart-92182dbf-c9d0-450a-98d9-8d98c4b4d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457179250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3457179250
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2851893195
Short name T465
Test name
Test status
Simulation time 11476430106 ps
CPU time 11.43 seconds
Started May 21 12:28:13 PM PDT 24
Finished May 21 12:29:12 PM PDT 24
Peak memory 234708 kb
Host smart-8582ca5c-39c0-4c30-b0c0-bdd54305e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851893195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2851893195
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.826000643
Short name T835
Test name
Test status
Simulation time 11708453 ps
CPU time 0.74 seconds
Started May 21 12:28:21 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 205428 kb
Host smart-3445d082-184b-4d6c-9dd6-cc23a0051d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826000643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.826000643
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.816997486
Short name T719
Test name
Test status
Simulation time 10022747950 ps
CPU time 6.76 seconds
Started May 21 12:28:21 PM PDT 24
Finished May 21 12:29:14 PM PDT 24
Peak memory 234428 kb
Host smart-c05ab65d-c90a-4ba5-9dde-234e1e861cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816997486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.816997486
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1689509004
Short name T378
Test name
Test status
Simulation time 134683590 ps
CPU time 0.77 seconds
Started May 21 12:28:18 PM PDT 24
Finished May 21 12:29:05 PM PDT 24
Peak memory 205236 kb
Host smart-27dacfe2-af3a-4830-806f-6c3f53d9c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689509004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1689509004
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1009291158
Short name T240
Test name
Test status
Simulation time 8682746121 ps
CPU time 84.38 seconds
Started May 21 12:28:20 PM PDT 24
Finished May 21 12:30:30 PM PDT 24
Peak memory 254228 kb
Host smart-30583aaa-bce9-40ef-b1cf-93799c82a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009291158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1009291158
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.98271901
Short name T904
Test name
Test status
Simulation time 13304393521 ps
CPU time 60.14 seconds
Started May 21 12:28:20 PM PDT 24
Finished May 21 12:30:06 PM PDT 24
Peak memory 224216 kb
Host smart-7cc73eba-fd36-424e-bfc8-2919684f3096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98271901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.98271901
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3450965069
Short name T229
Test name
Test status
Simulation time 34033708053 ps
CPU time 43.82 seconds
Started May 21 12:28:18 PM PDT 24
Finished May 21 12:29:48 PM PDT 24
Peak memory 237040 kb
Host smart-bb2b2fe7-02ba-4112-9f2a-5f8a2ea44494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450965069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3450965069
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1219940777
Short name T896
Test name
Test status
Simulation time 1413970696 ps
CPU time 20.79 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:23 PM PDT 24
Peak memory 224192 kb
Host smart-6837f291-dc3c-426e-8ffd-fa41d98770c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219940777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1219940777
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.428810807
Short name T665
Test name
Test status
Simulation time 1378086080 ps
CPU time 4.82 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 219964 kb
Host smart-b3b64676-3734-4ab9-8a7c-f207e31789f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428810807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.428810807
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1849557983
Short name T502
Test name
Test status
Simulation time 315755046 ps
CPU time 5.23 seconds
Started May 21 12:28:17 PM PDT 24
Finished May 21 12:29:09 PM PDT 24
Peak memory 234676 kb
Host smart-fbc3945b-b2f0-42fe-97f2-70e76276e96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849557983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1849557983
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.205367850
Short name T259
Test name
Test status
Simulation time 1886619768 ps
CPU time 6.14 seconds
Started May 21 12:28:17 PM PDT 24
Finished May 21 12:29:10 PM PDT 24
Peak memory 217644 kb
Host smart-4af3c652-314e-4f94-bd30-825cee8c68ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205367850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.205367850
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.621026813
Short name T810
Test name
Test status
Simulation time 86375766288 ps
CPU time 21.9 seconds
Started May 21 12:28:17 PM PDT 24
Finished May 21 12:29:26 PM PDT 24
Peak memory 219104 kb
Host smart-1ac4158e-31f0-402e-9396-74b2f750513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621026813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.621026813
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1928917512
Short name T954
Test name
Test status
Simulation time 184554939 ps
CPU time 4.48 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 222680 kb
Host smart-0fd1b249-8954-43a8-b7c6-4b3d9de2c85e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1928917512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1928917512
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2942708614
Short name T171
Test name
Test status
Simulation time 18674821431 ps
CPU time 126.78 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:31:10 PM PDT 24
Peak memory 273464 kb
Host smart-acedc940-ac11-4f12-87ac-57b1dcb0aa6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942708614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2942708614
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.114987435
Short name T539
Test name
Test status
Simulation time 21715874997 ps
CPU time 25.86 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:28 PM PDT 24
Peak memory 216172 kb
Host smart-d0e7530a-965d-4798-8875-7ab209b76648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114987435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.114987435
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.300221623
Short name T472
Test name
Test status
Simulation time 4396031892 ps
CPU time 15.48 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:18 PM PDT 24
Peak memory 215924 kb
Host smart-82f70dee-6499-4ad9-b1e5-c2a0701d82f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300221623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.300221623
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4137381027
Short name T960
Test name
Test status
Simulation time 49068280 ps
CPU time 1.03 seconds
Started May 21 12:28:19 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 206784 kb
Host smart-0f49ad3e-528f-4ddf-85f0-a36059c71969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137381027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4137381027
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4284829682
Short name T529
Test name
Test status
Simulation time 106532260 ps
CPU time 0.8 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 205564 kb
Host smart-f7737450-c46e-42d0-bb7a-bc9899ffaa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284829682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4284829682
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4123772797
Short name T62
Test name
Test status
Simulation time 27972823539 ps
CPU time 24.45 seconds
Started May 21 12:28:17 PM PDT 24
Finished May 21 12:29:28 PM PDT 24
Peak memory 229616 kb
Host smart-0ba7abc0-88ad-415a-a754-5f3cc6c492a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123772797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4123772797
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3846500004
Short name T452
Test name
Test status
Simulation time 61164230 ps
CPU time 0.71 seconds
Started May 21 12:28:24 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 205236 kb
Host smart-03900dd9-cee4-4cd1-9c6a-d78e5fcc9f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846500004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3846500004
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4076823542
Short name T706
Test name
Test status
Simulation time 108922248 ps
CPU time 2.4 seconds
Started May 21 12:28:25 PM PDT 24
Finished May 21 12:29:10 PM PDT 24
Peak memory 233580 kb
Host smart-e664fbfb-b222-4066-8b72-161f0a05689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076823542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4076823542
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2881111216
Short name T553
Test name
Test status
Simulation time 16330661 ps
CPU time 0.8 seconds
Started May 21 12:28:19 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 206736 kb
Host smart-4be195dd-0175-4d5f-9866-806f980664a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881111216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2881111216
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2947587340
Short name T284
Test name
Test status
Simulation time 1815953129 ps
CPU time 39.14 seconds
Started May 21 12:28:18 PM PDT 24
Finished May 21 12:29:43 PM PDT 24
Peak memory 252912 kb
Host smart-ec0957e1-bdfb-4e79-8bcf-ca547a5da981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947587340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2947587340
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.775861836
Short name T538
Test name
Test status
Simulation time 18720483529 ps
CPU time 54.6 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:29:58 PM PDT 24
Peak memory 248916 kb
Host smart-0e832963-ec0f-420b-8495-8e97bf78f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775861836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.775861836
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.876610619
Short name T951
Test name
Test status
Simulation time 5651734849 ps
CPU time 79.27 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 248848 kb
Host smart-d04fed40-503f-42b1-ab16-53eccfb777e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876610619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.876610619
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2923850935
Short name T956
Test name
Test status
Simulation time 814065093 ps
CPU time 10.23 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:13 PM PDT 24
Peak memory 224200 kb
Host smart-4a9f36ab-709e-4d6b-aa28-e271a9cb6b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923850935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2923850935
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3365810974
Short name T411
Test name
Test status
Simulation time 103960308 ps
CPU time 1.96 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:04 PM PDT 24
Peak memory 215828 kb
Host smart-d5d3fa94-635e-4ab7-82dc-0d04a6336bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365810974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3365810974
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1506996642
Short name T422
Test name
Test status
Simulation time 274769540 ps
CPU time 8.02 seconds
Started May 21 12:28:19 PM PDT 24
Finished May 21 12:29:14 PM PDT 24
Peak memory 240672 kb
Host smart-74523b34-8b2b-4a8a-8691-c0abf5927a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506996642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1506996642
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4067023372
Short name T570
Test name
Test status
Simulation time 3148004816 ps
CPU time 10.46 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:29:14 PM PDT 24
Peak memory 218544 kb
Host smart-ae972b10-f9b9-495b-8c32-79062816b35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067023372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4067023372
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3774359490
Short name T476
Test name
Test status
Simulation time 1661485536 ps
CPU time 4.87 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:07 PM PDT 24
Peak memory 233720 kb
Host smart-ddb22075-3606-49d1-9a56-c81062b16519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774359490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3774359490
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2916415557
Short name T847
Test name
Test status
Simulation time 4055436828 ps
CPU time 9.57 seconds
Started May 21 12:28:18 PM PDT 24
Finished May 21 12:29:14 PM PDT 24
Peak memory 222204 kb
Host smart-5e4fd13f-338e-4e6a-ab04-cf481ce696dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2916415557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2916415557
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4242779911
Short name T558
Test name
Test status
Simulation time 719718043 ps
CPU time 12.63 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:15 PM PDT 24
Peak memory 215980 kb
Host smart-8477819c-cceb-413c-bf69-ac1eb7579731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242779911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4242779911
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1220912896
Short name T853
Test name
Test status
Simulation time 66843077395 ps
CPU time 11.97 seconds
Started May 21 12:28:14 PM PDT 24
Finished May 21 12:29:14 PM PDT 24
Peak memory 215932 kb
Host smart-ebcd7b48-da2c-4d08-a421-c12e17b14c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220912896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1220912896
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2979604519
Short name T26
Test name
Test status
Simulation time 540871634 ps
CPU time 2.6 seconds
Started May 21 12:28:16 PM PDT 24
Finished May 21 12:29:06 PM PDT 24
Peak memory 215964 kb
Host smart-000c882a-9c9d-4aa5-adad-05d7653d7d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979604519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2979604519
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1860858585
Short name T950
Test name
Test status
Simulation time 16509874 ps
CPU time 0.77 seconds
Started May 21 12:28:15 PM PDT 24
Finished May 21 12:29:03 PM PDT 24
Peak memory 205356 kb
Host smart-0fef4542-56e9-4a0f-924b-b1bb87dac86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860858585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1860858585
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3294693255
Short name T207
Test name
Test status
Simulation time 2961759946 ps
CPU time 9.73 seconds
Started May 21 12:28:18 PM PDT 24
Finished May 21 12:29:15 PM PDT 24
Peak memory 217508 kb
Host smart-758b72d7-cf9c-49fc-a560-6f432d130a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294693255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3294693255
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2401282395
Short name T342
Test name
Test status
Simulation time 12977844 ps
CPU time 0.7 seconds
Started May 21 12:28:24 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 204580 kb
Host smart-719e12af-7676-4c1b-99b7-213d6384c869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401282395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2401282395
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.343808483
Short name T768
Test name
Test status
Simulation time 156774241 ps
CPU time 3.14 seconds
Started May 21 12:28:22 PM PDT 24
Finished May 21 12:29:11 PM PDT 24
Peak memory 218544 kb
Host smart-0cbc14b8-1a8a-452a-bc09-b59440e7a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343808483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.343808483
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.917933035
Short name T377
Test name
Test status
Simulation time 44073468 ps
CPU time 0.8 seconds
Started May 21 12:28:23 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 206308 kb
Host smart-a6052fc6-d826-4c45-9537-035945ed2c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917933035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.917933035
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.907511432
Short name T685
Test name
Test status
Simulation time 20512522 ps
CPU time 0.82 seconds
Started May 21 12:28:37 PM PDT 24
Finished May 21 12:29:14 PM PDT 24
Peak memory 215708 kb
Host smart-ecd08830-3dca-479a-be2a-0eab817d00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907511432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.907511432
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2653855881
Short name T929
Test name
Test status
Simulation time 40113275678 ps
CPU time 143.56 seconds
Started May 21 12:28:29 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 250072 kb
Host smart-27695030-59e1-4f8a-bb1e-12f35903d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653855881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2653855881
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3891608567
Short name T247
Test name
Test status
Simulation time 113280382860 ps
CPU time 107.2 seconds
Started May 21 12:28:23 PM PDT 24
Finished May 21 12:30:54 PM PDT 24
Peak memory 252492 kb
Host smart-9146b478-70a2-40b4-ad10-754af0119e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891608567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3891608567
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3845010133
Short name T845
Test name
Test status
Simulation time 1385522359 ps
CPU time 23.83 seconds
Started May 21 12:28:25 PM PDT 24
Finished May 21 12:29:31 PM PDT 24
Peak memory 232772 kb
Host smart-898f8990-ea1b-47d1-870d-2f901f622c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845010133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3845010133
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3549083366
Short name T756
Test name
Test status
Simulation time 1394749968 ps
CPU time 14.26 seconds
Started May 21 12:28:23 PM PDT 24
Finished May 21 12:29:22 PM PDT 24
Peak memory 218284 kb
Host smart-89b6fbd1-2ebd-4295-a4e0-b1ff847b4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549083366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3549083366
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2489833507
Short name T109
Test name
Test status
Simulation time 2043145781 ps
CPU time 24.71 seconds
Started May 21 12:28:29 PM PDT 24
Finished May 21 12:29:35 PM PDT 24
Peak memory 240684 kb
Host smart-40c421f0-5728-40a9-b82a-3f55914687de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489833507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2489833507
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.333369129
Short name T736
Test name
Test status
Simulation time 1898116534 ps
CPU time 8.71 seconds
Started May 21 12:28:24 PM PDT 24
Finished May 21 12:29:16 PM PDT 24
Peak memory 238664 kb
Host smart-07a1b016-c831-4237-92c3-cfc892533224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333369129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.333369129
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2789816684
Short name T909
Test name
Test status
Simulation time 21418010172 ps
CPU time 19.62 seconds
Started May 21 12:28:22 PM PDT 24
Finished May 21 12:29:27 PM PDT 24
Peak memory 238800 kb
Host smart-7411a556-aaa1-4e03-949a-cbcc15cde5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789816684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2789816684
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2567580169
Short name T385
Test name
Test status
Simulation time 2009746519 ps
CPU time 11.22 seconds
Started May 21 12:28:27 PM PDT 24
Finished May 21 12:29:20 PM PDT 24
Peak memory 222496 kb
Host smart-4f2e024a-3cd0-4720-8900-23e535cbbf35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2567580169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2567580169
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2451394981
Short name T186
Test name
Test status
Simulation time 73063131341 ps
CPU time 632.59 seconds
Started May 21 12:28:22 PM PDT 24
Finished May 21 12:39:40 PM PDT 24
Peak memory 272804 kb
Host smart-e3d37f2a-ad86-482f-bd78-d2fbb0e2d3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451394981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2451394981
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1320716279
Short name T649
Test name
Test status
Simulation time 5809111912 ps
CPU time 29.76 seconds
Started May 21 12:28:26 PM PDT 24
Finished May 21 12:29:38 PM PDT 24
Peak memory 216088 kb
Host smart-87864950-0795-4bf4-908e-d6b4f045ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320716279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1320716279
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1907982877
Short name T599
Test name
Test status
Simulation time 34701187 ps
CPU time 0.68 seconds
Started May 21 12:28:22 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 205316 kb
Host smart-69532b69-2f40-42db-94ae-892fbaa65a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907982877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1907982877
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4129382077
Short name T498
Test name
Test status
Simulation time 52402210 ps
CPU time 3.1 seconds
Started May 21 12:28:25 PM PDT 24
Finished May 21 12:29:11 PM PDT 24
Peak memory 215996 kb
Host smart-4904a602-a5e9-4cbe-8069-df429445efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129382077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4129382077
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3726512252
Short name T721
Test name
Test status
Simulation time 25014775 ps
CPU time 0.74 seconds
Started May 21 12:28:24 PM PDT 24
Finished May 21 12:29:08 PM PDT 24
Peak memory 205476 kb
Host smart-a604a291-31d8-4ff4-a137-707cec7f88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726512252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3726512252
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4019574404
Short name T639
Test name
Test status
Simulation time 23927949288 ps
CPU time 20 seconds
Started May 21 12:28:22 PM PDT 24
Finished May 21 12:29:27 PM PDT 24
Peak memory 239736 kb
Host smart-8b58c1a2-f39b-48fc-ba8f-587c1a487738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019574404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4019574404
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.535447908
Short name T679
Test name
Test status
Simulation time 14451275 ps
CPU time 0.7 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:26:53 PM PDT 24
Peak memory 204536 kb
Host smart-164cab72-d0fc-410e-9349-6e82ba5a46d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535447908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.535447908
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.900603389
Short name T350
Test name
Test status
Simulation time 227105863 ps
CPU time 5.87 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 233768 kb
Host smart-8e3c164f-7a86-4ada-bcee-10690cb71cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900603389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.900603389
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3920151036
Short name T534
Test name
Test status
Simulation time 19990935 ps
CPU time 0.79 seconds
Started May 21 12:26:05 PM PDT 24
Finished May 21 12:26:30 PM PDT 24
Peak memory 206244 kb
Host smart-d771c18d-5c41-4c36-b9ab-4d6550256902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920151036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3920151036
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3636689182
Short name T514
Test name
Test status
Simulation time 1305583021 ps
CPU time 7.69 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:24 PM PDT 24
Peak memory 240512 kb
Host smart-839a6c43-7cf5-436e-b35a-d0ed56f50f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636689182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3636689182
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3052667855
Short name T244
Test name
Test status
Simulation time 294954710157 ps
CPU time 553.12 seconds
Started May 21 12:26:06 PM PDT 24
Finished May 21 12:35:45 PM PDT 24
Peak memory 265292 kb
Host smart-4112030f-4744-4695-9f37-c7816ccd87e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052667855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3052667855
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3371603117
Short name T857
Test name
Test status
Simulation time 20051658232 ps
CPU time 136.4 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:29:18 PM PDT 24
Peak memory 252508 kb
Host smart-48b2a258-85d8-4610-9757-f075023d63d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371603117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3371603117
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3384383535
Short name T533
Test name
Test status
Simulation time 383307978 ps
CPU time 5.57 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:29 PM PDT 24
Peak memory 232452 kb
Host smart-c23f0703-96e0-40ee-bb60-7e737193fe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384383535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3384383535
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.545441428
Short name T209
Test name
Test status
Simulation time 4884387559 ps
CPU time 22.58 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:22 PM PDT 24
Peak memory 232460 kb
Host smart-f269fa55-4414-4930-9b0a-5c899ba5de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545441428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.545441428
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2263596008
Short name T219
Test name
Test status
Simulation time 12658927513 ps
CPU time 13.58 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 219508 kb
Host smart-15419656-18a4-4348-b794-3da9f6b97764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263596008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2263596008
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.126773807
Short name T33
Test name
Test status
Simulation time 47513419832 ps
CPU time 24.68 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:41 PM PDT 24
Peak memory 232468 kb
Host smart-d18ee620-bf97-4403-9521-4c025c3a3cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126773807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
126773807
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1198321859
Short name T843
Test name
Test status
Simulation time 311371863 ps
CPU time 4.36 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 232968 kb
Host smart-7504f214-a593-4113-821b-1a0588f7f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198321859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1198321859
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1291144325
Short name T344
Test name
Test status
Simulation time 5145027025 ps
CPU time 13.94 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:21 PM PDT 24
Peak memory 219788 kb
Host smart-02e06d6f-5377-4580-94a1-d7ccc1fcf167
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1291144325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1291144325
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2691595754
Short name T820
Test name
Test status
Simulation time 16734282 ps
CPU time 0.69 seconds
Started May 21 12:26:23 PM PDT 24
Finished May 21 12:27:12 PM PDT 24
Peak memory 205392 kb
Host smart-d0922324-c8ad-44ed-9114-cc015824ce22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691595754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2691595754
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1213667139
Short name T363
Test name
Test status
Simulation time 2278148509 ps
CPU time 6.94 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 215952 kb
Host smart-78d453f3-ce70-44ab-ace6-c1b1914bd770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213667139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1213667139
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2103339021
Short name T17
Test name
Test status
Simulation time 141537973 ps
CPU time 1.09 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:51 PM PDT 24
Peak memory 207688 kb
Host smart-8c067b72-1b76-47fd-b3c6-49c99589e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103339021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2103339021
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.765847307
Short name T459
Test name
Test status
Simulation time 560906669 ps
CPU time 0.83 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:51 PM PDT 24
Peak memory 205536 kb
Host smart-3c2fc38d-f14f-467a-8fe1-e1dea5e52956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765847307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.765847307
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3314647348
Short name T724
Test name
Test status
Simulation time 415442511 ps
CPU time 3.58 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 218500 kb
Host smart-1b763310-d530-4711-84f2-ac0db94dc76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314647348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3314647348
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2068170975
Short name T389
Test name
Test status
Simulation time 12453618 ps
CPU time 0.76 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:27:22 PM PDT 24
Peak memory 205472 kb
Host smart-88077b5b-5bd0-4d75-a9ca-314c0ff251dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068170975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
068170975
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4069719341
Short name T952
Test name
Test status
Simulation time 697179853 ps
CPU time 7.09 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 220644 kb
Host smart-806541ec-5bd8-4ef5-8f12-8e45d1cbf06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069719341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4069719341
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2834702156
Short name T548
Test name
Test status
Simulation time 23870631 ps
CPU time 0.77 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:51 PM PDT 24
Peak memory 206380 kb
Host smart-bd5ec4fe-ea2b-4ecb-9aed-539e564ef257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834702156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2834702156
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2455813082
Short name T826
Test name
Test status
Simulation time 11614205074 ps
CPU time 15.97 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 218932 kb
Host smart-4b1742dd-6a96-4cb2-b58e-72afeb7aa54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455813082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2455813082
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2729513182
Short name T859
Test name
Test status
Simulation time 120982275010 ps
CPU time 99.38 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:28:31 PM PDT 24
Peak memory 249016 kb
Host smart-b1bb181d-e857-47e5-88ff-cd75dd32b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729513182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2729513182
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2473542104
Short name T647
Test name
Test status
Simulation time 8589705643 ps
CPU time 52.7 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:28:00 PM PDT 24
Peak memory 233708 kb
Host smart-aff53c03-ebee-4f04-ab5e-5d1978dadf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473542104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2473542104
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1539264070
Short name T393
Test name
Test status
Simulation time 148979208 ps
CPU time 2.79 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:17 PM PDT 24
Peak memory 232316 kb
Host smart-c31f443a-01df-478c-9988-b05bf561a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539264070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1539264070
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.609563564
Short name T773
Test name
Test status
Simulation time 1683142619 ps
CPU time 10.41 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 218388 kb
Host smart-cdccf0fa-ee64-4adf-81e2-5a4f916cdfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609563564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.609563564
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1905004661
Short name T684
Test name
Test status
Simulation time 1754996185 ps
CPU time 10.05 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:34 PM PDT 24
Peak memory 236216 kb
Host smart-aa0255c4-7ef8-4c2c-9f9f-57bb672f9185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905004661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1905004661
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.724530633
Short name T535
Test name
Test status
Simulation time 22088863648 ps
CPU time 4.82 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:11 PM PDT 24
Peak memory 219380 kb
Host smart-b3300065-abed-4d0a-8109-95d85b37a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724530633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
724530633
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3414074728
Short name T543
Test name
Test status
Simulation time 1310672854 ps
CPU time 6.3 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:10 PM PDT 24
Peak memory 233452 kb
Host smart-68e01ba1-3d4f-4568-bdf8-b1d84d82b525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414074728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3414074728
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1727067749
Short name T431
Test name
Test status
Simulation time 4572098158 ps
CPU time 15.47 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:34 PM PDT 24
Peak memory 220036 kb
Host smart-ad97052e-bd5e-4839-b74b-ffe81b4e0e53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1727067749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1727067749
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.400901724
Short name T269
Test name
Test status
Simulation time 41442775150 ps
CPU time 329.65 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:32:52 PM PDT 24
Peak memory 255588 kb
Host smart-6b4373eb-e2c8-46f1-85fc-595d3576cb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400901724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.400901724
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3186334919
Short name T602
Test name
Test status
Simulation time 8149437127 ps
CPU time 38.4 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:45 PM PDT 24
Peak memory 216096 kb
Host smart-0386d26d-94dc-4350-b338-b2ac84c73084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186334919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3186334919
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4162949517
Short name T358
Test name
Test status
Simulation time 11406400752 ps
CPU time 17.7 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:36 PM PDT 24
Peak memory 215908 kb
Host smart-5d8d9a4b-69e8-4ede-a9ee-36f2538ada37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162949517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4162949517
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2952726838
Short name T320
Test name
Test status
Simulation time 153758633 ps
CPU time 1.75 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:18 PM PDT 24
Peak memory 216032 kb
Host smart-8da82556-c712-4b8a-b701-44f976001ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952726838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2952726838
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3501370444
Short name T505
Test name
Test status
Simulation time 22313991 ps
CPU time 0.72 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:26:53 PM PDT 24
Peak memory 205500 kb
Host smart-fb8a3804-bfe7-4a89-b104-17e6e91209c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501370444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3501370444
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2406970819
Short name T645
Test name
Test status
Simulation time 83338596 ps
CPU time 2.23 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:03 PM PDT 24
Peak memory 217040 kb
Host smart-a07952ae-fe9a-491e-8089-00b97738e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406970819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2406970819
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4218774556
Short name T786
Test name
Test status
Simulation time 35656480 ps
CPU time 0.68 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:00 PM PDT 24
Peak memory 205144 kb
Host smart-b54c1a94-6824-4d08-ad00-47a103ef9678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218774556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
218774556
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2442258577
Short name T885
Test name
Test status
Simulation time 202471206 ps
CPU time 3.84 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:10 PM PDT 24
Peak memory 218380 kb
Host smart-823b938b-c672-44e5-8f6a-ce5f19140ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442258577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2442258577
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.781489200
Short name T373
Test name
Test status
Simulation time 17357995 ps
CPU time 0.74 seconds
Started May 21 12:26:22 PM PDT 24
Finished May 21 12:27:14 PM PDT 24
Peak memory 206220 kb
Host smart-44a1f8c2-dd2d-467c-aac4-13ae81df0e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781489200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.781489200
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1891461361
Short name T715
Test name
Test status
Simulation time 54561881754 ps
CPU time 200.06 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 252668 kb
Host smart-e0c78aff-9766-4179-bd47-ad4c43556c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891461361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1891461361
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1171589873
Short name T828
Test name
Test status
Simulation time 13360913468 ps
CPU time 63.02 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 221820 kb
Host smart-a20b6a10-9714-43cd-823a-36762bd1c6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171589873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1171589873
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.478835849
Short name T311
Test name
Test status
Simulation time 7005139307 ps
CPU time 28.47 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:44 PM PDT 24
Peak memory 240452 kb
Host smart-0abd189f-feae-4309-9491-1e4e3f635b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478835849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.478835849
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2985257862
Short name T464
Test name
Test status
Simulation time 2055260500 ps
CPU time 4.47 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:14 PM PDT 24
Peak memory 218580 kb
Host smart-18316ada-c406-4c33-bc09-f3cebb00ec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985257862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2985257862
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2422752037
Short name T303
Test name
Test status
Simulation time 2051609898 ps
CPU time 11.45 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 218124 kb
Host smart-21397a55-01a4-46d3-8ddb-e4740dcb4164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422752037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2422752037
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3085388150
Short name T29
Test name
Test status
Simulation time 24251021294 ps
CPU time 7.31 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 224204 kb
Host smart-9b1ca9f7-a8aa-4f97-96e1-37816009cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085388150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3085388150
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.636725436
Short name T844
Test name
Test status
Simulation time 1412573452 ps
CPU time 4.99 seconds
Started May 21 12:26:30 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 218320 kb
Host smart-a2623d62-6988-4650-a3fd-cd86f3beab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636725436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.636725436
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.163337345
Short name T906
Test name
Test status
Simulation time 518942929 ps
CPU time 7.45 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 222592 kb
Host smart-993ee3bc-7e75-4516-9a0e-9b4710328565
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=163337345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.163337345
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1578728206
Short name T780
Test name
Test status
Simulation time 53287543 ps
CPU time 1 seconds
Started May 21 12:26:26 PM PDT 24
Finished May 21 12:27:19 PM PDT 24
Peak memory 206572 kb
Host smart-2ddb7168-2f6a-478f-8965-d01ed77573ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578728206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1578728206
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.605805675
Short name T713
Test name
Test status
Simulation time 15642909158 ps
CPU time 32.31 seconds
Started May 21 12:26:35 PM PDT 24
Finished May 21 12:28:05 PM PDT 24
Peak memory 216560 kb
Host smart-504dcbbd-5f3b-4196-b6b5-74f782c42ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605805675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.605805675
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3567491855
Short name T339
Test name
Test status
Simulation time 46766532 ps
CPU time 1.05 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:02 PM PDT 24
Peak memory 206640 kb
Host smart-08964261-6560-4d6d-90dd-08452c82f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567491855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3567491855
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3144348440
Short name T507
Test name
Test status
Simulation time 64557613 ps
CPU time 1.06 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 207420 kb
Host smart-ad10fdf1-e24d-43c8-a87c-58d9c642fc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144348440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3144348440
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1999327367
Short name T94
Test name
Test status
Simulation time 84227531 ps
CPU time 0.89 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 205564 kb
Host smart-344f06de-204e-480c-b313-4e6107cc35fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999327367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1999327367
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3218738928
Short name T830
Test name
Test status
Simulation time 4782023748 ps
CPU time 8.09 seconds
Started May 21 12:26:34 PM PDT 24
Finished May 21 12:27:39 PM PDT 24
Peak memory 234420 kb
Host smart-e00c5b1f-5713-41d8-8121-ea144d017ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218738928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3218738928
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3437446315
Short name T708
Test name
Test status
Simulation time 17245252 ps
CPU time 0.75 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:01 PM PDT 24
Peak memory 204508 kb
Host smart-98736ed1-1d32-486e-a738-eb2bd0557d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437446315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
437446315
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3388630323
Short name T614
Test name
Test status
Simulation time 6846506244 ps
CPU time 11.5 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:35 PM PDT 24
Peak memory 233596 kb
Host smart-32a4ab79-534b-4154-ba6c-61b0fd42054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388630323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3388630323
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.652973229
Short name T420
Test name
Test status
Simulation time 87771301 ps
CPU time 0.74 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:16 PM PDT 24
Peak memory 205748 kb
Host smart-49ef7c00-7b2e-4bba-b1ee-6b1ef389e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652973229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.652973229
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.213242411
Short name T480
Test name
Test status
Simulation time 20077426915 ps
CPU time 27.34 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 232724 kb
Host smart-d236527b-96d8-46bd-b7f8-c84ffcec45ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213242411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.213242411
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3877951584
Short name T382
Test name
Test status
Simulation time 51905138232 ps
CPU time 222.59 seconds
Started May 21 12:26:32 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 251256 kb
Host smart-ac95962c-98cb-48ee-a87d-7ec42d4ff03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877951584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3877951584
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2267932413
Short name T390
Test name
Test status
Simulation time 2122082370 ps
CPU time 8.08 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:27:30 PM PDT 24
Peak memory 232400 kb
Host smart-86c0f3d5-4eeb-4f18-94c8-84b683e94b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267932413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2267932413
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.806779523
Short name T441
Test name
Test status
Simulation time 999130422 ps
CPU time 11.19 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:27:27 PM PDT 24
Peak memory 218344 kb
Host smart-e1e2dac1-07f3-4e38-adea-9d8d3c2ed9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806779523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.806779523
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.439241935
Short name T475
Test name
Test status
Simulation time 61711830669 ps
CPU time 120.11 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:29:28 PM PDT 24
Peak memory 230284 kb
Host smart-f2391088-ff1d-4a41-a1f0-b8b593fbe2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439241935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.439241935
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1664513042
Short name T197
Test name
Test status
Simulation time 15445641195 ps
CPU time 11.41 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:17 PM PDT 24
Peak memory 233228 kb
Host smart-9f82aa2b-bc47-4863-88c5-3da96b5af6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664513042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1664513042
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1620533913
Short name T710
Test name
Test status
Simulation time 880815763 ps
CPU time 5.41 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:52 PM PDT 24
Peak memory 218484 kb
Host smart-523835e5-8ae9-47c6-84e4-bddcb3c54342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620533913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1620533913
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1682891181
Short name T490
Test name
Test status
Simulation time 10885171691 ps
CPU time 7.34 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:28 PM PDT 24
Peak memory 221340 kb
Host smart-1da82ee6-8a7d-40d7-ab6b-1105e6d4606e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1682891181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1682891181
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2247162349
Short name T211
Test name
Test status
Simulation time 91049981742 ps
CPU time 285.49 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:32:16 PM PDT 24
Peak memory 255016 kb
Host smart-0c1a3b29-8f63-4292-9e2e-97850f3362be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247162349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2247162349
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2566255336
Short name T673
Test name
Test status
Simulation time 12898942519 ps
CPU time 24.22 seconds
Started May 21 12:26:24 PM PDT 24
Finished May 21 12:27:39 PM PDT 24
Peak memory 215976 kb
Host smart-03940b51-a1de-48d3-b804-8ea70f7e1e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566255336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2566255336
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3007122515
Short name T790
Test name
Test status
Simulation time 1013572473 ps
CPU time 3.49 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:03 PM PDT 24
Peak memory 215928 kb
Host smart-51e5afd2-01a4-4b59-afd6-fc6faddc8d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007122515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3007122515
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3889066802
Short name T886
Test name
Test status
Simulation time 169213441 ps
CPU time 0.93 seconds
Started May 21 12:26:15 PM PDT 24
Finished May 21 12:26:58 PM PDT 24
Peak memory 206908 kb
Host smart-095d4b81-34d9-42c7-867e-9584c2f2720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889066802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3889066802
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1204450854
Short name T907
Test name
Test status
Simulation time 21592737 ps
CPU time 0.67 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:10 PM PDT 24
Peak memory 205336 kb
Host smart-58c345c8-6390-4a60-b97d-dee05914b252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204450854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1204450854
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.694151016
Short name T593
Test name
Test status
Simulation time 9534212406 ps
CPU time 11.15 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:17 PM PDT 24
Peak memory 240628 kb
Host smart-3e5c3ce0-8eef-48eb-b95d-c68404c51fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694151016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.694151016
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3338583545
Short name T848
Test name
Test status
Simulation time 39736731 ps
CPU time 0.69 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:27:27 PM PDT 24
Peak memory 204656 kb
Host smart-866bb42b-8852-42cf-9131-c8928041af05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338583545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
338583545
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2338214108
Short name T618
Test name
Test status
Simulation time 644503369 ps
CPU time 7.05 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:13 PM PDT 24
Peak memory 217388 kb
Host smart-872877ce-92bc-4d83-9860-f007f23d4fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338214108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2338214108
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1528441311
Short name T676
Test name
Test status
Simulation time 17864745 ps
CPU time 0.76 seconds
Started May 21 12:26:31 PM PDT 24
Finished May 21 12:27:27 PM PDT 24
Peak memory 206552 kb
Host smart-1ad2d202-6ea7-4a45-8424-9b207bd00235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528441311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1528441311
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2348643478
Short name T910
Test name
Test status
Simulation time 1511565891 ps
CPU time 28.97 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:32 PM PDT 24
Peak memory 239264 kb
Host smart-1830f0a5-7058-45fb-ae51-dba1d494748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348643478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2348643478
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2168763225
Short name T735
Test name
Test status
Simulation time 5512251721 ps
CPU time 8.73 seconds
Started May 21 12:26:29 PM PDT 24
Finished May 21 12:27:31 PM PDT 24
Peak memory 224264 kb
Host smart-3b0ab03c-14cb-453b-9e7e-f54dbdd23f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168763225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2168763225
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1829088136
Short name T759
Test name
Test status
Simulation time 69907293 ps
CPU time 3.68 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:09 PM PDT 24
Peak memory 233220 kb
Host smart-9bc0eac3-11e2-43a3-afe1-532792d4bc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829088136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1829088136
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4167068261
Short name T220
Test name
Test status
Simulation time 916728171 ps
CPU time 6.93 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:26 PM PDT 24
Peak memory 234176 kb
Host smart-7310458e-6cd2-4db1-9a4e-448ed84a7e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167068261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4167068261
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1313246979
Short name T288
Test name
Test status
Simulation time 51535147106 ps
CPU time 28.83 seconds
Started May 21 12:26:20 PM PDT 24
Finished May 21 12:27:36 PM PDT 24
Peak memory 235164 kb
Host smart-d08782c1-ecee-483c-b086-3d09e0c0f605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313246979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1313246979
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1784124094
Short name T600
Test name
Test status
Simulation time 8074060662 ps
CPU time 14.27 seconds
Started May 21 12:26:39 PM PDT 24
Finished May 21 12:27:51 PM PDT 24
Peak memory 232452 kb
Host smart-a70f182b-d032-4acd-842c-96543cf82ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784124094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1784124094
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1689570936
Short name T218
Test name
Test status
Simulation time 6581861568 ps
CPU time 4.54 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:27:26 PM PDT 24
Peak memory 233324 kb
Host smart-2840dc44-5a77-44a8-be32-0ef8ab345965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689570936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1689570936
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1676975510
Short name T357
Test name
Test status
Simulation time 2389181974 ps
CPU time 10.74 seconds
Started May 21 12:26:23 PM PDT 24
Finished May 21 12:27:23 PM PDT 24
Peak memory 219952 kb
Host smart-09f55cdf-b221-418a-b56b-c63844da6a9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1676975510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1676975510
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.922731800
Short name T234
Test name
Test status
Simulation time 92585585029 ps
CPU time 419.89 seconds
Started May 21 12:26:25 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 267404 kb
Host smart-2799f8d6-4004-42d7-9ee0-3526e0d24a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922731800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.922731800
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3704988073
Short name T678
Test name
Test status
Simulation time 1972360256 ps
CPU time 15.05 seconds
Started May 21 12:26:33 PM PDT 24
Finished May 21 12:27:46 PM PDT 24
Peak memory 216032 kb
Host smart-548aac68-6a95-4789-8ce6-517f42f8c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704988073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3704988073
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3460513290
Short name T413
Test name
Test status
Simulation time 29870958 ps
CPU time 0.69 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:00 PM PDT 24
Peak memory 205352 kb
Host smart-c56fa9ea-777d-49d6-9f93-14761accfcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460513290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3460513290
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2770705467
Short name T632
Test name
Test status
Simulation time 39517038 ps
CPU time 1.65 seconds
Started May 21 12:26:19 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 215864 kb
Host smart-a1b834c6-cc18-46ac-adf0-848770f66419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770705467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2770705467
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1697190289
Short name T815
Test name
Test status
Simulation time 77723683 ps
CPU time 0.75 seconds
Started May 21 12:26:28 PM PDT 24
Finished May 21 12:27:22 PM PDT 24
Peak memory 205484 kb
Host smart-c9a85feb-147c-48d1-8dca-dd3a2d954426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697190289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1697190289
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1868481233
Short name T811
Test name
Test status
Simulation time 51742055569 ps
CPU time 13.76 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:33 PM PDT 24
Peak memory 232436 kb
Host smart-7129aa32-e2cf-47fd-88e3-f4f4ef8f8467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868481233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1868481233
Directory /workspace/9.spi_device_upload/latest
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