Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2719529	1			T1	3		T2	1		T3	263
all_values[1]	2719529	1			T1	3		T2	1		T3	263
all_values[2]	2719529	1			T1	3		T2	1		T3	263
all_values[3]	2719529	1			T1	3		T2	1		T3	263
all_values[4]	2719529	1			T1	3		T2	1		T3	263
all_values[5]	2719529	1			T1	3		T2	1		T3	263
all_values[6]	2719529	1			T1	3		T2	1		T3	263
all_values[7]	2719529	1			T1	3		T2	1		T3	263

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21062980

1

T1

24

T2

8

T3

2104

auto[1]

693252

1

T36

40064

T69

72

T73

6734

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21732639

1

T1

24

T2

8

T3

2104

auto[1]

23593

1

T11

201

T17

2

T20

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2589687	1			T1	3		T2	1		T3	263
all_values[0]	auto[0]	auto[1]	11718	1			T11	131		T27	53		T29	174
all_values[0]	auto[1]	auto[0]	117479	1			T36	9909		T69	7		T73	1344
all_values[0]	auto[1]	auto[1]	645	1			T36	97		T69	5		T73	1
all_values[1]	auto[0]	auto[0]	2651250	1			T1	3		T2	1		T3	263
all_values[1]	auto[0]	auto[1]	6230	1			T11	36		T27	52		T29	138
all_values[1]	auto[1]	auto[0]	61677	1			T36	7		T69	6		T73	1339
all_values[1]	auto[1]	auto[1]	372	1			T36	5		T69	3		T73	2
all_values[2]	auto[0]	auto[0]	2666474	1			T1	3		T2	1		T3	263
all_values[2]	auto[0]	auto[1]	2212	1			T11	34		T29	40		T36	48
all_values[2]	auto[1]	auto[0]	50519	1			T36	6		T69	6		T73	1340
all_values[2]	auto[1]	auto[1]	324	1			T36	2		T69	2		T73	3
all_values[3]	auto[0]	auto[0]	2665219	1			T1	3		T2	1		T3	263
all_values[3]	auto[0]	auto[1]	178	1			T36	4		T47	4		T69	1
all_values[3]	auto[1]	auto[0]	53932	1			T36	4		T69	4		T73	7
all_values[3]	auto[1]	auto[1]	200	1			T36	5		T69	3		T73	4
all_values[4]	auto[0]	auto[0]	2622563	1			T1	3		T2	1		T3	263
all_values[4]	auto[0]	auto[1]	191	1			T36	5		T69	3		T73	5
all_values[4]	auto[1]	auto[0]	96589	1			T36	10003		T69	6		T73	1337
all_values[4]	auto[1]	auto[1]	186	1			T36	6		T69	3		T73	2
all_values[5]	auto[0]	auto[0]	2608398	1			T1	3		T2	1		T3	263
all_values[5]	auto[0]	auto[1]	351	1			T17	2		T20	13		T26	9
all_values[5]	auto[1]	auto[0]	110583	1			T36	10001		T69	9		T73	4
all_values[5]	auto[1]	auto[1]	197	1			T36	4		T69	3		T73	2
all_values[6]	auto[0]	auto[0]	2605218	1			T1	3		T2	1		T3	263
all_values[6]	auto[0]	auto[1]	198	1			T36	10		T69	1		T73	4
all_values[6]	auto[1]	auto[0]	113923	1			T36	10000		T69	9		T73	1340
all_values[6]	auto[1]	auto[1]	190	1			T36	5		T69	2		T73	3
all_values[7]	auto[0]	auto[0]	2632883	1			T1	3		T2	1		T3	263
all_values[7]	auto[0]	auto[1]	210	1			T36	7		T69	3		T73	4
all_values[7]	auto[1]	auto[0]	86245	1			T36	5		T69	2		T73	2
all_values[7]	auto[1]	auto[1]	191	1			T36	5		T69	2		T73	4