Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29937	1			T3	4		T4	8		T11	52
auto[SpiFlashAddrCfg]	6394	1			T2	2		T4	2		T11	20
auto[SpiFlashAddr3b]	7766	1			T1	1		T2	2		T3	4
auto[SpiFlashAddr4b]	6603	1			T1	2		T4	8		T11	16

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29252

1

T1

3

T2

4

T3

8

auto[1]

21448

1

T4

20

T11

34

T30

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27298

1

T2

4

T3

6

T4

6

auto[1]

23402

1

T1

3

T3

2

T4

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34019	1			T1	2		T3	6		T4	10
values[1]	934	1			T4	2		T30	2		T25	2
values[2]	1237	1			T11	2		T25	1		T27	2
values[3]	1171	1			T4	2		T11	4		T16	6
values[4]	1209	1			T11	4		T51	1		T25	8
values[5]	1248	1			T11	5		T15	1		T30	3
values[6]	1258	1			T11	3		T14	4		T30	3
values[7]	1254	1			T11	6		T16	2		T25	4
values[8]	8370	1			T1	1		T2	4		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22320

1

T2

4

T3

8

T4

20

auto[1]

28380

1

T1

3

T11

111

T15

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48668

1

T1

3

T2

4

T3

8

write

2032

1

T11

9

T16

2

T30

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16740

1

T1

1

T2

4

T3

2

valids[0x1]

33960

1

T1

2

T3

6

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1415	1			T11	4		T14	2		T25	4
internal_process_ops[0x5a]	1396	1			T11	3		T30	2		T25	7
internal_process_ops[0x05]	17873	1			T3	4		T11	15		T16	77
internal_process_ops[0x35]	1365	1			T4	4		T11	5		T13	2
internal_process_ops[0x15]	1326	1			T4	4		T11	3		T13	2
internal_process_ops[0x03]	835	1			T11	1		T30	2		T25	2
internal_process_ops[0x0b]	813	1			T1	2		T11	1		T30	3
internal_process_ops[0x3b]	798	1			T2	2		T11	3		T14	4
internal_process_ops[0x6b]	788	1			T14	2		T51	1		T27	4
internal_process_ops[0xbb]	864	1			T4	2		T30	4		T25	1
internal_process_ops[0xeb]	839	1			T1	1		T2	2		T3	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49718

1

T1

3

T2

4

T3

8

auto[1]

982

1

T11

4

T25

5

T27

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48849

1

T1

3

T2

4

T3

8

auto[1]

1851

1

T11

8

T16

2

T25

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7781

1

T3

4

T13

4

T14

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4063

1

T4

8

T27

24

T29

22

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1570

1

T2

2

T16

6

T30

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1427

1

T4

2

T30

7

T27

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1938

1

T2

2

T3

4

T14

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1594

1

T4

2

T30

3

T27

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1639

1

T13

2

T14

2

T16

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1443

1

T4

8

T30

11

T27

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

57

1

T29

1

T31

1

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

51

1

T27

1

T36

1

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

53

1

T32

1

T158

1

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

47

1

T33

2

T39

1

T34

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

50

1

T16

2

T32

1

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T27

1

T36

1

T33

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

45

1

T30

1

T27

3

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

54

1

T34

3

T159

1

T160

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

62

1

T37

2

T39

1

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

50

1

T27

2

T31

2

T39

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

47

1

T29

1

T32

1

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

52

1

T29

5

T31

1

T41

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T29

2

T31

2

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

46

1

T32

2

T38

2

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

65

1

T29

3

T32

1

T31

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

46

1

T31

1

T150

1

T40

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10440

1

T11

36

T25

144

T43

36

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7166

1

T11

12

T25

23

T43

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1458

1

T11

9

T15

1

T25

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1473

1

T11

10

T25

14

T43

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1876

1

T1

1

T11

16

T51

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1863

1

T11

3

T25

11

T43

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1518

1

T1

2

T11

11

T25

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1419

1

T11

5

T25

13

T43

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

74

1

T11

2

T65

3

T80

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

51

1

T11

1

T65

1

T82

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

84

1

T11

1

T50

2

T161

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T43

1

T65

1

T82

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

73

1

T102

1

T80

1

T50

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T82

5

T102

1

T80

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T11

1

T43

2

T65

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

53

1

T25

1

T82

1

T50

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

43

1

T11

1

T80

1

T39

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T11

1

T82

1

T102

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

72

1

T50

6

T161

4

T42

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

74

1

T11

2

T80

1

T50

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

71

1

T25

1

T65

1

T50

8

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

99

1

T25

3

T65

2

T50

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

93

1

T65

1

T50

5

T162

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

74

1

T25

1

T43

1

T65

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3145	1			T30	3		T35	2		T27	16
auto[0]	values[0]	valids[0x1]	10830	1			T3	6		T4	10		T13	4
auto[0]	values[1]	valids[0x1]	441	1			T4	2		T30	2		T27	4
auto[0]	values[2]	valids[0x0]	371	1			T27	1		T29	5		T36	6
auto[0]	values[2]	valids[0x1]	240	1			T27	1		T29	6		T36	1
auto[0]	values[3]	valids[0x0]	363	1			T29	5		T36	3		T37	2
auto[0]	values[3]	valids[0x1]	257	1			T4	2		T16	6		T27	2
auto[0]	values[4]	valids[0x0]	397	1			T27	5		T29	3		T36	8
auto[0]	values[4]	valids[0x1]	210	1			T27	3		T29	2		T32	2
auto[0]	values[5]	valids[0x0]	408	1			T30	2		T87	8		T27	4
auto[0]	values[5]	valids[0x1]	259	1			T30	1		T27	2		T29	4
auto[0]	values[6]	valids[0x0]	404	1			T14	4		T30	3		T27	3
auto[0]	values[6]	valids[0x1]	221	1			T27	4		T29	2		T36	6
auto[0]	values[7]	valids[0x0]	403	1			T16	2		T27	3		T29	2
auto[0]	values[7]	valids[0x1]	214	1			T29	1		T36	2		T31	4
auto[0]	values[8]	valids[0x0]	2600	1			T2	4		T3	2		T4	6
auto[0]	values[8]	valids[0x1]	1557	1			T16	4		T30	7		T27	10
auto[1]	values[0]	valids[0x0]	4094	1			T11	21		T25	38		T43	23
auto[1]	values[0]	valids[0x1]	15950	1			T1	2		T11	48		T25	152
auto[1]	values[1]	valids[0x1]	493	1			T25	2		T65	2		T82	6
auto[1]	values[2]	valids[0x0]	367	1			T43	2		T65	1		T82	3
auto[1]	values[2]	valids[0x1]	259	1			T11	2		T25	1		T65	4
auto[1]	values[3]	valids[0x0]	326	1			T11	1		T25	1		T43	1
auto[1]	values[3]	valids[0x1]	225	1			T11	3		T43	3		T82	5
auto[1]	values[4]	valids[0x0]	375	1			T11	4		T51	1		T25	5
auto[1]	values[4]	valids[0x1]	227	1			T25	3		T43	2		T65	4
auto[1]	values[5]	valids[0x0]	337	1			T11	2		T15	1		T43	1
auto[1]	values[5]	valids[0x1]	244	1			T11	3		T25	3		T43	2
auto[1]	values[6]	valids[0x0]	360	1			T11	3		T25	1		T43	1
auto[1]	values[6]	valids[0x1]	273	1			T82	1		T102	3		T80	3
auto[1]	values[7]	valids[0x0]	363	1			T11	3		T25	1		T43	3
auto[1]	values[7]	valids[0x1]	274	1			T11	3		T25	3		T65	5
auto[1]	values[8]	valids[0x0]	2427	1			T1	1		T11	9		T25	20
auto[1]	values[8]	valids[0x1]	1786	1			T11	9		T25	17		T43	8