Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2797043

1

T1

8595

T2

1898

T3

1247

auto[1]

16444

1

T11

11

T16

75

T25

107

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859472

1

T1

8595

T2

1898

T3

1

auto[1]

1954015

1

T3

1246

T11

3687

T14

436

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	561804	1			T1	5811		T2	955		T3	1247
auto[524288:1048575]	327046	1			T2	114		T11	1		T14	483
auto[1048576:1572863]	319321	1			T1	488		T2	800		T11	486
auto[1572864:2097151]	348622	1			T1	2		T11	1042		T30	258
auto[2097152:2621439]	332954	1			T1	1		T11	523		T14	494
auto[2621440:3145727]	280862	1			T1	2292		T2	2		T11	513
auto[3145728:3670015]	313899	1			T14	144		T87	3		T25	257
auto[3670016:4194303]	328979	1			T1	1		T2	27		T14	512

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1973020

1

T1

65

T2

8

T3

1247

auto[1]

840467

1

T1

8530

T2

1890

T14

3412

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2463751

1

T1

8595

T2

1898

T3

1247

auto[1]

349736

1

T11

2

T30

3

T25

2969

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	187343	1			T1	5811		T2	955		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	316152	1			T3	1246		T11	1145		T14	216
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	113019	1			T2	114		T11	1		T14	482
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	181024	1			T14	1		T100	1516		T25	1395
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	80792	1			T1	488		T2	800		T11	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	192412	1			T11	485		T14	218		T99	171
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	94150	1			T1	2		T11	9		T30	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	208916	1			T11	1028		T30	256		T100	257
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	93594	1			T1	1		T11	7		T14	494
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	198699	1			T11	514		T30	2982		T100	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	89015	1			T1	2292		T2	2		T11	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	150778	1			T11	512		T14	1		T99	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	85974	1			T14	144		T87	3		T25	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	168936	1			T25	256		T27	128		T29	769
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	107928	1			T1	1		T2	27		T14	512
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	181419	1			T99	1		T25	1366		T27	385
auto[0]	auto[1]	auto[0:524287]	auto[0]	1556	1			T65	3		T82	2		T158	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	54063	1			T25	384		T65	2		T82	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	652	1			T25	1		T27	8		T36	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	30619	1			T32	3		T82	109		T50	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1059	1			T32	3		T31	5		T65	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	43000	1			T25	2583		T32	259		T31	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	261	1			T11	2		T27	2		T29	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43221	1			T29	1		T31	257		T65	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	469	1			T30	3		T27	1		T29	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	38128	1			T27	2378		T29	1		T31	3222
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	422	1			T25	1		T27	1		T43	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	38616	1			T36	129		T65	133		T158	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	508	1			T27	1		T29	1		T43	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56345	1			T27	256		T29	3		T31	129
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	879	1			T32	1		T31	1		T82	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	37094	1			T31	256		T82	936		T102	257
auto[1]	auto[0]	auto[0:524287]	auto[0]	257	1			T11	3		T16	2		T31	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2078	1			T11	3		T16	73		T31	31
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	193	1			T25	4		T43	1		T36	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1266	1			T25	69		T43	1		T32	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	191	1			T25	2		T32	2		T31	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1466	1			T25	17		T32	1		T31	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	186	1			T11	3		T27	1		T29	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1475	1			T29	3		T36	2		T31	10
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	200	1			T11	2		T27	2		T29	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1498	1			T27	14		T29	1		T36	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	159	1			T25	3		T27	2		T29	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1431	1			T25	12		T27	1		T29	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	179	1			T29	1		T36	3		T32	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1646	1			T29	1		T36	11		T82	52
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	152	1			T65	2		T82	2		T33	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1223	1			T65	6		T82	6		T33	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	38	1			T65	2		T82	1		T80	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	317	1			T65	3		T82	35		T40	10
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	36	1			T178	1		T161	1		T42	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	237	1			T178	31		T161	1		T160	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	51	1			T31	2		T80	2		T207	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	350	1			T31	4		T80	4		T207	12
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	46	1			T29	1		T31	1		T80	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	367	1			T29	6		T31	15		T80	15
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	46	1			T29	1		T31	1		T80	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	320	1			T29	1		T31	1		T80	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	40	1			T36	1		T158	1		T162	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	401	1			T36	5		T162	1		T39	12
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T31	1		T102	1		T50	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	267	1			T31	8		T102	5		T197	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	33	1			T102	1		T80	1		T162	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	251	1			T102	12		T80	5		T39	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1613256	1			T1	65		T2	8		T3	1247
auto[0]	auto[0]	auto[1]	836895	1			T1	8530		T2	1890		T14	3412
auto[0]	auto[1]	auto[0]	343676	1			T11	2		T30	3		T25	2969
auto[0]	auto[1]	auto[1]	3216	1			T31	1		T102	1		T89	15
auto[1]	auto[0]	auto[0]	13305	1			T11	11		T16	75		T25	105
auto[1]	auto[0]	auto[1]	295	1			T25	2		T31	5		T82	3
auto[1]	auto[1]	auto[0]	2783	1			T29	9		T36	6		T31	30
auto[1]	auto[1]	auto[1]	61	1			T31	3		T80	1		T178	1