Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13384

1

T2

4

T3

8

T13

6

auto[1]

8936

1

T4

20

T30

22

T27

62

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2762	1			T2	4		T30	20		T87	8
values[1]	2485	1			T27	20		T36	70		T32	42
values[2]	2740	1			T4	20		T13	6		T27	21
values[3]	2425	1			T100	6		T27	42		T29	73
values[4]	3206	1			T99	6		T27	20		T29	22
values[5]	3161	1			T14	10		T35	2		T31	93
values[6]	2978	1			T16	91		T30	20		T27	37
values[7]	2563	1			T3	8		T29	20		T36	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3215	1			T14	10		T100	6		T27	22
values[1]	2446	1			T29	72		T36	20		T32	22
values[2]	2777	1			T36	20		T32	20		T189	24
values[3]	2866	1			T13	6		T16	91		T30	20
values[4]	2786	1			T3	8		T30	20		T99	6
values[5]	2715	1			T2	4		T29	27		T36	69
values[6]	2513	1			T4	20		T35	2		T29	22
values[7]	3002	1			T87	8		T27	37		T36	53

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	293	1			T36	8		T188	12		T83	41
auto[0]	values[0]	values[1]	140	1			T29	17		T36	12		T38	11
auto[0]	values[0]	values[2]	143	1			T42	17		T160	8		T203	18
auto[0]	values[0]	values[3]	96	1			T32	13		T186	12		T232	4
auto[0]	values[0]	values[4]	403	1			T30	8		T41	14		T83	14
auto[0]	values[0]	values[5]	148	1			T2	4		T32	13		T176	4
auto[0]	values[0]	values[6]	218	1			T38	11		T34	7		T42	11
auto[0]	values[0]	values[7]	193	1			T87	8		T36	28		T150	15
auto[0]	values[1]	values[0]	162	1			T36	9		T32	13		T204	11
auto[0]	values[1]	values[1]	135	1			T34	10		T41	7		T160	12
auto[0]	values[1]	values[2]	166	1			T233	13		T133	11		T195	15
auto[0]	values[1]	values[3]	148	1			T27	13		T36	9		T33	30
auto[0]	values[1]	values[4]	190	1			T160	17		T204	10		T192	13
auto[0]	values[1]	values[5]	233	1			T36	15		T32	13		T31	14
auto[0]	values[1]	values[6]	170	1			T234	4		T160	12		T204	11
auto[0]	values[1]	values[7]	190	1			T31	13		T41	13		T159	36
auto[0]	values[2]	values[0]	214	1			T39	11		T41	9		T159	27
auto[0]	values[2]	values[1]	199	1			T156	6		T42	11		T159	16
auto[0]	values[2]	values[2]	180	1			T34	21		T235	20		T159	12
auto[0]	values[2]	values[3]	246	1			T13	6		T27	11		T159	12
auto[0]	values[2]	values[4]	246	1			T39	21		T150	12		T34	15
auto[0]	values[2]	values[5]	185	1			T31	12		T40	13		T188	11
auto[0]	values[2]	values[6]	194	1			T89	10		T33	14		T174	14
auto[0]	values[2]	values[7]	181	1			T37	14		T32	8		T196	11
auto[0]	values[3]	values[0]	169	1			T100	6		T27	15		T29	14
auto[0]	values[3]	values[1]	159	1			T29	13		T227	22		T134	17
auto[0]	values[3]	values[2]	184	1			T39	21		T41	8		T159	55
auto[0]	values[3]	values[3]	197	1			T33	10		T236	11		T133	13
auto[0]	values[3]	values[4]	274	1			T27	11		T29	10		T49	4
auto[0]	values[3]	values[5]	237	1			T225	22		T40	18		T132	12
auto[0]	values[3]	values[6]	153	1			T31	15		T223	14		T160	9
auto[0]	values[3]	values[7]	122	1			T31	18		T34	53		T217	18
auto[0]	values[4]	values[0]	313	1			T41	11		T207	32		T151	29
auto[0]	values[4]	values[1]	117	1			T40	6		T159	9		T233	10
auto[0]	values[4]	values[2]	135	1			T160	15		T179	20		T152	9
auto[0]	values[4]	values[3]	265	1			T27	14		T224	8		T159	17
auto[0]	values[4]	values[4]	222	1			T99	6		T237	4		T238	8
auto[0]	values[4]	values[5]	181	1			T36	27		T39	14		T159	8
auto[0]	values[4]	values[6]	115	1			T29	13		T151	9		T239	4
auto[0]	values[4]	values[7]	300	1			T207	9		T240	12		T151	11
auto[0]	values[5]	values[0]	266	1			T14	10		T31	16		T241	14
auto[0]	values[5]	values[1]	220	1			T31	42		T34	15		T83	5
auto[0]	values[5]	values[2]	338	1			T189	24		T187	11		T83	65
auto[0]	values[5]	values[3]	226	1			T172	10		T210	16		T160	8
auto[0]	values[5]	values[4]	121	1			T33	15		T40	10		T83	6
auto[0]	values[5]	values[5]	182	1			T33	12		T38	18		T83	15
auto[0]	values[5]	values[6]	241	1			T35	2		T31	12		T128	4
auto[0]	values[5]	values[7]	369	1			T40	72		T133	28		T152	13
auto[0]	values[6]	values[0]	270	1			T33	23		T150	6		T34	10
auto[0]	values[6]	values[1]	203	1			T42	12		T207	20		T204	16
auto[0]	values[6]	values[2]	448	1			T32	15		T40	12		T83	136
auto[0]	values[6]	values[3]	307	1			T16	91		T30	10		T34	30
auto[0]	values[6]	values[4]	223	1			T204	13		T233	11		T151	11
auto[0]	values[6]	values[5]	140	1			T29	23		T32	8		T34	12
auto[0]	values[6]	values[6]	103	1			T33	8		T242	12		T92	12
auto[0]	values[6]	values[7]	213	1			T27	14		T158	17		T196	11
auto[0]	values[7]	values[0]	425	1			T159	8		T233	35		T243	21
auto[0]	values[7]	values[1]	224	1			T29	10		T32	9		T31	21
auto[0]	values[7]	values[2]	142	1			T36	12		T160	13		T132	12
auto[0]	values[7]	values[3]	115	1			T244	2		T151	14		T195	7
auto[0]	values[7]	values[4]	144	1			T3	8		T160	8		T245	2
auto[0]	values[7]	values[5]	145	1			T246	12		T39	16		T159	12
auto[0]	values[7]	values[6]	286	1			T31	34		T38	13		T34	26
auto[0]	values[7]	values[7]	217	1			T192	11		T205	43		T247	12
auto[1]	values[0]	values[0]	150	1			T36	12		T188	8		T83	10
auto[1]	values[0]	values[1]	74	1			T29	7		T36	8		T38	14
auto[1]	values[0]	values[2]	90	1			T42	8		T160	12		T203	2
auto[1]	values[0]	values[3]	201	1			T32	8		T83	30		T151	13
auto[1]	values[0]	values[4]	153	1			T30	12		T41	6		T83	6
auto[1]	values[0]	values[5]	124	1			T32	9		T33	3		T248	6
auto[1]	values[0]	values[6]	164	1			T38	9		T34	13		T42	9
auto[1]	values[0]	values[7]	172	1			T36	25		T150	5		T159	11
auto[1]	values[1]	values[0]	141	1			T36	15		T32	9		T204	9
auto[1]	values[1]	values[1]	182	1			T34	10		T41	61		T160	9
auto[1]	values[1]	values[2]	161	1			T233	15		T133	45		T195	12
auto[1]	values[1]	values[3]	130	1			T27	7		T36	11		T101	18
auto[1]	values[1]	values[4]	134	1			T160	9		T204	15		T192	7
auto[1]	values[1]	values[5]	102	1			T36	11		T32	7		T31	18
auto[1]	values[1]	values[6]	116	1			T160	10		T204	9		T151	8
auto[1]	values[1]	values[7]	125	1			T31	7		T41	17		T159	23
auto[1]	values[2]	values[0]	134	1			T39	11		T41	11		T159	11
auto[1]	values[2]	values[1]	108	1			T42	16		T159	4		T233	6
auto[1]	values[2]	values[2]	105	1			T34	5		T159	8		T194	19
auto[1]	values[2]	values[3]	132	1			T27	10		T159	8		T187	3
auto[1]	values[2]	values[4]	111	1			T39	8		T150	8		T34	36
auto[1]	values[2]	values[5]	101	1			T31	8		T40	7		T188	13
auto[1]	values[2]	values[6]	263	1			T4	20		T33	35		T200	8
auto[1]	values[2]	values[7]	141	1			T48	4		T32	15		T196	9
auto[1]	values[3]	values[0]	85	1			T27	7		T29	11		T32	13
auto[1]	values[3]	values[1]	130	1			T29	15		T227	1		T134	3
auto[1]	values[3]	values[2]	96	1			T39	20		T41	18		T159	13
auto[1]	values[3]	values[3]	241	1			T33	10		T236	14		T133	18
auto[1]	values[3]	values[4]	96	1			T27	9		T29	10		T40	7
auto[1]	values[3]	values[5]	151	1			T40	13		T132	8		T133	9
auto[1]	values[3]	values[6]	77	1			T31	5		T160	13		T188	8
auto[1]	values[3]	values[7]	54	1			T31	4		T34	6		T217	7
auto[1]	values[4]	values[0]	248	1			T41	30		T207	33		T151	21
auto[1]	values[4]	values[1]	175	1			T40	32		T159	11		T233	10
auto[1]	values[4]	values[2]	130	1			T160	8		T179	22		T152	11
auto[1]	values[4]	values[3]	186	1			T27	6		T159	11		T187	8
auto[1]	values[4]	values[4]	109	1			T39	7		T42	21		T160	23
auto[1]	values[4]	values[5]	338	1			T36	16		T39	6		T159	47
auto[1]	values[4]	values[6]	87	1			T29	9		T151	12		T192	14
auto[1]	values[4]	values[7]	285	1			T207	36		T240	8		T151	11
auto[1]	values[5]	values[0]	145	1			T31	4		T160	11		T83	5
auto[1]	values[5]	values[1]	117	1			T31	11		T34	5		T83	15
auto[1]	values[5]	values[2]	216	1			T187	11		T83	12		T236	10
auto[1]	values[5]	values[3]	99	1			T160	13		T179	22		T249	11
auto[1]	values[5]	values[4]	131	1			T33	16		T40	10		T83	14
auto[1]	values[5]	values[5]	181	1			T33	12		T38	6		T83	76
auto[1]	values[5]	values[6]	118	1			T31	8		T160	18		T133	7
auto[1]	values[5]	values[7]	191	1			T40	13		T133	19		T152	11
auto[1]	values[6]	values[0]	70	1			T33	3		T150	14		T34	11
auto[1]	values[6]	values[1]	183	1			T180	4		T42	8		T207	3
auto[1]	values[6]	values[2]	128	1			T32	5		T40	8		T83	11
auto[1]	values[6]	values[3]	204	1			T30	10		T34	20		T160	10
auto[1]	values[6]	values[4]	125	1			T204	8		T233	56		T151	10
auto[1]	values[6]	values[5]	149	1			T29	4		T32	12		T34	8
auto[1]	values[6]	values[6]	78	1			T33	18		T250	18		T251	10
auto[1]	values[6]	values[7]	134	1			T27	23		T158	4		T196	9
auto[1]	values[7]	values[0]	130	1			T159	12		T252	20		T233	4
auto[1]	values[7]	values[1]	80	1			T29	10		T32	13		T31	7
auto[1]	values[7]	values[2]	115	1			T36	8		T160	13		T132	13
auto[1]	values[7]	values[3]	73	1			T151	11		T195	13		T203	8
auto[1]	values[7]	values[4]	104	1			T160	14		T194	10		T56	10
auto[1]	values[7]	values[5]	118	1			T39	7		T159	18		T217	21
auto[1]	values[7]	values[6]	130	1			T31	12		T38	7		T253	4
auto[1]	values[7]	values[7]	115	1			T192	9		T205	22		T247	8