Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	301	1			T14	4		T27	2		T29	4
auto[ReadAddrCrossIntoMailbox]	223	1			T30	2		T27	1		T29	3
auto[ReadAddrCrossOutOfMailbox]	261	1			T30	5		T27	4		T29	2
auto[ReadAddrCrossAllMailbox]	180	1			T30	2		T27	6		T29	7
auto[ReadAddrOutsideMailbox]	2536	1			T2	4		T3	2		T4	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1779

1

T2

2

T3

1

T4

1

auto[1]

1722

1

T2

2

T3

1

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	577	1			T30	2		T27	6		T29	5
read_ops[0x0b]	580	1			T30	3		T27	5		T29	5
read_ops[0x3b]	580	1			T2	2		T14	4		T30	1
read_ops[0x6b]	574	1			T27	4		T29	5		T36	9
read_ops[0xbb]	616	1			T4	2		T30	4		T27	6
read_ops[0xeb]	574	1			T2	2		T3	2		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T34	1		T204	2		T192	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T29	1		T32	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T30	1		T32	2		T41	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T36	1		T150	2		T160	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T30	1		T29	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T39	2		T34	1		T133	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T27	2		T34	1		T160	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T31	1		T187	1		T83	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T27	2		T29	2		T36	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	185	1			T27	2		T29	1		T36	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T254	1		T160	1		T188	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T29	1		T31	1		T254	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T30	1		T33	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T31	1		T150	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T30	1		T32	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T29	1		T36	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T38	1		T160	1		T132	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T150	1		T187	1		T160	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	236	1			T30	1		T27	4		T29	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	182	1			T27	1		T29	1		T36	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T14	2		T128	1		T233	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T14	2		T36	1		T31	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T39	1		T34	1		T187	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T36	1		T159	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T31	1		T187	1		T83	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T30	1		T27	2		T39	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T29	3		T34	2		T207	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T27	1		T36	1		T159	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	192	1			T2	1		T27	2		T29	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	219	1			T2	1		T29	1		T36	7
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	15	1			T27	2		T36	1		T236	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T159	1		T160	1		T83	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T32	1		T151	1		T203	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T159	2		T83	1		T151	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T36	1		T207	2		T236	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T159	1		T188	1		T204	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T29	2		T31	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T38	1		T188	1		T233	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	204	1			T29	1		T36	6		T49	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	218	1			T27	2		T29	2		T36	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T29	1		T224	1		T172	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T38	1		T224	1		T172	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T27	1		T29	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T29	1		T34	1		T160	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T27	1		T33	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T30	1		T27	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T29	1		T83	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T30	2		T27	1		T29	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	220	1			T4	1		T27	2		T29	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	229	1			T4	1		T30	1		T36	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T172	1		T34	1		T41	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T29	1		T172	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T33	1		T159	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T29	1		T31	1		T34	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T30	1		T36	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T38	1		T34	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T36	1		T32	1		T33	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T27	2		T224	1		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	215	1			T2	1		T3	1		T13	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	204	1			T2	1		T3	1		T13	1