Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2719529	1			T1	3		T2	1		T3	263
all_pins[1]	2719529	1			T1	3		T2	1		T3	263
all_pins[2]	2719529	1			T1	3		T2	1		T3	263
all_pins[3]	2719529	1			T1	3		T2	1		T3	263
all_pins[4]	2719529	1			T1	3		T2	1		T3	263
all_pins[5]	2719529	1			T1	3		T2	1		T3	263
all_pins[6]	2719529	1			T1	3		T2	1		T3	263
all_pins[7]	2719529	1			T1	3		T2	1		T3	263

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21638800	1			T1	24		T2	8		T3	2104
values[0x1]	117432	1			T36	10555		T69	23		T73	1344
transitions[0x0=>0x1]	115284	1			T36	10116		T69	17		T73	1340
transitions[0x1=>0x0]	115293	1			T36	10117		T69	17		T73	1341

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2718828	1			T1	3		T2	1		T3	263
all_pins[0]	values[0x1]	701	1			T36	104		T69	5		T73	1
all_pins[0]	transitions[0x0=>0x1]	629	1			T36	104		T69	4		T73	1
all_pins[0]	transitions[0x1=>0x0]	321	1			T36	5		T69	2		T73	2
all_pins[1]	values[0x0]	2719136	1			T1	3		T2	1		T3	263
all_pins[1]	values[0x1]	393	1			T36	5		T69	3		T73	2
all_pins[1]	transitions[0x0=>0x1]	209	1			T36	3		T69	2		T73	2
all_pins[1]	transitions[0x1=>0x0]	147	1			T69	1		T73	3		T39	2
all_pins[2]	values[0x0]	2719198	1			T1	3		T2	1		T3	263
all_pins[2]	values[0x1]	331	1			T36	2		T69	2		T73	3
all_pins[2]	transitions[0x0=>0x1]	280	1			T36	1		T69	1		T73	2
all_pins[2]	transitions[0x1=>0x0]	149	1			T36	4		T69	2		T73	3
all_pins[3]	values[0x0]	2719329	1			T1	3		T2	1		T3	263
all_pins[3]	values[0x1]	200	1			T36	5		T69	3		T73	4
all_pins[3]	transitions[0x0=>0x1]	150	1			T36	3		T69	2		T73	3
all_pins[3]	transitions[0x1=>0x0]	136	1			T36	4		T69	2		T73	1
all_pins[4]	values[0x0]	2719343	1			T1	3		T2	1		T3	263
all_pins[4]	values[0x1]	186	1			T36	6		T69	3		T73	2
all_pins[4]	transitions[0x0=>0x1]	141	1			T36	3		T69	2		T73	2
all_pins[4]	transitions[0x1=>0x0]	1782	1			T36	431		T69	2		T73	2
all_pins[5]	values[0x0]	2717702	1			T1	3		T2	1		T3	263
all_pins[5]	values[0x1]	1827	1			T36	434		T69	3		T73	2
all_pins[5]	transitions[0x0=>0x1]	163	1			T36	4		T69	3		T73	2
all_pins[5]	transitions[0x1=>0x0]	111939	1			T36	9564		T69	2		T73	1326
all_pins[6]	values[0x0]	2605926	1			T1	3		T2	1		T3	263
all_pins[6]	values[0x1]	113603	1			T36	9994		T69	2		T73	1326
all_pins[6]	transitions[0x0=>0x1]	113559	1			T36	9994		T69	2		T73	1325
all_pins[6]	transitions[0x1=>0x0]	147	1			T36	5		T69	2		T73	3
all_pins[7]	values[0x0]	2719338	1			T1	3		T2	1		T3	263
all_pins[7]	values[0x1]	191	1			T36	5		T69	2		T73	4
all_pins[7]	transitions[0x0=>0x1]	153	1			T36	4		T69	1		T73	3
all_pins[7]	transitions[0x1=>0x0]	672	1			T36	104		T69	4		T73	1