Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2851	1			T36	70		T37	14		T31	22
values[1]	2557	1			T4	20		T30	20		T36	31
values[2]	2325	1			T99	6		T27	20		T29	28
values[3]	2743	1			T2	4		T14	10		T30	20
values[4]	2817	1			T13	6		T27	59		T36	20
values[5]	3120	1			T16	91		T29	49		T36	40
values[6]	3025	1			T3	8		T36	20		T32	21
values[7]	2882	1			T87	8		T100	6		T27	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2985	1			T27	41		T36	24		T32	62
values[1]	2677	1			T4	20		T35	2		T27	57
values[2]	3292	1			T2	4		T31	163		T101	18
values[3]	2753	1			T30	20		T29	24		T36	23
values[4]	2587	1			T30	20		T36	42		T37	14
values[5]	2734	1			T13	6		T14	10		T16	91
values[6]	2738	1			T87	8		T100	6		T27	20
values[7]	2554	1			T3	8		T99	6		T27	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21924

1

T2

4

T3

8

T4

20

auto[1]

396

1

T27

4

T29

5

T36

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	330	1			T36	24		T210	16		T83	18
auto[0]	values[0]	values[1]	213	1			T41	41		T204	25		T236	20
auto[0]	values[0]	values[2]	346	1			T31	22		T39	20		T160	23
auto[0]	values[0]	values[3]	235	1			T255	6		T200	20		T160	22
auto[0]	values[0]	values[4]	213	1			T37	14		T33	31		T160	18
auto[0]	values[0]	values[5]	347	1			T36	45		T172	10		T182	50
auto[0]	values[0]	values[6]	661	1			T224	8		T40	30		T159	46
auto[0]	values[0]	values[7]	461	1			T252	18		T93	20		T152	36
auto[0]	values[1]	values[0]	408	1			T34	20		T159	20		T236	104
auto[0]	values[1]	values[1]	296	1			T4	20		T32	20		T176	4
auto[0]	values[1]	values[2]	285	1			T31	20		T101	18		T158	21
auto[0]	values[1]	values[3]	362	1			T30	20		T32	20		T89	10
auto[0]	values[1]	values[4]	292	1			T33	20		T196	20		T159	28
auto[0]	values[1]	values[5]	269	1			T36	31		T33	20		T187	20
auto[0]	values[1]	values[6]	170	1			T254	2		T40	20		T205	20
auto[0]	values[1]	values[7]	426	1			T42	24		T159	68		T187	19
auto[0]	values[2]	values[0]	447	1			T27	20		T42	23		T159	37
auto[0]	values[2]	values[1]	177	1			T29	28		T240	17		T256	4
auto[0]	values[2]	values[2]	339	1			T31	38		T40	152		T242	12
auto[0]	values[2]	values[3]	219	1			T34	21		T160	20		T232	4
auto[0]	values[2]	values[4]	319	1			T257	12		T258	44		T209	45
auto[0]	values[2]	values[5]	263	1			T237	4		T40	19		T177	14
auto[0]	values[2]	values[6]	260	1			T48	4		T33	25		T253	4
auto[0]	values[2]	values[7]	247	1			T99	6		T38	22		T40	34
auto[0]	values[3]	values[0]	265	1			T27	21		T192	20		T259	2
auto[0]	values[3]	values[1]	543	1			T35	2		T29	17		T159	20
auto[0]	values[3]	values[2]	258	1			T2	4		T39	20		T40	20
auto[0]	values[3]	values[3]	354	1			T38	20		T90	14		T83	76
auto[0]	values[3]	values[4]	391	1			T30	20		T248	6		T217	19
auto[0]	values[3]	values[5]	401	1			T14	10		T33	20		T34	25
auto[0]	values[3]	values[6]	305	1			T27	20		T29	22		T31	20
auto[0]	values[3]	values[7]	183	1			T39	29		T41	20		T205	20
auto[0]	values[4]	values[0]	438	1			T32	40		T34	51		T41	26
auto[0]	values[4]	values[1]	368	1			T27	37		T160	25		T204	20
auto[0]	values[4]	values[2]	355	1			T207	20		T83	50		T233	31
auto[0]	values[4]	values[3]	300	1			T31	20		T241	14		T187	19
auto[0]	values[4]	values[4]	328	1			T150	19		T83	64		T244	2
auto[0]	values[4]	values[5]	287	1			T13	6		T235	20		T159	55
auto[0]	values[4]	values[6]	446	1			T36	20		T49	4		T42	20
auto[0]	values[4]	values[7]	242	1			T27	19		T83	20		T205	20
auto[0]	values[5]	values[0]	425	1			T32	20		T39	22		T34	20
auto[0]	values[5]	values[1]	212	1			T36	20		T31	32		T38	20
auto[0]	values[5]	values[2]	670	1			T34	40		T160	20		T233	43
auto[0]	values[5]	values[3]	267	1			T29	22		T32	23		T246	12
auto[0]	values[5]	values[4]	425	1			T187	20		T204	19		T192	22
auto[0]	values[5]	values[5]	446	1			T16	91		T29	25		T150	40
auto[0]	values[5]	values[6]	193	1			T36	20		T34	20		T133	20
auto[0]	values[5]	values[7]	419	1			T33	25		T34	20		T188	20
auto[0]	values[6]	values[0]	391	1			T33	36		T174	14		T34	20
auto[0]	values[6]	values[1]	292	1			T38	25		T233	20		T133	19
auto[0]	values[6]	values[2]	668	1			T260	63		T192	20		T205	20
auto[0]	values[6]	values[3]	496	1			T32	21		T189	24		T133	33
auto[0]	values[6]	values[4]	223	1			T36	19		T31	46		T159	21
auto[0]	values[6]	values[5]	270	1			T34	29		T203	20		T173	23
auto[0]	values[6]	values[6]	368	1			T39	21		T188	20		T83	77
auto[0]	values[6]	values[7]	268	1			T3	8		T39	20		T180	4
auto[0]	values[7]	values[0]	238	1			T42	24		T159	19		T188	20
auto[0]	values[7]	values[1]	525	1			T27	19		T29	27		T39	19
auto[0]	values[7]	values[2]	317	1			T31	79		T134	67		T203	36
auto[0]	values[7]	values[3]	479	1			T36	23		T32	22		T33	49
auto[0]	values[7]	values[4]	341	1			T36	22		T156	6		T238	8
auto[0]	values[7]	values[5]	409	1			T32	22		T188	20		T192	83
auto[0]	values[7]	values[6]	285	1			T87	8		T100	6		T29	20
auto[0]	values[7]	values[7]	248	1			T128	4		T34	75		T188	21
auto[1]	values[0]	values[0]	4	1			T83	2		T134	1		T261	1
auto[1]	values[0]	values[1]	1	1			T151	1		-	-		-	-
auto[1]	values[0]	values[2]	7	1			T152	4		T201	2		T222	1
auto[1]	values[0]	values[3]	4	1			T160	1		T56	3		-	-
auto[1]	values[0]	values[4]	4	1			T160	2		T199	2		-	-
auto[1]	values[0]	values[5]	6	1			T36	1		T160	1		T262	2
auto[1]	values[0]	values[6]	9	1			T40	1		T159	1		T207	1
auto[1]	values[0]	values[7]	10	1			T252	2		T217	2		T243	3
auto[1]	values[1]	values[0]	3	1			T201	2		T263	1		-	-
auto[1]	values[1]	values[1]	5	1			T160	1		T227	4		-	-
auto[1]	values[1]	values[2]	4	1			T207	1		T264	2		T139	1
auto[1]	values[1]	values[3]	8	1			T41	2		T201	1		T139	3
auto[1]	values[1]	values[4]	16	1			T33	4		T227	1		T134	1
auto[1]	values[1]	values[5]	2	1			T187	1		T183	1		-	-
auto[1]	values[1]	values[6]	4	1			T265	2		T24	2		-	-
auto[1]	values[1]	values[7]	7	1			T187	1		T160	1		T194	3
auto[1]	values[2]	values[0]	18	1			T42	4		T159	1		T188	1
auto[1]	values[2]	values[1]	5	1			T240	3		T203	1		T266	1
auto[1]	values[2]	values[2]	6	1			T31	2		T40	1		T192	3
auto[1]	values[2]	values[3]	1	1			T233	1		-	-		-	-
auto[1]	values[2]	values[4]	7	1			T209	1		T173	2		T222	1
auto[1]	values[2]	values[5]	3	1			T40	1		T139	1		T267	1
auto[1]	values[2]	values[6]	9	1			T33	1		T264	4		T261	4
auto[1]	values[2]	values[7]	5	1			T38	2		T40	3		-	-
auto[1]	values[3]	values[0]	3	1			T243	2		T199	1		-	-
auto[1]	values[3]	values[1]	8	1			T29	3		T222	1		T267	1
auto[1]	values[3]	values[2]	7	1			T39	2		T268	2		T269	3
auto[1]	values[3]	values[3]	1	1			T83	1		-	-		-	-
auto[1]	values[3]	values[4]	7	1			T217	1		T209	1		T154	4
auto[1]	values[3]	values[5]	8	1			T34	1		T192	3		T261	2
auto[1]	values[3]	values[6]	2	1			T270	2		-	-		-	-
auto[1]	values[3]	values[7]	7	1			T205	3		T247	2		T271	2
auto[1]	values[4]	values[0]	8	1			T32	2		T83	2		T205	1
auto[1]	values[4]	values[1]	8	1			T160	1		T133	4		T272	2
auto[1]	values[4]	values[2]	5	1			T83	1		T63	3		T154	1
auto[1]	values[4]	values[3]	5	1			T187	1		T160	1		T236	2
auto[1]	values[4]	values[4]	3	1			T150	1		T201	1		T273	1
auto[1]	values[4]	values[5]	9	1			T154	1		T274	1		T275	6
auto[1]	values[4]	values[6]	6	1			T205	1		T203	1		T221	4
auto[1]	values[4]	values[7]	9	1			T27	3		T209	4		T56	2
auto[1]	values[5]	values[0]	1	1			T39	1		-	-		-	-
auto[1]	values[5]	values[1]	9	1			T134	3		T249	2		T194	2
auto[1]	values[5]	values[2]	11	1			T160	2		T133	1		T205	2
auto[1]	values[5]	values[3]	6	1			T29	2		T152	2		T201	2
auto[1]	values[5]	values[4]	13	1			T187	2		T204	1		T203	1
auto[1]	values[5]	values[5]	8	1			T159	2		T276	1		T277	2
auto[1]	values[5]	values[6]	8	1			T195	1		T203	3		T135	1
auto[1]	values[5]	values[7]	7	1			T33	1		T133	1		T63	1
auto[1]	values[6]	values[0]	2	1			T179	1		T54	1		-	-
auto[1]	values[6]	values[1]	8	1			T133	1		T183	1		T135	2
auto[1]	values[6]	values[2]	8	1			T227	2		T278	1		T154	1
auto[1]	values[6]	values[3]	13	1			T152	2		T217	4		T261	1
auto[1]	values[6]	values[4]	2	1			T36	1		T139	1		-	-
auto[1]	values[6]	values[5]	3	1			T34	1		T173	1		T222	1
auto[1]	values[6]	values[6]	2	1			T83	1		T209	1		-	-
auto[1]	values[6]	values[7]	11	1			T160	2		T203	3		T218	2
auto[1]	values[7]	values[0]	4	1			T42	1		T159	1		T222	1
auto[1]	values[7]	values[1]	7	1			T27	1		T39	1		T34	2
auto[1]	values[7]	values[2]	6	1			T31	2		T134	1		T201	3
auto[1]	values[7]	values[3]	3	1			T159	1		T160	1		T192	1
auto[1]	values[7]	values[4]	3	1			T41	2		T204	1		-	-
auto[1]	values[7]	values[5]	3	1			T192	2		T201	1		-	-
auto[1]	values[7]	values[6]	10	1			T152	4		T154	2		T279	2
auto[1]	values[7]	values[7]	4	1			T34	4		-	-		-	-