Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1776

1

T7

5

T8

2

T9

13

auto[1]

1884

1

T7

2

T8

1

T9

23

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2050

1

T10

11

T11

24

T18

8

auto[1]

1610

1

T7

7

T8

3

T9

36

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2877

1

T7

7

T8

3

T9

36

auto[1]

783

1

T10

2

T11

4

T18

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	728	1			T8	1		T9	4		T10	2
valid[1]	714	1			T8	1		T9	6		T10	4
valid[2]	750	1			T7	2		T9	5		T10	5
valid[3]	730	1			T7	3		T8	1		T9	8
valid[4]	738	1			T7	2		T9	13		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	130	1			T11	3		T36	1		T32	1
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T9	2		T88	3		T44	1
auto[0]	auto[0]	valid[1]	auto[0]	105	1			T11	2		T29	1		T32	1
auto[0]	auto[0]	valid[1]	auto[1]	154	1			T8	1		T9	1		T10	1
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T10	1		T11	1		T21	1
auto[0]	auto[0]	valid[2]	auto[1]	144	1			T7	1		T9	1		T10	1
auto[0]	auto[0]	valid[3]	auto[0]	124	1			T11	3		T18	3		T32	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T7	3		T8	1		T9	3
auto[0]	auto[0]	valid[4]	auto[0]	133	1			T10	1		T11	2		T44	1
auto[0]	auto[0]	valid[4]	auto[1]	145	1			T7	1		T9	6		T88	4
auto[0]	auto[1]	valid[0]	auto[0]	141	1			T10	2		T11	1		T27	1
auto[0]	auto[1]	valid[0]	auto[1]	144	1			T8	1		T9	2		T18	1
auto[0]	auto[1]	valid[1]	auto[0]	114	1			T10	1		T11	2		T18	1
auto[0]	auto[1]	valid[1]	auto[1]	182	1			T9	5		T10	1		T88	6
auto[0]	auto[1]	valid[2]	auto[0]	138	1			T10	2		T11	3		T18	1
auto[0]	auto[1]	valid[2]	auto[1]	175	1			T7	1		T9	4		T10	1
auto[0]	auto[1]	valid[3]	auto[0]	123	1			T10	2		T43	1		T289	1
auto[0]	auto[1]	valid[3]	auto[1]	176	1			T9	5		T88	5		T46	3
auto[0]	auto[1]	valid[4]	auto[0]	132	1			T11	3		T27	2		T44	1
auto[0]	auto[1]	valid[4]	auto[1]	176	1			T7	1		T9	7		T10	1
auto[1]	auto[0]	valid[0]	auto[0]	89	1			T18	1		T36	1		T32	1
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T11	1		T44	1		T36	1
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T18	1		T29	1		T44	1
auto[1]	auto[0]	valid[3]	auto[0]	67	1			T10	1		T27	1		T44	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T11	1		T65	1		T73	1
auto[1]	auto[1]	valid[0]	auto[0]	70	1			T11	1		T18	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T10	1		T44	2		T32	2
auto[1]	auto[1]	valid[2]	auto[0]	82	1			T11	1		T27	2		T29	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T44	1		T32	1		T38	1
auto[1]	auto[1]	valid[4]	auto[0]	76	1			T29	1		T43	1		T44	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal