Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51010

1

T10

342

T11

461

T17

6

auto[1]

16365

1

T7

7

T8

3

T9

403

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49017

1

T7

7

T8

3

T9

403

auto[1]

18358

1

T10

140

T11

160

T17

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34577	1			T7	7		T8	3		T9	196
others[1]	5790	1			T9	42		T10	45		T11	35
others[2]	5691	1			T9	38		T10	30		T11	38
others[3]	6423	1			T9	36		T10	26		T11	43
interest[1]	3693	1			T9	19		T10	32		T11	24
interest[4]	22730	1			T7	7		T8	3		T9	133
interest[64]	11201	1			T9	72		T10	79		T11	75

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16588	1			T10	90		T11	160		T17	2
auto[0]	auto[0]	others[1]	2840	1			T10	27		T11	25		T17	1
auto[0]	auto[0]	others[2]	2815	1			T10	17		T11	22		T18	12
auto[0]	auto[0]	others[3]	3118	1			T10	15		T11	28		T18	8
auto[0]	auto[0]	interest[1]	1788	1			T10	17		T11	16		T18	10
auto[0]	auto[0]	interest[4]	10849	1			T10	58		T11	103		T17	2
auto[0]	auto[0]	interest[64]	5503	1			T10	36		T11	50		T17	2
auto[0]	auto[1]	others[0]	8642	1			T7	7		T8	3		T9	196
auto[0]	auto[1]	others[1]	1380	1			T9	42		T10	6		T18	4
auto[0]	auto[1]	others[2]	1322	1			T9	38		T10	5		T18	1
auto[0]	auto[1]	others[3]	1536	1			T9	36		T10	1		T18	7
auto[0]	auto[1]	interest[1]	831	1			T9	19		T10	3		T18	4
auto[0]	auto[1]	interest[4]	5749	1			T7	7		T8	3		T9	133
auto[0]	auto[1]	interest[64]	2654	1			T9	72		T10	11		T18	5
auto[1]	auto[0]	others[0]	9347	1			T10	66		T11	86		T17	1
auto[1]	auto[0]	others[1]	1570	1			T10	12		T11	10		T18	10
auto[1]	auto[0]	others[2]	1554	1			T10	8		T11	16		T18	3
auto[1]	auto[0]	others[3]	1769	1			T10	10		T11	15		T18	5
auto[1]	auto[0]	interest[1]	1074	1			T10	12		T11	8		T18	3
auto[1]	auto[0]	interest[4]	6132	1			T10	47		T11	60		T17	1
auto[1]	auto[0]	interest[64]	3044	1			T10	32		T11	25		T18	9

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal