Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	820	1			T36	17		T69	11		T73	14
all_values[1]	820	1			T36	17		T69	11		T73	14
all_values[2]	820	1			T36	17		T69	11		T73	14
all_values[3]	820	1			T36	17		T69	11		T73	14
all_values[4]	820	1			T36	17		T69	11		T73	14
all_values[5]	820	1			T36	17		T69	11		T73	14
all_values[6]	820	1			T36	17		T69	11		T73	14
all_values[7]	820	1			T36	17		T69	11		T73	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3395

1

T36

75

T69

43

T73

57

auto[1]

3165

1

T36

61

T69

45

T73

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2631

1

T36

45

T69

38

T73

53

auto[1]

3929

1

T36

91

T69

50

T73

59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3720

1

T36

70

T69

54

T73

68

auto[1]

2840

1

T36

66

T69

34

T73

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	148	1			T36	1		T73	1		T157	6
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T36	3		T69	1		T73	2
all_values[0]	auto[0]	auto[1]	auto[0]	150	1			T36	4		T69	1		T73	6
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T36	2		T69	2		T50	2
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T36	5		T69	3		T73	1
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T36	2		T69	4		T73	4
all_values[1]	auto[0]	auto[0]	auto[0]	167	1			T36	2		T69	1		T73	11
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T69	1		T157	2		T50	1
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T36	6		T69	3		T73	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T36	2		T69	2		T73	1
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T36	5		T69	2		T157	3
all_values[1]	auto[1]	auto[1]	auto[1]	163	1			T36	2		T69	2		T73	1
all_values[2]	auto[0]	auto[0]	auto[0]	143	1			T36	3		T69	1		T73	2
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T36	3		T69	1		T73	2
all_values[2]	auto[0]	auto[1]	auto[0]	172	1			T36	3		T69	4		T73	5
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T69	2		T73	1		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T36	6		T69	2		T73	3
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T36	2		T69	1		T73	1
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T36	3		T69	5		T157	4
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T36	2		T73	1		T157	1
all_values[3]	auto[0]	auto[1]	auto[0]	172	1			T36	2		T69	2		T73	5
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T73	1		T39	3		T42	1
all_values[3]	auto[1]	auto[0]	auto[1]	165	1			T36	3		T69	1		T73	5
all_values[3]	auto[1]	auto[1]	auto[1]	182	1			T36	7		T69	3		T73	2
all_values[4]	auto[0]	auto[0]	auto[0]	184	1			T69	2		T73	3		T157	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T36	2		T69	2		T73	2
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T36	5		T69	1		T73	3
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T36	1		T69	1		T157	1
all_values[4]	auto[1]	auto[0]	auto[1]	182	1			T36	5		T69	2		T73	3
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T36	4		T69	3		T73	3
all_values[5]	auto[0]	auto[0]	auto[0]	240	1			T36	7		T69	3		T73	4
all_values[5]	auto[0]	auto[1]	auto[0]	208	1			T36	3		T69	4		T73	3
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T36	5		T69	2		T73	4
all_values[5]	auto[1]	auto[1]	auto[1]	189	1			T36	2		T69	2		T73	3
all_values[6]	auto[0]	auto[0]	auto[0]	178	1			T36	2		T69	1		T157	3
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T36	3		T73	2		T157	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T69	5		T73	4		T157	3
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T36	2		T69	1		T73	1
all_values[6]	auto[1]	auto[0]	auto[1]	191	1			T36	9		T69	3		T73	5
all_values[6]	auto[1]	auto[1]	auto[1]	166	1			T36	1		T69	1		T73	2
all_values[7]	auto[0]	auto[0]	auto[0]	142	1			T36	1		T69	5		T73	2
all_values[7]	auto[0]	auto[0]	auto[1]	93	1			T36	3		T69	2		T73	1
all_values[7]	auto[0]	auto[1]	auto[0]	160	1			T36	3		T73	3		T157	2
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T36	2		T69	1		T73	1
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T36	2		T69	3		T73	3
all_values[7]	auto[1]	auto[1]	auto[1]	154	1			T36	6		T73	4		T157	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal