Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2532744	1			T1	3465		T2	1		T3	1
all_values[1]	2532744	1			T1	3465		T2	1		T3	1
all_values[2]	2532744	1			T1	3465		T2	1		T3	1
all_values[3]	2532744	1			T1	3465		T2	1		T3	1
all_values[4]	2532744	1			T1	3465		T2	1		T3	1
all_values[5]	2532744	1			T1	3465		T2	1		T3	1
all_values[6]	2532744	1			T1	3465		T2	1		T3	1
all_values[7]	2532744	1			T1	3465		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19928955

1

T1

27720

T2

8

T3

8

auto[1]

332997

1

T17

31177

T41

27

T60

139

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20241072

1

T1

27720

T2

8

T3

8

auto[1]

20880

1

T9

62

T12

110

T14

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2469788	1			T1	3465		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10792	1			T9	24		T12	77		T17	3
all_values[0]	auto[1]	auto[0]	51687	1			T17	6192		T41	1		T60	16
all_values[0]	auto[1]	auto[1]	477	1			T17	39		T41	3		T60	5
all_values[1]	auto[0]	auto[0]	2481774	1			T1	3465		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5040	1			T9	24		T12	33		T17	41
all_values[1]	auto[1]	auto[0]	45556	1			T17	6		T41	1		T60	6
all_values[1]	auto[1]	auto[1]	374	1			T17	7		T41	2		T60	7
all_values[2]	auto[0]	auto[0]	2469168	1			T1	3465		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	1948	1			T9	14		T17	6		T23	17
all_values[2]	auto[1]	auto[0]	61321	1			T17	6220		T41	1		T60	11
all_values[2]	auto[1]	auto[1]	307	1			T17	8		T60	8		T77	1
all_values[3]	auto[0]	auto[0]	2514635	1			T1	3465		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	169	1			T17	3		T41	5		T142	3
all_values[3]	auto[1]	auto[0]	17759	1			T17	5		T41	3		T60	11
all_values[3]	auto[1]	auto[1]	181	1			T17	4		T60	9		T77	2
all_values[4]	auto[0]	auto[0]	2520662	1			T1	3465		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	190	1			T17	7		T41	5		T60	6
all_values[4]	auto[1]	auto[0]	11699	1			T17	7		T60	7		T77	2
all_values[4]	auto[1]	auto[1]	193	1			T17	4		T41	2		T60	3
all_values[5]	auto[0]	auto[0]	2480248	1			T1	3465		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	320	1			T14	1		T15	6		T16	1
all_values[5]	auto[1]	auto[0]	52018	1			T17	6224		T41	3		T60	14
all_values[5]	auto[1]	auto[1]	158	1			T17	1		T41	3		T60	5
all_values[6]	auto[0]	auto[0]	2508399	1			T1	3465		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	176	1			T17	4		T41	1		T60	5
all_values[6]	auto[1]	auto[0]	23993	1			T17	6226		T41	4		T60	7
all_values[6]	auto[1]	auto[1]	176	1			T17	5		T60	14		T155	2
all_values[7]	auto[0]	auto[0]	2465468	1			T1	3465		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	178	1			T17	4		T41	2		T60	7
all_values[7]	auto[1]	auto[0]	66897	1			T17	6220		T60	11		T77	2
all_values[7]	auto[1]	auto[1]	201	1			T17	9		T41	4		T60	5