---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.InterceptLevel_M	0	0	125384149	0	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckAckNeedsReq	0	0	125383265	0	0	0
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckHoldReq	0	0	372648194	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	125383265	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	125383265	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	125383265	0	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	125383265	0	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataHoldSrc2Dst	0	0	372648194	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	372648194	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	372648194	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	372648194	0	0	0
tb.dut.u_tlul2sram_egress.rvalidHighReqFifoEmpty	0	0	372648194	0	0	0
tb.dut.u_tlul2sram_egress.rvalidHighWhenRspFifoFull	0	0	372648194	0	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.DataKnown_A	0	0	372648194	0	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	0	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DataKnown_A	0	0	372648194	0	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	125383265	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	125383265	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	125383265	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	125383265	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A	0	0	125383265	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	125383265	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	372648194	372565523	0	0
tb.dut.CioSdoEnOKnown	0	0	372648194	372565523	0	0
tb.dut.CioSdoEnOffWhenInactive	0	0	372648194	372565523	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	372648194	100	0	0
tb.dut.IntrReadbufFlipOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrReadbufWatermarkOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrTpmHeaderNotEmptyOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrTpmRdfifoCmdEndOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrTpmRdfifoDropOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrUploadCmdfifoNotEmptyOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrUploadPayloadNotEmptyOKnown	0	0	372648194	372565523	0	0
tb.dut.IntrUploadPayloadOverflowOKnown	0	0	372648194	372565523	0	0
tb.dut.PayloadStartIdxWidthMatch_A	0	0	905	905	0	0
tb.dut.SpiModeKnown_A	0	0	372648194	372565523	0	0
tb.dut.TpmEnableWhenTpmCsbIdle_M	0	0	372648194	344	0	0
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A	0	0	372648194	1557504	0	0
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A	0	0	372648194	146842	0	0
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A	0	0	372648194	1668	0	0
tb.dut.g_sram_connect[3].ReqAlwaysAccepted_A	0	0	372648194	1277	0	0
tb.dut.g_sram_connect[4].ReqAlwaysAccepted_A	0	0	372648194	192758	0	0
tb.dut.scanmodeKnown	0	0	372648194	372648194	0	0
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A	0	0	374978110	4154	0	0
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A	0	0	374978110	3435	0	0
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A	0	0	374978110	3546	0	0
tb.dut.spi_device_csr_assert.cfg_rd_A	0	0	374978110	3685	0	0
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A	0	0	374978110	7600	0	0
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A	0	0	374978110	8518	0	0
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A	0	0	374978110	7108	0	0
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A	0	0	374978110	8601	0	0
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A	0	0	374978110	8202	0	0
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A	0	0	374978110	8156	0	0
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A	0	0	374978110	7074	0	0
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A	0	0	374978110	7643	0	0
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A	0	0	374978110	4730	0	0
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A	0	0	374978110	5205	0	0
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A	0	0	374978110	4685	0	0
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A	0	0	374978110	5155	0	0
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A	0	0	374978110	5204	0	0
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A	0	0	374978110	5410	0	0
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A	0	0	374978110	5398	0	0
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A	0	0	374978110	5210	0	0
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A	0	0	374978110	5062	0	0
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A	0	0	374978110	4946	0	0
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A	0	0	374978110	5201	0	0
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A	0	0	374978110	5302	0	0
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A	0	0	374978110	4870	0	0
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A	0	0	374978110	5064	0	0
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A	0	0	374978110	5248	0	0
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A	0	0	374978110	5143	0	0
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A	0	0	374978110	5254	0	0
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A	0	0	374978110	5002	0	0
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A	0	0	374978110	5074	0	0
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A	0	0	374978110	5236	0	0
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A	0	0	374978110	4764	0	0
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A	0	0	374978110	5219	0	0
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A	0	0	374978110	5023	0	0
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A	0	0	374978110	5067	0	0
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A	0	0	374978110	3487	0	0
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A	0	0	374978110	3520	0	0
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A	0	0	374978110	3564	0	0
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A	0	0	374978110	3474	0	0
tb.dut.spi_device_csr_assert.intercept_en_rd_A	0	0	374978110	3850	0	0
tb.dut.spi_device_csr_assert.intr_enable_rd_A	0	0	374978110	4973	0	0
tb.dut.spi_device_csr_assert.jedec_cc_rd_A	0	0	374978110	3384	0	0
tb.dut.spi_device_csr_assert.jedec_id_rd_A	0	0	374978110	3537	0	0
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A	0	0	374978110	3450	0	0
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A	0	0	374978110	3258	0	0
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A	0	0	374978110	3296	0	0
tb.dut.spi_device_csr_assert.read_threshold_rd_A	0	0	374978110	3316	0	0
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A	0	0	374978110	3686	0	0
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A	0	0	374978110	3490	0	0
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A	0	0	374978110	3824	0	0
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A	0	0	374978110	3353	0	0
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A	0	0	374978110	3401	0	0
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A	0	0	374978110	3317	0	0
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A	0	0	374978110	3300	0	0
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A	0	0	374978110	3406	0	0
tb.dut.spi_device_csr_assert.tpm_rid_rd_A	0	0	374978110	3485	0	0
tb.dut.spi_device_csr_assert.tpm_sts_rd_A	0	0	374978110	3280	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	374978110	8568483	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	374978110	374854043	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	374978110	15162218	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	374978110	374854043	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1080	1080	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	374978785	4207753	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	374978110	7720	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	374978785	6138925	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	374978785	8560774	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	374978110	6305	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	374978785	8568483	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	374978785	15162218	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	374978785	8568483	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	374978785	15162218	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	374978785	15162218	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	374978785	15162218	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	374978110	6085	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	374978110	6284	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1080	1080	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0	0	0	50936	50031	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0	0	0	125384149	125383244	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1	0	0	125383265	125382509	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0	0	0	125383265	125382509	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	125384149	125383244	0	0
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_cmdparse.OnlyOneDatapath_A	0	0	125383265	49126	0	0
tb.dut.u_cmdparse.SelDpKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_cmdparse.StKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	50031	49404	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A	0	0	372648194	341	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M	0	0	125383265	341	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A	0	0	372648194	193	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M	0	0	125383265	193	0	0
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_payload_not_empty.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_payload_overflow.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_readbuf_flip.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_readbuf_watermark.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_tpm_rdfifo_cmd_end.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_intr_tpm_rdfifo_drop.IntrTKind_A	0	0	905	905	0	0
tb.dut.u_jedec.JedecStKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_p2s.IoModeChangeValid_A	0	0	125384149	5915	0	0
tb.dut.u_p2s.IoModeDefault_A	0	0	125384149	19308	0	0
tb.dut.u_passthrough.PassThroughStKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_passthrough.PayloadSwapConstraint_M	0	0	125383265	1008368	0	0
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A	0	0	125383265	3622801	0	0
tb.dut.u_readcmd.MailboxSizeMatch_M	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.ValidCmdConfig_A	0	0	125383265	167496	0	0
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A	0	0	125383265	6336	0	0
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M	0	0	125383265	55435	0	0
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A	0	0	125383265	3622801	0	0
tb.dut.u_readcmd.u_readsram.NotOverflow_A	0	0	125383265	913570	0	0
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M	0	0	125383265	6336	0	0
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M	0	0	125383265	913185	0	0
tb.dut.u_readcmd.u_readsram.SramReadOnly_A	0	0	125383265	913570	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A	0	0	125383265	18349437	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	125383265	18349437	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A	0	0	125383265	17454875	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	125383265	17454875	0	0
tb.dut.u_reg.en2addrHit	0	0	374978110	5453186	0	0
tb.dut.u_reg.reAfterRv	0	0	374978110	5453186	0	0
tb.dut.u_reg.rePulse	0	0	374978110	3880602	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1080	1080	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1080	1080	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1080	1080	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1080	1080	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1080	1080	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1080	1080	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1080	1080	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	374978110	8568483	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	374978110	15162218	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	374978110	2367254	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	374978110	2642150	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	374978110	157677	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	374978110	350887	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	374978110	5892296	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	374978110	12169181	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	374978110	374854043	0	0
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1080	1080	0	0
tb.dut.u_reg.u_socket.maxN	0	0	1080	1080	0	0
tb.dut.u_reg.wePulse	0	0	374978110	1572584	0	0
tb.dut.u_s2p.IoModeDefault_A	0	0	125383265	19308	0	0
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	905	905	0	0
tb.dut.u_scanmode_sync.OutputsKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	372648194	372565523	0	0
tb.dut.u_spi_tpm.CmdAddrAvailable_A	0	0	125383265	49778	0	0
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A	0	0	125383265	518600	0	0
tb.dut.u_spi_tpm.CmdAddrInfo_A	0	0	125383265	51578	0	0
tb.dut.u_spi_tpm.CmdPowerof2_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.DataFifoLessThan64_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.DataSelKnown_A	0	0	125384149	29178333	0	0
tb.dut.u_spi_tpm.HwRegCondition2_a	0	0	125383265	9341	0	0
tb.dut.u_spi_tpm.HwRegCondition_A	0	0	125383265	64825	0	0
tb.dut.u_spi_tpm.HwRegIdxKnown_A	0	0	125384149	29178333	0	0
tb.dut.u_spi_tpm.LocalityLatchCondition_A	0	0	125383265	64825	0	0
tb.dut.u_spi_tpm.RdFifoDepthPoT_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.RdPowerof2_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A	0	0	125383265	64825	0	0
tb.dut.u_spi_tpm.TpmRegSizeMatch_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.WrDepthSpec_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.WrFifoAvailable_A	0	0	125383265	428079	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	125383265	639203	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DataKnown_A	0	0	125383265	192758	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DepthKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	125383265	192758	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A	0	0	372648194	372564414	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A	0	0	125383265	125382490	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.u_sram_fifo.DataKnown_A	0	0	125383265	5997172	0	0
tb.dut.u_spi_tpm.u_sram_fifo.DepthKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_sram_fifo.RvalidKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_sram_fifo.WreadyKnown_A	0	0	125383265	29178333	0	0
tb.dut.u_spi_tpm.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	125383265	5997172	0	0
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	905	905	0	0
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckAckNeedsReq	0	0	125383265	82370	0	0
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckHoldReq	0	0	372648194	78410	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataReg	0	0	905	905	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	125383265	580	0	0
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	372648194	580	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.CannotHaveEccAndParity_A	0	0	905	905	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	905	905	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	905	905	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	125383265	865525	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	125383265	865525	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	125383265	865525	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	125383265	865525	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.CannotHaveEccAndParity_A	0	0	905	905	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	905	905	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	905	905	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	372648194	1750262	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	372648194	1750262	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	372648194	1750262	0	0
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	372648194	1750262	0	0
tb.dut.u_spid_status.BusyBitZero_A	0	0	905	905	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A	0	0	125383265	125382490	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A	0	0	372648194	372564414	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A	0	0	905	905	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	905	905	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	372648194	3	0	905
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	372648194	1900049	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A	0	0	372648194	149787	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	149787	0	0
tb.dut.u_tlul2sram_egress.AddrOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.DataIntgOptions_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.ReqOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.SramDwHasByteGranularity_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.SramDwIsMultipleOfTlulWidth_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.TlOutKnownIfFifoKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.TlOutValidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.WdataOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.WeOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.WmaskOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.adapterNoReadOrWrite	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.u_err.dataWidthOnly32_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.DataKnown_A	0	0	372648194	2608902	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	2608902	0	0
tb.dut.u_tlul2sram_egress.u_rsp_gen.DataWidthCheck_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.u_rsp_gen.PayLoadWidthCheck	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_rspfifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_sram_byte.SramReadbackAndIntg	0	0	905	905	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_egress.u_sramreqfifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.AddrOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.DataIntgOptions_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.ReqOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.SramDwHasByteGranularity_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.SramDwIsMultipleOfTlulWidth_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.TlOutKnownIfFifoKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.TlOutValidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.WdataOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.WeOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.WmaskOutKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.adapterNoReadOrWrite	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.rvalidHighReqFifoEmpty	0	0	372648194	146842	0	0
tb.dut.u_tlul2sram_ingress.rvalidHighWhenRspFifoFull	0	0	372648194	146842	0	0
tb.dut.u_tlul2sram_ingress.u_err.dataWidthOnly32_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.DataKnown_A	0	0	372648194	340851	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	340851	0	0
tb.dut.u_tlul2sram_ingress.u_rsp_gen.DataWidthCheck_A	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.u_rsp_gen.PayLoadWidthCheck	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.DataKnown_A	0	0	372648194	340851	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	340851	0	0
tb.dut.u_tlul2sram_ingress.u_sram_byte.SramReadbackAndIntg	0	0	905	905	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DataKnown_A	0	0	372648194	146842	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DepthKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.RvalidKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.WreadyKnown_A	0	0	372648194	372565523	0	0
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	372648194	146842	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	65684	65298	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	65684	65298	0	0
tb.dut.u_upload.AddrFifoNeverFull_M	0	0	125383265	1277	0	0
tb.dut.u_upload.CmdFifoNeverFull_M	0	0	125383265	1668	0	0
tb.dut.u_upload.CmdFifoPush_A	0	0	125383265	1668	0	0
tb.dut.u_upload.FifosOnlyOneValid_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.PayloadNeverFull_M	0	0	125383265	434501	0	0
tb.dut.u_upload.u_addrfifo.MinDepth_A	0	0	905	905	0	0
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A	0	0	372648194	1277	0	0
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A	0	0	125383265	1277	0	0
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A	0	0	905	905	0	0
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M	0	0	372648194	1277	0	0
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A	0	0	372648194	1277	0	0
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A	0	0	372648194	1277	0	0
tb.dut.u_upload.u_addrfifo.RptrIncrease_A	0	0	372648194	1277	0	0
tb.dut.u_upload.u_addrfifo.SramRvalid_A	0	0	372648194	1277	0	0
tb.dut.u_upload.u_addrfifo.WSramRvalid_A	0	0	125383265	125383265	0	0
tb.dut.u_upload.u_addrfifo.WidthMatch_A	0	0	905	905	0	0
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A	0	0	125383265	1277	0	0
tb.dut.u_upload.u_addrfifo.WptrIncrease_A	0	0	125383265	1277	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	905	905	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	125383265	437446	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	125383265	94966372	0	0
tb.dut.u_upload.u_cmdfifo.MinDepth_A	0	0	905	905	0	0
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A	0	0	372648194	1668	0	0
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A	0	0	125383265	1668	0	0
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A	0	0	905	905	0	0
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M	0	0	372648194	1668	0	0
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A	0	0	372648194	1668	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A	0	0	372648194	1668	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A	0	0	372648194	1668	0	0
tb.dut.u_upload.u_cmdfifo.SramRvalid_A	0	0	372648194	1668	0	0
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A	0	0	125383265	125383265	0	0
tb.dut.u_upload.u_cmdfifo.WidthMatch_A	0	0	905	905	0	0
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A	0	0	125383265	1668	0	0
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A	0	0	125383265	1668	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	905	905	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	905	905	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A	0	0	372648194	1668	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M	0	0	125383265	1668	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	372648194	3	0	905

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	374978785	63515	63515	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	374978785	1965	1965	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	374978785	2016	2016	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	374978785	1339	1339	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	374978785	169	169	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	374978785	1044	1044	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	374978785	917	917	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	374978785	16193	16193	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	374978785	870265	870265	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	374978785	3347409	3347409	1060

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	374978785	63515	63515	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	374978785	1965	1965	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	374978785	2016	2016	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	374978785	1339	1339	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	374978785	169	169	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	374978785	1044	1044	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	374978785	917	917	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	374978785	16193	16193	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	374978785	870265	870265	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	374978785	3347409	3347409	1060